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confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1999
MOS INTEGRATED CIRCUIT
PD444008
4M-BIT CMOS FAST SRAM
512K-WORD BY 8-BIT
DATA SHEET
Document No. M14428EJ5V0DS00 (5th edition)
Date Published May 2002 NS CP(K)
Printed in Japan
The mark shows major revised points.
Description
The
PD444008 is a high speed, low power, 4,194,304 bits (524,288 words by 8 bits) CMOS static RAM.
Operating supply voltage is 5.0 V
0.5 V.
The
PD444008 is packaged in 36-pin PLASTIC SOJ.
Features
524,288 words by 8 bits organization
Fast access time : 8, 10, 12 ns (MAX.)
Output Enable input for easy application
Single +5.0 V power supply
Ordering Information
Part number
Package
Access time
Supply current mA (MAX.)
ns (MAX.)
At operating
At standby
PD444008LE-8
36-pin PLASTIC SOJ
8
200
10
PD444008LE-10
(10.16 mm (400))
10
180
PD444008LE-12
12
170
2
PD444008
Data Sheet M14428EJ5V0DS
Pin Configuration (Marking Side)
/
indicates active low signal.
36-pin PLASTIC SOJ (10.16 mm (400))
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A0
A1
A2
A3
A4
/CS
I/O1
I/O2
V
CC
GND
I/O3
I/O4
/WE
A5
A6
A7
A8
A9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
/OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0 - A18
: Address Inputs
I/O1 - I/O8 : Data Inputs / Outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
NC
: No connection
Remark Refer to Package Drawing for the 1-pin index mark.
3
PD444008
Data Sheet M14428EJ5V0DS
Block Diagram
A0
|
A18
Address buffer
Row decoder
Memory cell array
4,194,304 bits
GND
V
CC
/WE
/OE
/CS
Input data
controller
Sense amplifier /
Switching circuit
Column decoder
Address buffer
I/O1
|
I/O8
Output data
controller
Truth Table
/CS
/OE
/WE
Mode
I/O
Supply current
H
Not selected
High impedance
I
SB
L
L
H
Read
D
OUT
I
CC
L
L
Write
D
IN
L
H
H
Output disable
High impedance
Remark
: Don't care
4
PD444008
Data Sheet M14428EJ5V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
V
CC
0.5
Note
to +7.0
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+0.5
V
Operating ambient temperature
T
A
0 to 70
C
Storage temperature
T
stg
55 to +125
C
Note 2.0 V (MIN.) (pulse width : 2 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply voltage
V
CC
4.5
5.0
5.5
V
High level input voltage
V
IH
2.2
V
CC
+0.5
V
Low level input voltage
V
IL
0.5
Note
+0.8
V
Operating ambient temperature
T
A
0
70
C
Note 2.0 V (MIN.) (pulse width : 2 ns)
5
PD444008
Data Sheet M14428EJ5V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
I
LI
V
IN
= 0 V to V
CC
2
+2
A
Output leakage current
I
LO
V
I/O
= 0 V to V
CC
,
2
+2
A
/CS = V
IH
or /OE = V
IH
or /WE = V
IL
Operating supply current
I
CC
/CS = V
IL
,
Cycle time : 8 ns
200
mA
I
I/O
= 0 mA,
Cycle time : 10 ns
180
Minimum cycle time
Cycle time : 12 ns
170
Standby supply current
I
SB
/CS = V
IH
, V
IN
= V
IH
or V
IL
40
mA
I
SB1
/CS
V
CC
0.2 V,
10
V
IN
0.2 V or V
IN
V
CC
0.2 V
High level output voltage
V
OH
I
OH
= 4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Remark
V
IN
: Input voltage
V
I/O
: Input / Output voltage
Capacitance (T
A
=
25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8
pF
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
6
PD444008
Data Sheet M14428EJ5V0DS
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time
3 ns)
Test Points
GND
3.0 V
1.5 V
1.5 V
Output Waveform
Test Points
1.5 V
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or
Figure 2.
Figure 1
Figure 2
(t
AA
, t
ACS
, t
OE
, t
OH
)
(t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, t
OW
)
V
TT
= +1.5 V
I/O (Output)
50
Z
O
= 50
30 pF
C
L
+5.0 V
I/O (Output)
480
5 pF
C
L
255
Remark C
L
includes capacitances of the probe and jig, and stray capacitances.
7
PD444008
Data Sheet M14428EJ5V0DS
Read Cycle
Parameter
Symbol
-8
-10
-12
Unit
Notes
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
8
10
12
ns
Address access time
t
AA
8
10
12
ns
1
/CS access time
t
ACS
8
10
12
ns
/OE access time
t
OE
4
5
6
ns
Output hold from address change
t
OH
3
3
3
ns
/CS to output in low impedance
t
CLZ
3
3
3
ns
2, 3
/OE to output in low impedance
t
OLZ
0
0
0
ns
/CS to output in high impedance
t
CHZ
4
5
6
ns
/OE to output hold in high impedance
t
OHZ
4
5
6
ns
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at
200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
I/O (Output)
Previous data out
Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = V
IL
8
PD444008
Data Sheet M14428EJ5V0DS
Read Cycle Timing Chart 2 (/CS Access)
Address (Input)
t
RC
t
AA
t
OLZ
/CS (Input)
I/O (Output)
Data out
t
OHZ
High impedance
t
ACS
/OE (Input)
t
OE
t
CLZ
t
CHZ
High impedance
Caution Address valid prior to or coincident with /CS low level input.
Remark In read cycle, /WE should be fixed to high level.
9
PD444008
Data Sheet M14428EJ5V0DS
Write Cycle
Parameter
Symbol
-8
-10
-12
Unit
Notes
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
8
10
12
ns
/CS to end of write
t
CW
6
7
8
ns
Address valid to end of write
t
AW
6
7
8
ns
Write pulse width
t
WP
6
7
8
ns
Data valid to end of write
t
DW
4
5
6
ns
Data hold time
t
DH
0
0
0
ns
Address setup time
t
AS
0
0
0
ns
Write recovery time
t
WR
0
0
0
ns
/WE to output in high impedance
t
WHZ
4
5
6
ns
1, 2
Output active from end of write
t
OW
3
3
3
ns
Notes 1. Transition is measured at
200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WP
t
AS
t
WR
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input / Output)
t
DH
t
WHZ
t
AW
High
impe-
dance
High
impe-
dance
t
OW
Indefinite data out
Data in
Indefinite data out
t
DW
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
10
PD444008
Data Sheet M14428EJ5V0DS
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
AW
t
WP
t
WR
t
DW
t
DH
Address (Input)
/CS (Input)
/WE (Input)
I/O (Input)
High impedance
Data in
High impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
11
PD444008
Data Sheet M14428EJ5V0DS
Package Drawing
M
N
K
M
Q
G
H
J
E
T
U
B
C
D
E
F
G
H
I
J
K
23.6
0.20
11.18
0.2
1.005
0.1
0.74
3.5
0.2
2.545
0.2
0.8 MIN.
10.16
0.1
NOTE
P
Q
0.1
9.4
0.20
0.12
0.42
1.27 (T.P.)
2.6
Each lead centerline is located within 0.12 mm
of its true position (T.P.) at maximum material
condition.
M
N
T
U
0.22
R 0.85
+
0.08
-
0.07
36-PIN PLASTIC SOJ (10.16 mm (400))
P36LE-400A-2
ITEM
MILLIMETERS
+
0.08
-
0.07
19
18
36
1
S
S
I
F
P
C
D
B
12
PD444008
Data Sheet M14428EJ5V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD444008.
Type of Surface Mount Device
PD444008LE
: 36-pin PLASTIC SOJ (10.16 mm (400))
13
PD444008
Data Sheet M14428EJ5V0DS
Revision History
Edition/
Page
Type of
Location
Description
Date
This
Previous
revision
(Previous edition
This edition)
edition
edition
5th edition/
p.1, 2, 11, 12
p.1, 3, 13, 14
Deletion
Ordering Information,
44-pin PLASTIC TSOP (II)
May 2002
Pin Configuration,
Package Drawing,
Type of Surface Mount Device
p.5
p.6
Deletion
DC Characteristics
Remark 2
p.7, 9
p.8, 10
Deletion
Read Cycle, Write Cycle
Remark
14
PD444008
Data Sheet M14428EJ5V0DS
[MEMO]
15
PD444008
Data Sheet M14428EJ5V0DS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD444008
M8E 00. 4
The information in this document is current as of May, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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