Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagrams
- Electrical Specifications
- Package Drawing
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2000
MOS INTEGRATED CIRCUIT
PD4442162, 4442182, 4442322, 4442362
4M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
SINGLE CYCLE DESELECT
Document No. M14520EJ3V0DS00 (3rd edition)
Date Published May 2001 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
The mark
5
5
5
5
shows major revised points.
Description
The
PD4442162 is a 262,144-word by 16-bit, the
PD4442182 is a 262,144-word by 18-bit,
PD4442322 is a
131,072-word by 32-bit and the
PD4442362 is a 131,072-word by 36-bit synchronous static RAM fabricated with
advanced CMOS technology using Full-CMOS six-transistor memory cell.
The
PD4442162,
PD4442182,
PD4442322 and
PD4442362 integrates unique synchronous peripheral circuitry,
2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The
PD4442162,
PD4442182,
PD4442322 and
PD4442362 are suitable for applications which require
synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer
memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State
("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes
normal operation.
The
PD4442162,
PD4442182,
PD4442322 and
PD4442362 are packaged in 100-pin PLASTIC LQFP with a
1.4 mm package thickness for high density and low capacitive loading.
Features
3.3 V (A version) or 2.5 V (C version) Core Supply
Synchronous operation
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
Single-Cycle deselect timing
All registers triggered off positive clock edge
3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 2.5 ns (250 MHz), 2.8 ns (225 MHz), 3.0 ns (200 MHz), 3.5 ns (167 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 - /BW4 (
PD4442322,
PD4442362), /BW1 - /BW2 (
PD4442162,
PD4442182), /BWE
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
Preliminary Data Sheet M14520EJ3V0DS
PD4442162, 4442182, 4442322, 4442362
Ordering Information
Part number
Access
Clock
Core Supply
I/O
Package
Remark
Time
Frequency
Voltage
Interface
ns
MHz
V
PD4442162GF-A40
2.5
250
3.3 0.165
3.3 V LVTTL
100-pin PLASTIC
A version
PD4442162GF-A44
2.8
225
LQFP (14
20)
PD4442162GF-A50
3.0
200
PD4442162GF-A60
3.5
167
PD4442182GF-A40
2.5
250
PD4442182GF-A44
2.8
225
PD4442182GF-A50
3.0
200
PD4442182GF-A60
3.5
167
PD4442322GF-A40
2.5
250
PD4442322GF-A44
2.8
225
PD4442322GF-A50
3.0
200
PD4442322GF-A60
3.5
167
PD4442362GF-A40
2.5
250
PD4442362GF-A44
2.8
225
PD4442362GF-A50
3.0
200
PD4442362GF-A60
3.5
167
PD4442162GF-A44C
Note
2.8
225
3.3 0.165
2.5 V LVTTL
PD4442162GF-A50C
Note
3.0
200
PD4442162GF-A60C
Note
3.5
167
PD4442182GF-A44C
Note
2.8
225
PD4442182GF-A50C
Note
3.0
200
PD4442182GF-A60C
Note
3.5
167
PD4442322GF-A44C
Note
2.8
225
PD4442322GF-A50C
Note
3.0
200
PD4442322GF-A60C
Note
3.5
167
PD4442362GF-A44C
Note
2.8
225
PD4442362GF-A50C
Note
3.0
200
PD4442362GF-A60C
Note
3.5
167
PD4442162GF-C50
Note
3.0
200
2.5 0.125
2.5 V LVTTL
C version
PD4442162GF-C60
Note
3.5
167
PD4442182GF-C50
Note
3.0
200
PD4442182GF-C60
Note
3.5
167
PD4442322GF-C50
Note
3.0
200
PD4442322GF-C60
Note
3.5
167
PD4442362GF-C50
Note
3.0
200
PD4442362GF-C60
Note
3.5
167
Note Under development
5
5
5
5
3
Preliminary Data Sheet M14520EJ3V0DS
PD4442162, 4442182, 4442322, 4442362
Pin Configurations (Marking Side)
/
indicates active low signal.
100-pin PLASTIC LQFP (14
20)
[
PD4442162GF,
PD4442182GF ]
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A17
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
NC
NC
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for 1-pin index mark.
4
Preliminary Data Sheet M14520EJ3V0DS
PD4442162, 4442182, 4442322, 4442362
Pin Identifications
[
PD4442162GF,
PD4442182GF ]
Symbol
Pin No.
Description
A0 - A17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81,
Synchronous Address Input
44, 45, 46, 47, 48, 49, 50, 80
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12,
Synchronous Data In,
13, 18, 19, 22, 23
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
74
Synchronous Data In (Parity),
I/OP2, NC
Note
24
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,
No Connection
39, 42, 43, 51, 52, 53, 56, 57, 66, 75,
78, 79, 95, 96
Note NC (No Connection) is used in the
PD4442162GF.
I/OP1 - I/OP2 are used in the
PD4442182GF.
5
Preliminary Data Sheet M14520EJ3V0DS
PD4442162, 4442182, 4442322, 4442362
100-pin PLASTIC LQFP (14
20)
[
PD4442322GF,
PD4442362GF ]
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
NC
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for 1-pin index mark.
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