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2001

MOS INTEGRATED CIRCUIT

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

4M-BIT CMOS SYNCHRONOUS FAST SRAM

FLOW THROUGH OPERATION

Document No. M15502EJ1V0DS00 (1st edition)
Date Published May 2001 NS CP(K)
Printed in Japan

PRELIMINARY DATA SHEET

Description

The

PD4442161-Y is a 262,144-word by 16-bit, the

PD4442181-Y is a 262,144-word by 18-bit, the

PD4442321-Y

is a 131,072-word by 32-bit and the

PD4442361-Y is a 131,072-word by 36-bit synchronous static RAM fabricated

with advanced CMOS technology using Full-CMOS six-transistor memory cell.
The

PD4442161-Y,

PD4442181-Y,

PD4442321-Y and

PD4442361-Y integrate unique synchronous peripheral

circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive
edge of the single clock input (CLK).
The

PD4442161-Y,

PD4442181-Y,

PD4442321-Y and

PD4442361-Y are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer
memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep").
In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The

PD4442161-Y,

PD4442181-Y,

PD4442321-Y and

PD4442361-Y are packaged in 100-pin PLASTIC LQFP

with a 1.4 mm package thickness for high density and low capacitive loading.

Features

3.3 V (A version) or 2.5 V (C version) Core Supply

Synchronous operation

Extended operating temperature (T

= 40 to +85

Internally self-timed write control

Burst read / write : Interleaved burst and linear burst sequence

Fully registered inputs for flow through operation

All registers triggered off positive clock edge

3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs

Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)

Asynchronous output enable : /G

Burst sequence selectable : MODE

Sleep mode : ZZ (ZZ = Open or Low : Normal operation)

Separate byte write enable : /BW1 - /BW4 (

PD4442321-Y,

PD4442361-Y), /BW1 - /BW2 (

PD4442161-Y,

PD4442181-Y), /BWE

Global write enable : /GW

Three chip enables for easy depth expansion

Common I/O using three state outputs

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Ordering Information

Part number

Access

Clock

Core Supply

I/O

Package

Remark

Time

Frequency

Voltage

Interface

MHz

PD4442161GF-A65Y

6.5

133

3.3 ± 0.165

3.3 V or 2.5 V

100-pin PLASTIC

A version

PD4442161GF-A75Y

7.5

117

LVTTL

LQFP (14

20)

PD4442161GF-A85Y

8.5

100

PD4442181GF-A65Y

6.5

133

PD4442181GF-A75Y

7.5

117

PD4442181GF-A85Y

8.5

100

PD4442321GF-A65Y

6.5

133

PD4442321GF-A75Y

7.5

117

PD4442321GF-A85Y

8.5

100

PD4442361GF-A65Y

6.5

133

PD4442361GF-A75Y

7.5

117

PD4442361GF-A85Y

8.5

100

PD4442161GF-C75Y

Note

7.5

117

2.5 ± 0.125

2.5 V LVTTL

C version

PD4442161GF-C85Y

Note

8.5

100

PD4442181GF-C75Y

Note

7.5

117

PD4442181GF-C85Y

Note

8.5

100

PD4442321GF-C75Y

Note

7.5

117

PD4442321GF-C85Y

Note

8.5

100

PD4442361GF-C75Y

Note

7.5

117

PD4442361GF-C85Y

Note

8.5

100

Note Under development

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Pin Configurations (Marking Side)

×××

indicates active low signal.

100-pin PLASTIC LQFP (14

×
×
×
×

20)

[

µ
µ
µ
µ

PD4442161GF-Y,

µ
µ
µ
µ

PD4442181GF-Y ]

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/OP2, NC

A17

I/OP1, NC

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

/CE

CE2

/BW2

/BW1

/CE2

CLK

/GW

/BWE

/AC

/AP

/ADV

MODE

A10

A11

A12

A13

A14

A15

A16

Remark Refer to Package Drawing for 1-pin index mark.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Pin Identifications

[

µ
µ
µ
µ

PD4442161GF-Y,

µ
µ
µ
µ

PD4442181GF-Y ]

Symbol

Pin No.

Description

A0 - A17

37, 36, 35, 34, 33, 32, 100, 99, 82, 81,

Synchronous Address Input

44, 45, 46, 47, 48, 49, 50, 80

I/O1 - I/O16

58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12,

Synchronous Data In,

13, 18, 19, 22, 23

Synchronous / Asynchronous Data Out

I/OP1, NC

Note

Synchronous Data In (Parity),

I/OP2, NC

Note

Synchronous / Asynchronous Data Out (Parity)

/ADV

Synchronous Burst Address Advance Input

/AP

Synchronous Address Status Processor Input

/AC

Synchronous Address Status Controller Input

/CE, CE2, /CE2

98, 97, 92

Synchronous Chip Enable Input

/BW1, /BW2, /BWE

93, 94, 87

Synchronous Byte Write Enable Input

/GW

Synchronous Global Write Input

Asynchronous Output Enable Input

CLK

Clock Input

MODE

Asynchronous Burst Sequence Select Input

Do not change state during normal operation

Asynchronous Power Down State Input

15, 41, 65, 91

Power Supply

17, 40, 67, 90

Ground

4, 11, 20, 27, 54, 61, 70, 77

Output Buffer Power Supply

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Ground

1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38,

No Connection

39, 42, 43, 51, 52, 53, 56, 57, 66, 75,

78, 79, 95, 96

Note NC (No Connection) is used in the

PD4442161GF-Y.

I/OP1 - I/OP2 are used in the

PD4442181GF-Y.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

100-pin PLASTIC LQFP (14

×
×
×
×

20)

[

µ
µ
µ
µ

PD4442321GF-Y,

µ
µ
µ
µ

PD4442361GF-Y ]

I/OP3, NC

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

I/OP4, NC

I/OP2, NC

I/O16

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/OP1, NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

/CE

CE2

/BW4

/BW3

/BW2

/BW1

/CE2

CLK

/GW

/BWE

/AC

/AP

/ADV

MODE

A10

A11

A12

A13

A14

A15

A16

Remark Refer to Package Drawing for 1-pin index mark.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

[

µ
µ
µ
µ

PD4442321GF-Y,

µ
µ
µ
µ

PD4442361GF-Y ]

Symbol

Pin No.

Description

A0 - A16

37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input

45, 46, 47, 48, 49, 50

I/O1 - I/O32

52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72,

Synchronous Data In,

73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13,

Synchronous / Asynchronous Data Out

18, 19, 22, 23, 24, 25, 28, 29

I/OP1, NC

Note

Synchronous Data In (Parity),

I/OP2, NC

Note

Synchronous / Asynchronous Data Out (Parity)

I/OP3, NC

Note

I/OP4, NC

Note

/ADV

Synchronous Burst Address Advance Input

/AP

Synchronous Address Status Processor Input

/AC

Synchronous Address Status Controller Input

/CE, CE2, /CE2

98, 97, 92

Synchronous Chip Enable Input

/BW1 - /BW4, /BWE

93, 94, 95, 96, 87

Synchronous Byte Write Enable Input

/GW

Synchronous Global Write Input

Asynchronous Output Enable Input

CLK

Clock Input

MODE

Asynchronous Burst Sequence Select Input

Do not change state during normal operation

Asynchronous Power Down State Input

15, 41, 65, 91

Power Supply

17, 40, 67, 90

Ground

4, 11, 20, 27, 54, 61, 70, 77

Output Buffer Power Supply

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Ground

14, 16, 38, 39, 42, 43, 66

No Connection

Note NC (No Connection) is used in the

PD4442321GF-Y.

I/OP1 - I/OP4 are used in the

PD4442361GF-Y.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Block Diagrams

[

µ
µ
µ
µ

PD4442161-Y,

µ
µ
µ
µ

PD4442181-Y ]

Address
register

Binary

counter

and logic

CLR

Byte 1
Write register

Byte 1
Write driver

8/9

Byte 2
Write register

Byte 2
Write driver

8/9

Enable
register

Row and column

Input
register

Output
buffer

A0, A1

A1'

A0'

16/18

A0 - A17

MODE

/ADV

CLK

/AC

/AP

/BW1

/BW2

/BWE

/GW

/CE

CE2

/CE2

I/O1 - I/O16

I/OP1 - I/OP2

Power down control

16/18

Memory Cell Array

512 rows

512

16 columns

(4,194,304 bits)

512

18 columns

(4,718,592 bits)

decoders

Burst Sequence

[

µ
µ
µ
µ

PD4442161-Y,

µ
µ
µ
µ

PD4442181-Y ]

Interleaved Burst Sequence Table (MODE = Open or V

)

External Address

A17 - A2, A1, A0

1st Burst Address

A17 - A2, A1, /A0

2nd Burst Address

A17 - A2, /A1, A0

3rd Burst Address

A17 - A2, /A1, /A0

Linear Burst Sequence Table (MODE = V

)

External Address

A17 - A2, 0, 0

A17 - A2, 0, 1

A17 - A2, 1, 0

A17 - A2, 1, 1

1st Burst Address

A17 - A2, 0, 1

A17 - A2, 1, 0

A17 - A2, 1, 1

A17 - A2, 0, 0

2nd Burst Address

A17 - A2, 1, 0

A17 - A2, 1, 1

A17 - A2, 0, 0

A17 - A2, 0, 1

3rd Burst Address

A17 - A2, 1, 1

A17 - A2, 0, 0

A17 - A2, 0, 1

A17 - A2, 1, 0

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

[

µ
µ
µ
µ

PD4442321-Y,

µ
µ
µ
µ

PD4442361-Y ]

Address
register

Binary

counter

and logic

CLR

Byte 1
Write register

Byte 1
Write driver

8/9

Byte 2
Write register

Byte 2
Write driver

8/9

Byte 3
Write register

Byte 3
Write driver

8/9

Byte 4
Write register

Byte 4
Write driver

8/9

Enable
register

Row and column

Input
register

Output
buffer

32/36

A0, A1

A1'

A0'

32/36

A0 - A16

MODE

/ADV

CLK

/AC

/AP

/BW1

/BW2

/BW3

/BW4

/BWE

/GW

/CE

CE2

/CE2

I/O1 - I/O32

I/OP1 - I/OP4

Power down control

Memory Cell Array

512 rows

256

32 columns

(4,194,304 bits)

256

36 columns

(4,718,592 bits)

decoders

[

µ
µ
µ
µ

PD4442321-Y,

µ
µ
µ
µ

PD4442361-Y ]

Interleaved Burst Sequence Table (MODE = Open or V

)

External Address

A16 - A2, A1, A0

1st Burst Address

A16 - A2, A1, /A0

2nd Burst Address

A16 - A2, /A1, A0

3rd Burst Address

A16 - A2, /A1, /A0

Linear Burst Sequence Table (MODE = V

)

External Address

A16 - A2, 0, 0

A16 - A2, 0, 1

A16 - A2, 1, 0

A16 - A2, 1, 1

1st Burst Address

A16 - A2, 0, 1

A16 - A2, 1, 0

A16 - A2, 1, 1

A16 - A2, 0, 0

2nd Burst Address

A16 - A2, 1, 0

A16 - A2, 1, 1

A16 - A2, 0, 0

A16 - A2, 0, 1

3rd Burst Address

A16 - A2, 1, 1

A16 - A2, 0, 0

A16 - A2, 0, 1

A16 - A2, 1, 0

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Asynchronous Truth Table

Operation

I/O

Read Cycle

Dout

Read Cycle

Hi-Z

Write Cycle

Hi-Z, Din

Deselected

Hi-Z

Remark

: don't care

Synchronous Truth Table

Operation

/CE

CE2

/CE2

/AP

/AC

/ADV

/WRITE

CLK

Address

Deselected

Note

None

Deselected

Note

None

Deselected

Note

None

Deselected

Note

None

Deselected

Note

None

Read Cycle / Begin Burst

External

Read Cycle / Begin Burst

External

Read Cycle / Continue Burst

Read Cycle / Suspend Burst

Current

Read Cycle / Suspend Burst

Current

Write Cycle / Begin Burst

External

Write Cycle / Continue Burst

Write Cycle / Suspend Burst

Current

Write Cycle / Suspend Burst

Current

Note Deselect status is held until new "Begin Burst" entry.

Remarks 1.

: don't care

2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are LOW

or /GW is LOW.
/WRITE = H means the following two cases.

(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Partial Truth Table for Write Enables

[

µ
µ
µ
µ

PD4442161-Y,

µ
µ
µ
µ

PD4442181-Y ]

Operation

/GW

/BWE

/BW1

/BW2

Read Cycle

Write Cycle / Byte 1 Only

Write Cycle / All Bytes

Remark

: don't care

[

µ
µ
µ
µ

PD4442321-Y,

PD4442361-Y ]

Operation

/GW

/BWE

/BW1

/BW2

/BW3

/BW4

Read Cycle

Write Cycle / Byte 1 Only

Write Cycle / All Bytes

Remark

: don't care

ZZ (Sleep) Truth Table

Chip Status

0.2 V

Active

Open

Active

0.2 V

Sleep

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Note

Supply voltage (A version)

0.5

+4.0

Supply voltage (C version)

0.5

+3.0

Output supply voltage

0.5

Input voltage

0.5

+ 0.5

1, 2

Input / Output voltage

I/O

0.5

+ 0.5

1, 2

Operating ambient temperature

+85

°C

Storage temperature

stg

+125

°C

Notes 1. 2.0 V (MIN.) (Pulse width : 2 ns)

2. V

Q + 2.3 V (MAX.) (Pulse width : 2 ns)

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (T

= 40 to +85

°
°
°
°

(A version)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

3.135

3.3

3.465

2.5 V LVTTL interface

Output supply voltage

2.375

2.5

2.9

High level input voltage

1.7

+ 0.3

Low level input voltage

0.3

Note

+0.7

3.3 V LVTTL interface

Output supply voltage

3.135

3.3

3.465

High level input voltage

2.0

+ 0.3

Low level input voltage

0.3

Note

+0.8

Note 0.8 V (MIN.) (Pulse width : 2 ns)

(C version)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

2.375

2.5

2.625

Output supply voltage

2.375

2.5

2.625

High level input voltage

1.7

+ 0.3

Low level input voltage

0.3

Note

+0.7

Note 0.8 V (MIN.) (Pulse width : 2 ns)

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Note

Input leakage current

(except ZZ, MODE) = 0 V to V

I/O leakage current

I/O

= 0 V to V

Q, Outputs are disabled.

Operating supply current

Device selected, Cycle = MAX.

-A65Y

330

or V

-A75Y, -C75Y

300

I/O

= 0 mA

-A85Y, -C85Y

280

DD1

Suspend cycle, Cycle = MAX.

150

/AC, /AP, /ADV, /GW, /BWEs

or V

, I

I/O

= 0 mA

Standby supply current

Device deselected, Cycle = 0 MHz,

or V

, All inputs are static.

SB1

Device deselected, Cycle = 0 MHz,

0.2 V or V

0.2 V,

I/O

0.2 V, All inputs are static.

SB2

Device deselected, Cycle = MAX.

150

or V

Power down supply current

SBZZ

0.2 V, V

I/O

Q + 0.2 V

2.5 V LVTTL interface

High level output voltage

= 2.0 mA

1.7

= 1.0 mA

2.1

Low level output voltage

= +2.0 mA

0.7

= +1.0 mA

0.4

3.3 V LVTTL interface

High level output voltage

= 4.0 mA

2.4

Low level output voltage

= +8.0 mA

0.4

Remark These DC characteristics are in common regardless product classification.

Capacitance (T

= 25

°
°
°
°

C, f = 1MHz)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Input capacitance

= 0 V

4.5

Input / Output capacitance

I/O

= 0 V

7.0

Clock input capacitance

clk

= 0 V

6.0

Remark These parameters are not 100

tested.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)

AC Test Conditions

2.5 V LVTTL Interface

Input waveform (Rise / Fall time

2.4 ns)

Test points

2.4 V

Q/2

Output waveform

Test points

Q/2

3.3 V LVTTL Interface

Input waveform (Rise / Fall time

3.0 ns)

Test points

3.0 V

1.5 V

Output waveform

Test points

1.5 V

Output load condition

: 30 pF

5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)

Figure1 External load at test

= +1.2 V/+1.5 V

I/O (Output)

= 50

Remark C

includes capacitances of the probe and jig, and stray capacitances.

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

Read and Write Cycle

Parameter

Symbol

-A65Y

-A75Y, -C75Y

-A85Y, -C85Y

Unit

Note

(133 MHz)

(117 MHz)

(100MHz)

Standard

Alias

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

Cycle time

TKHKH

TCYC

7.5

8.6

10.0

Clock access time

TKHQV

TCD

6.5

7.5

8.5

Output enable access time

TGLQV

TOE

3.5

Clock high to output active

TKHQX1

TDC1

2.5

Clock high to output change

TKHQX2

TDC2

2.5

Output enable to output active

TGLQX

TOLZ

Output disable to output high-Z

TGHQZ

TOHZ

3.5

Clock high to output high-Z

TKHQZ

TCZ

2.5

4.0

2.5

4.0

2.5

4.0

Clock high pulse width

TKHKL

TCH

2.5

Clock low pulse width

TKLKH

TCL

2.5

Setup times Address

TAVKH

TAS

1.5

2.0

Address status

TADSVKH

TSS

Data in

TDVKH

TDS

Write enable

TWVKH

TWS

Address advance TADVVKH

Chip enable

TEVKH

Hold times

Address

TKHAX

TAH

0.5

Address status

TKHADSX

TSH

Data in

TKHDX

TDH

Write enable

TKHWX

TWH

Address advance TKHADVX

Chip enable

TKHEX

Power down entry time

TZZE

7.5

8.6

10.0

Power down recovery time

TZZR

7.5

8.6

10.0

Preliminary Data Sheet M15502EJ1V0DS

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

PD4442161-Y, 4442181-Y, 4442321-Y, 4442361-Y

M8E 00. 4

The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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