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2001
Document No. M15867EJ5V0DS00 (5th edition)
Date Published August 2002 NS CP (K)
Printed in Japan
MOS INTEGRATED CIRCUIT
PD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
PRELIMINARY DATA SHEET
The mark shows major revised points.
Description
The
PD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile
Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The
PD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The
PD4664312-X is packed in 93-pin TAPE FBGA.
Features
4,194,304 words by 16 bits organization
Fast access time: 65, 75 ns (MAX.)
Fast page access time: 18, 25 ns (MAX.)
Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
Low voltage operation: 2.7 to 3.1 V (-B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X)
Operating ambient temperature: T
A
= 25 to +85 C
Output Enable input for easy application
Chip Enable input: /CS pin
Standby Mode input: MODE pin
Standby Mode1: Normal standby (Memory cell data hold valid)
Standby Mode2: Density of memory cell data hold is variable
PD4664312
Access
Operating supply
Operating
Supply current
time
voltage
ambient
At operating
At standby
A (MAX.)
ns (MAX.)
V
temperature
mA (MAX.)
Density of data hold
Chip
I/O
C
64M bits 16M bits 8M bits 4M bits 0M bit
-B65X
65
2.7 to 3.1
25 to +85
45
100
60
50
45
10
-BE75X
Note
75
2.7 to 3.1 1.65 to 2.1
40
Note Under development
Preliminary Data Sheet M15867EJ5V0DS
3
PD4664312-X
Pin Configurations
/xxx indicates active low signal.
93-pin TAPE FBGA (12 x 9)
[
PD4664312F9-B65X-CR2 ]
Top View
GND
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
NC
NC
I/O10
NC
/WE
V
CC
A16
I/O11
NC
NC
A12
I/O6
I/O13
A9
A15
A19
I/O14
/CS
I/O15
I/O1
A1
A2
A4
A10
NC
I/O2
A0
A3
MODE
A20
A14
/LB
NC
NC
/UB
I/O3
A21
NC
GND
A
B
C
D
E
F
G
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
K
L
J
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L K J H G F E D C B A
M
B C D E F G H J K L M
10
9
8
7
6
5
4
3
2
1
A
Top View
Bottom View
N
P
N P
NC
NC
NC
NC
N
P
NC
NC
NC
NC
NC
NC
NC
NC
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
A0 to A21
: Address inputs
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
MODE
: Standby mode
/WE
: Write enable
/OE
: Output enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
Note
: No Connection
Preliminary Data Sheet M15867EJ5V0DS
4
PD4664312-X
93-pin TAPE FBGA (12 x 9)
[
PD4664312F9-BE75X-CR2 ]
Top View
GND
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
NC
NC
I/O10
NC
/WE
V
CC
A16
I/O11
NC
NC
A12
I/O6
I/O13
A9
A15
A19
I/O14
/CS
I/O15
I/O1
A1
A2
A4
A10
V
CC
Q
I/O2
A0
A3
MODE
A20
A14
/LB
NC
NC
/UB
I/O3
A21
NC
GND
A
B
C
D
E
F
G
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
K
L
J
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L K J H G F E D C B A
M
B C D E F G H J K L M
10
9
8
7
6
5
4
3
2
1
A
Top View
Bottom View
N
P
N P
NC
NC
NC
NC
N
P
NC
NC
NC
NC
NC
NC
NC
NC
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
A0 to A21
: Address inputs
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
MODE
: Standby mode
/WE
: Write enable
/OE
: Output enable
/LB, /UB
: Byte data select
V
CC
: Power supply
V
CC
Q
: Input / Output power supply
GND
: Ground
NC
Note
: No Connection
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