1995, 1999
DATA SHEET
COMPOUND TRANSISTOR
PA103
FEATURES
FIVE MONOLITHIC 9 GHz f
T
TRANSISTORS:
Two of these use a common emitter pin and can be used as differential amplifiers
OUTSTANDING h
FE
LINEARITY
TWO PACKAGE OPTIONS:
PA103B: Superior thermal dissipation due to studded ceramic package
PA103G: Reduced circuit size due to 14-pin plastic SOP package for surface mounting
DESCRIPTION AND APPLICATIONS
The
PA103 is a user configurable Silicon bipolar transistor array consisting of a common emitter pair and three
individual bipolar transistors. It is available in a surface mount 14-pin plastic SOP package and a 14-pin ceramic package.
Typical applications include: differential amplifiers and oscillators, high speed comparators, advanced cellular phone
systems, electro-optic and other signal processing up to 1.5 gigabits/second.
ORDERING INFORMATION
PART NUMBER
PACKAGE
PA103B-E1
14-pin ceramic package
PA103G-E1
14-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
C)
SYMBOLS
PARAMETERS
UNITS
RATINGS
V
CBO
*
Collector to Base Voltage
V
15
V
CEO
*
Collector to Emitter Voltage
V
6
V
EBO
*
Emitter to Base Voltage
V
2.5
I
C
*
Collector Current
mA
40
P
T
Power Dissipation
PA103B
mW
650
PA103G
mW
350
T
J
Junction Temperature
PA103B
C
200
PA103G
C
125
T
STG
Storage Temperature
PA103B
C
55 to +200
PA103G
C
55 to +125
* Absolute maximum ratings for each transistor.
HIGH FREQUENCY NPN TRANSISTOR ARRAY
Caution electro-static sensitive devices
Document No. P10708EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark
shows major revised points.
PA103
2
Data Sheet P10708EJ2V0DS00
PACKAGE DIMENSIONS
(UNIT: mm)
PA103B
14 PIN CERAMIC PACKAGE
PA103G
See connection diagram for description of leads.
0.8
TOP VIEW
0.35
1.27
6.2
5.0 MAX.
4.5 MIN.
0.08
2.3 MIN.
1.6
2. 7
MAX.
SIDE VIEW
BOTTOM VIEW
1.8
3.0
14 PIN PLASTIC SOP (225 mil)
10.2
0.26
1.27
0.10
NOTE Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition.
detail of lead end
M
1
7
14
8
1.42 MAX
6.55
0.2
4.38
0.1
0.6
0.2
1.1
0.16
0.10
0.15
+0.10
0.05
3
+7
3
0.40
+0.10
0.05
1.49
0.1
0.1
1.59
+0.21
0.20
PA103
3
Data Sheet P10708EJ2V0DS00
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified T
A
= +25 C
PA103B,
PA103G common)
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN.
TYP.
MAX.
I
CBO
Collector Cutoff Current at V
CB
= 5 V, I
E
= 0 (Q1 to Q5)
A
1.0
I
EBO
Emitter Cutoff Current at V
EB
= 1 V, I
C
= 0 (Q1 to Q5)
A
1.0
h
FE
Direct Current Amplification at V
CE
= 3 V, I
C
= 5 mA (Q1 to Q5)
40
100
250
h
FE1
/h
FE2
Direct Current Amplification Ratio at V
CE
= 3 V, I
C
= 5 mA, (Q1, Q2)
0.9
1.0
1.1
V
BE
Emitter to Base Voltage at V
CE
= 3 V, I
C
= 5 mA (Q1, Q2)
V
0.8
1.0
V
BE
Emitter to Base Voltage Difference, V
CE
= 3 V, I
C
= 5 mA |Q1 - Q2|
mV
8.0
20
C
CB
Collector to Base Capacitance at V
CB
= 3 V, f = 1 MHz (Q1 to Q5)
pF
0.9
1.8
C
EB
Emitter to Base Capacitance at V
EB
= 0, f = 1 MHz (Q1 to Q4)
pF
1.4
2.8
C
CS
Collector/Substrate Capacitance at V
CS
= 3 V, f = 1 MHz (Q1 to Q4)
pF
1.4
2.8
f
T
Gain Bandwidth Product* at V
CE
= 3 V, I
C
= 10 mA
GHz
9.0
* Measured by installing a single transistor in a Micro-X package: the value shown is a reference value.
CONNECTION DIAGRAM
(Top View)
PA103B
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Q
1
SUB
Q
5
Q
3
Q
2
Q
4
PA103G
Q
1
SUB
Q
5
Q
2
14
13
12
11
10
9
8
1
2
3
4
5
6
7
Q
4
Q
3
PA103
4
Data Sheet P10708EJ2V0DS00
TYPICAL PERFORMANCE CHARACTERISTICS
(T
A
= +25
C)
10
8
6
4
2
0
0
1
2
3
4
5
Collector to Emitter Voltage, V
CE
(V)
I
B
= 20 A
100
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
20
0.4
Collector Current, I
C
(mA)
Base to Emitter Voltage, V
BE
(V)
COLLECTOR CURRENT vs.
BASE TO EMITTER VOLTAGE
Collector Current, I
C
(mA)
10
2
5
1
0.1
0.5
0.5 0.6 0.7 0.8 0.9 1.0
V
CE
= 3 V
1000
0.5
1
2
Collector Current, I
C
(mA)
DC CURRENT GAIN vs.
COLLECTOR CURRENT
12
10
8
6
4
1
Gain Bandwidth Product, f
T
(GHz)
Collector Current, I
C
(mA)
GAIN BANDWIDTH PRODUCT vs.
COLLECTOR CURRENT
DC Current Gain, h
FE
200
500
100
20
50
10
5
10
20
50
50
2
5
10
20
V
CE
= 5 V
3 V
1 V
100
50
20
10
0
1
Gain (dB)
Collector Current, I
C
(mA)
GAIN AND NOISE FIGURE OF
INDIVIDUAL TRANSISTOR
2
5
10
20
50 100
V
CC
= 3 V
f = 1 GHz
8
6
4
2
0
Noise Figure, NF (dB)
GAIN
NF
80
60
40
200
1.1
PA103
5
Data Sheet P10708EJ2V0DS00
TYPICAL HIGH SPEED COMPARATOR
Q
1
ANALOG INPUT
REFERENCE
Q
2
R
1
R
2
Q
3
Q
4
LATCH
LATCH
Q
11
Q
12
Q
9
Q
5
Q
10
Q
6
R
3
R
5
R
4
R
6
Q
7
Q
8
OUTPUT
FEATURES:
1.
2.
3.
High Sensitivity
Low Positive Feedback time
Optimized latch recovery time
TYPICAL DIFFERENTIAL OSCILLATOR
Q
2
BENEFITS:
1.
2.
3.
4.
5.
Ease of Integration
Very Low Distortion
Automatic Gain Control
Minimum Loading on Tank Circuit
Very Low 1/f Noise
V
CC
V
CC
C
1
C
2
R
2
Q
1
V
OUT
RFC
BIAS
4
AC
SHORT
TYPICAL COMMON MODE DIFFERENTIAL AMP
FEATURES:
1.
2.
3.
High Gain
Stable
Auto Gain Control
IN
V
BB1
(5 V)
V
BB2
1 K
1 K
1 K
160
1000 pF
100 pF
100
V
CC
(10 V)
OUT
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
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