1999,2000
MOS FIELD EFFECT TRANSISTOR
PA1764
SWITCHING
DUAL N-CHANNEL POWER MOS FET
INDUSTRIAL USE
DATA SHEET
Document No.
G14329EJ1V0DS00 (1st edition)
Date Published
January 2000 NS CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark
5
shows major revised points.
DESCRIPTION
The
PA1764 is N-channel MOS Field Effect
Transistor designed for high current switching
applications.
FEATURES
Dual chip type
Low On-state Resistance
R
DS(on)1
= 27 m
(TYP.) (V
GS
= 10 V, I
D
= 3.5
A)
R
DS(on)2
= 32 m
(TYP.) (V
GS
= 4.5 V, I
D
= 3.5
A)
R
DS(on)3
= 34 m
(TYP.) (V
GS
= 4.0 V, I
D
= 3.5
A)
Low input capacitance
C
iss
= 1300 pF (TYP.)
Built-in G-S protection diode
Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
PA1764G
Power SOP8
ABSOLUTE MAXIMUM RATINGS (T
A
= 25C, All terminals are connected.)
Drain to Source Voltage
V
DSS
60
V
Gate to Source Voltage
V
GSS
20
V
Drain Current (DC)
I
D(DC)
7
A
Drain Current (pulse)
Note1
I
D(pulse)
28
A
Total Power Dissipation (1 unit)
Note2
P
T
1.7
W
Total Power Dissipation (2 unit)
Note2
P
T
2.0
W
Channel Temperature
T
ch
150
C
Storage Temperature
T
stg
55 to +150
C
Single Avalanche Current
Note3
I
AS
7
A
Single Avalanche Energy
Note3
E
AS
98
mJ
Notes 1. PW
10
s, Duty Cycle
1
%
2. Mounted on ceramic substrate of 2000
mm
2
x 2.2
mm
3. Starting T
ch
= 25 C, R
G
= 25
,
V
GS
= 20 V
0 V
PACKAGE DRAWING (Unit : mm)
1.27
0.12 M
6.0 0.3
4.4
0.40
+0.10
0.05
0.78 MAX.
0.05 MIN.
1.8 MAX.
1.44
0.8
0.5 0.2
0.15
+0.10
0.05
5.37 MAX.
0.10
1
4
8
5
1
: Source 1
2
: Gate 1
7, 8 : Drain 1
3
: Source 2
4
: Gate 2
5, 6 : Drain 2
EQUIVALENT CIRCUIT
(1/2 circuit)
Source
Body
Diode
Gate
Protection
Diode
Gate
Drain
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
5
5
5
5
5
5
Data Sheet G14329EJ1V0DS00
2
PA1764
ELECTRICAL CHARACTERISTICS (T
A
= 25 C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Drain to Source On-state Resistance
R
DS(on)1
V
GS
= 10 V, I
D
= 3.5 A
27
35
m
R
DS(on)2
V
GS
= 4.5 V, I
D
= 3.5 A
32
42
m
R
DS(on)3
V
GS
= 4.0 V, I
D
= 3.5 A
34
46
m
Gate to Source Cut-off Voltage
V
GS(off)
V
DS
= 10 V, I
D
= 1 mA
1.5
2.0
2.5
V
Forward Transfer Admittance
| y
fs
|
V
DS
= 10 V, I
D
= 3.5 A
5.0
9.0
S
Drain Leakage Current
I
DSS
V
DS
= 60 V, V
GS
= 0 V
10
A
Gate to Source Leakage Current
I
GSS
V
GS
= 20 V, V
DS
= 0 V
10
A
Input Capacitance
C
iss
V
DS
= 10 V
1300
pF
Output Capacitance
C
oss
V
GS
= 0 V
230
pF
Reverse Transfer Capacitance
C
rss
f = 1
MHz
110
pF
Turn-on Delay Time
t
d(on)
I
D
= 3.5 A
15
ns
Rise Time
t
r
V
GS(on)
= 10 V
69
ns
Turn-off Delay Time
t
d(off)
V
DD
= 30 V
65
ns
Fall Time
t
f
R
G
= 10
27
ns
Total Gate Charge
Q
G
I
D
= 7.0 A
29
nC
Gate to Source Charge
Q
GS
V
DD
= 48 V
3.6
nC
Gate to Drain Charge
Q
GD
V
GS
= 10 V
7.4
nC
Body Diode Forward Voltage
V
F(S-D)
I
F
= 7.0 A, V
GS
= 0 V
0.84
V
Reverse Recovery Time
t
rr
I
F
= 7.0 A, V
GS
= 0 V
40
ns
Reverse Recovery Charge
Q
rr
di/dt = 100 A
/
s
66
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
R
G
= 25
50
PG.
L
V
DD
V
GS
= 20
0 V
BV
DSS
I
AS
I
D
V
DS
Starting T
ch
V
DD
D.U.T.
TEST CIRCUIT 3 GATE CHARGE
TEST CIRCUIT 2 SWITCHING TIME
PG.
R
G
0
V
GS
D.U.T.
R
L
V
DD
= 1 s
Duty Cycle
1 %
V
GS
Wave Form
I
D
Wave Form
V
GS
10 %
90 %
V
GS
(on)
10 %
0
I
D
90 %
90 %
t
d(on)
t
r
t
d(off)
t
f
10 %
I
D
0
t
on
t
off
PG.
50
D.U.T.
R
L
V
DD
I
G
= 2 mA
5
PA1764
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confirm that this is the latest version.
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