1998
DATA SHEET
MOS INTEGRATED CIRCUIT
PD16337
64-BIT AC-PDP DRIVER
The
PD16337 is a high-voltage CMOS driver designed for flat display panels such as PDPs, VFDs and ELs. It
consists of a 64-bit bi-directional shift register (16 bit
4 circuits), 64-bit latch and high-voltage CMOS driver. The
logic block is designed to operate at 5-V power supply, enabling direct connection to a microcontroller. In addition,
the
PD16337 achieves low power dissipation by employing CMOS structure while having a high withstand voltage
output (150 V, 40 mA MAX.)
FEATURES
Built in four 16-bit bi-directional shift register circuits
Data control with transfer clock (external) and latch
High-speed data transfer (f
max.
= 20 MHz MIN. at cascade connection)
Wide operating temperature range (T
A
= 40 to +85
C)
High withstand output voltage (150 V, 40 mA MAX.)
5-V CMOS input interface
High withstand voltage CMOS structure
Capable of reversing all driver outputs by PC pin
ORDERING INFORMATION
Part Number
Package
PD16337GF-3BA
100-pin plastic QFP
Document No. S12363EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan
PD16337
2
BLOCK DIAGRAM
PC
BLK
LE
O
1
Note
S
64
S
61
S
62
S
63
S
64
L
64
S
1
S
2
S
3
S
4
LE
L
1
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A
1
A
2
B
2
A
3
B
3
A
4
B
4
A
1
SR1
S
1
CLK
CLK
S
5
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R/L
R/L
S
61
B
1
B
1
A
2
SR2
S
2
CLK
S
6
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R/L
S
62
B
2
A
3
SR3
S
3
CLK
S
7
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R/L
S
63
B
3
A
4
SR4
S
4
CLK
S
8
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R/L
S
64
B
4
SRn: 16-bit shift register
Note High withstand voltage CMOS driver, 150 V,
40 mA (MAX.)
PD16337
3
PIN CONFIGURATION (Top View)
100
O
42
O
41
O
40
O
39
O
38
O
37
O
36
O
35
O
34
O
33
O
32
O
31
O
30
O
29
O
28
O
27
O
26
O
25
O
24
O
23
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DD2
NC
V
SS2
NC
O
22
O
21
O
20
O
19
O
18
O
17
O
16
O
15
O
14
O
13
O
12
O
11
O
10
O
9
O
8
O
7
O
6
O
5
O
4
O
3
O
2
O
1
NC
V
DD2
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
NC
V
DD2
NC
V
SS2
NC
O
43
O
44
O
45
O
46
O
47
O
48
O
49
O
50
O
51
O
52
O
53
O
54
O
55
O
56
O
57
O
58
O
59
O
60
O
61
O
62
O
63
O
64
NC
V
DD2
NC
V
SS2
NC
CLK
LE
B
4
B
3
B
2
B
1
V
SS1
NC
R/L
V
DD1
A
1
A
2
A
3
A
4
PC
BLK
NC
V
SS2
31
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
100-pin plaxtic QFP
Cautions
1. Pin 40 is connected to the lead frame, and therefore must be left open.
2. Ensure that the V
DD1
, V
DD2
, V
SS1
and V
SS2
pins are all used, and that V
SS1
and V
SS2
are used
at the same potential.
3. To prevent latch up breakdown, the power should be turned on in the order V
DD1
, logic signal,
V
DD2
. It should be turned off in the opposite order.
PD16337
4
PIN DESCRIPTION
Symbol
Pin Name
Pin Number
Description
PC
Polarity change input
47
PC = L: All driver output invert
BLK
Blank input
48
BLK = H: All output = H or L
LE
Latch enable input
34
Automatically executes latch by setting High at rising edge
of the clock
A
1
to A
4
RIGHT data input/output
43 to 46
When R/L = H,
A
1
to A
4
: Input B
1
to B
4
: Output
B
1
to B
4
LEFT data input/output
38 to 35
When R/L = L,
A
1
to A
4
: Output B
1
to B
4
: Input
CLK
Clock input
33
Shift executed on fall
R/L
Shift control input
41
Right shift mode when R/L = H
SR
1
: A
1
S
1
S
61
B
1
(Same direction for SR
2
SR
4
)
Left shift mode when R/L = L
SR
1
: B
1
S
61
S
1
A
1
(Same direction for SR
2
SR
4
)
O
1
to O
64
High withstand voltage output
54 to 75, 81 to
130 V, 40 mA MAX.
100, 6 to 27
V
DD1
Power supply for logic block
42
5 V
10%
V
DD2
Power supply for driver block
2, 29, 52, 79
30 to 130 V
V
SS1
Logic GND
39
Connect to system GND
V
SS2
Driver GND
4, 31, 50, 77
Connect to system GND
NC
Non-connection
1, 3, 5, 28, 30,
Non-connection
32, 40, 49, 51,
Ensure that pin 40 is left open.
53, 76, 78, 80
PD16337
5
TRUTH TABLE 1 (Shift Register Block)
Input
Output
Shift Register
R/L
CLK
A
B
H
Input
Output
Note 1
Right shift execution
H
H or L
Output
Hold
L
Output
Note 2
Input
Left shift execution
L
H or L
Output
Hold
Notes 1. The data of S
57
, S
58
, S
59
, S
60
shifts to S
61
, S
62
, S
63
, S
64
and is output from B
1
, B
2
, B
3
, B
4
at the falling
edge of the clock, respectively.
2. The data of S
5
, S
6
, S
7
, S
8
shifts to S
1
, S
2
, S
3
, S
4
and is output from A
1
, A
2
, A
3
, A
4
at the falling edge of
the clock, respectively.
TRUTH TABLE 2 (Latch Block)
LE
CLK
Output State of Latch Block (L
n
)
H
Latch S
n
data and hold output data
Hold latch data
L
Hold latch data
TRUTH TABLE 3 (Driver Block)
L
n
BLK
PC
Output State of Driver Block
H
H
H (All driver outputs: H)
H
L
L (All driver outputs: L)
L
H
Output latch data (L
n
)
L
L
Output reversed latch data (L
n
)
: H or L, H: High level, L: Low level
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