MOS INTEGRATED CIRCUIT
PD16602
312-OUTPUT TFT-LCD FULL COLOR DRIVER
1998
Document No. S10671EJ1V0DS00 (1st edition)
Date Published August 1998 N CP(K)
Printed in Japan
DATA SHEET
The
PD16602 is a TFT-LCD source driver with full color display capability. It is ideal for 1024
768 pixel (XGA) class
high definition displays. The internal circuit consists of 12 channels (4
3) of analog input pins, 12 channels of 16-bit shift
registers and 312 channels of sample & hold circuits (2 latch type).
Analog display signals are sampled in 12 channels simultaneously by the sample & hold circuits and they are output in
the next line. The output voltage of the sample & hold circuits is as great as 10.5 V
P-P
and maintains high accuracy with an
output deviation of 20 mV
MAX
. Inputting analog display signals that been
-processed in the previous stage signal
processing circuit allows realization of a high definition 256-gray-scale-equivalent full color display without requiring line
inversion.
FEATURES
4
3 (RGB)-channel analog input allows display signal input wiring to be reduced.
High dynamic range (10.0 V
P-PMIN.
V
DD2
= 11.0 V)
High accuracy sample & hold circuits (output deviation; 20 mV
MAX.
, 5.0 mV
TYP.
)
High-speed sampling frequency (for both analog and digital; f
max.
=
20 MHz
MIN.
)
Low power control (reduction of output buffer bias current) function on chip
(operating power consumption; 82 mW
TYP.
, V
DD2
=
12.5 V)
Bi-directional data store function on chip
Corresponding to high-density mounting (slim TCP)
ORDERING INFORMATION
Part Number
Package
PD16602N-
TCP
5
PD16602
3. PIN DESCRIPTION
Pin Symbol
Pin Name
Description
S
1
to S
312
Driver outputs
Output pins for sampled analog image signals. When driven with V
DD2
=
12.5 V, a
11.5 V
P-P
analog voltage whose input/output characteristic is gain 1 is output.
CLK
Clock input
This pin reads the start pulse at the rising of CLK and starts sampling of analog
display signals in 12 channels simultaneously. The active edges of CLK are all
rising edges.
D
R0
to D
R3
D
G0
to D
G3
D
B0
to D
B3
Analog display
signal inputs
Analog image signal input pins. Please input analog display signals by inverting the
polarity for each display line.
R/L
Shift direction
switching input
The shift direction of the shift register is as follows.
R/L = H (right shift) ; SPR input, S
1
S
312
, SPL output
R/L = L (left shift)
; SPL input, S
312
S
1
, SPR output
SPR
Start pulse input/
output
R/L = H (right shift) ; start pulse input pin
R/L = L (left shift)
; start pulse output pin
SPL
Start pulse input/
output
R/L = H (right shift) ; start pulse output pin
R/L = L (left shift)
; start pulse input pin
PL/NL
Note
Polarity inversion
input
S/D = L; When PL/NL = H, Both odd number pin and even number pin samples
negative analog display signals and outputs positive analog signals from the
driver output.
When PL/NL = L, Both odd number pin and even number pin samples
positive analog display signals and outputs negative analog signals from the
driver output.
S/D = H; When PL/NL = H, Odd number pin samples negative analog display signals
and outputs positive analog signals from the driver output. Even number pin
samples positive analog display signals and outputs negative analog signals
from the driver output.
When PL/NL = L, Odd number pin samples positive analog display signals
and outputs negative analog signals from the driver output. Even number pin
samples negative analog display signals and outputs positive analog signals
from the driver output.
S/D
Arrangement
switching input
S/D = H; Complying with one side arrangement dot inverting.
S/D = L; Complying with both sides arrangement dot inverting.
HS
Note
Horizontal
synchronous input
This pin shuts off the output at the falling edge and then outputs analog display
signals at the rising. When HS = L, after the driver output pin goes to high impedance
this pin switches PL/NL and resets the internal hold capacity and output buffer to the
V
COM
level.
LPC
Low power control
input
This pin shuts off the output buffer low current supply and increases the output
impedance. The LPC = "H" mode allows the static current consumption to be
reduced by approximately 20 %.
BIAS
1
BIAS
2
Bias voltage inputs
These pins control the current consumption of the output buffer by applying a
stabilized external power supply.
V
DD1
Logic power supply
3.3 V
0.3 V
V
DD2(D)
Driver power supply
13.5 V
MAX.
V
DD2(A)
Driver power supply
13.5 V
MAX.
V
COM
Common power
supply
This pin applies the intermediate voltage of a stable LCD drive voltage from a voltage
follower, etc.
V
SS1
Logic ground
Logic ground
V
SS2(D)
Driver ground
High voltage block (level shifter)
V
SS2(A)
Driver ground
High voltage block (output buffer)
V
SS2(C)
Driver ground
High voltage block (sample & hold)
TEST
Test pin
"L" or left open
Note Sample & hold operation and reset operation of the output buffer capacitance and V
COM
level are performed
by the PL/NL and HS logic.
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