2002

MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD16878

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

DATA SHEET

Document No.

S15974EJ1V0DS00 (1st edition)

Date Published

February 2002 N CP(K)

Printed in Japan

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

DESCRIPTION

The

µPD16878 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET

output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional

driver ICs that use bipolar transistors.

Because the

µPD16878 controls a motor by inputting serial data, its package has been shrunk and the number of

pins reduced. As a result, the performance of the application set can be improved and the size of the set has been

reduced.

The

µPD16878 employs a current-controlled 64-step micro step driving method that drives stepper motor with low

vibration.

The

µPD16878 is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set.

The

µPD16878 can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.

FEATURES

· Four H bridge circuits employing power MOS FETs
· Current-controlled 64-step micro step driving
· Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input)

Data is input with the LSB first.

EVR reference setting voltage: 100 to 250 mV (@V

REF

= 250 mV) ... 4-bit data input (10-mV step)

Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step)

Original oscillation division or internal oscillation selectable

Number of pulses in 1 V

: 0 to 126 pulses ... 6 bits + 2-bit data input (2 pulses/step)

Step cycle: 0.25 to 8191.75

µs ... 15-bit data input (0.25- µs step)

· 3-V power supply. Minimum operating voltage: 2.7 V (MIN.)
· Low current consumption I

: 3.0 mA (MAX.), I

(RESET)

: 100

µA (MAX.), I

MO(RESET)

: 1.0

µA (MAX.)

· 38-pin plastic shrink SOP (7.62 mm (300))

ORDERING INFORMATION

Part number

Package

µPD16878GS-BGG

38-pin plastic shrink SOP (7.62 mm (300))

ta S

heet S

15974E

J1V

µ
µ
µ
µ

PD16878

BLOCK DIAGRAM

RESET

OSC

OUT

REF

x 2

SCLK

SDATA

LATCH

SERIAL-PARARELLE DECODER

PULSE GENERATER

EVR1

1/N

SELECTOR

FILTER

OSC

EVR2

CURRENT SET

EVR1

EVR2

CURRENT SET

EXTOUT SELECTOR

EXP0

EXP1

EXP2

EXP3

OSC

LGND

PGND

FIL

EXT

H BRIDGE

1ch

H BRIDGE

2ch

H BRIDGE

1ch

H BRIDGE

2ch

EXT

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

1. PIN FUNCTIONS

Pin No.

Symbol

Function

LGND

Control circuit GND pin

OSC

Chopping capacitor connection pin

FIL

1-ch filter capacitor connection pin (1000 pF TYP.)

FIL

2-ch filter capacitor connection pin (1000 pF TYP.)

FIL

1-ch filter capacitor connection pin (1000 pF TYP.)

FIL

2-ch filter capacitor connection pin (1000 pF TYP.)

REF

Reference voltage input pin (250 mV TYP.)

Control circuit supply voltage input pin

Output circuit supply voltage input pin

2-ch output pin

2-ch sense resistor connection pin

2-ch output pin

Output circuit supply voltage connection pin

1-ch output pin

1-ch sense resistor connection pin

1-ch output pin

EXP0

Output monitor pin (open drain)

EXP1

Output monitor pin (open drain)

EXP2

Output monitor pin (open drain)

PGND

Power circuit GND pin

EXP3

Output monitor pin (open drain)

EXT

Logic circuit monitor pin

Output circuit supply voltage input pin

1-ch output pin

1-ch sense resistor connection pin

1-ch output pin

Output circuit supply voltage input pin

2-ch output pin

2-ch sense resistor connection pin

2-ch output pin

EXT

Logic circuit monitor pin

Video sync signal input pin

LATCH

Latch signal input pin

SDATA

Serial data input pin

SCLK

Serial clock input pin

OSC

Original oscillation input pin (4 MHz TYP.)

OSC

OUT

Original oscillation output pin

RESET

Reset signal output pin

ta S

heet S

15974E

J1V

µ
µ
µ
µ

PD16878

3. E

LE
OF S

ANDARD CONNE

CTION

RESET

OSC

OUT

REF

SCLK SDATA LATCH

SERIAL-PARARELLE DECODER

PULSE GENERATER

EVR1

1/N

SELECTOR

FILTER

OSC

REGULATOR

EVR2

CURRENT SET

EVR1 EVR2

CURRENT SET

EXTOUT SELECTOR

EXP0 EXP1 EXP2 EXP3

OSC

LGND

PGND

FIL

MOTOR 1

MOTOR 2

EXT

H BRIDGE

1ch

H BRIDGE

2ch

H BRIDGE

1ch

H BRIDGE

2ch

CPU

250 mV
EVR : 1010
f

OSC

: 64 kHz

100 k

x 4

4 MHz

3.3 V

33 pF

BATTERY
4.8 to 11 V

6.8

x 2

1000 pF x 2

1000 pF

6.8

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

4. STANDARD CHARACTERISTICS CURVES

vs. T

Characteristics

MO (RESET)

vs. V

Characteristics

1.4

1.2

1.0

0.8

0.6

0.4

0.2

Total Power Dissipation P

(W)

Ambient Temperature T

(

°C)

100

120

125

°C/W

0.8

0.6

0.4

0.2

Output Circuit Supply Voltage V

(V)

OFF V

pin Current I

MO (RESET)

( A)

= 25

°C,

no load,
after reset

vs. V

Characteristics

Control Circuit Supply Volage V

(V)

pin Current I

(mA)

DD (RESET)

vs. V

Characteristics

200

150

100

Control Circuit Supply Volage V

(V)

pin Current at Reset State I

DD (RESET)

( A)

= 25

°C,

operating,

output open

, V

vs. V

Characteristics

0.8

0.6

0.4

0.2

Control Circuit Supply Volage V

(V)

Input Voltage V

, V

(V)

= 25

°C

= 25

°C,

after reset

vs. V

Characteristics

Input Voltage V

(V)

High-level/Low-level Input Current I

( A)

= 25

°C,

: V

= V

: V

= 0

20 40 60

10 0

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

OSC

vs. V

Characteristics

STEP

vs. V

Characteristics

150

140

130

120

110

100

Chopping Frequency f

OSC

(kHz)

Control Circuit Supply Voltage V

(V)

Control Circuit Supply Voltage V

(V)

Step Frequency f

STEP

(kHz)

= 25

°C,

OSC

= 100 pF

M (MAX)

vs. EVR Characteristics

100

150

200

250

300

Reference Setting Voltage EVR (mV)

Sine Wave Peak Output Current I

M (MAX)

(mA)

= 25

°C,

OSC

= 100 pF,

DATA: all high

, t

OFF

vs. V

Characteristics

500

400

300

200

100

Output Circuit Supply Voltage V

(V)

Turn-on Time, Turn-off Time t

OFF

(ns)

= 25

°C, V

= 6 V

Rs = 6.8

, f

OSC

= 64 kHz,

L = 25 mH/R = 100

at 1 kHz

REFVER

vs. V

Characteristics

Control Circuit Supply Voltage V

(V)

EVR Variable Voltage V

REFVER

(mV)

= 25

°C,

REF

= 250 mV

= 25

°C,

= 100 mA,

FIL

: none

OFF

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (f

CLK

= 4-MHz EXTERNAL CLOCK INPUT)

Input data consists of serial data (8 bytes x 8 bits).

Input serial data with the LSB first, from the 1st byte to 8th byte.

(1) Initial data (2) Standard data

<1st byte> <1st byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

HEADER DATA2

HEADER DATA1

HEADER DATA0

DATA selection

HEADER DATA0

DATA selection

1 or 0

EXP3

Hi-Z or L

1 or 0

EXP3

Hi-Z or L

1 or 0

EXP2

Hi-Z or L

1 or 0

EXP2

Hi-Z or L

1 or 0

EXP1

Hi-Z or L

1 or 0

EXP1

Hi-Z or L

1 or 0

EXP0

Hi-Z or L

1 or 0

EXP0

Hi-Z or L

Remark Hi-Z : High impedance,

L : Low level (current sink)

Remark Hi-Z : High impedance,

L : Low level (current sink)

<2nd byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

1 or 0

ROTATION

ch CCW/CW

1 or 0

ENABLE

ch ON/OFF

8-bit data

input

Note

First Point Wait

Start point wait

µs to 2.04 ms

Setting

(1 to 255)

t = 8

µs

6-bit data

input

Pulse Number

Number of

pulses in 1 VD

Setting (0 to 63)

n = 2 pulses

Note

Note Input other than "0".

Note The number of pulses can be varied in 2-pulse

steps.

<3rd byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

8-bit data

input

Note

First Point

Magnetize Wait

Start point drive

wait

µs to 2.04 ms

Setting

(1 to 255)

t = 8

µs

15-bit data

Low-order

8-bit data

input

Pulse Width

ch pulse

cycle

0.25 to 8191.75

µs

Setting

(1 to 32767)

t = 0.25

µs

Note Input other than "0".

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

<4th byte> <4th byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

1 or 0

OSCSEL

Internal/external

1 or 0

Current Set

set2/set1

5-bit data

input

Chopping

Frequency

Chopping

frequency :

32 to 124 kHz

Setting

(8 to 31)

Note

f = 4 kHz

15-bit data

High-order

7-bit data

input

Pulse Width

pulse cycle :

0.25 to 8191.75

µs

Setting

(1 to 32767)

t = 0.25

µs

Note The frequency is 0 kHz if 0 to 7 is input.

<5th byte>

Bit

Data

EXT

Bit

Data

Function

Setting

1 or 0

ROTATION

ch CCW/CW

Note 5

ENABLE

Note1

ENABLE

Note1

1 or 0

ENABLE

ch ON/OFF

Note 5

ROTATION

Note2

ROTATION

Note2

Note 5

Pulse Out

Note 5

FF7

Note 5

FF3

Note 5

Checksum

Note3

FF2

Note 5

Chopping

Note4

FF1

6-bit data

input

Pulse Number

Number of

pulses in 1 VD

Setting (1 to 63)

n = 2 pulses

Note

Notes 1. H level : Conducts, L level : Stops

2. H level : Reverse (CCW),

L level : Forward (CW)

3. H level : Normal data input,

L level : Abnormal data input

4. Not output in internal oscillation mode.

5. Select one of D0 to D6 and input "1".

If two or more of D0 to D6 are selected,

they are positively ORed for output.

Note The number of pulses can be varied in 2-pulse

steps.

<6th byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

4-bit data

input

Current Set2

ch Output current

setting 2

EVR : 100

to 250 mV

Setting (0 to 15)

Note

4-bit data

input

Current Set1

ch Output current

setting 1

EVR : 100

to 250 mV

Setting (0 to 15)

Note

15-bit data

Low-order

8-bit data

input

Pulse Width

ch pulse

cycle:

0.25 to 8191.75

µs

Setting

(1 to 32767)

t = 0.25

µs

Note A voltage of about double EVR is output to

the FIL pin.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

<7th byte> <7th byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

1 or 0

Current Set

set2/set1

4-bit data

input

Current Set2

ch Output

current setting 2

EVR: 100 to 250 mV

Setting (0 to 15)

Note

4-bit data

input

Current Set1

ch Output

current setting 1

EVR: 100 to 250 mV

Setting (0 to 15)

Note

15-bit data

High-order

7-bit data

input

Pulse Width

ch pulse

cycle:

0.25 to 8191.75

µs

Setting

(1 to 32767)

t = 0.25

µs

Note A voltage of about double EVR is output to

the FIL pin.

<8th byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

1 or 0

Checksum

Note

1 or 0

Checksum

Note

Note Data is input so that the sum of the 1st

through the 8th bytes is 00H.

Note Data is input so that the sum of the 1st

through the 8th bytes is 00H.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Data Configuration

Data can be input in either of two ways. Initial data can be input when the power is first applied, or standard data

can be input during normal operation. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the 1st

byte. Therefore, the D7 bit of the 8th byte is the most significant bit (MSB).

When inputting initial data, set a start point wait time that specifies the delay from power application to pulse

output, and the start point drive wait time. At the same time, also set a chopping frequency and a reference voltage

(EVR) that determines the output current of each channel. Because the

µPD16878 has an EXT pin for monitoring the

internal operations, the parameter to be monitored can be selected by initial data.

When inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for

the pulse cycle.

Initial data or standard data is selected by using bits D5 to D7 of the 1st byte (see Table 5-1).

Table 5-1. Data Selection Mode (1st byte)

Data type

Initial data

Standard data

Remark If the high-order three bits are high, the initial data is selected;

if they are low, the standard data is selected.

Data other than (0, 0, 0) and (1, 1, 1) must not be input.

Input the serial data during start point wait time.

Details of Data Configuration

How to input initial data and standard data is described below.

(1) Initial data input

<1st byte>

The 1st byte specifies the type of data (initial data or standard data) and determines the presence or absence of

the EXP pin output. Bits D5 to D7 of this byte specify the type of data as shown in Table 5-1, while bits D0 to D3

select the EXP output (open drain).

Table 5-2. 1st Byte Data Configuration

Bit

Data

0 or 1

The EXP pin goes low (current sink) when the input data is "0", and high (high impedance state) when the input

data is "1". Pull this pin up to V

for use. Input "0" to bit D4.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

<2nd byte>

The 2nd byte specifies the delay between data being read and data being output. This delay is called the start up

wait time, and the motor can be driven from that point at which the start up wait time is "0". This time is counted at the

rising edge of V

. The start up wait time can be set to 2.04 ms (when a 4-MHz clock is input), and can be fine-tuned

by means of 8-bit division (8-

µs step: with 4-MHz clock). The start up wait time is set to 2.04 ms when all the bits of

the 2nd byte are set to "1".

Caution Always input data other than "0" to this byte because the start up wait time is necessary for

latching data. If "0" is input to this byte, data cannot be updated. Transfer standard data during the

start up wait time.

<3rd byte>

The 3rd byte specifies the delay between the start point wait time being cleared and the output pulse being

generated. This time is called the start up drive wait time, and the output pulse is generated from the point at which

the start up drive wait time reaches "0". The start up drive wait time is counted at the falling edge of the start up wait

time. The start up drive wait time can be set to 2.04 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit

division (8

µs step: with 4-MHz clock). The start up drive wait time is set to 2.04 ms when all the bits of the 3rd byte

are "1".

Caution Always input data other than "0" to this byte because the start up drive wait time is necessary for

latching data. If "0" is input to this byte, data cannot be updated.

<4th byte>

The 4th byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is

created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping

frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this

bit is "0", the original oscillation (external clock input to OSC

) is used; when it is "1", the internal oscillator is used.

Bits D5 and D6 are fixed to "0".

The chopping signal is output after the initial data has been input and the first standard data has been latched

(see Timing Chart).

Table 5-3. 4th Byte Data Configuration (Initial data)

Bit

Data

0 or 1

The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows.

Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the low-

order 2 bits fixed to 0).

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Bit

Data

0 or 1

OSC

= 0 kHz

Bit

Data

0 or 1

OSC

= 0 kHz

Bit

Data

0 or 1

OSC

= 32 kHz

Bit

Data

0 or 1

OSC

= 36 kHz

Bit

Data

0 or 1

OSC

= 124 kHz

<5th byte>

The 5th byte selects a parameter to be output to the EXT pin (logic operation monitor pin). Input data to bits D0 to

D6 of this byte. Bit D7 is fixed to "0".

There are two EXT pins. EXT

indicates the operating status of

ch, and EXT

indicates that of

ch. The

relationship between each bit and each EXT pin is as shown in Table 5-4.

Table 5-4. 5th Byte Data Configuration (Initial data)

Bit

Data

EXT

Not used

0 or 1

ENABLE

0 or 1

ROTATION

0 or 1

PULSEOUT

0 or 1

FF7

0 or 1

FF3

0 or 1

CHECKSUM

FF2

0 or 1

CHOPPING

FF1

The checksum bit is cleared to "0" in the event of an error. Normally, it is "1".

If two or more signals that output signals to EXT

and EXT

are selected, they are positively ORed for output.

Caution The CHOPPING signal is not output in internal oscillation mode.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Remark

The meanings of the symbols listed in Table 5-4 are as follows:

ENABLE : Output setting (H : Conducts, L : Stops)

ROTATION : Rotation direction (H : Reverse (CCW), L : Forward (CW))

PULSEOUT : Output pulse signal

FF7 : Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in

standard data.)

FF3 : Pulse gate (output while pulse exists)

FF2 : Outputs H level during start up wait time + start up drive wait time

FF1 : Outputs H level during start up wait time

CHECKSUM : Checksum output (H : when normal data is transmitted,

L : when abnormal data is transmitted)

CHOPPING : Chopping wave output (in original oscillation mode only)

<6th byte>

The 6th byte sets the peak output current value of

ch. The output current is determined by the EVR reference

voltage.

The 250-mV (TYP.) voltage input from an external source to the V

REF

pin is internally doubled and input to a 4-bit

D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within the

range of 200 to 500 mV, in units of 20 mV.

The

µPD16878 can set two values of the EVR reference voltage in advance. This is done by using bits D0 to D3

or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in

the standard data.

If all the bits of the 6th byte are "0", the EVR reference voltage of 200 mV is selected; if they are "1", the EVR

reference voltage of 500 mV is selected.

Table 5-5. 6th Byte Data Configuration (Initial data)

Bit

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR

)

Bits D0 to D3 : Reference voltage 1 (EVR

)

<7th byte>

The 7th byte specifies the peak output current value of

ch. The output current is determined by the EVR

reference voltage.

The 250-mV (TYP.) voltage input from an external source to the V

REF

pin is internally doubled and input to a 4-bit

D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within a range

of 200 to 500 mV, in units of 20 mV.

The

µPD16878 can set two values of the EVR reference voltage in advance. This is done using bits D0 to D3 or

D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in the

standard data.

If all the bits of the 7th byte are "0", the EVR reference voltage of 200 mV is selected; if they are "1", the EVR

reference voltage of 500 mV is selected.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Table 5-6. 7th Byte Data Configuration (Initial data)

Bit

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR

)

Bits D0 to D3 : Reference voltage 1 (EVR

)

<8th byte>

The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.

If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the

checksum output pin (EXT pin) is kept "L".

(2) Standard data input

<1st byte>

The 1st byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is

input.

Table 5-7. 1st Byte Data Configuration

Bit

Data

0 or 1

The EXP pin goes low (current sink) when the input data is "0", and high (high impedance state) when the input

data is "1". Input "0" to bit D4.

<2nd byte>

The 2nd byte specifies the rotation direction of the

channel, enables output of the channel, and the number of

pulses (126 pulses MAX.) during the 1V

period (in 1 cycle of FF2) of the

channel.

Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is

"0"; it is in the reverse direction (CCW mode) when the bit is "1".

Bit D6 is used to enable the output of the

channel. The channel enters the high impedance state when this bit

is "0"; it is in conduction mode when the bit is "1".

The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit

uses an 8-bit counter with the low-order two bits fixed to "0". Therefore, the number of pulses that is actually

generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x

2. The number of

pulses can be set to a value in the range of 0 to 126, in units of 2 pulses.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Table 5-8. 2nd Byte Data Configuration (Standard data)

Bit

Data

0 or 1

Rotation direction ENABLE Number of pulses

<3rd and 4th bytes>

The 3rd and 4th bytes select the pulse cycle of the

channel and which of the two reference voltages, created in

the initial mode, is to be used (CURRENT SET

The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 3rd byte, and bits D0 to D6

(most significant bit) of the 4th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75

µs in units

of 0.25

µs (with a 4-MHz clock).

CURRENT SET

is specified by bit D7 of the 4th byte. When this bit is "0", reference voltage 1 (EVR

) is

selected; when it is "1", reference voltage 2 (EVR

) is selected. For further information, refer to the description of the

6th byte of the initial data.

Table 5-9. 4th Byte Data Configuration (Standard data)

Table 5-10. 3rd Byte Data Configuration (Standard data)

Bit

Data

0 or 1

CURRENT SET

Most significant

bit

Least significant bit

(Reference) 6th Byte Data Configuration for Initial Data

Bit

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR

)

Bits D0 to D3 : Reference voltage 1 (EVR

)

<5th byte>

The 5th byte specifies the rotation direction of the

channel, enables output of the channel, and the number of

pulses (126 pulses MAX.) during the 1V

period (in one cycle of FF2) of the

channel.

Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is

"0"; it is in the reverse direction (CCW mode) when the bit is "1".

Bit D6 is used to enable the output of the

channel. The channel goes into a high impedance state when this bit

is "0"; it is in the conduction mode when the bit is "1".

The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit

uses an 8-bit decoder with the low-order two bits fixed to "0". Therefore, the number of pulses that is actually

generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x

2. The number of

pulses can be set in a range of 0 to 126 and in units of 2 pulses.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Table 5-11. 5th Byte Data Configuration (Standard data)

Bit

Data

0 or 1

Rotation direction ENABLE Number of pulses

<6th and 7th bytes>

The 6th and 7th bytes select the pulse cycle of the

channel and which of the two reference voltages, created in

the initial mode, is to be used (CURRENT SET

The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 6th byte, and bits D0 to D6

(most significant bit) of the 7th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75

µs in units

of 0.25

µs (with a 4-MHz clock).

CURRENT SET

is specified by bit D7 of the 7th byte. When this bit is "0", reference voltage 1 (EVR

) is

selected; when it is "1", reference voltage 2 (EVR

) is selected. For further information, refer to the description of the

7th byte of the initial data.

Table 5-12. 7th Byte Data Configuration (Standard data)

Table 5-13. 6th Byte Data Configuration (Standard data)

Bit

Data

0 or 1

CURRENT SET

Most significant bit

Least significant bit

(Reference) 7th Byte Data Configuration for Initial Data

Bit

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR

)

Bits D0 to D3 : Reference voltage 1 (EVR

)

<8th byte>

The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.

If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the

checksum output pin (EXT pin) is held at "L".

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

(Data Update Timing)

The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product

are set and updated at the following latch timing.

Table 5-14. Data Update Timing

ENABLE change

Pulse width

FF2

Number of pulses

FF2

Rotation direction

FF2

Current setting

FF2

FF1

FF2

ENABLE

FF2

FF1

FF2

The timing at which data is to be updated differs, as shown in Table 5-14, depending on the enabled status.

For example, suppose the enable signal is currently "0" (output high impedance) and "1" (output conduction) is

input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at

FF2(upon the completion of start up wait), and the current setting and ENABLE signals are updated at FF1 (upon

completion of start up drive wait).

FF1

Start up wait

FF2

Start up wait +

start up drive wait

Pulse output

LATCH

Pulse width, number of pulses, and rotation direction
are updated.

Current setting and ENABLE are updated
(ENABLE change: 0 to 1).

Initial data
identification

(1)

(2)

(3)

Standard data
identification

I1 data is output.

FF1, FF2 output

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

(1)

(2)

(3)

Pulse width

Internal data retained.

Output reset

Not output

Rotation direction

Internal output retained

Not output

Number of pulses

Internal data retained.

Output reset

Not output

Updated to S2 data at FF2

Current setting

Internal output retained

Not output

ENABLE

Internal output retained

Not output

Updated to S2 data at either FF1 or FF2

by enable data of (2)

The initial mode of this product is as follows.

The IC operation can be initialized as follows:

(1) Turns ON V

(2) Make RESET input "L".

(3) Input serial initial data.

In initial mode, the operating status of the IC is as shown in Table 5-15.

Table 5-15. Operations in Initial Mode

Item

Specifications

Current consumption

100

µA

OSC

Oscillation stops.

Input of external clock is inhibited.

Input inhibited.

FF1 to FF7

"L" level

PULSE OUT

"L" level

EXP0 to EXP3

Undefined in the case of (1) above.

Previous value is retained in the case of (2) above.

Can be updated by serial data in the case of (3) above.

Serial operation

Can be accessed after initialization in the case of (1) above.

Can be accessed after RESET has gone "H" in the case of (2) above.

Can be accessed in the case of (3) above.

Step pulse output is inhibited and FF7 is made "L" if the following conditions are satisfied.

(1) If the set number of pulses (2nd/5th: standard data) is 00H.

(2) If the checksum value is other than 00H.

(3) If the start up wait time is set to 1 V

or longer.

(4) If the start up wait time + start up drive wait time is set to 1 V

or longer.

(5) If start up wait is completed earlier than LATCH (

(6) If V

is not input.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

Cautions on Correct Use

(1) With this product, input the data for start up wait and start up drive wait. Because the standard data are

set or updated by these wait times, if the start up wait time and start up drive wait time are not input, the

data are not updated.

(2) The start up wait time must be longer than LATCH.

(3) If the rising of the start up drive wait time is the same as the falling of the last output pulse, a count error

occurs, and the IC may malfunction.

(4) Input the initial data in a manner that it does not straddle the video sync signal (V

). If it does, the initial

data is not latched.

(5) Transmit the standard data during the start up wait time (FF1). If it is input at any other time, the data

may

not be transmitted correctly.

(6) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the

minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to

prevent the leakage of noise from the output circuit.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

6. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25°C)

Parameter

Symbol

Condition

Rating

Unit

0.5 to +6.0

Supply voltage

0.5 to +11.2

Input voltage

0.5 to V

+ 0.5

Reference voltage

REF

500

H bridge drive current

Note 1

M(DC)

±150

mA/phase

Instantaneous H bridge drive

current

Note 1

M(pulse)

10 ms, Duty 5%

±300

mA/phase

Power consumption

Note 2

1.0

Peak junction temperature

CH(MAX.)

150

°C

Storage temperature

stg

55 to +150

°C

Notes 1. Permissible current per phase with the IC mounted on a PCB.

2. When the IC is mounted on a glass epoxy PCB (10 cm x 10 cm x 1 mm).

Caution

If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,

specify the values exceeding which the product may be physically damaged. Be sure to use the

product within the range of the absolute maximum ratings.

Recommended Operating Range

Parameter

Symbol

MIN.

TYP.

MAX.

Unit

2.7

5.5

Supply voltage

4.8

Input voltage

+ 0.4

Reference voltage

REF

225

250

275

EXP pin input voltage

EXPIN

EXP pin input current

EXPIN

100

µA

H bridge drive current

M(DC)

-100

+100

H bridge drive current

M(pulse)

Note 1

-200

+200

Clock frequency (OSC

)

CLK

Note 2

3.9

5.0

MHz

Clock frequency amplitude

fCLK

Note 2

0.7 V

Serial clock frequency (SCLK)

SCLK

5.0

MHz

Video sync signal width

(VD)

Note 3

250

LATCH signal wait time

(VD-LATCH)

Note 4

400

SCLK wait time

(SCLK-LATCH)

Note 4

400

SDATA setup time

setup

Note 4

SDATA hold time

hold

Note 4

Chopping frequency

OSC

Note 3

124

kHz

Reset signal pulse width

RST

100

µs

Operating temperature

-10

+85

°C

Peak junction temperature

CH(MAX.)

125

°C

Notes 1. PW

10 ms, duty 5%

2. C

OSC

= 33 pF, V

REF

= 250 mV

3. f

CLK

= 4 MHz

4. Serial data delay time(see the figure on the next page.)

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

ELECTRICAL CHARACTERISTICS

DC Characteristics (Unless otherwise specified, V

= 3.3 V, V

= 6.0 V, V

REF

= 250 mV, T

= 25°C, f

CLK

= 4 MHz,

OSC

= 33 pF, C

FIL

= 1000 pF, EVR = 100 mV (0000))

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Off V

pin current

MO(RESET)

No load, reset period

1.0

µA

pin current

Output open

3.0

pin current

DD(RESET)

Reset period

100

µA

High level input voltage

0.7 V

Low level input voltage

0.3 V

Input hysteresis voltage

LATCH, SCLK, SDATA, V

RESET, OSC

300

(H)

, V

(H)

5th byte

0.9 V

Monitor output voltage 1

(EXT

)

(L)

, V

(L)

5th byte

0.1 V

OEXP(H)

Pull up (V

)

Monitor output voltage 2

(EXP0 to EXP3 : open drain)

OEXP(L)

OEXP

= 100

µA

0.1 V

High level input current

= V

0.06

Low level input current

= 0 V

-1.0

µA

Reset pin high level input

current

IH(RST)

RST

= V

1.0

µA

Reset pin low level input

current

IL(RST)

RST

= 0

-1.0

µA

Input pull down resistor

IND

LATCH, SCLK, SDATA, V

200

H bridge ON resistance

Note 1

= 100 mA

3.5

5.0

OSC(1)

DATA: 00000 (4th byte)

Chopping frequency (internal

oscillation: C

OSC

= 100 pF)

OSC(2)

DATA: 11111 (4th byte)

100

124

150

kHz

Step frequency

STEP

Minimum step

kHz

delay time

Note 2

250

Sine wave peak output

current

Note 3

L = 25 mH/R = 100

(1 kHz)

EVR = 200 mV (1010)

= 6.8

, f

OSC

= 64 kHz

FIL pin voltage

Note 4

EVR

EVR = 200 mV (1010)

370

400

430

FIL pin step voltage

Note 4

EVRSTEP

Minimum step

AC Characteristics (Unless otherwise specified, V

= 3.3 V, V

= 6.0 V, T

= 25°C, f

CLK

= 4 MHz)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

H bridge output circuit turn on

time

ONH

= 100 mA

Note 5

1.0

2.0

µs

H bridge output circuit turn off

time

OFFH

= 100 mA

Note 5

1.0

2.0

µs

Notes 1. Total of ON resistance at top and bottom of output H bridge

2. By OSC

and V

sync circuit

3. FB pin is monitored.

4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.

5. 10 to 90% of the pulse peak value without filter capacitor (C

FIL

)

ta S

heet S

15974E

J1V

µ
µ
µ
µ

PD16878

TIMING CHART (1

)

Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low

to high, and at the falling edge of FF2 when the level changes from high

to low.

2. FF7 is an output signal that is used to check for the presence or absence

of a pulse in the standard data, is updated at the rising edge of LATCH

and reset once at the falling edge of LATCH. If CHECK SUM is other than

"00H", FF7 goes low, inhibiting pulse output, even if a pulse is generated.

3. CHECK SUM output is updated at the rising edge of LATCH.

RESET

LATCH

DATA

OSC

OUT

(original oscillation)

Start point wait

(FF1)

Start point wait +

start point drive wait

(FF2)

ENABLE OUT

Note 1

Chopping pulse

EXP0 to EXP3

PULSE OUT

PULSE GATE

(FF3)

PULSE CHECK

Note 2

(FF7)

CHECK SUM

Note 3

SCLK

SDATA

1st byte

8th byte

Initialization

Initial

Standard

Dummy data

EXP: 1

EXP : 0
ENABLE: 0

EXP : 1
ENABLE: 1

Standard

EXP : 0
ENABLE: 1

Standard

EXP : 1
ENABLE: 0

Standard

EXP : 1
error DATA

Input at rising
edge of RESET

Output by
I1 data

Output by chopping
setting of I1 data

Output by EXP
setting of I1 data

Output by EXP
setting of S1 data

Output by EXP
setting of S2DATA

Output by
I1 data

Output by S2
data setting

Output by S5
data setting

DATA output

Pulse error

Enable

DATA output

Outputs high level while
pulse is being generated

Outputs high level for standard data while a
pulse output signal exists (LATCH cycle)

High level because
data is normal.

Low level because
data is abnormal.

Restore to high level because
data is normal.

No pulse output because
data is erroneous

(LSB)

Data is held at rising edge of SCLK.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

TIMING CHART (2)

H bridge ,

1ch output status

H bridge ,

2ch output status

(CW mode)

MOB

CLK

(PULSE OUT)

CLK

PULSE OUT

H bridge

1ch output status

H bridge

2ch output status

Position No.

CCW

Current direction: A1

Current direction: B1

CW mode

CCW mode

CW mode

Current direction: A2

Current direction: B2

In CW mode

In CCW mode

(Expanded view)

Notes1.

: Position No. is incremented.

: Position No. is decremented.

Note1

Note2

Remarks 1. The current value of the actual wave is approximated to the value shown on the next page.

2. The C

, C

, D

, and D

pins of

channel correspond to the A

, A

, B

, and B

pins of

channel.

3. The CW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is "0".

4. The CCW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is "1".

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

RELATION BETWEEN ROTATION ANGLE, PHASE CURRENT, AND VECTOR QUANTITY

(64-DIVISION MICRO STEP)

(Values of

µ
µ
µ
µPD16878 for reference)

Step

Rotation angle (

)

A phase current

B phase current

Vector quantity

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

TYP.

100

5.6

2.5

9.8

17.0

100

100.48

11.3

12.4

19.5

26.5

93.2

98.1

103

100

16.9

22.1

29.1

36.1

90.7

95.7

100.7

100.02

22.5

31.3

38.3

45.3

87.4

92.4

97.4

100.02

28.1

40.1

47.1

54.1

83.2

88.2

93.2

99.99

33.8

48.6

55.6

62.6

78.1

83.1

88.1

99.98

39.4

58.4

63.4

68.4

72.3

77.3

82.3

99.97

65.7

70.7

75.7

65.7

70.7

75.7

99.98

50.6

72.3

77.3

82.3

58.4

63.4

68.4

99.97

56.3

78.1

83.1

88.1

48.6

55.6

62.6

99.98

61.9

83.2

88.2

93.2

40.1

47.1

54.1

99.99

67.5

87.4

92.4

97.4

31.3

38.3

45.3

100.02

73.1

90.7

95.7

100.7

22.1

29.1

36.1

100.02

78.8

93.2

98.1

103

12.4

19.5

26.5

100

84.4

100

2.5

9.8

17.0

100.48

100

Remark These data do not indicate guaranteed values.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

8. RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below. If other

soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult

with our sales offices.

For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"

(C10535E).

Type of Surface Mount Device

µ
µ
µ
µPD16878GS-BGG: 38-pin plastic shrink SOP (7.62 mm (300))

Process

Soldering conditions

Symbol

Infrared Ray Reflow

Peak temperature: 235°C or below (Package surface temperature),

Reflow time: 30 seconds or less (at 210°C or higher),

Maximum number of reflow processes: 3 time or less,

Number of days: None

Note

Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is

recommended.

IR35-00-3

Vapor Phase Soldering

Peak temperature: 215°C or below (Package surface temperature),

Reflow time: 40 seconds or less (at 200°C or higher),

Maximum number of reflow processes: 3 time or less,

Number of days: None

Note

Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is

recommended.

VP15-00-3

Wave Soldering

Solder temperature: 260°C or below, Flow time: 10 seconds or less,

Maximum number of flow processes: 1 time,

Pre-heating temperature: 120°C or below (Package surface temperature),

Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is

recommended.

WS60-00-1

Partial Heating Method

Pin temperature: 300°C or below,

Heat time: 3 seconds or less (Per each side of the device).

Note Number of days the device can be stored after the dry pack has been opened, at conditions of 25°C, 65%RH.

Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the

device will be damaged by heat stress.

Data Sheet S15974EJ1V0DS

µ
µ
µ
µPD16878

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

µ
µ
µ
µPD16878

M8E 00. 4

The information in this document is current as of January, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD16878GS-BGG

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD16878GS-BGG