Document Outline

• COVER
• FEATURE
• ORDERING INFORMATION
• uPD17005 FUNCTION OUTLINE
• PIN CONFIGURATION (Top View)
• 1. PIN FUNCTIONS
  • 1.1 EXPLANATION ON EACH PIN FUNCTION
  • 1.2 NOTES ON USING A GENERAL PURPOSE PORT
  • 1.3 PIN EQUIVALENT CIRCUITS
• 2. BLOCK DIAGRAM
• 3. PROGRAM MEMORY (ROM)
  • 3.1 STRUCTURE OF PROGRAM MEMORY
  • 3.2 PROGRAM MEMORY FUNCTIONS
  • 3.3 PROGRAM FLOW
  • 3.4 PROGRAM BRANCHING
  • 3.5 SUBROUTINE
  • 3.6 TABLE REFERENCING
  • 3.7 NOTES ON USING A BRANCHING INSTRUCTION AND A SUBROUTINE CALLL INSTRUCTION
• 4. PROGRAM COUNTER (PC)
  • 4.1 STRUCTURE OF A PROGRAM COUNTER
  • 4.2 FUNCTIONS OF A PROGRAM COUNTER
  • 4.3 NOTES ON PROGRAM COUNTER OPERATION
• 5. STACK
  • 5.1 STRUCTURE OF STACK
  • 5.2 FUNCTIONS OF A STACK
  • 5.3 STACK POINTER (SP)
  • 5.4 ADDRESS STACK REGISTER (ASR)
  • 5.5 INTERRUPT STACK REGISTER
  • 5.6 STACK OPERATION AT EXECUTION OF EACH STATEMENT (SUBROUTINE, TABLE REFERENCE, AND INTERRUPT)
  • 5.7 STACK NESTING LEVEL, PUSH INSTRUCTION, AND POP INSTRUCTION
• 6. DATA MEMORY (RAM)
  • 6.1 STRUCTURE OF DATA MEMORY
  • 6.2 FUNCTIONS OF DATA MEMORY
  • 6.3 NOTES ON USING DATA MEMORY
• 7. GENERAL REGISTER (GR)
  • 7.1 STRUCTURE OF A GENERAL REGISTER
  • 7.2 FUNCTION OF A GENERAL REGISTER
  • 7.3 GENERAL REGISTER IN EACH INSTRUCTION AND DATA MEMORY ADDRESS GENERATION AND OPERATION
  • 7.4 NOTES ON USING A GENERAL REGISTER
• 8. ALU (ARITHMETIC LOGIC UNIT) BLOCK
  • 8.1 STRUCTURE OF AN ALU BLOCK
  • 8.2 FUNCTION OF AN ALU BLOCK
  • 8.3 ARITHMETIC OPERATION (ADDITION AND SUBTRACTION IN BINARY MODE OR DECIMAL MODE)
  • 8.4 LOGICAL OPERATION
  • 8.5 BIT CHECKING
  • 8.6 COMPARISON CHECKING
  • 8.7 ROTATION PROCESSING
• 9. SYSTEM REGISTER (SYSREG)
  • 9.1 STRUCTURE OF A SYSTEM REGISTER
  • 9.2 FUNCTION OF A SYSTEM REGISTER
  • 9.3 ADDRESS REGISTER (AR)
  • 9.4 WINDOW REGISTER (WR)
  • 9.5 BANK REGISTER (BANK)
  • 9.6 INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP: MEMORY POINTER)
  • 9.7 GENERAL REGISTER POINTER (RP)
  • 9.8 PROGRAM STATUS WORD (PSWORD)
  • 9.9 NOTES ON USING SYSTEM REGISTERS
• 10. REGISTER FILE (RF)
  • 10.1 STRUCTURE OF A REGISTER FILE
  • 10.2 FUNCTION OF A REGISTER FILE
  • 10.3 CONTROL REGISTER
  • 10.4 NOTES ON USING A REGISTER FILE
• 11. DATA BUFFER (DBF)
  • 11.1 STRUCTURE OF A DATA BUFFER
  • 11.2 FUNCTION OF A DATA BUFFER
  • 11.3 DATA BUFFER AND TABLE REFERENCE
  • 11.4 BUFFER DATA AND PERIPHERAL HARDWARE
  • 11.5 NOTES ON USING DATA BUFFERS
• 12. INTERRUPT
  • 12.1 STRUCTURE OF AN INTERRUPT BLOCK
  • 12.2 INTERRUPT FUNCTION
  • 12.3 INTERRUPT ACCEPTANCE OPERATION
  • 12.4 OPERATION AFTER ACCEPTANCE OF INTERRUPT
  • 12.5 RETURN PROCESSING FROM AN INTERRUPT PROCESSING ROUTINE
  • 12.6 INTERRUPT PROCESSING ROUTINE
  • 12.7 EXTERNAL (INT0 PIN AND INT1 PIN) INTERRUPT
  • 12.8 INTERNAL (TIMER, SERIAL INTERFACE 1, FREQUENCY COUNTER) INTERRUPT
  • 12.9 MULTIPLE INTERRUPT
  • 12.10 NOTES ON USING INTERRUPT
• 13. TIMER FUNCTION
  • 13.1 CONFIGURATION
  • 13.2 FUNCTIONS
  • 13.3 TIMER CARRY FLIP-FLOP
  • 13.4 CAUTIONS WHEN USING TIMER CARRY FLIP-FLOP
  • 13.5 TIMER INTERRUPT
  • 13.6 CAUTIONS DURING TIMER INTERRUPT
• 14. STANDBY
  • 14.1 STANDBY BLOCK CONFIGURATION
  • 14.2 STANDBY FUNCTIONS
  • 14.3 DEVICE OPERATING MODE USING CE PIN
  • 14.4 HALT FUNCTIONS
  • 14.5 CLOCK STOP FUNCTION
  • 14.6 DEVICE OPERATION IN HALT AND CLOCK STOP MODES
  • 14.7 POWER CONSUMPTION IN HALT AND CLOCK STOP MODES
• 15. RESET
  • 15.1 RESET BLOCK CONFIGURATION
  • 15.2 RESET FUNCTION
  • 15.3 CE RESET
  • 15.4 POWER ON RESET
  • 15.5 RELATION BETWEEN CE RESET AND POWER ON RESET
  • 15.6 POWER FAILURE DETECTION
• 16. PLL FREQUENCY SYNTHESIZER
  • 16.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION
  • 16.2 PLL FREQUENCY SYNTHESIZER FUNCTIONS
  • 16.3 INPUT SELECTION CIRCUIT AND PROGRAMMABLE DIVIDER
  • 16.4 REFERENCE FREQUENCY GENERATOR
  • 16.5 PHASE COMPARATOR (PHI-DET), CHARGE PUMP, AND UNLOCK DETECTOR CIRCUIT
  • 16.6 LOW-PASS FILTER OPERATIONAL AMPLIFIER
  • 16.7 PLL DISABLE MODE
  • 16.8 USE OF PLL FREQUENCY SYNTHESIZER
  • 16.9 STATE DURING RESET
• 17. GENERAL-PURPOSE PORT
  • 17.1 GENERAL-PURPOSE PORT CONFIGURATION AND FUNCTIONS
  • 17.2 GENERAL-PURPOSE PORT FUNCTIONS
  • 17.3 GENERAL-PURPOSE INPUT/OUTPUT PORTS (P0A, P0B, P0C, AND P1A)
  • 17.4 GENERAL-PURPOSE INPUT PORTS (P0D AND P1D)
  • 17.5 GENERAL-PURPOSE OUTPUT PORTS (P1B, P1C, AND P2A)
  • 17.6 GENERAL-PURPOSE OUTPUT PORTS (P0E, P0F, P0X, AND P0Y)
• 18. A/D CONVERTER (ADC)
  • 18.1 A/D CONVERTER CONFIGURATION
  • 18.2 A/D CONVERTER FUNCTIONS
  • 18.3 INPUT SELECTOR CIRCUIT
  • 18.4 COMPARISON VOLTAGE GENERATOR CIRCUIT
  • 18.5 COMPARATOR CIRCUIT
  • 18.6 A/D CONVERTER PERFORMANCE
  • 18.7 USE OF A/D CONVERTER
  • 18.8 CAUTIONS WHEN USING A/D CONVERTER
  • 18.9 STATE DURING RESET
• 19. D/A CONVERTER (DAC)
  • 19.1 D/A CONVERTER CONFIGURATION
  • 19.2 D/A CONVERTER FUNCTIONS
  • 19.3 OUTPUT SELECTOR CIRCUITS
  • 19.4 DUTY CYCLE SETTING CIRCUITS AND CLOCK GENERATOR CIRCUIT
  • 19.5 STATE DURING RESET
• 20. CLOCK GENERATOR PORT (CGP)
  • 20.1 CLOCK GENERATOR PORT CONFIGURATION
  • 20.2 CLOCK GENERATOR PORT FUNCTIONS
  • 20.3 OUTPUT SELECTOR CIRCUIT
  • 20.4 VDP/SG SETTING CIRCUIT AND CLOCK GENERATOR CIRCUIT
  • 20.5 USE OF CLOCK GENERATOR PORT
  • 20.6 STATE DURING RESET
  • 20.7 CAUTIONS WHEN USING CLOCK GENERATOR PORT
• 21. SERIAL INTERFACE
  • 21.1 SERIAL INTERFACE CONFIGURATION
  • 21.2 OUTLINE OF FUNCTIONS OF SERIAL INTERFACE
  • 21.3 CONFIGURATION OF SERIAL INTERFACE 1 (SIO1)
  • 21.4 OUTLINE OF FUNCTIONS OF SERIAL INTERFACE 1
  • 21.5 SHIFT CLOCK AND SERIAL DATA INPUT/OUTPUT PIN CONTROL BLOCK
  • 21.6 CLOCK GENERATION BLOCK
  • 21.7 CLOCK COUNTER AND START/STOP DETECTION BLOCK
  • 21.8 PRESETTABLE SHIFT REGISTER (PSR)
  • 21.9 WAIT BLOCK AND ACKNOWLEDGE BLOCK
  • 21.10 INTERRUPT CONTROL BLOCK
  • 21.11 HOW TO USE SERIAL INTERFACE 1
  • 21.12 SERIAL INTERFACE 1 RESET STATUS
  • 21.13 CONFIGURATION OF SERIAL INTERFACE 2 (SIO2)
  • 21.14 OUTLINE OF FUNCTION OF SERIAL INTERFACE 2
  • 21.15 SHIFT CLOCK AND SERIAL DATA INPUT/OUTPUT CONTROL BLOCK
  • 21.16 CLOCK GENERATION BLOCK
  • 21.17 CLOCK COUNTER
  • 21.18 PRESETTABLE SHIFT REGISTER (PSR2)
  • 21.19 WAIT BLOCK
  • 21.20 USAGE OF SERIAL INTERFACE 2
  • 21.21 RESET STATUS OF SERIAL INTERFACE 2
• 22. FREQUENCY COUNTER (FC)
  • 22.1 CONFIGURATION OF FREQUENCY COUNTER
  • 22.2 OUTLINE OF FUNCTION OF FREQUENCY COUNTER
  • 22.3 INPUT/OUTPUT SWITCH BLOCK AND GATE TIME CONTROL BLOCK
  • 22.4 START/STOP CONTROL BLOCK AND IF COUNTER
  • 22.5 USAGE OF IF COUNTER FUNCTION
  • 22.6 USAGE OF FCG FUNCTION
  • 22.7 RESET STATUS
  • 22.8 PRECAUTIONS IN USING FREQUENCY COUNTER
• 23. LCD CONTROLLER/DRIVER
  • 23.1 CONFIGURATION OF LCD CONTROLLER/DRIVER
  • 23.2 OUTLINE OF FUNCTION OF LCD CONTROLLER/DRIVER
  • 23.3 LCD DOT REGISTER AND LCD GROUP REGISTER
  • 23.4 OUTPUT TIMING CONTROL BLOCK AND SEGMENT/PORT SWITCHING BLOCK
  • 23.5 USAGE OF LCD CONTROLLER/DRIVER
  • 23.6 RESET STATUS
• 24. KEY SOURCE CONTROLLER/DECODER
  • 24.1 CONFIGURATION OF KEY SOURCE CONTROLLER/DECODER
  • 24.2 OUTLINE OF FUNCTIONS OF KEY SOURCE CONTROLLER/DECODER
  • 24.3 KEY SOURCE DATA SETTING BLOCK
  • 24.4 OUTPUT TIMING CONTROL BLOCK AND SEGMENT/PORT SWITCHING BLOCK
  • 24.5 KEY INPUT CONTROL BLOCK
  • 24.6 USAGE OF KEY SOURCE CONTROLLER/DECODER
  • 24.7 RESET STATUS
• 25. uPD17005 INSTRUCTIONS
  • 25.1 INSTRUCTION SET
  • 25.2 LIST OF INSTRUCTIONS
  • 25.3 ASSEMBLER (AS17K) BUILT-IN MACRO INSTRUCTION
• 26. uPD17005 RESERVED WORDS
  • 26.1 LIST OF RESERVED WORDS
• 27. ELECTRICAL CHARACTERISTICS
  • 27.1 ABSOLUTE MAXIMUM RATINGS (Unless otherwise specified, Ta = 25 +/- 2 degrees)
  • 27.2 RECOMMENDED OPERATING CONDITIONS
  • 27.3 DC CHARACTERISTICS (Unless otherwise specified, Ta = -40 to +85 degrees, VDD = 4.5 to 5.5 V)
  • 27.4 AC CHARACTERISTICS (Unless otherwise specified, Ta = -40 to +85 degrees, VDD = 4.5 to 5.5 V)
  • 27.5 REFERENCE CHARACTERISTICS
• 28. PACKAGE DIMENSION
• 29. RECOMMENDED SOLDERING CONDITIONS
• APPENDIX A DIFFERENCE BETWEEN uPD17003A AND uPD17005
• APPENDIX B DEVELOPMENT TOOL