1999
DATA SHEET
PD3799
MOS INTEGRATED CIRCUIT
The
PD3799 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
PD3799 has 3 rows of 5300 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits, clamp pulse generation circuit and voltage amplifiers. Therefore,
it is suitable for 600 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
Valid photocell
: 5300 pixels
3
Photocell's pitch : 7
m
Line spacing
: 28
m (4 lines) Red line-Green line, Green line-Blue line
Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lxhour)
Resolution
: 24 dot/mm A4 (210
297 mm) size (shorter side)
600 dpi US letter (8.5"
11") size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: 4 MHz MAX.
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
Clamp pulse generation circuit
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD3799CY
CCD linear image sensor 32-pin plastic DIP (400 mil)
Document No. S14083EJ1V0DS00 (1st edition)
Date published April 1999 N CP(K)
Printed in Japan
5300 PIXELS
3 COLOR CCD LINEAR IMAGE SENSOR
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
PD3799
2
DATA SHEET S14083EJ1V0DS00
BLOCK DIAGRAM
31
32
1
30
2
11
25
24
23
22
10
9
8
3
D14
D64
D65
D66
S5299
S5300
S1
S2
Photocell
(Blue)
Transfer gate
CCD analog shift register
D67
D14
D64
D65
D66
S5299
S5300
S1
S2
Photocell
(Green)
Transfer gate
CCD analog shift register
D67
D14
D64
D65
D66
S5299
S5300
S1
S2
Photocell
(Red)
Transfer gate
CCD analog shift register
D67
TG1
(Blue)
TG2
(Green)
TG3
(Red)
RB
2
1
2
1
GND
GND
V
OD
V
OUT
3
(Red)
V
OUT
2
(Green)
V
OUT
1
(Blue)
Clamp pulse
generator
PD3799
3
DATA SHEET S14083EJ1V0DS00
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (400 mil)
PD3799CY
Caution
Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
1
2
3
4
5
6
7
8
9
10
11
31
30
29
28
27
26
25
24
23
22
32
NC
NC
V
OUT
2
V
OUT
1
IC
1
TG1
No connection
No connection
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
Internal connection
Shift register clock 1
Transfer gate clock 2
(for Green)
V
OUT
3
GND
IC
IC
1
TG3
No connection
No connection
Output signal 3 (Red)
Ground
Reset gate clock
Shift register clock 2
Internal connection
Internal connection
Shift register clock 1
5300
5300
5300
Red
Green
Blue
1
1
1
Internal connection
Transfer gate clock 1
(for Blue)
Transfer gate clock 3
(for Red)
V
OD
IC
2
2
Shift register clock 2
GND
Ground
RB
NC
NC
TG2
12
13
14
15
16
21
20
19
18
17
IC
Internal connection
IC
Internal connection
NC
No connection
NC
No connection
NC
No connection
IC
Internal connection
IC
Internal connection
NC
No connection
NC
No connection
NC
No connection
PD3799
4
DATA SHEET S14083EJ1V0DS00
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
7 m
4 m
m
3
Channel stopper
Aluminum
shield
Blue photocell array
7 m
Green photocell array
7 m
Red photocell array
7 m
4 lines
(28 m)
4 lines
(28 m)
PD3799
5
DATA SHEET S14083EJ1V0DS00
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
0.3 to +15
V
Shift register clock voltage
V
1
, V
2
0.3 to +8
V
Reset gate clock voltage
V
RB
0.3 to +8
V
Transfer gate clock voltage
V
TG1
to V
TG3
0.3 to +8
V
Operating ambient temperature
T
A
25 to +60
C
Storage temperature
T
stg
40 to +70
C
Caution
Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
1H
, V
2H
4.5
5.0
5.5
V
Shift register clock low level
V
1L
, V
2L
0.3
0
+0.5
V
Reset gate clock high level
V
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
RBL
0.3
0
+0.5
V
Transfer gate clock high level
V
TG1H
to V
TG3H
4.5
V
1H
Note
V
1H
Note
V
Transfer gate clock low level
V
TG1L
to V
TG3L
0.3
0
+0.5
V
Data rate
f
RB
1.0
4.0
MHz
Note
When Transfer gate clock high level (V
TG1H
to V
TG3H
) is higher than Shift register clock high level (V
1H
),
Image lag can increase.
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