Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagram
- Electrical Specifications
- Package Drawings
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confirm that this is the latest version.
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availability and additional information.
1995
MOS INTEGRATED CIRCUIT
PD43256B-X
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
DATA SHEET
Document No. M11012EJ4V0DSJ1 (4th edition)
Date Published December 2000 NS CP (K)
Printed in Japan
The mark
5
shows major revised points.
Description
The
PD43256B-X is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
The
PD43256B-X is an extended-operating-temperature version of the
PD43256B (X version : T
A
= 25 to +85
C). And A and B versions are low voltage operations. Battery backup is available.
The
PD43256B-X is packed in 28-pin plastic TSOP (I) (8 x 13.4 mm).
Features
32,768 words by 8 bits organization
Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
Operating ambient temperature: T
A
= 25 to +85
C
Low voltage operation (A version: V
CC
= 3.0 to 5.5 V, B version: V
CC
= 2.7 to 5.5 V)
Low V
CC
data retention: 2.0 V (MIN.)
/OE input for easy application
Part number
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V
C
mA (MAX.)
A (MAX.)
A (MAX.)
Note1
PD43256B-xxX
70, 85
4.5 to 5.5
-
25 to +85
45
50
2
PD43256B-AxxX
85
Note2
, 100, 120
Note2
3.0 to 5.5
PD43256B-BxxX
Note2
100, 120
Note2
, 150
Note2
2.7 to 5.5
40
Notes 1. T
A
40
C, V
CC
= 3.0 V
2. 100 s (MAX.) (V
CC
= 4.5 to 5.5 V)
Version X
This Data sheet can be applied to the version X. Each version is identified with its lot number. Letter X in the fifth
character position in a lot number signifies version X.
D43256B-X
Lot number
JAPAN
2
PD43256B-X
Data Sheet M11012EJ4V0DS
Ordering Information
Part number
Package
Access time
Operating supply Operating ambient
Remark
ns (MAX.)
voltage
temperature
V
C
PD43256BGW-70X-9JL
28-PIN PLASTIC TSOP(I)
70
4.5 to 5.5
25 to +85
PD43256BGW-85X-9JL
(8x13.4) (Normal bent)
85
PD43256BGW-A85X-9JL
85
3.0 to 5.5
A version
PD43256BGW-A10X-9JL
100
PD43256BGW-A12X-9JL
120
PD43256BGW-B10X-9JL
100
2.7 to 5.5
B version
PD43256BGW-B12X-9JL
120
PD43256BGW-B15X-9JL
150
PD43256BGW-70X-9KL
28-PIN PLASTIC TSOP(I)
70
4.5 to 5.5
PD43256BGW-85X-9KL
(8x13.4) (Reverse bent)
85
PD43256BGW-A85X-9KL
85
3.0 to 5.5
A version
PD43256BGW-A10X-9KL
100
PD43256BGW-A12X-9KL
120
PD43256BGW-B10X-9KL
100
2.7 to 5.5
B version
PD43256BGW-B12X-9KL
120
PD43256BGW-B15X-9KL
150
3
PD43256B-X
Data Sheet M11012EJ4V0DS
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
[
PD43256BGW-xxX-9JL]
[
PD43256BGW-AxxX-9JL]
[
PD43256BGW-BxxX-9JL]
/OE
A11
A9
A8
A13
/WE
V
CC
A14
A12
A7
A6
A5
A4
A3
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
[
PD43256BGW-xxX-9KL]
[
PD43256BGW-AxxX-9KL]
[
PD43256BGW-BxxX-9KL]
/OE
A11
A9
A8
A13
/WE
V
CC
A14
A12
A7
A6
A5
A4
A3
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0 - A14
: Address inputs
I/O1 - I/O8
: Data inputs / outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
4
PD43256B-X
Data Sheet M11012EJ4V0DS
Block Diagram
Address buffer
Memory cell array
262,144 bits
Input data
controller
A0
A14
I/O8
Sense amplifier / Switching circuit
Column decoder
/WE
I/O1
V
CC
GND
/CS
/OE
Address
buffer
Row
decoder
Output data
controller
Truth Table
/CS
/OE
/WE
Mode
I/O
Supply current
H
Not selected
High impedance
I
SB
L
H
H
Output disable
I
CCA
L
L
Write
D
IN
L
L
H
Read
D
OUT
Remark
: V
IH
or V
IL
5
PD43256B-X
Data Sheet M11012EJ4V0DS
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
V
CC
0.5
Note
to +7.0
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+ 0.5
V
Operating ambient temperature
T
A
25 to +85
C
Storage temperature
T
stg
55 to +125
C
Note 3.0 V (MIN.) (Pulse width : 50 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
PD43256B-xxX
PD43256B-AxxX
PD43256B-BxxX
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
4.5
5.5
3.0
5.5
2.7
5.5
V
High level input voltage
V
IH
2.4
V
CC
+0.5
2.4
V
CC
+0.5
2.4
V
CC
+0.5
V
Low level input voltage
V
IL
0.3
Note
+0.6
0.3
Note
+0.4
0.3
Note
+0.4
V
Operating ambient temperature
T
A
25
+85
25
+85
25
+85
C
Note 3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
5
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8
pF
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
6
PD43256B-X
Data Sheet M11012EJ4V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
PD43256B-xxX
Unit
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /OE = V
IH
or
1.0
+1.0
A
/CS = V
IH
or /WE = V
IL
Operating supply current
I
CCA1
/CS = V
IL
, Minimum cycle time, I
I/O
= 0 mA
45
mA
I
CCA2
/CS = V
IL
, I
I/O
= 0 mA
15
I
CCA3
/CS
0.2 V, Cycle = 1 MHz,
15
I
I/O
= 0 mA, V
IL
0.2 V, V
IH
V
CC
0.2 V
Standby supply current
I
SB
/CS = V
IH
3
mA
I
SB1
/CS
V
CC
-
0.2 V
1.0
50
A
High level output voltage
V
OH1
I
OH
= 1.0 mA
2.4
V
V
OH2
I
OH
= 0.1 mA
V
CC
0.5
Low level output voltage
V
OL
I
OL
= 2.1 mA
0.4
V
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of package types.
7
PD43256B-X
Data Sheet M11012EJ4V0DS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
PD43256B-AxxX
PD43256B-BxxX
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /OE = V
IH
or
1.0
+1.0
1.0
+1.0
A
/CS = V
IH
or /WE = V
IL
Operating supply current
I
CCA1
/CS = V
IL
,
PD43256B-A85X
45
mA
Minimum cycle time,
PD43256B-A10X
40
I
I/O
= 0 mA
PD43256B-A12X
40
PD43256B-B10X
40
PD43256B-B12X
40
PD43256B-B15X
40
V
CC
3.3 V
25
I
CCA2
/CS = V
IL
, I
I/O
= 0 mA
15
15
V
CC
3.3 V
10
I
CCA3
/CS
0.2 V, Cycle = 1 MHz, I
I/O
= 0 mA,
15
15
V
IL
0.2 V, V
IH
V
CC
0.2 V V
CC
3.3 V
10
Standby supply current
I
SB
/CS = V
IH
3
3
mA
V
CC
3.3 V
2
I
SB1
/CS
V
CC
-
0.2 V
1.0
50
1.0
50
A
V
CC
3.3 V
25
High level output voltage
V
OH1
I
OH
= 1.0 mA, V
CC
4.5 V
2.4
2.4
V
I
OH
= 0.5 mA, V
CC
< 4.5 V
2.4
2.4
V
OH2
I
OH
= 0.02 mA
V
CC
0.1
V
CC
0.1
Low level output voltage
V
OL
I
OL
= 2.1 mA, V
CC
4.5 V
0.4
0.4
V
I
OL
= 1.0 mA, V
CC
< 4.5 V
0.4
0.4
V
OL1
I
OL
= 0.02 mA
0.1
0.1
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of package types.
8
PD43256B-X
Data Sheet M11012EJ4V0DS
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
PD43256B-70X,
PD43256B-85X]
Input Waveform (Rise and Fall Time
5 ns)
Test points
1.5 V
1.5 V
2.4 V
0.6 V
Output Waveform
Test points
1.5 V
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(t
AA
, t
ACS
, t
OE
, t
OH
)
(t
CHZ
, t
CLZ
, t
OHZ
, t
OLZ
, t
WHZ
, t
OW
)
+5 V
I/O (Output)
1.8 k
5 pF
C
L
990
+5 V
I/O (Output)
1.8 k
100 pF
C
L
990
Remark C
L
includes capacitance of the probe and jig, and stray capacitance.
[
PD43256B-A85X,
PD43256B-A10X,
PD43256B-A12X,
PD43256B-B10X,
PD43256B-B12X,
PD43256B-B15X]
Input Waveform (Rise and Fall Time
5 ns)
Test points
1.5 V
1.5 V
2.4 V
0.4 V
Output Waveform
Test points
1.5 V
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
t
AA
, t
ACS
, t
OE
, t
OH
t
CHZ
, t
CLZ
, t
OHZ
, t
OLZ
, t
WHZ
, t
OW
1TTL + 50 pF
1TTL + 5 pF
9
PD43256B-X
Data Sheet M11012EJ4V0DS
Read Cycle (1/2)
Parameter
Symbol
V
CC
4.5 V
Unit
Con-
PD43256B-70X
PD43256B-85X
PD43256B-AxxX
PD43256B-BxxX
dition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
70
85
100
ns
Address access time
t
AA
70
85
100
ns
Note
/CS access time
t
ACS
70
85
100
ns
/OE access time
t
OE
35
40
50
ns
Output hold from address change
t
OH
10
10
10
ns
/CS to output in low impedance
t
CLZ
10
10
10
ns
/OE to output in low impedance
t
OLZ
5
5
5
ns
/CS to output in high impedance
t
CHZ
30
30
35
ns
/OE to output in high impedance
t
OHZ
30
30
35
ns
Note
See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
Parameter
Symbol
V
CC
3.0 V
V
CC
2.7 V
Unit
Con-
PD43256B-
A85X
PD43256B-
A10X
PD43256B-
A12X
PD43256B-
B10X
PD43256B-
B12X
PD43256B-
B15X
dition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
85
100
120
100
120
150
ns
Address access
time
t
AA
85
100
120
100
120
150
ns
Note
/CS access time
t
ACS
85
100
120
100
120
150
ns
/OE access time
t
OE
50
60
60
60
60
70
ns
Output hold from
address change
t
OH
10
10
10
10
10
10
ns
/CS to output in
low impedance
t
CLZ
10
10
10
10
10
10
ns
/OE to output in
low impedance
t
OLZ
5
5
5
5
5
5
ns
/CS to output in
high impedance
t
CHZ
35
35
40
35
40
50
ns
/OE to output in
high impedance
t
OHZ
35
35
40
35
40
50
ns
Note
See the output load.
Remark These AC characteristics are in common regardless of package types.
10
PD43256B-X
Data Sheet M11012EJ4V0DS
Read Cycle Timing Chart
t
OHZ
t
RC
t
OH
t
CHZ
t
OLZ
t
OE
t
CLZ
t
ACS
t
AA
High impedance
Data out
/OE (Input)
/CS (Input)
Address (Input)
I/O (Output)
Remark
In read cycle, /WE should be fixed to high level.
11
PD43256B-X
Data Sheet M11012EJ4V0DS
Write Cycle (1/2)
Parameter
Symbol
V
CC
4.5 V
Unit
Con-
PD43256B-70X
PD43256B-85X
PD43256B-AxxX
PD43256B-BxxX
dition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
70
85
100
ns
/CS to end of write
t
CW
60
70
80
ns
Address valid to end of write
t
AW
60
70
80
ns
Write pulse width
t
WP
55
60
70
ns
Data valid to end of write
t
DW
30
35
40
ns
Data hold time
t
DH
5
5
5
ns
Address setup time
t
AS
0
0
0
ns
Write recovery time
t
WR
0
0
0
ns
/WE to output in high impedance
t
WHZ
30
30
35
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note
See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
Parameter
Symbol
V
CC
3.0 V
V
CC
2.7 V
Unit
Con-
PD43256B-
A85X
PD43256B-
A10X
PD43256B-
A12X
PD43256B-
B10X
PD43256B-
B12X
PD43256B-
B15X
dition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
85
100
120
100
120
150
ns
/CS to end of write
t
CW
70
70
90
70
90
100
ns
Address valid to
end of write
t
AW
70
70
90
70
90
100
ns
Write pulse width
t
WP
60
60
80
60
80
90
ns
Data valid to end
of write
t
DW
60
60
70
60
70
80
ns
Data hold time
t
DH
5
5
5
5
5
5
ns
Address setup time
t
AS
0
0
0
0
0
0
ns
Write recovery time
t
WR
0
0
0
0
0
0
ns
/WE to output in
high impedance
t
WHZ
35
35
40
35
40
40
ns
Note
Output active
from end of write
t
OW
5
5
5
5
5
5
ns
Note
See the output load.
Remark These AC characteristics are in common regardless of package types.
12
PD43256B-X
Data Sheet M11012EJ4V0DS
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
/CS (Input)
I/O (Input / Output)
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins
will remain high impedance state.
13
PD43256B-X
Data Sheet M11012EJ4V0DS
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
DW
t
DH
Data in
High impedance
Address (Input)
/CS (Input)
I/O (Input)
High
impedance
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark
Write operation is done during the overlap time of a low level /CS and a low level /WE.
14
PD43256B-X
Data Sheet M11012EJ4V0DS
Low V
CC
Data Retention Characteristics (T
A
=
-
-
-
-
25 to +85
C)
Parameter
Symbol
Test Condition
MIN.
TYP.
MAX.
Unit
Data retention supply voltage
V
CCDR
/CS
V
CC
-
0.2 V
2.0
5.5
V
Data retention supply current
I
CCDR
V
CC
= 3.0 V, /CS
V
CC
-
0.2 V
0.5
20
Note
A
Chip deselection to data retention mode
t
CDR
0
ns
Operation recovery time
t
R
5
ms
Note 2
A (T
A
40
C), 7
A (T
A
70
C)
Data Retention Timing Chart
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CS
/CS
V
CC
0.2 V
GND
4.5 V
Note
t
CDR
Data retention mode
t
R
Note A version : 3.0 V, B version : 2.7 V
Remark
The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
15
PD43256B-X
Data Sheet M11012EJ4V0DS
Package Drawings
+
7
-
3
28-PIN PLASTIC TSOP(
I
) (8x13.4)
ITEM
MILLIMETERS
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
P28GW-55-9JL-2
M
0.08
N
0.10
H
12.4
0.2
I
11.8
0.1
J
0.8
0.2
S
1.2 MAX.
A
8.0
0.1
B
0.6 MAX.
C
0.55 (T.P.)
G
1.0
K
0.145
L
0.5
0.1
P
13.4
0.2
Q
0.1
0.05
R
3
D
0.22
+
0.08
-
0.07
M
detail of lead end
Q
R
G
B
C
D
M
L
K
+
0.025
-
0.015
S
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
1
14
28
15
S
N
S
A
J
P
I
H
16
PD43256B-X
Data Sheet M11012EJ4V0DS
28-PIN PLASTIC TSOP(
I
) (8x13.4)
ITEM
MILLIMETERS
NOTE
P28GW-55-9KL-2
M
0.08
N
0.10
H
12.4
0.2
I
11.8
0.1
J
0.8
0.2
S
1.2 MAX.
A
8.0
0.1
B
0.6 MAX.
C
0.55 (T.P.)
G
1.0
K
0.145
L
0.5
0.1
P
13.4
0.2
Q
0.1
0.05
R
3
+
7
-
3
D
0.22
+
0.08
-
0.07
detail of lead end
R
Q
S
B
C
D
+
0.025
-
0.015
M
M
N
G
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
1
14
28
15
S
S
A
J
L
K
P
I
H
17
PD43256B-X
Data Sheet M11012EJ4V0DS
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD43256B-X.
Types of Surface Mount Device
PD43256BGW-xxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
PD43256BGW-xxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
PD43256BGW-AxxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
PD43256BGW-AxxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
PD43256BGW-BxxX-9JL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
PD43256BGW-BxxX-9KL: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
18
PD43256B-X
Data Sheet M11012EJ4V0DS
[MEMO]
19
PD43256B-X
Data Sheet M11012EJ4V0DS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD43256B-X
M8E 00. 4
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
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"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
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Customers must check the quality grade of each semiconductor product before using it in a particular
application.
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and visual equipment, home electronic appliances, machine tools, personal electronic equipment
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"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
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