Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagram
- Electrical Specifications
- Package Drawings
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1998
MOS INTEGRATED CIRCUIT
PD441000L-X
1M-BIT CMOS STATIC RAM
128K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
DATA SHEET
Document No. M13714EJ5V0DSJ1 (5th edition)
Date Published December 2000 NS CP (K)
Printed in Japan
The mark
shows major revised points.
Description
The
PD441000L-X is a high speed, low power, 1,048,576 bits (131,072 words by 8 bits) CMOS static RAM.
The
PD441000L-X has two chip enable pins (/CE1, CE2) to extend the capacity.
The
PD441000L-X is packed in 32-pin plastic SOP and 32-pin plastic TSOP (I) (8
13.4 mm) and (8
20 mm).
Features
131,072 words by 8 bits organization
Fast access time : 70, 85, 100, 120, 150 ns (MAX.)
Low voltage operation
(B version : V
CC
= 2.7 to 3.6 V, C version : V
CC
= 2.2 to 3.6 V, D version : V
CC
= 1.8 to 3.6 V)
Low V
CC
data retention
(B version : 2.0 V (MIN.), C version, D version : 1.5 V (MIN.))
Operating ambient temperature : T
A
= 25 to +85 C
Output Enable input for easy application
Two Chip Enable inputs : /CE1, CE2
Part number
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V
C
mA (MAX.)
A (MAX.)
A (MAX.)
PD441000L-BxxX
70, 85, 100
2.7 to 3.6
-
25 to +85
25
2
2
Note
PD441000L-CxxX
100, 120
2.2 to 3.6
PD441000L-DxxX
120, 150
1.8 to 3.6
Note 0.5
A (T
A
40 C)
5
Data Sheet M13714EJ5V0DS
2
PD441000L-X
Ordering Information
Part number
Package
Access time
Operating
Operating
Remark
ns (MAX.)
supply voltage
temperature
V
C
PD441000LGW-B70X
32-pin Plastic SOP
70
2.7 to 3.6
-
25 to +85
B version
PD441000LGW-B85X
(13.34 mm (525))
85
PD441000LGW-B10X
100
PD441000LGU-B70X-9JH
32-pin Plastic TSOP (I)
70
PD441000LGU-B85X-9JH
(8
13.4) (Normal bent)
85
PD441000LGU-B10X-9JH
100
PD441000LGU-B70X-9KH
32-pin Plastic TSOP (I)
70
PD441000LGU-B85X-9KH
(8
13.4) (Reverse bent)
85
PD441000LGU-B10X-9KH
100
PD441000LGZ-B70X-KJH
32-pin Plastic TSOP (I)
70
PD441000LGZ-B85X-KJH
(8
20) (Normal bent)
85
PD441000LGZ-B10X-KJH
100
PD441000LGZ-B70X-KKH
32-pin Plastic TSOP (I)
70
PD441000LGZ-B85X-KKH
(8
20) (Reverse bent)
85
PD441000LGZ-B10X-KKH
100
PD441000LGW-C10X
32-pin Plastic SOP
100
2.2 to 3.6
C version
PD441000LGW-C12X
(13.34 mm (525))
120
PD441000LGU-C10X-9JH
32-pin Plastic TSOP (I)
100
PD441000LGU-C12X-9JH
(8
13.4) (Normal bent)
120
PD441000LGU-C10X-9KH
32-pin Plastic TSOP (I)
100
PD441000LGU-C12X-9KH
(8
13.4) (Reverse bent)
120
PD441000LGZ-C10X-KJH
32-pin Plastic TSOP (I)
100
PD441000LGZ-C12X-KJH
(8
20) (Normal bent)
120
PD441000LGZ-C10X-KKH
32-pin Plastic TSOP (I)
100
PD441000LGZ-C12X-KKH
(8
20) (Reverse bent)
120
PD441000LGW-D12X
32-pin Plastic SOP
120
1.8 to 3.6
D version
PD441000LGW-D15X
(13.34 mm (525))
150
PD441000LGU-D12X-9JH
32-pin Plastic TSOP (I)
120
PD441000LGU-D15X-9JH
(8
13.4) (Normal bent)
150
PD441000LGU-D12X-9KH
32-pin Plastic TSOP (I)
120
PD441000LGU-D15X-9KH
(8
13.4) (Reverse bent)
150
PD441000LGZ-D12X-KJH
32-pin Plastic TSOP (I)
120
PD441000LGZ-D15X-KJH
(8
20) (Normal bent)
150
PD441000LGZ-D12X-KKH
32-pin Plastic TSOP (I)
120
PD441000LGZ-D15X-KKH
(8
20) (Reverse bent)
150
5
Data Sheet M13714EJ5V0DS
3
PD441000L-X
Pin Configurations (Marking Side)
/xxx indicates active low signal.
32-pin Plastic SOP (13.34 mm (525))
[
PD441000LGW-BxxX ]
[
PD441000LGW-CxxX ]
[
PD441000LGW-DxxX ]
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
CE2
/WE
A13
A8
A9
A11
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
A0 - A16
: Address inputs
I/O1 - I/O8
: Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M13714EJ5V0DS
4
PD441000L-X
32-pin Plastic TSOP (I) (8
13.4) (Normal bent)
[
PD441000LGU-BxxX-9JH ]
[
PD441000LGU-CxxX-9JH ]
[
PD441000LGU-DxxX-9JH ]
32-pin Plastic TSOP (I) (8
20) (Normal bent)
[
PD441000LGZ-BxxX-KJH ]
[
PD441000LGZ-CxxX-KJH ]
[
PD441000LGZ-DxxX-KJH ]
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
A0 - A16
: Address inputs
I/O1 - I/O8
: Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M13714EJ5V0DS
5
PD441000L-X
32-pin Plastic TSOP (I) (8
13.4) (Reverse bent)
[
PD441000LGU-BxxX-9KH ]
[
PD441000LGU-CxxX-9KH ]
[
PD441000LGU-DxxX-9KH ]
32-pin Plastic TSOP (I) (8
20) (Reverse bent)
[
PD441000LGZ-BxxX-KKH ]
[
PD441000LGZ-CxxX-KKH ]
[
PD441000LGZ-DxxX-KKH ]
/OE
A10
/CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
/WE
CE2
A15
V
CC
NC
A16
A14
A12
A7
A6
A5
A4
A0 - A16
: Address inputs
I/O1 - I/O8
: Data inputs / outputs
/CE1, CE2
: Chip Enable 1, 2
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
NC
: No connection
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M13714EJ5V0DS
6
PD441000L-X
Block Diagram
Address
buffer
Row
decoder
Memory cell array
1,048,576 bits
Input data
controller
A0
A16
I/O1
I/O8
Sense amplifier /
Switching circuit
Column decoder
Output data
controller
Address buffer
/CE1
CE2
/OE
/WE
V
CC
GND
Truth Table
/CE1
CE2
/OE
/WE
Mode
I/O
Supply current
H
Not selected
High impedance
I
SB
L
Not selected
High impedance
L
H
H
H
Output disable
High impedance
I
CCA
L
H
L
H
Read
D
OUT
L
H
L
Write
D
IN
Remark
: V
IH
or V
IL
Data Sheet M13714EJ5V0DS
7
PD441000L-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
V
CC
0.5
Note
to +4.6
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+0.5
V
Operating ambient temperature
T
A
25 to +85
C
Storage temperature
T
stg
55 to +125
C
Note 3.0 V (MIN.) (Pulse width : 30 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
PD441000L-BxxX
PD441000L-CxxX
PD441000L-DxxX
Unit
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
2.7
3.6
2.2
3.6
1.8
3.6
V
High level input voltage
V
IH
2.7 V
V
CC
3.6 V
2.4
V
CC
+0.5
2.4
V
CC
+0.5
2.4
V
CC
+0.5
V
2.2 V
V
CC
< 2.7 V
2.0
V
CC
+0.5
2.0
V
CC
+0.5
1.8 V
V
CC
< 2.2 V
1.6
V
CC
+0.5
Low level input voltage
V
IL
0.3
Note
+0.5
0.3
Note
+0.3
0.3
Note
+0.2
V
Operating ambient
temperature
T
A
25
+85
25
+85
25
+85
C
Note 3.0 V (MIN.) (Pulse width : 30 ns)
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M13714EJ5V0DS
8
PD441000L-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
PD441000L-BxxX
PD441000L-CxxX
PD441000L-DxxX
Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
1.0
+1.0
1.0
+1.0
A
current
I/O leakage
I
LO
V
I/O
= 0 V to V
CC
, /CE1 = V
IH
or
1.0
+1.0
1.0
+1.0
1.0
+1.0
A
current
CE2 = V
IL
or /WE = V
IL
or /OE = V
IH
Operating
I
CCA1
/CE1 = V
IL
, CE2 = V
IH
,
23
25
23
25
23
25
mA
supply current
Minimum cycle time,
V
CC
2.7 V
20
23
20
23
I
I/O
= 0 mA
V
CC
2.2 V
17
20
I
CCA2
/CE1 = V
IL
, CE2 = V
IH
,
5
5
5
I
I/O
= 0 mA
V
CC
2.7 V
4
4
V
CC
2.2 V
3
I
CCA3
/CE1
0.2 V, CE2
V
CC
0.2 V,
4
4
4
Cycle = 1 MHz, I
I/O
= 0 mA,
V
IL
0.2 V,
V
CC
2.7 V
3
3
V
IH
V
CC
0.2 V
V
CC
2.2 V
3
Standby
I
SB
/CE1 = V
IH
or CE2 = V
IL
0.3
0.3
0.3
mA
supply current
I
SB1
/CE1
V
CC
0.2 V,
0.05
2
0.05
2
0.05
2
A
CE2
V
CC
0.2 V
V
CC
2.7 V
0.04
2
0.04
2
V
CC
2.2 V
0.03
1.5
I
SB2
CE2
0.2 V
0.05
2
0.05
2
0.05
2
V
CC
2.7 V
0.04
2
0.04
2
V
CC
2.2 V
0.03
1.5
High level
V
OH
I
OH
= 0.5 mA
2.4
2.4
2.4
V
output voltage
V
CC
2.7 V
1.8
1.8
V
CC
2.2 V
1.5
Low level
V
OL
I
OL
= 1.0 mA
0.4
0.4
0.4
V
output voltage
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These DC characteristics are in common regardless of package types and access time.
Data Sheet M13714EJ5V0DS
9
PD441000L-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[
PD441000L-B70X,
PD441000L-B85X,
PD441000L-B10X ]
Input Waveform (Rise and Fall Time
5 ns)
Test Points
0.5 V
2.4 V
1.5 V
1.5 V
Output Waveform
Test Points
1.5 V
1.5 V
Output Load
1TTL + 50 pF
[
PD441000L-C10X,
PD441000L-C12X ]
Input Waveform (Rise and Fall Time
5 ns)
Test Points
0.3 V
2.0 V
1.1 V
1.1 V
Output Waveform
Test Points
1.1 V
1.1 V
Output Load
1TTL + 30 pF
[
PD441000L-D12X,
PD441000L-D15X ]
Input Waveform (Rise and Fall Time
5 ns)
Test Points
0.2 V
1.6 V
0.9 V
0.9 V
Output Waveform
Test Points
0.9 V
0.9 V
Output Load
1TTL + 30 pF
Data Sheet M13714EJ5V0DS
10
PD441000L-X
Read Cycle (1/3) (B version)
Parameter
Symbol
PD441000L-B70X
PD441000L-B85X
PD441000L-B10X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
70
85
100
ns
Address access time
t
AA
70
85
100
ns
Note 1
/CE1 access time
t
CO1
70
85
100
ns
CE2 access time
t
CO2
70
85
100
ns
/OE to output valid
t
OE
35
45
50
ns
Output hold from address change
t
OH
10
10
10
ns
/CE1 to output in low impedance
t
LZ1
10
10
10
ns
Note 2
CE2 to output in low impedance
t
LZ2
10
10
10
ns
/OE to output in low impedance
t
OLZ
5
5
5
ns
/CE1 to output in high impedance
t
HZ1
25
30
35
ns
CE2 to output in high impedance
t
HZ2
25
30
35
ns
/OE to output in high impedance
t
OHZ
25
30
35
ns
Notes 1. The output load is 1TTL + 50 pF.
2. The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Read Cycle (2/3) (C version)
Parameter
Symbol
PD441000L-C10X
PD441000L-C12X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
100
120
ns
Address access time
t
AA
100
120
ns
Note 1
/CE1 access time
t
CO1
100
120
ns
CE2 access time
t
CO2
100
120
ns
/OE to output valid
t
OE
50
60
ns
Output hold from address change
t
OH
10
10
ns
/CE1 to output in low impedance
t
LZ1
10
10
ns
Note 2
CE2 to output in low impedance
t
LZ2
10
10
ns
/OE to output in low impedance
t
OLZ
5
5
ns
/CE1 to output in high impedance
t
HZ1
35
40
ns
CE2 to output in high impedance
t
HZ2
35
40
ns
/OE to output in high impedance
t
OHZ
35
40
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M13714EJ5V0DS
11
PD441000L-X
Read Cycle (3/3) (D version)
Parameter
Symbol
PD441000L-D12X
PD441000L-D15X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
120
150
ns
Address access time
t
AA
120
150
ns
Note 1
/CE1 access time
t
CO1
120
150
ns
CE2 access time
t
CO2
120
150
ns
/OE to output valid
t
OE
60
70
ns
Output hold from address change
t
OH
10
10
ns
/CE1 to output in low impedance
t
LZ1
10
10
ns
Note 2
CE2 to output in low impedance
t
LZ2
10
10
ns
/OE to output in low impedance
t
OLZ
5
5
ns
/CE1 to output in high impedance
t
HZ1
40
50
ns
CE2 to output in high impedance
t
HZ2
40
50
ns
/OE to output in high impedance
t
OHZ
40
50
ns
Notes 1. The output load is 1TTL + 30 pF.
2. The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Read Cycle Timing Chart
t
HZ2
t
RC
t
OH
t
HZ1
t
LZ2
t
CO2
t
LZ1
t
CO1
t
AA
High impedance
Data out
CE2 (Input)
/CE1 (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark
In read cycle, /WE should be fixed to high level.
Data Sheet M13714EJ5V0DS
12
PD441000L-X
Write Cycle (1/3) (B version)
Parameter
Symbol
PD441000L-B70X
PD441000L-B85X
PD441000L-B10X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
70
85
100
ns
/CE1 to end of write
t
CW1
55
70
80
ns
CE2 to end of write
t
CW2
55
70
80
ns
Address valid to end of write
t
AW
55
70
80
ns
Address setup time
t
AS
0
0
0
ns
Write pulse width
t
WP
50
60
60
ns
Write recovery time
t
WR
0
0
0
ns
Data valid to end of write
t
DW
35
35
40
ns
Data hold time
t
DH
0
0
0
ns
/WE to output in high impedance
t
WHZ
25
30
35
ns
Note
Output active from end of write
t
OW
5
5
5
ns
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Write Cycle (2/3) (C version)
Parameter
Symbol
PD441000L-C10X
PD441000L-C12X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
100
120
ns
/CE1 to end of write
t
CW1
80
100
ns
CE2 to end of write
t
CW2
80
100
ns
Address valid to end of write
t
AW
80
100
ns
Address setup time
t
AS
0
0
ns
Write pulse width
t
WP
60
85
ns
Write recovery time
t
WR
0
0
ns
Data valid to end of write
t
DW
45
60
ns
Data hold time
t
DH
0
0
ns
/WE to output in high impedance
t
WHZ
35
40
ns
Note
Output active from end of write
t
OW
5
5
ns
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M13714EJ5V0DS
13
PD441000L-X
Write Cycle (3/3) (D version)
Parameter
Symbol
PD441000L-D12X
PD441000L-D15X
Unit
Condition
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
120
150
ns
/CE1 to end of write
t
CW1
100
120
ns
CE2 to end of write
t
CW2
100
120
ns
Address valid to end of write
t
AW
100
120
ns
Address setup time
t
AS
0
0
ns
Write pulse width
t
WP
85
100
ns
Write recovery time
t
WR
0
0
ns
Data valid to end of write
t
DW
60
80
ns
Data hold time
t
DH
0
0
ns
/WE to output in high impedance
t
WHZ
40
50
ns
Note
Output active from end of write
t
OW
5
5
ns
Note The output load is 1TTL + 5 pF.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M13714EJ5V0DS
14
PD441000L-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW1
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
/CE1 (Input)
I/O (Input / Output)
CE2 (Input)
t
CW2
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M13714EJ5V0DS
15
PD441000L-X
Write Cycle Timing Chart 2 (/CE1 Controlled)
t
WC
t
AS
t
CW1
t
DW
t
DH
Data in
High impedance
Address (Input)
/CE1 (Input)
I/O (Input)
High
impedance
CE2 (Input)
t
CW2
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
Data Sheet M13714EJ5V0DS
16
PD441000L-X
Write Cycle Timing Chart 3 (CE2 Controlled)
t
WC
t
AS
t
CW2
t
DW
t
DH
Data in
High impedance
Address (Input)
CE2 (Input)
I/O (Input)
High
impedance
/CE1 (Input)
t
CW1
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CE1, /WE, and a high level CE2.
Data Sheet M13714EJ5V0DS
17
PD441000L-X
Low V
CC
Data Retention Characteristics (T
A
= 25 to +85
C)
Parameter
Symbol
Test Condition
PD441000L
-BxxX
PD441000L
-CxxX
PD441000L
-DxxX
Unit
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX.
Data retention
supply voltage
V
CCDR1
/CE1
V
CC
-
0.2 V,
CE2
V
CC
-
0.2 V
2
3.6
1.5
3.6
1.5
3.6
V
V
CCDR2
CE2
0.2 V
2
3.6
1.5
3.6
1.5
3.6
Data retention
supply current
I
CCDR1
V
CC
= 3.0 V, /CE1
V
CC
-
0.2 V,
CE2
V
CC
-
0.2 V or CE2
0.2 V
0.05 2
Note
0.05 2
Note
0.05 2
Note
A
I
CCDR2
V
CC
= 3.0 V, CE2
0.2 V
0.05 2
Note
0.05 2
Note
0.05 2
Note
Chip deselection to
data retention mode
t
CDR
0
0
0
ns
Operation recovery
time
t
R
5
5
5
ms
Note 0.5
A (T
A
40 C)
Data Sheet M13714EJ5V0DS
18
PD441000L-X
Data Retention Timing Chart
(1) /CE1 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
/CE1
/CE1
V
CC
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark
On the data retention mode by controlling /CE1, the input level of CE2 must be
V
CC
-
0.2 V or
0.2 V.
The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
(2) CE2 Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
V
CC
CE2
CE2
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V
Remark On the data retention mode by controlling CE2, the other pins (/CE1, Address, I/O, /WE, /OE) can be in
high impedance state.
5
5
Data Sheet M13714EJ5V0DS
19
PD441000L-X
Package Drawings
32
17
1
16
S
32-PIN PLASTIC SOP (13.34 mm (525))
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
C
0.78 MAX.
B
20.61 MAX.
A
1.27 (T.P.)
E
0.15
0.05
F
2.95 MAX.
G
2.7
H
14.1
0.3
I
11.3
J
1.4
0.2
D
0.40
+
0.10
-
0.05
M
0.12
N
0.10
L
0.8
0.2
K
0.20
+
0.10
-
0.05
P
3
+
7
-
3
P32GW-50-525A-1
K
L
G
P
D
M
B
J
detail of lead end
S
N
A
H
I
M
F
E
C
5
Data Sheet M13714EJ5V0DS
20
PD441000L-X
32-PIN PLASTIC TSOP(
I
) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
P32GU-50-9JH-2
B
0.45 MAX.
C
0.5 (T.P.)
detail of lead end
A
8.0
0.1
H
12.4
0.2
B
T
D
0.22
0.05
G
1.0
0.05
I
11.8
0.1
J
0.8
0.2
K
L
0.5
M
0.08
N
0.08
Q
0.1
0.05
P
13.4
0.2
S
1.2 MAX.
R
3
T
0.25
U
0.6
0.15
+
5
-
3
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
M
U
L
R
Q
S
D
M
C
G
J
0.145
+
0.025
-
0.015
1
16
32
17
S
S
N
K
H
P
I
A
5
Data Sheet M13714EJ5V0DS
21
PD441000L-X
+
0.025
-
0.015
32-PIN PLASTIC TSOP(
I
) (8x13.4)
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
P32GU-50-9KH-2
B
0.45 MAX.
C
0.5 (T.P.)
detail of lead end
A
8.0
0.1
H
12.4
0.2
T
D
0.22
0.05
G
1.0
0.05
I
11.8
0.1
J
0.8
0.2
K
L
0.5
M
0.08
N
0.08
Q
0.1
0.05
P
13.4
0.2
S
1.2 MAX.
R
3
T
0.25
U
0.6
0.15
+
5
-
3
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
U
L
R
Q
S
0.145
1
16
32
17
S
N
S
B
M
D
M
C
G
A
K
H
P
I
J
5
Data Sheet M13714EJ5V0DS
22
PD441000L-X
NOTES
32-PIN PLASTIC TSOP(
I
) (8x20)
ITEM
MILLIMETERS
A
B
C
E
I
8.0
0.1
0.5 (T.P.)
0.1
0.05
0.45 MAX.
K
1.2 MAX.
18.4
0.1
0.145
0.05
F
0.10
M
D
0.22
0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
R
L
0.97
0.08
G
L
0.5
0.10
N
P
20.0
0.2
Q
3
+
5
-
3
0.25
R
S32GZ-50-KJH1-2
S
0.60
0.15
J
0.8
0.2
G
F
E
S
Q
detail of lead end
1
16
32
17
S
N
S
C
D
M
M
B
A
P
K
I
J
5
Data Sheet M13714EJ5V0DS
23
PD441000L-X
NOTES
32-PIN PLASTIC TSOP(
I
) (8x20)
ITEM
MILLIMETERS
A
B
C
E
I
8.0
0.1
0.5 (T.P.)
0.1
0.05
0.45 MAX.
K
1.2 MAX.
18.4
0.1
0.145
0.05
F
0.10
M
D
0.22
0.05
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.3 mm MAX.)
C
R
D
M
M
G
0.97
0.08
G
L
0.5
0.10
N
P
20.0
0.2
Q
3
+
5
-
3
0.25
R
S32GZ-50-KKH1-2
S
0.60
0.15
J
0.8
0.2
B
F
E
Q
S
L
detail of lead end
1
16
32
17
S
A
S
N
K
I
P
J
5
Data Sheet M13714EJ5V0DS
24
PD441000L-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD441000L-X.
Types of Surface Mount Device
PD441000LGW-BxxX
: 32-pin Plastic SOP (13.34 mm (525))
PD441000LGW-CxxX
: 32-pin Plastic SOP (13.34 mm (525))
PD441000LGW-DxxX
: 32-pin Plastic SOP (13.34 mm (525))
PD441000LGU-BxxX-9JH
: 32-pin Plastic TSOP (I) (8
13.4) (Normal bent)
PD441000LGU-CxxX-9JH
: 32-pin Plastic TSOP (I) (8
13.4) (Normal bent)
PD441000LGU-DxxX-9JH
: 32-pin Plastic TSOP (I) (8
13.4) (Normal bent)
PD441000LGU-BxxX-9KH
: 32-pin Plastic TSOP (I) (8
13.4) (Reverse bent)
PD441000LGU-CxxX-9KH
: 32-pin Plastic TSOP (I) (8
13.4) (Reverse bent)
PD441000LGU-DxxX-9KH
: 32-pin Plastic TSOP (I) (8
13.4) (Reverse bent)
PD441000LGZ-BxxX-KJH
: 32-pin Plastic TSOP (I) (8
20) (Normal bent)
PD441000LGZ-CxxX-KJH
: 32-pin Plastic TSOP (I) (8
20) (Normal bent)
PD441000LGZ-DxxX-KJH
: 32-pin Plastic TSOP (I) (8
20) (Normal bent)
PD441000LGZ-BxxX-KKH
: 32-pin Plastic TSOP (I) (8
20) (Reverse bent)
PD441000LGZ-CxxX-KKH
: 32-pin Plastic TSOP (I) (8
20) (Reverse bent)
PD441000LGZ-DxxX-KKH
: 32-pin Plastic TSOP (I) (8
20) (Reverse bent)
5
Data Sheet M13714EJ5V0DS
25
PD441000L-X
[ MEMO ]
Data Sheet M13714EJ5V0DS
26
PD441000L-X
[ MEMO ]
Data Sheet M13714EJ5V0DS
27
PD441000L-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD441000L-X
M8E 00. 4
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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NEC semiconductor products are classified into the following three quality grades:
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Customers must check the quality grade of each semiconductor product before using it in a particular
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
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