The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
1999
MOS INTEGRATED CIRCUIT
PD4416004
16M-BIT CMOS FAST SRAM
4M-WORD BY 4-BIT
DATA SHEET
Document No. M14078EJ4V0DS00 (4th edition)
Date Published December 2000 NS CP(K)
Printed in Japan
The mark
shows major revised points.
Description
The
PD4416004 is a high speed, low power, 16,777,216 bits (4,194,304 words by 4 bits) CMOS static RAM.
Operating supply voltage is 3.3 V
0.3 V.
The
PD4416004 is packaged in a 54-PIN PLASTIC TSOP (II).
Features
4,194,304 words by 4 bits
Fast access time : 15, 17 ns (MAX.)
Output Enable input for easy application
Ordering Information
Part number
Package
Supply voltage
Access time
Supply current (MAX.)
V
(MAX.) ns
At operating mA
At standby mA
PD4416004G5-A15-9JF
54-PIN PLASTIC TSOP (II)
3.3
0.3
15
220
10
PD4416004G5-A17-9JF
(10.16 mm (400))
17
210
Data Sheet M14078EJ4V0DS
2
PD4416004
Pin Configuration (Marking Side)
/xxx indicates active low signal.
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
[
PD4416004G5
-
-
-
-
xxx
-
-
-
-
9JF]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
V
CC
NC
NC
GND
I/O 4
A0
A1
A2
A3
A4
A5
/CS
V
CC
/WE
NC
A6
A7
A8
A9
A10
I/O 1
V
CC
NC
NC
GND
NC
NC
GND
NC
NC
V
CC
I/O 3
A21
A20
A19
A18
A17
NC
/OE
GND
IC
A16
A15
A14
A13
A12
A11
I/O 2
GND
NC
NC
V
CC
NC
A0 - A21
: Address Inputs
I/O1 - I/O4 : Data Inputs / Outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
V
CC
: Power supply
GND
: Ground
NC
: No connection
IC
: Internal connection
Note
Note
Leave this pin connect to GND.
Remark Refer to Package Drawing for 1-pin index mark.
Data Sheet M14078EJ4V0DS
3
PD4416004
Block Diagram
Address buffer
Address
buffer
Row
decoder
Memory cell array
16,777,216 bits
Input data
controller
A0
A21
Sense amplifier /
Switching circuit
Column decoder
/CS
/WE
/OE
V
CC
GND
Output data
controller
I/O1 - I/O4
Truth Table
/CS
/OE
/WE
Mode
I/O
Supply current
H
Not selected
High impedance
I
SB
L
L
H
Read
D
OUT
I
CC
L
L
Write
D
IN
L
H
H
Output disable
High impedance
Remark
: Don't care
Data Sheet M14078EJ4V0DS
4
PD4416004
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Supply voltage
V
CC
0.5
Note
to +4.0
V
Input / Output voltage
V
T
0.5
Note
to +4.0
V
Operating ambient temperature
T
A
0 to 70
C
Storage temperature
T
stg
55 to +125
C
Note 2.0 V (MIN.) (pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply voltage
V
CC
3.0
3.3
3.6
V
High level input voltage
V
IH
2.0
V
CC
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.8
V
Operating ambient temperature
T
A
0
70
C
Note 2.0 V (MIN.) (pulse width : 2 ns)
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input leakage current
I
LI
V
IN
= 0 V to V
CC
2
+2
A
Output leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or /OE = V
IH
or
2
+2
A
/WE = V
IL
Operating supply current
I
CC
/CS = V
IL
, I
I/O
= 0 mA,
Cycle time : 15 ns
220
mA
Minimum cycle time
Cycle time : 17 ns
210
Standby supply current
I
SB
/CS = V
IH
, V
IN
= V
IH
or V
IL
, Minimum cycle time
80
mA
I
SB1
/CS
V
CC
0.2 V,
10
V
IN
0.2 V or V
IN
V
CC
0.2 V
High level output voltage
V
OH
I
OH
= 4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Remark
V
IN
: Input voltage, V
I/O
: Input / Output voltage
Capacitance (T
A
=
25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8
pF
Remarks 1. V
IN
: Input voltage, V
I/O
: Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M14078EJ4V0DS
5
PD4416004
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
LVTTL Interface
Input Waveform (Rise and Fall Time
3 ns)
Test Points
GND
3.0 V
1.5 V
1.5 V
Output Waveform
Test Points
1.5 V
1.5 V
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 1 or Figure 2.
Figure 1
Figure 2
(for t
AA
, t
ACS
, t
OE
, t
OH
)
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
WHZ
, t
OW
)
V
TT
= +1.5 V
I/O (Output)
50
Z
O
= 50
30 pF
C
L
+3.3 V
I/O (Output)
317
5 pF
C
L
351
Remark
C
L
includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M14078EJ4V0DS
6
PD4416004
Read Cycle
Parameter
Symbol
-A 15
-A 17
Unit
Notes
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
15
17
ns
Address access time
t
AA
15
17
ns
1
/CS access time
t
ACS
15
17
ns
/OE access time
t
OE
7
8
ns
Output hold from address change
t
OH
3
3
ns
/CS to output in low impedance
t
CLZ
3
3
ns
2, 3
/OE to output in low impedance
t
OLZ
0
0
ns
/CS to output in high impedance
t
CHZ
7
8
ns
/OE to output hold in high impedance
t
OHZ
7
8
ns
Notes 1. See the output load shown in Figure 1.
2. Transition is measured at
200 mV from steady-state voltage with the output load shown in Figure 2.
3. These parameters are periodically sampled and not 100% tested.
Read Cycle Timing Chart 1 (Address Access)
t
OH
t
RC
t
AA
Address (Input)
I/O (Output)
Previous data out
Data out
Remarks 1. In read cycle, /WE should be fixed to high level.
2. /CS = /OE = V
IL
Read Cycle Timing Chart 2 (/CS Access)
Address (Input)
t
RC
t
AA
t
OLZ
/CS (Input)
Data output
t
OHZ
High impedance
t
ACS
/OE (Input)
t
OE
t
CLZ
t
CHZ
High impedance
I/O (Output)
Caution
Address valid prior to or coincident with /CS low level input.
Remark
In read cycle, /WE should be fixed to high level.
Data Sheet M14078EJ4V0DS
7
PD4416004
Write Cycle
Parameter
Symbol
-A 15
-A 17
Unit
Notes
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
15
17
ns
/CS to end of write
t
CW
10
11
ns
Address valid to end of write
t
AW
10
11
ns
Write pulse width
t
WP
10
11
ns
Data valid to end of write
t
DW
7
8
ns
Data hold time
t
DH
0
0
ns
Address setup time
t
AS
0
0
ns
Write recovery time
t
WR
1
1
ns
/WE to output in high impedance
t
WHZ
7
8
ns
1, 2
Output active from end of write
t
OW
3
3
ns
Notes 1. Transition is measured at
200 mV from steady-state voltage with the output load shown in Figure 2.
2. These parameters are periodically sampled and not 100% tested.
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data output
High
impe-
dance
Data input
Indefinite data output
Address (Input)
/CS (Input)
t
AW
t
WP
t
AS
t
WR
/WE (Input)
High
impe-
dance
I/O (Input / Output)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE.
2. During t
WHZ
, I/O pins are in the output state, therefore the input signals of opposite phase to the output
must not be applied.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read
operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
Data Sheet M14078EJ4V0DS
8
PD4416004
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
DW
t
DH
Data input
High impedance
Address (Input)
/CS (Input)
I/O (Input)
High impedance
t
AW
t
WP
t
WR
/WE (Input)
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. Do not input data to the I/O pins while they are in the output state.
Remark
Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M14078EJ4V0DS
9
PD4416004
Package Drawing
NOTES
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold fiash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
M
P
A
G
C
N
B
M
D
L
K
J
H
I
E
F
detail of lead end
S
54
28
1
27
S
ITEM
B
C
I
L
M
N
54-PIN PLASTIC TSOP (
II
) (10.16 mm (400))
A
D
E
F
G
H
J
P
MILLIMETERS
0.80 (T.P.)
0.91 MAX.
0.13
0.50
0.10
10.16
0.10
0.10
22.22
0.05
0.10
0.05
0.32
1.1
0.1
11.76
0.20
1.00
+
0.08
-
0.07
0.80
0.20
3
+
7
-
3
K
0.145
+
0.025
-
0.015
S54G5-80-9JF-2
Data Sheet M14078EJ4V0DS
10
PD4416004
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD4416004.
Type of Surface Mount Device
PD4416004 : 54-PIN PLASTIC TSOP (II) (10.16 mm (400))
Data Sheet M14078EJ4V0DS
11
PD4416004
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD4416004
M8E 00. 4
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
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