Document Outline
- COVER
- Features
- Ordering Information
- Pin Configuration
- Block Diagram
- Electrical Specifications
- Package Drawing
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MOS INTEGRATED CIRCUIT
PD442002-X
2M-BIT CMOS STATIC RAM
128K-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
DATA SHEET
Document No. M14670EJ7V
1DS00 (7th edition)
Date Published
July 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2000
Description
The
PD442002-X is a high speed, low power, 2,097,152 bits (131,072 words by 16 bits) CMOS static RAM.
The
PD442002-X is packed in 48-pin TAPE FBGA.
Features
131,072 words by 16 bits organization
Fast access time : 70, 85, 100 ns (MAX.)
Byte data control : /LB (I/O1 to I/O8), /UB (I/O9 to I/O16)
Low voltage operation : V
CC
= 2.7 to 3.6 V (-BB70X)
V
CC
= 2.2 to 3.6 V (-BC70X)
V
CC
= 1.8 to 2.2 V (-DD85X, -DD10X)
Low V
CC
data retention : 1.0 V (MIN.)
Operating ambient temperature : T
A
= 25 to +85 C
Output Enable input for easy application
PD442002
Access time
Operating supply
Operating ambient
Supply current
ns (MAX.)
voltage
temperature
At operating
At standby
At data retention
V C
mA
(MAX.)
A (MAX.)
A (MAX.)
-BB70X
70
2.7 to 3.6
-25 to +85
30
4
2
-BC70X
70
2.2 to 3.6
-DD85X, -DD10X
85, 100
1.8 to 2.2
15 3
Data Sheet M14670EJ7V
1DS
2
PD442002-X
Ordering Information
Part number
Package
Access time
Operating
Operating
ns (MAX.)
supply voltage
temperature
V
C
PD442002F9-BB70X-BC2-A
Note
48-pin TAPE FBGA (8
6)
70
2.7 to 3.6
-25 to +85
PD442002F9-BC70X-BC2-A
Note
70
2.2 to 3.6
PD442002F9-DD85X-BC2-A
Note
85
1.8 to 2.2
PD442002F9-DD10X-BC2-A
Note
100
Note Lead-free product
Marking Image
Part number
Marking (XX)
PD442002F9-BB70X-BC2-A B2
PD442002F9-BC70X-BC2-A C2
PD442002F9-DD85X-BC2-A D3
PD442002F9-DD10X-BC2-A D4
INDEX MARK
Lot No.
J
S2M0-XX
Data Sheet M14670EJ7V
1DS
3
PD442002-X
Pin Configuration
/xxx indicates active low signal.
48-pin TAPE FBGA (8
6)
A
B
C
D
E
F
G
H
1
2
3
4
5
6
Bottom View
6
5
4
3
2
1
Top View
1 2 3 4 5 6 6 5 4 3 2 1
A /LB /OE A0 A1 A2 NC A NC A2 A1 A0 /OE /LB
B I/O9 /UB A3 A4 /CS I/O1
B I/O1 /CS A4 A3 /UB I/O9
C I/O10 I/O11 A5 A6 I/O2 I/O3
C I/O3 I/O2 A6 A5 I/O11 I/O10
D GND
I/O12 NC A7 I/O4 V
CC
D
V
CC
I/O4 A7 NC I/O12
GND
E V
CC
I/O13 NC A16 I/O5 GND
E GND I/O5 A16 NC I/O13 V
CC
F I/O15 I/O14 A14 A15 I/O6 I/O7
F I/O7 I/O6 A15 A14 I/O14 I/O15
G I/O16 NC A12 A13 /WE I/O8
G I/O8 /WE A13 A12 NC I/O16
H NC A8 A9 A10 A11 NC H NC A11 A10 A9 A8 NC
A0 to A16
: Address inputs
I/O1 to I/O16 : Data inputs / outputs
/CS
:
Chip
Select
/WE
:
Write
Enable
/OE
:
Output
Enable
/LB, /UB
: Byte data select
V
CC
:
Power
supply
GND
:
Ground
NC
:
No
Connection
Remark Refer to Package Drawing for the index mark.
Data Sheet M14670EJ7V
1DS
4
PD442002-X
Block Diagram
Address buffer
Address
buffer
Row
decoder
Memory cell array
2,097,152 bits
Input data
controller
A0
A16
I/O9 to I/O16
Column decoder
/CS
/WE
/OE
/UB
/LB
Output data
controller
I/O1 to I/O8
V
CC
GND
Sense amplifier /
Switching circuit
Data Sheet M14670EJ7V
1DS
5
PD442002-X
Truth Table
/CS /OE /WE /LB /UB
Mode
I/O
Supply
current
I/O1 to I/O8
I/O9 to I/O16
H
Not
selected
High-Z
High-Z
I
SB
H H Not
selected
High-Z
High-Z
L H H L
Output
disable
High-Z
High-Z
I
CCA
L Output
disable
High-Z
High-Z
L H L L Word
read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High-Z
H
L
Upper byte read
High-Z
D
OUT
L L L Word
write
D
IN
D
IN
L
H
Lower byte write
D
IN
High-Z
H
L
Upper byte write
High-Z
D
IN
Remark
: V
IH
or V
IL
Data Sheet M14670EJ7V
1DS
6
PD442002-X
Electrical Specifications
Absolute Maximum Ratings
Parameter Symbol
Condition
Rating
Unit
-BB70X, -BC70X
-DD85X, -DD10X
Supply voltage
V
CC
0.5
Note
to +4.0
0.5
Note
to +2.7
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+0.4 (4.0 V MAX.) 0.5
Note
to V
CC
+0.4 (2.7 V MAX.)
V
Operating ambient temperature
T
A
25 to +85
25 to +85
C
Storage temperature
T
stg
55 to +125
55 to +125
C
Note 3.0 V (MIN.) (Pulse width : 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol
Condition -BB70X -BC70X
-DD85X,
-DD10X
Unit
MIN. MAX. MIN. MAX. MIN. MAX.
Supply voltage
V
CC
2.7 3.6 2.2 3.6 1.8 2.2 V
High level input voltage
V
IH
2.7
V
V
CC
3.6 V
2.4
V
CC
+0.4
2.4 V
CC
+0.4
V
2.2
V
V
CC
< 2.7 V
2.0
V
CC
+0.3
1.8
V
V
CC
< 2.2 V
1.6
V
CC
+0.2
Low level input voltage
V
IL
0.3
Note
+0.5 0.3
Note
+0.4 0.2
Note
+0.2
V
Operating ambient
T
A
25 +85 25 +85 25 +85
C
temperature
Note 1.0 V (MIN.) (Pulse width : 20 ns)
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter Symbol
Test
condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
8
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks 1. V
IN
: Input voltage
V
I/O
: Input / Output voltage
2. These parameters are not 100% tested.
Data Sheet M14670EJ7V
1DS
7
PD442002-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter Symbol
Test
condition
-BB70X
Unit
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CS = V
IL
, I
I/O
= 0 mA, Minimum cycle time
30
mA
I
CCA2
/CS = V
IL
, I
I/O
= 0 mA, Cycle time =
4
I
CCA3
/CS
0.2 V, Cycle time = 1
s, I
I/O
= 0 mA,
4
V
IL
0.2 V, V
IH
V
CC
0.2 V
Standby supply current
I
SB
/CS = V
IH
or /LB = /UB = V
IH
0.6
mA
I
SB1
/CS
V
CC
0.2 V
0.3
4
A
I
SB2
/LB = /UB
V
CC
0.2 V, /CS
0.2 V
0.3
4
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
Remark V
IN
: Input voltage
V
I/O
: Input / Output voltage
Data Sheet M14670EJ7V
1DS
8
PD442002-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter Symbol Test
condition
-BC70X -DD85X,
-DD10X
Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0 +1.0
1.0 +1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or
1.0 +1.0
1.0 +1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA1
/CS = V
IL
, I
I/O
= 0 mA,
30
mA
Minimum cycle time
V
CC
2.7 V
25
V
CC
2.2 V
15
I
CCA2
/CS = V
IL
, I
I/O
= 0 mA,
4
Cycle time =
V
CC
2.7 V
2
V
CC
2.2 V
1
I
CCA3
/CS
0.2 V, Cycle time = 1
s,
4
I
I/O
= 0 mA, V
IL
0.2 V, V
CC
2.7 V
3
V
IH
V
CC
0.2 V
V
CC
2.2 V
3
Standby supply current
I
SB
/CS = V
IH
or /LB = /UB = V
IH
0.6 mA
V
CC
2.7 V
0.6
V
CC
2.2 V
0.6
I
SB1
/CS
V
CC
0.2 V
0.3
4
A
V
CC
2.7 V
0.25
3.5
V
CC
2.2 V
0.2
3
I
SB2
/LB = /UB
V
CC
0.2 V,
0.3
4
/CS
0.2 V
V
CC
2.7 V
0.25
3.5
V
CC
2.2 V
0.2
3
High level output voltage
V
OH
I
OH
= 0.5 mA
2.4
V
V
CC
2.7 V
1.8
V
CC
2.2 V
1.5
Low level output voltage
V
OL
I
OL
= 1.0 mA
0.4
V
V
CC
2.7 V
0.4
V
CC
2.2 V
0.4
Remark V
IN
: Input voltage
V
I/O
: Input / Output voltage
Data Sheet M14670EJ7V
1DS
9
PD442002-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input Waveform (Rise and Fall Time
5 ns)
0.1
V
CC
0.9
V
CC
Test points
V
CC
/2
V
CC
/2
Output Waveform
Test points
V
CC
/2
V
CC
/2
Output Load
[ -BB70X ]
1TTL + 50 pF
[ -BC70X, -DD85X, -DD10X ]
1TTL + 30 pF
Data Sheet M14670EJ7V
1DS
10
PD442002-X
Read Cycle (1/2)
Parameter Symbol
V
CC
2.7 V
Unit
Condition
-BB70X
MIN. MAX.
Read cycle time
t
RC
70
ns
Address access time
t
AA
70
ns
Note 1
/CS access time
t
ACS
70
ns
/OE to output valid
t
OE
35
ns
/LB, /UB to output valid
t
BA
70
ns
Output hold from address change
t
OH
10
ns
/CS to output in low impedance
t
LZ
10
ns
Note 2
/OE to output in low impedance
t
OLZ
5
ns
/LB, /UB to output in low impedance
t
BLZ
10
ns
/CS to output in high impedance
t
HZ
25
ns
/OE to output in high impedance
t
OHZ
25
ns
/LB, /UB to output in high impedance
t
BHZ
25
ns
Notes 1. The output load is 1TTL + 50 pF.
2.
The output load is 1TTL + 5 pF.
Read Cycle (2/2)
Parameter Symbol
V
CC
2.2 V
V
CC
1.8 V
Unit
Condition
-BC70X
-DD85X
-DD10X
MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time
t
RC
70 85 100 ns
Address access time
t
AA
70 85 100
ns
Note 1
/CS access time
t
ACS
70 85 100
ns
/OE to output valid
t
OE
35 40 50
ns
/LB, /UB to output valid
t
BA
70 85 100
ns
Output hold from address change
t
OH
10 10 10 ns
/CS to output in low impedance
t
LZ
10 10 10 ns
Note 2
/OE to output in low impedance
t
OLZ
5 5 5
ns
/LB, /UB to output in low impedance
t
BLZ
10 10 10 ns
/CS to output in high impedance
t
HZ
25 30 35
ns
/OE to output in high impedance
t
OHZ
25 30 35
ns
/LB, /UB to output in high impedance
t
BHZ
25 30 35
ns
Notes 1. The output load is 1TTL + 30 pF.
2.
The output load is 1TTL + 5 pF.
Data Sheet M14670EJ7V
1DS
11
PD442002-X
Read Cycle Timing Chart
t
RC
t
OH
t
HZ
t
BLZ
t
BA
t
LZ
t
ACS
t
BHZ
t
AA
High-Z
Data out
/LB, /UB (Input)
/CS (Input)
Address (Input)
I/O (Output)
t
OLZ
t
OE
t
OHZ
/OE (Input)
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M14670EJ7V
1DS
12
PD442002-X
Write Cycle (1/2)
Parameter Symbol
V
CC
2.7 V
Unit
Condition
-BB70X
MIN. MAX.
Write cycle time
t
WC
70
ns
/CS to end of write
t
CW
55
ns
/LB, /UB to end of write
t
BW
55
ns
Address valid to end of write
t
AW
55
ns
Address setup time
t
AS
0
ns
Write pulse width
t
WP
50
ns
Write recovery time
t
WR
0
ns
Data valid to end of write
t
DW
30
ns
Data hold time
t
DH
0
ns
/WE to output in high impedance
t
WHZ
25
ns
Note
Output active from end of write
t
OW
5
ns
Note The output load is 1TTL + 5 pF.
Write Cycle (2/2)
Parameter Symbol
V
CC
2.2 V
V
CC
1.8 V
Unit
Condition
-BC70X
-DD85X
-DD10X
MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time
t
WC
70 85 100 ns
/CS to end of write
t
CW
55 70 80 ns
/LB, /UB to end of write
t
BW
55 70 80 ns
Address valid to end of write
t
AW
55 70 80 ns
Address setup time
t
AS
0 0 0
ns
Write pulse width
t
WP
50 55 60 ns
Write recovery time
t
WR
0 0 0
ns
Data valid to end of write
t
DW
30 35 40 ns
Data hold time
t
DH
0 0 0
ns
/WE to output in high impedance
t
WHZ
25 30 35
ns
Note
Output active from end of write
t
OW
5 5 5
ns
Note The output load is 1TTL + 5 pF.
Data Sheet M14670EJ7V
1DS
13
PD442002-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW
t
BW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High-Z
High-Z
Data in
Indefinite data out
Address (Input)
/CS (Input)
/LB, /UB (Input)
I/O (Input / Output)
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1. Write operation is done during the overlap time of a low level /CS, a low level /WE and a low
level /LB (or low level /UB).
2. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins
will remain high impedance state.
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Data Sheet M14670EJ7V
1DS
14
PD442002-X
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
t
AS
t
CW
t
DW
t
DH
Data in
High-Z
Address (Input)
/CS (Input)
/LB, /UB (Input)
I/O (Input)
High-Z
t
AW
t
WP
t
WR
/WE (Input)
t
BW
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or
low level /UB).
Data Sheet M14670EJ7V
1DS
15
PD442002-X
Write Cycle Timing Chart 3 (/LB, /UB Controlled)
t
WC
t
DW
t
DH
Data in
High-Z
Address (Input)
/LB, /UB (Input)
I/O (Input)
High-Z
t
AW
t
WP
t
WR
/WE (Input)
t
AS
t
BW
/CS (Input)
t
CW
Cautions 1. During address transition, at least one of pins /CS, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remark Write operation is done during the overlap time of a low level /CS, a low level /WE and a low level /LB (or
low level /UB).
Data Sheet M14670EJ7V
1DS
16
PD442002-X
Low V
CC
Data Retention Characteristics (T
A
= 25 to +85
C)
Parameter
Symbol
Test Condition
-BB70X
-BC70X
-DD85X, -DD10X
Unit
MIN. TYP. MAX. MIN. TYP. MAX.
MIN.
TYP.
MAX.
Data retention
V
CCDR1
/CS
V
CC
- 0.2
V
1.0 3.6
1.0 3.6
1.0 2.2 V
supply voltage
V
CCDR2
/LB = /UB
V
CC
- 0.2
V,
1.0 3.6
1.0 3.6
1.0 2.2
/CS
0.2 V
Data retention
I
CCDR1
V
CC
= 1.2 V, /CS
V
CC
-
0.2
V
0.15 2 0.15 2 0.15 2
A
supply current
I
CCDR2
V
CC
= 1.2 V,
0.15
2
0.15
2
0.15
2
/LB = /UB
V
CC
- 0.2 V,
/CS
0.2 V
Chip deselection
t
CDR
0 0 0 ns
to
data
retention
mode
Operation
t
R
t
RC
Note
t
RC
Note
t
RC
Note
ns
recovery time
Note t
RC
: Read cycle time
Data Sheet M14670EJ7V
1DS
17
PD442002-X
Data Retention Timing Chart
(1) /CS Controlled
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
/CS
/CS
V
CC
0.2 V
GND
V
CC
(MIN.)
Note
t
CDR
Data retention mode
t
R
V
CC
Note 2.7 V (-BB70X), 2.2 V (-BC70X), 1.8 V (-DD85X, -DD10X)
Remark On the data retention mode by controlling /CS, the other pins (Address, I/O, /WE, /OE, /LB, /UB) can be
in high impedance state.
(2) /LB, /UB Controlled
t
CDR
Data retention mode
V
IH
(MIN.)
V
CCDR
(MIN.)
V
IL
(MAX.)
t
R
/LB, /UB
/LB, /UB
V
CC
0.2 V
GND
V
CC
V
CC
(MIN.)
Note
Note 2.7 V (-BB70X), 2.2 V (-BC70X), 1.8 V (-DD85X, -DD10X)
Remark On the data retention mode by controlling /LB and /UB, the input level of /CS must be
V
CC
- 0.2 V
or
0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state.
Data Sheet M14670EJ7V
1DS
18
PD442002-X
Package Drawing
S
w
B
S
w
A
6
5
4
3
2
1
A
B
A
B
C
D
E
F
G
H
S
y
S
y1
M
S
b
x
A B
S
48-PIN TAPE FBGA (8x6)
ITEM
MILLIMETERS
D
E
8.0
0.1
6.0
0.1
w
A
0.2
0.94
0.10
b
x
0.08
y
0.1
e
0.75
A1
0.24
0.05
A2
0.70
0.40
0.05
INDEX MARK
INDEX MARK
A
A2
A1
ZE
ZD
y1
0.2
ZD
1.125
ZE
1.375
P48F9-75-BC2
e
E
D
Data Sheet M14670EJ7V
1DS
19
PD442002-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD442002-X.
Types of Surface Mount Device
PD442002F9-BC2-A
Note
: 48-pin TAPE FBGA (8x6)
Note Lead-free product
Data Sheet M14670EJ7V
1DS
20
PD442002-X
Revision History
Edition/ Page Type
of
Location
Description
Date
Previous
This
revision
(Previous edition
This edition)
edition
edition
7th edition/
Throughout
Throughout
Deletion
Class
-BB55X, -BB85X, -BC85X, -BC10X, -DD12X
Dec. 2003
p.2, 21
p.2, 19
Modification Package code
F9-BC1
F9-BC2-A
Addition
"Note Lead-free product" has been added.
p.2
p.2
Modification Marking image
Lead-free mark has been added.
Index mark has been modified.
p.20
p.18
Modification Package Drawing
Package drawing has been changed
Data Sheet M14670EJ7V
1DS
21
PD442002-X
[ MEMO ]
Data Sheet M14670EJ7V
1DS
22
PD442002-X
[ MEMO ]
Data Sheet M14670EJ7V1DS
23
PD442002-X
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
NOTES FOR CMOS DEVICES
PD442002-X
The information in this document is current as of July, 2004. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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