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MOS INTEGRATED CIRCUIT

PD44321181, 44321361

32M-BIT ZEROSB

SRAM

FLOW THROUGH OPERATION

Document No. M15958EJ5V0DS00 (5th edition)
Date Published April 2005 NS CP(K)
Printed in Japan

DATA SHEET

The mark shows major revised points.

2002, 2005

Description

The

PD44321181 is a 2,097,152-word by 18-bit and the

PD44321361 is a 1,048,576-word by 36-bit ZEROSB

static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.

The

PD44321181 and

PD44321361 are optimized to eliminate dead cycles for read to write, or write to read

transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and
output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input
(CLK).

The

PD44321181 and

PD44321361 are suitable for applications which require synchronous operation, high

speed, low voltage, high density and wide bit configuration, such as buffer memory.

ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State

("Sleep"). In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes
normal operation.

The

PD44321181 and

PD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.4 mm package thickness

for high density and low capacitive loading.

Features

· Low voltage core supply: V

= 3.3 ± 0.165 V / 2.5 ± 0.125 V

· Synchronous operation
· 100 percent bus utilization
· Internally self-timed write control
· Burst read / write : Interleaved burst and linear burst sequence
· Fully registered inputs and outputs for flow through operation
· All registers triggered off positive clock edge
· 3.3V or 2.5V LVTTL Compatible : All inputs and outputs
· Fast clock access time : 7.5 ns (117 MHz)
· Asynchronous output enable : /G
· Burst sequence selectable : MODE
· Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
· Separate byte write enable : /BW1 to /BW4 (

PD44321361)

/BW1 and /BW2 (

PD44321181)

· Three chip enables for easy depth expansion
· Common I/O using three state outputs

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Pin Configurations

××× indicates active low signal.

100-pin PLASTIC LQFP (14

× 20)

[

PD44321181GF]

Marking Side

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/OP2

A20

I/OP1

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

/CE

CE2

/BW2

/BW1

/CE2

CLK

/WE

/CKE

ADV

A18

A17

MODE

A19

A10

A11

A12

A13

A14

A15

A16

Remark Refer to Package Drawing for the 1-pin index mark.

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Pin Identifications

[

PD44321181GF]

Symbol Pin

No.

Description

A0 to A20

37, 36, 35, 34, 33, 32, 100, 99, 82, 81,

Synchronous Address Input

44, 45, 46, 47, 48, 49, 50, 83, 84, 43, 80

I/O1 to I/O16

58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,

18, 19, 22, 23

Synchronous / Asynchronous Data Out

I/OP1, I/OP2

74, 24

Synchronous Data In (Parity),

Synchronous / Asynchronous Data Out (Parity)

ADV

Synchronous Address Load / Advance Input

/CE, CE2, /CE2

98, 97, 92

Synchronous Chip Enable Input

/WE

Synchronous Write Enable Input

/BW1, /BW2

93, 94

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

CLK 89

Clock

Input

/CKE

Synchronous Clock Enable Input

MODE

Asynchronous Burst Sequence Select Input

Have to tied to V

or V

during normal operation

Asynchronous Power Down State Input

15, 16, 41, 65, 91

Power Supply

14, 17, 40, 66, 67, 90

Ground

4, 11, 20, 27, 54, 61, 70, 77

Output Buffer Power Supply

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Ground

1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42,

No Connection

51, 52, 53, 56, 57, 75, 78, 79, 95, 96

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

100-pin PLASTIC LQFP (14

× 20)

[

PD44321361GF]

Marking Side

I/OP3

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

I/OP4

I/OP2

I/O16

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/OP1

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

/CE

CE2

/BW4

/BW3

/BW2

/BW1

/CE2

CLK

/WE

/CKE

ADV

A18

A17

MODE

A19

A10

A11

A12

A13

A14

A15

A16

Remark Refer to Package Drawing for the 1-pin index mark.

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Pin Identifications

[

PD44321361GF]

Symbol Pin

No.

Description

A0 to A19

37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input

45, 46, 47, 48, 49, 50, 83, 84, 43

I/O1 to I/O32

52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, Synchronous Data In,

73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13,

Synchronous / Asynchronous Data Out

18, 19, 22, 23, 24, 25, 28, 29

I/OP1 to I/OP4

51, 80, 1, 30

Synchronous Data In (Parity),

Synchronous / Asynchronous Data Out (Parity)

ADV

Synchronous Address Load / Advance Input

/CE, CE2, /CE2

98, 97, 92

Synchronous Chip Enable Input

/WE

Synchronous Write Enable Input

/BW1 to /BW4

93, 94, 95, 96

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

CLK 89

Clock

Input

/CKE

Synchronous Clock Enable Input

MODE

Asynchronous Burst Sequence Select Input

Have to tied to V

or V

during normal operation

Asynchronous Power Down State Input

15, 16, 41, 65, 91

Power Supply

14, 17, 40, 66, 67, 90

Ground

4, 11, 20, 27, 54, 61, 70, 77

Output Buffer Power Supply

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Ground

38, 39, 42

No Connection

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Block Diagrams

[

PD44321181]

A0 to A20

MODE

CLK

/CKE

ADV

/BW1
/BW2

/WE

/CE

CE2

/CE2

Address
register 0

Burst

logic

Write address
register

Write registry and

data coherency

control logic

Write

drivers

Data steering

ADV

Memory Cell Array

2,048 x 18 columns

(37,748,736 bits)

A1'

A0'

Sense amplifiers

Read

logic

Input
register E

Output buffers

I/O1 to I/O16

I/OP1, I/OP2

Power down control

1,024 rows

Burst Sequence

[

PD44321181]

Interleaved Burst Sequence Table (MODE = V

)

External Address

A20 to A2, A1, A0

1st Burst Address

A20 to A2, A1, /A0

2nd Burst Address

A20 to A2, /A1, A0

3rd Burst Address

A20 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = V

)

External Address

A20 to A2, 0, 0

A20 to A2, 0, 1

A20 to A2, 1, 0

A20 to A2, 1, 1

1st Burst Address

A20 to A2, 0, 1

A20 to A2, 1, 0

A20 to A2, 1, 1

A20 to A2, 0, 0

2nd Burst Address

A20 to A2, 1, 0

A20 to A2, 1, 1

A20 to A2, 0, 0

A20 to A2, 0, 1

3rd Burst Address

A20 to A2, 1, 1

A20 to A2, 0, 0

A20 to A2, 0, 1

A20 to A2, 1, 0

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

[

PD44321361]

A0 to A19

MODE

CLK

/CKE

ADV

/BW1
/BW2

/WE

/CE

CE2

/CE2

Address
register 0

Burst

logic

Write address
register

Write registry and

data coherency

control logic

Write

drivers

Data steering

ADV

A1'

A0'

Sense amplifiers

Read

logic

Input
register E

Output buffers

I/O1 to I/O32

I/OP1 to I/OP4

/BW3
/BW4

Power down control

Memory Cell Array

1,024 x 36 columns

(37,748,736 bits)

1,024 rows

Burst Sequence

[

PD44321361]

Interleaved Burst Sequence Table (MODE = V

)

External Address

A19 to A2, A1, A0

1st Burst Address

A19 to A2, A1, /A0

2nd Burst Address

A19 to A2, /A1, A0

3rd Burst Address

A19 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = V

)

External Address

A19 to A2, 0, 0

A19 to A2, 0, 1

A19 to A2, 1, 0

A19 to A2, 1, 1

1st Burst Address

A19 to A2, 0, 1

A19 to A2, 1, 0

A19 to A2, 1, 1

A19 to A2, 0, 0

2nd Burst Address

A19 to A2, 1, 0

A19 to A2, 1, 1

A19 to A2, 0, 0

A19 to A2, 0, 1

3rd Burst Address

A19 to A2, 1, 1

A19 to A2, 0, 0

A19 to A2, 0, 1

A19 to A2, 1, 0

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Asynchronous Truth Table

Operation /G

I/O

Read Cycle

Data-Out

Read Cycle

High-Z

Write Cycle

× High-Z,

Data-In

Deselected

× High-Z

Remark

× : don't care

Synchronous Truth Table

Operation

/CE CE2 /CE2 ADV /WE /BWs

/CKE CLK

I/O

Address Note

Deselected H

× L ×

× L L

High-Z

None

Deselected

× L × L ×

× L L

High-Z

None

Deselected

× H L ×

× L L

High-Z

None

Continue Deselected

× H ×

× L L

High-Z

None

Read Cycle / Begin Burst

× L L

Data-Out

External

Read Cycle / Continue Burst

× H ×

× L L

Data-Out

Write Cycle / Begin Burst

Data-In

External

Write Cycle / Continue Burst

× H × L L L

Data-In

Write Cycle / Write Abort

High-Z

External

Write Cycle / Write Abort

× H × H L L

High-Z

Stall / Ignore Clock Edge

× H L

- Current 2

Notes 1.

Deselect status is held until new "Begin Burst" entry.

2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (Low

impedance). If it occurs during a write cycle, the bus will remain High impedance. No write operation will

be performed during the Ignore Clock Edge cycle.

Remarks 1.

× : don't care

/BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.

/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Partial Truth Table for Write Enables

[

PD44321181]

Operation /WE

/BW1

/BW2

Read Cycle

Write Cycle / Byte 1 (I/O [1:8], I/OP1)

Write Cycle / Byte 2 (I/O [9:16], I/OP2)

Write Cycle / All Bytes

Write Abort / NOP

Remark

× : don't care

[

PD44321361]

Operation

/WE /BW1 /BW2 /BW3 /BW4

Read Cycle

Write Cycle / Byte 1 (I/O [1:8], I/OP1)

Write Cycle / Byte 2 (I/O [9:16], I/OP2)

Write Cycle / Byte 3 (I/O [17:24], I/OP3)

Write Cycle / Byte 4 (I/O [25:32], I/OP4)

Write Cycle / All Bytes

Write Abort / NOP

Remark

× : don't care

ZZ (Sleep) Truth Table

ZZ Chip

Status

0.2 V

Active

Open Active

- 0.2 V

Sleep

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Electrical Specifications

Absolute Maximum Ratings

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

0.5

+4.0

Output supply voltage

0.5

Input voltage

0.5

Note

+ 0.5

Input / Output voltage

I/O

0.5

Note

+ 0.5

Operating ambient

°C

temperature

Storage temperature

stg

+125

°C

Note 2.0 V (MIN.) (Pulse width : 2 ns)

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions (V

= 3.3 ± 0.165 V)

(1/2)

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

3.135

3.3

3.465

2.5 V LVTTL Interface

Output supply voltage

Q 2.375

2.5

2.9

High level input voltage

2.0

+ 0.3

Low level input voltage

0.3

Note

+0.7 V

3.3 V LVTTL Interface

Output supply voltage

Q 3.135

3.3

3.465

High level input voltage

2.0

+ 0.3

Low level input voltage

0.3

Note

+0.8 V

Note 0.8 V (MIN.) (Pulse width : 2 ns)

Recommended DC Operating Conditions (V

= 2.5 ± 0.125 V)

(2/2)

Parameter Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

2.375 2.5 2.625 V

Output supply voltage

2.375 2.5 2.625 V

High level input voltage

1.7

+ 0.3

Low level input voltage

0.3

Note

+0.7 V

Note 0.8 V (MIN.) (Pulse width : 2 ns)

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

DC Characteristics (V

= 3.3 ± 0.165 V or 2.5 ± 0.125 V)

Parameter Symbol

Test

condition

MIN.

TYP.

MAX.

Unit

Input leakage current

(except ZZ, MODE) = 0 V to V

2 +2

I/O leakage current

I/O

= 0 V to V

Q, Outputs are disabled.

Operating supply current

Device selected, Cycle = MAX.

290

or V

, I

I/O

= 0 mA

Standby supply current

Device deselected, Cycle = 0 MHz,

or V

, All inputs are static.

SB1

Device deselected, Cycle = 0 MHz,

0.2 V or V

0.2 V,

I/O

0.2 V, All inputs are static.

SB2

Device deselected, Cycle = MAX.

110

or V

Power down supply current

SBZZ

0.2 V, V

I/O

Q + 0.2 V

2.5 V LVTTL Interface

High level output voltage

= 2.0 mA

1.7

= 1.0 mA

2.1

Low level output voltage

= +2.0 mA

0.7

= +1.0 mA

0.4

3.3 V LVTTL Interface

High level output voltage

= 4.0 mA

2.4

Low level output voltage

= +8.0 mA

0.4

Capacitance (T

= 25

°C, f = 1MHz)

Parameter Symbol

Test

condition

MIN.

TYP.

MAX.

Unit

Input capacitance

= 0 V

6.0

Input / Output capacitance

I/O

= 0 V

8.0

Clock input capacitance

clk

= 0 V

6.0

Remark These parameters are periodically sampled and not 100

% tested.

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

Read and Write Cycle

Parameter

Symbol

-A75 (117 MHz)

Unit

Notes

Standard

Alias

MIN.

MAX.

Cycle time

TKHKH

TCYC

8.6

Clock access time

TKHQV

TCD

7.5

Output enable access time

TGLQV

TOE

3.5

Clock high to output active

TKHQX1

TDC1

2.5

1, 2

Clock high to output change

TKHQX2

TDC2

2.5

Output enable to output active

TGLQX

TOLZ

Output disable to output High-Z

TGHQZ

TOHZ

3.5

Clock high to output High-Z

TKHQZ

TCZ

2.5

1, 2

Clock high pulse width

TKHKL

TCH

2.5

Clock low pulse width

TKLKH

TCL

2.5

Setup times

Address

TAVKH

TAS

1.5

Address

advance

TADVVKH

TADVS

Clock

enable

TEVKH

TCES

Chip

enable

TCVKH

TCSS

Data

in TDVKH

TDS

Write

enable

TWVKH

TWS

Hold times

Address

TKHAX

TAH

0.5

Address

advance

TKHADVX

TADVH

(1.0)

()

Clock

enable

TKHEX

TCEH

Chip

enable

TKHCX

TCSH

Data

TKHDX TDH

Write

enable

TKHWX

TWH

Power down entry time

TZZE

8.6

Power down recovery time

TZZR

8.6

Notes 1. Transition is measured

±200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus

contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T

min.,

max.) than TKHQZ, which is a max. parameter (worse case at T

max., V

min.).

3. These values apply when V

= 3.3 V

±0.165 V with a 3.3 V LVTTL interface, or when V

= 2.5 V

±0.125 V with a 2.5 V LVTTL interface.

Values in parentheses apply when V

= 3.3 V

±0.165 V with a 2.5 V LVTTL interface.

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

READ / WRITE CYCLE

WRITE

D (A1)

CLK

/CKE

/CEs

ADV

/WE

Data In

Data Out

/BWs

Address

Command

D (A1)

D (A2)

D (A2+1)

D (A5)

Q (A3)

Q (A4)

Q (A4+1)

Q (A6)

Q (A7)

WRITE

D (A2)

BURST

WRITE

D (A2+1)

READ

Q (A3)

READ

Q (A4)

BURST

READ

Q (A4+1)

WRITE

D (A5)

READ

Q (A6)

WRITE

Q (A7)

DESELECT

TKHKH

TEVKH

TKHEX

TCVKH TKHCX

TKLKH

TDVKH

TKHDX

TKHQX1

TKHQV

TKHQX2

TGHQZ

TGLQX

TKHQX2

TGLQV TKHQZ

TKHKL

TADVVKH TKHADVX

TWVKH TKHWX

Note 1

Note 2

TAVKH

TKHAX

High-Z

Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When

/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.

2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables

(/BW1, /BW2, /BW3 or /BW4) are LOW.

Data Sheet M15958EJ5V0DS

PD44321181, 44321361

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

(MAX) and V

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MAX) and

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD44321181, 44321361

ZEROSB is a trademark of NEC Electronics Corporation.

The information in this document is current as of April, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.

(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

Document Outline

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Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD44321181