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MOS INTEGRATED CIRCUIT

PD4481162, 4481182, 4481322, 4481362

8M-BIT ZEROSB

SRAM

PIPELINED OPERATION

Document No. M15562EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan

DATA SHEET

The mark shows major revised points.

2001

Description

The

µPD4481162 is a 524,288-word by 16-bit, the µPD4481182 is a 524,288-word by 18-bit, the µPD4481322 is a

262,144-word by 32-bit and the

µPD4481362 is a 262,144-word by 36-bit ZEROSB static RAM fabricated with

advanced CMOS technology using full CMOS six-transistor memory cell.
The

µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are optimized to eliminate dead cycles for read to

write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit
burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the
single clock input (CLK).
The

µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are suitable for applications which require

synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep").
In the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal
operation.
The

µPD4481162, µPD4481182, µPD4481322 and µPD4481362 are packaged in 100-pin PLASTIC LQFP with a 1.4

mm package thickness for high density and low capacitive loading.

Features

· Low voltage core supply : V

= 3.3 ± 0.165 V (-A44, -A50, -A60, -A75, -A44Y, -A50Y, -A60Y, -A75Y)

= 2.5 ± 0.125 V (-C60, -C75, -C60Y, -C75Y)

· Synchronous operation
· Operating temperature : T

= 0 to 70

°C (-A44, -A50, -A60, -A75, -C60, -C75)

-40 to +85 °C (-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y)

· 100 percent bus utilization
· Internally self-timed write control
· Burst read / write : Interleaved burst and linear burst sequence
· Fully registered inputs and outputs for pipelined operation
· All registers triggered off positive clock edge
· 3.3V or 2.5V LVTTL Compatible : All inputs and outputs
· Fast clock access time : 2.8 ns (225 MHz), 3.2 ns (200 MHz), 3.5 ns (167 MHz) , 4.2 ns (133 MHz)
· Asynchronous output enable : /G
· Burst sequence selectable : MODE
· Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
· Separate byte write enable : /BW1 to /BW4 (

µPD4481322 and µPD4481362)

/BW1 and /BW2 (

µPD4481162 and µPD4481182)

· Three chip enables for easy depth expansion
· Common I/O using three state outputs

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Ordering Information

(1/2)

Part number

Access

Clock

Core Supply

I/O Interface

Operating

Package

Time

Frequency

Voltage

Temperature

MHz

°C

µPD4481162GF-A44

2.8

225

3.3 ± 0.165

3.3 V LVTTL

Note

0 to 70

100-pin PLASTIC

µPD4481162GF-A50

3.2

200

LQFP (14 x 20)

µPD4481162GF-A60

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481162GF-A75

4.2

133

µPD4481182GF-A44

2.8

225

3.3 V LVTTL

Note

µPD4481182GF-A50

3.2

200

µPD4481182GF-A60

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481182GF-A75

4.2

133

µPD4481322GF-A44

2.8

225

3.3 V LVTTL

Note

µPD4481322GF-A50

3.2

200

µPD4481322GF-A60

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481322GF-A75

4.2

133

µPD4481362GF-A44

2.8

225

3.3 V LVTTL

Note

µPD4481362GF-A50

3.2

200

µPD4481362GF-A60

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481362GF-A75

4.2

133

µPD4481162GF-C60

3.5

167

2.5 ± 0.125

2.5 V LVTTL

µPD4481162GF-C75

4.2

133

µPD4481182GF-C60

3.5

167

µPD4481182GF-C75

4.2

133

µPD4481322GF-C60

3.5

167

µPD4481322GF-C75

4.2

133

µPD4481362GF-C60

3.5

167

µPD4481362GF-C75

4.2

133

Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60 (167 MHz).

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

(2/2)

Part number

Access

Clock

Core Supply

I/O Interface

Operating

Package

Time

Frequency

Voltage

Temperature

MHz

°C

µPD4481162GF-A44Y

2.8

225

3.3 ± 0.165

3.3 V LVTTL

Note

-40 to +85

100-pin PLASTIC

µPD4481162GF-A50Y

3.2

200

LQFP (14 x 20)

µPD4481162GF-A60Y

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481162GF-A75Y

4.2

133

µPD4481182GF-A44Y

2.8

225

3.3 V LVTTL

Note

µPD4481182GF-A50Y

3.2

200

µPD4481182GF-A60Y

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481182GF-A75Y

4.2

133

µPD4481322GF-A44Y

2.8

225

3.3 V LVTTL

Note

µPD4481322GF-A50Y

3.2

200

µPD4481322GF-A60Y

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481322GF-A75Y

4.2

133

µPD4481362GF-A44Y

2.8

225

3.3 V LVTTL

Note

µPD4481362GF-A50Y

3.2

200

µPD4481362GF-A60Y

3.5

167

3.3 V or 2.5 V LVTTL

µPD4481362GF-A75Y

4.2

133

µPD4481162GF-C60Y

3.5

167

2.5 ± 0.125

2.5 V LVTTL

µPD4481162GF-C75Y

4.2

133

µPD4481182GF-C60Y

3.5

167

µPD4481182GF-C75Y

4.2

133

µPD4481322GF-C60Y

3.5

167

µPD4481322GF-C75Y

4.2

133

µPD4481362GF-C60Y

3.5

167

µPD4481362GF-C75Y

4.2

133

Note Although 2.5V LVTTL interface can also be used, a performance becomes equivalent to -A60Y (167 MHz).

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Pin Configurations

××× indicates active low signal.

100-pin PLASTIC LQFP (14

×
×
×
× 20)

[

µ
µ
µ
µPD4481162GF, µµµµPD4481182GF]

Marking Side

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/OP2, NC

A18

I/OP1, NC

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

/CE

CE2

/BW2

/BW1

/CE2

CLK

/WE

/CKE

ADV

A17

MODE

A10

A11

A12

A13

A14

A15

A16

Remark Refer to Package Drawing for the 1-pin index mark.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Pin Identifications

[

µ
µ
µ
µPD4481162GF, µµµµPD4481182GF]

Symbol

Pin No.

Description

A0 to A18

37, 36, 35, 34, 33, 32, 100, 99, 82, 81,

Synchronous Address Input

44, 45, 46, 47, 48, 49, 50, 83, 80

I/O1 to I/O16

58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, Synchronous Data In,

18, 19, 22, 23

Synchronous / Asynchronous Data Out

I/OP1, NC

Note

Synchronous Data In (Parity),

I/OP2, NC

Note

Synchronous / Asynchronous Data Out (Parity)

ADV

Synchronous Address Load / Advance Input

/CE, CE2, /CE2

98, 97, 92

Synchronous Chip Enable Input

/WE

Synchronous Write Enable Input

/BW1, /BW2

93, 94

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

CLK

Clock Input

/CKE

Synchronous Clock Enable Input

MODE

Asynchronous Burst Sequence Select Input

Have to tied to V

or V

during normal operation

Asynchronous Power Down State Input

14, 15, 16, 41, 65, 66, 91

Power Supply

17, 40, 67, 90

Ground

4, 11, 20, 27, 54, 61, 70, 77

Output Buffer Power Supply

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Ground

1, 2, 3, 6, 7, 25, 28, 29, 30, 38, 39, 42, 43, No Connection

51, 52, 53, 56, 57, 75, 78, 79, 84, 95, 96

Note NC (No Connection) is used in the

µPD4481162GF.

I/OP1 and I/OP2 are used in the

µPD4481182GF.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

100-pin PLASTIC LQFP (14

×
×
×
× 20)

[

µ
µ
µ
µPD4481322GF, µµµµPD4481362GF]

Marking Side

I/OP3, NC

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

I/OP4, NC

I/OP2, NC

I/O16

I/O15

I/O14

I/O13

I/O12

I/O11

I/O10

I/O9

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/OP1, NC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

/CE

CE2

/BW4

/BW3

/BW2

/BW1

/CE2

CLK

/WE

/CKE

ADV

A17

MODE

A10

A11

A12

A13

A14

A15

A16

Remark Refer to Package Drawing for the 1-pin index mark.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[

µ
µ
µ
µPD4481322GF, µµµµPD4481362GF]

Symbol

Pin No.

Description

A0 to A17

37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, Synchronous Address Input

45, 46, 47, 48, 49, 50, 83

I/O1 to I/O32

52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72,

Synchronous Data In,

73, 74, 75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13,

Synchronous / Asynchronous Data Out

18, 19, 22, 23, 24, 25, 28, 29

I/OP1, NC

Note

Synchronous Data In (Parity),

I/OP2, NC

Note

Synchronous / Asynchronous Data Out (Parity)

I/OP3, NC

Note

I/OP4, NC

Note

ADV

Synchronous Address Load / Advance Input

/CE, CE2, /CE2

98, 97, 92

Synchronous Chip Enable Input

/WE

Synchronous Write Enable Input

/BW1 to /BW4

93, 94, 95, 96

Synchronous Byte Write Enable Input

Asynchronous Output Enable Input

CLK

Clock Input

/CKE

Synchronous Clock Enable Input

MODE

Asynchronous Burst Sequence Select Input

Have to tied to V

or V

during normal operation

Asynchronous Power Down State Input

14, 15, 16, 41, 65, 66, 91

Power Supply

17, 40, 67, 90

Ground

4, 11, 20, 27, 54, 61, 70, 77

Output Buffer Power Supply

5, 10, 21, 26, 55, 60, 71, 76

Output Buffer Ground

38, 39, 42, 43, 84

No Connection

Note NC (No Connection) is used in the

µPD4481322GF.

I/OP1 to I/OP4 are used in the

µPD4481362GF.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Block Diagrams

[

µ
µ
µ
µPD4481162, µ

µPD4481182]

A0 to A18

MODE

CLK

/CKE

ADV

/BW1
/BW2

/WE

/CE

CE2

/CE2

Address

Burst

logic

Write address

Write registry and

data coherency

control logic

Write

drivers

Data steering

ADV

A1'

A0'

Sense amplifiers

Read

logic

Input

Output buffers

I/O1 to I/O16

I/OP1, I/OP2

16/18

Write address

Output registers

Input

16/18

Power down control

Memory Cell Array

512 x 16 columns

(8,388,608 bits)

512 x 18 columns

(9,437,184 bits)

1,024 rows

Burst Sequence

[

µ
µ
µ
µPD4481162, µ

µPD4481182]

Interleaved Burst Sequence Table (MODE = V

)

External Address

A18 to A2, A1, A0

1st Burst Address

A18 to A2, A1, /A0

2nd Burst Address

A18 to A2, /A1, A0

3rd Burst Address

A18 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = V

)

External Address

A18 to A2, 0, 0

A18 to A2, 0, 1

A18 to A2, 1, 0

A18 to A2, 1, 1

1st Burst Address

A18 to A2, 0, 1

A18 to A2, 1, 0

A18 to A2, 1, 1

A18 to A2, 0, 0

2nd Burst Address

A18 to A2, 1, 0

A18 to A2, 1, 1

A18 to A2, 0, 0

A18 to A2, 0, 1

3rd Burst Address

A18 to A2, 1, 1

A18 to A2, 0, 0

A18 to A2, 0, 1

A18 to A2, 1, 0

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

[

µ
µ
µ
µPD4481322, µ

µPD4481362]

A0 to A17

MODE

CLK

/CKE

ADV

/BW1
/BW2

/WE

/CE

CE2

/CE2

Address

Burst

logic

Write address

Write registry and

data coherency

control logic

Write

drivers

Data steering

ADV

A1'

A0'

Sense amplifiers

Read

logic

Input

Output buffers

I/O1 to I/O32

I/OP1 to I/OP4

32/36

Write address

Output registers

Input

32/36

/BW3
/BW4

Power down control

Memory Cell Array

256 x 32 columns

(8,388,608 bits)

256 x 36 columns

(9,437,184 bits)

1,024 rows

[

µ
µ
µ
µPD4481322, µ

µPD4481362]

Interleaved Burst Sequence Table (MODE = V

)

External Address

A17 to A2, A1, A0

1st Burst Address

A17 to A2, A1, /A0

2nd Burst Address

A17 to A2, /A1, A0

3rd Burst Address

A17 to A2, /A1, /A0

Linear Burst Sequence Table (MODE = V

)

External Address

A17 to A2, 0, 0

A17 to A2, 0, 1

A17 to A2, 1, 0

A17 to A2, 1, 1

1st Burst Address

A17 to A2, 0, 1

A17 to A2, 1, 0

A17 to A2, 1, 1

A17 to A2, 0, 0

2nd Burst Address

A17 to A2, 1, 0

A17 to A2, 1, 1

A17 to A2, 0, 0

A17 to A2, 0, 1

3rd Burst Address

A17 to A2, 1, 1

A17 to A2, 0, 0

A17 to A2, 0, 1

A17 to A2, 1, 0

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Asynchronous Truth Table

Operation

I/O

Read Cycle

Dout

Read Cycle

High-Z

Write Cycle

High-Z, Din

Deselected

High-Z

Remark

× : don't care

Synchronous Truth Table

Operation

/CE

CE2

/CE2

ADV

/WE

/BWs

/CKE

CLK

I/O

Address

Note

Deselected

High-Z

None

Deselected

High-Z

None

Deselected

High-Z

None

Continue Deselected

High-Z

None

Read Cycle / Begin Burst

Dout

External

Read Cycle / Continue Burst

Dout

Write Cycle / Begin Burst

Din

External

Write Cycle / Continue Burst

Din

Write Cycle / Write Abort

High-Z

External

Write Cycle / Write Abort

High-Z

Stall / Ignore Clock Edge

Current

Notes

1. Deselect status is held until new "Begin Burst" entry.
2. If an Ignore Clock Edge command occurs during a read operation, the I/O bus will remain active (low

impedance). If it occurs during a write cycle, the bus will remain high impedance. No write operation will
be performed during the Ignore Clock Edge cycle.

Remarks 1.

× : don't care

2. /BWs = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) are LOW.

/BWs = H means all byte write enables (/BW1, /BW2, /BW3 or /BW4) are HIGH.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Partial Truth Table for Write Enables

[

µ
µ
µ
µPD4481162, µ

µPD4481182]

Operation

/WE

/BW1

/BW2

Read Cycle

Write Cycle / Byte 1 (I/O [1:8], I/OP1)

Write Cycle / Byte 2 (I/O [9:16], I/OP2)

Write Cycle / All Bytes

Write Abort / NOP

Remark

× : don't care

[

µ
µ
µ
µPD4481322, µ

µPD4481362]

Operation

/WE

/BW1

/BW2

/BW3

/BW4

Read Cycle

Write Cycle / Byte 1 (I/O [1:8], I/OP1)

Write Cycle / Byte 2 (I/O [9:16], I/OP2)

Write Cycle / Byte 3 (I/O [17:24], I/OP3)

Write Cycle / Byte 4 (I/O [25:32], I/OP4)

Write Cycle / All Bytes

Write Abort / NOP

Remark

× : don't care

ZZ (Sleep) Truth Table

Chip Status

0.2 V

Active

Open

Active

- 0.2 V

Sleep

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Electrical Specifications

Absolute Maximum Ratings

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

-A44, -A50, -A60, -A75

0.5

+4.0

-A44Y, -A50Y, -A60Y, -A75Y

-C60, -C75

0.5

+3.0

-C60Y, -C75Y

Output supply voltage

0.5

Input voltage

0.5

Note

+ 0.5

Input / Output voltage

I/O

0.5

Note

+ 0.5

Operating ambient

-A44, -A50, -A60, -A75, -C60, -C75

°C

temperature

-A44Y, -A50Y, -A60Y, -A75Y, -C60Y, -C75Y

+85

Storage temperature

stg

+125

°C

Note 2.0 V (MIN.) (Pulse width : 2 ns)

Caution

Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.

Recommended DC Operating Conditions

(1/2)

Parameter

Symbol

Conditions

-A44, -A50, -A60, -A75

Unit

-A44Y, -A50Y, -A60Y, -A75Y

MIN.

TYP.

MAX.

Supply voltage

3.135

3.3

3.465

2.5 V LVTTL Interface

Output supply voltage

2.375

2.5

2.9

High level input voltage

1.7

+ 0.3

Low level input voltage

0.3

Note

+0.7

3.3 V LVTTL Interface

Output supply voltage

3.135

3.3

3.465

High level input voltage

2.0

+ 0.3

Low level input voltage

0.3

Note

+0.8

Note 0.8 V (MIN.) (Pulse width : 2 ns)

Recommended DC Operating Conditions

(2/2)

Parameter

Symbol

Conditions

-C60, -C75

Unit

-C60Y, -C75Y

MIN.

TYP.

MAX.

Supply voltage

2.375

2.5

2.625

Output supply voltage

2.375

2.5

2.625

High level input voltage

1.7

+ 0.3

Low level input voltage

0.3

Note

+0.7

Note 0.8 V (MIN.) (Pulse width : 2 ns)

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

DC Characteristics (V

= 3.3 ± 0.165 V or 2.5 ± 0.125 V)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Input leakage current

(except ZZ, MODE) = 0 V to V

µA

I/O leakage current

I/O

= 0 V to V

Q, Outputs are disabled.

µA

Operating supply current

Device selected,

-A44

440

Cycle = MAX.

-A44Y

or V

-A50

400

I/O

= 0 mA

-A50Y

-A60, -C60

320

-A60Y, -C60Y

-A75, -C75

300

-A75Y, -C75Y

Standby supply current

Device deselected, Cycle = 0 MHz,

or V

, All inputs are static.

SB1

Device deselected, Cycle = 0 MHz,

0.2 V or V

0.2 V,

I/O

0.2 V, All inputs are static.

SB2

Device deselected, Cycle = MAX.

130

or V

Power down supply current

SBZZ

0.2 V, V

I/O

Q + 0.2 V

2.5 V LVTTL Interface

High level output voltage

= 2.0 mA

1.7

= 1.0 mA

2.1

Low level output voltage

= +2.0 mA

0.7

= +1.0 mA

0.4

3.3 V LVTTL Interface

High level output voltage

= 4.0 mA

2.4

Low level output voltage

= +8.0 mA

0.4

Capacitance (T

= 25

°
°
°
°C, f = 1MHz)

Parameter

Symbol

Test condition

MIN.

TYP.

MAX.

Unit

Input capacitance

= 0 V

6.0

Input / Output capacitance

I/O

= 0 V

8.0

Clock input capacitance

clk

= 0 V

6.0

Remark These parameters are periodically sampled and not 100

% tested.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Read and Write Cycle (2.5 V LVTTL Interface)

Parameter

Symbol

-A44, -A50, -A60, -C60

-A75, -C75

Unit

Notes

-A44Y, -A50Y, -A60Y, -C60Y

-A75Y, -C75Y

(167 MHz)

(133 MHz)

Standard

Alias

MIN.

MAX.

MIN.

MAX.

Cycle time

TKHKH

TCYC

7.5

Clock access time

TKHQV

TCD

3.5

4.2

Output enable access time

TGLQV

TOE

3.5

4.2

Clock high to output active

TKHQX1

TDC1

1.5

1, 2

Clock high to output change

TKHQX2

TDC2

1.5

Output enable to output active

TGLQX

TOLZ

Output disable to output High-Z

TGHQZ

TOHZ

3.5

4.2

Clock high to output High-Z

TKHQZ

TCZ

1.5

3.5

1.5

3.5

1, 2

Clock high pulse width

TKHKL

TCH

1.8

2.2

Clock low pulse width

TKLKH

TCL

1.8

2.2

Setup times

Address

TAVKH

TAS

1.5

Address advance TADVVKH

TADVS

Clock enable

TEVKH

TCES

Chip enable

TCVKH

TCSS

Data in

TDVKH

TDS

Write enable

TWVKH

TWS

Hold times

Address

TKHAX

TAH

0.5

Address advance TKHADVX

TADVH

Clock enable

TKHEX

TCEH

Chip enable

TKHCX

TCSH

Data in

TKHDX

TDH

Write enable

TKHWX

TWH

Power down entry time

TZZE

Power down recovery time

TZZR

Notes 1. Transition is measured

±200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T

min.,

max.) than TKHQZ, which is a max. parameter (worse case at T

max., V

min.).

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

Read and Write Cycle (3.3 V LVTTL Interface)

Parameter

Symbol

-A44

-A50

-A60

-A75

Unit

Notes

-A44Y

-A50Y

-A60Y

-A75Y

(225 MHz)

(200 MHz)

(167 MHz)

(133 MHz)

Standard

Alias

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Cycle time

TKHKH

TCYC

4.4

7.5

Clock access time

TKHQV

TCD

2.8

3.2

3.5

4.2

Output enable access time

TGLQV

TOE

2.8

3.2

3.5

4.2

Clock high to output active

TKHQX1

TDC1

1.5

1, 2

Clock high to output change

TKHQX2

TDC2

1.5

Output enable to output active

TGLQX

TOLZ

Output disable to output High-Z

TGHQZ

TOHZ

2.8

3.2

3.5

4.2

Clock high to output High-Z

TKHQZ

TCZ

1.5

2.8

1.5

3.2

1.5

3.5

1.5

3.5

1, 2

Clock high pulse width

TKHKL

TCH

1.8

2.2

Clock low pulse width

TKLKH

TCL

1.8

2.2

Setup times

Address

TAVKH

TAS

1.4

1.5

Address advance TADVVKH

TADVS

Clock enable

TEVKH

TCES

Chip enable

TCVKH

TCSS

Data in

TDVKH

TDS

Write enable

TWVKH

TWS

Hold times

Address

TKHAX

TAH

0.4

0.5

Address advance TKHADVX

TADVH

Clock enable

TKHEX

TCEH

Chip enable

TKHCX

TCSH

Data in

TKHDX

TDH

Write enable

TKHWX

TWH

Power down entry time

TZZE

8.8

Power down recovery time

TZZR

8.8

Notes 1. Transition is measured

±200 mV from steady state.

2. To avoid bus contention, the output buffers are designed such that TKHQZ (device turn-off) is faster than

TKHQX1 (device turn-on) at a given temperature and voltage. The specs as shown do not imply bus
contention because TKHQX1 is a min. parameter that is worse case at totally different conditions (T

min.,

max.) than TKHQZ, which is a max. parameter (worse case at T

max., V

min.).

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

READ / WRITE CYCLE

WRITE

D (A1)

CLK

/CKE

/CEs

ADV

/WE

Data In

Data Out

/BWs

Address

Command

D (A1)

D (A2)

D (A2+1)

D (A5)

Q (A3)

Q (A4)

Q (A4+1)

Q (A6)

WRITE

D (A2)

BURST

WRITE

D (A2+1)

READ

Q (A3)

READ

Q (A4)

BURST

READ

Q (A4+1)

WRITE

D (A5)

READ

Q (A6)

WRITE

Q (A7)

DESELECT

TKHKH

TEVKH

TKHEX

TCVKH

TKHCX

TKHKL TKLKH

TDVKH

TKHDX

TKHQX1

TKHQV

TKHQX2

TGHQZ

TGLQX

TKHQX2

TGLQV TKHQZ

TADVVKH TKHADVX

TWVKH TKHWX

Note 1

Note 2

TAVKH

TKHAX

High-Z

Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH. When

/CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.

2. /BWs refers to /BW1, /BW2, /BW3 and /BW4. When /BWs is LOW, any one or more byte write enables

(/BW1, /BW2, /BW3 or /BW4) are LOW.

Data Sheet M15562EJ3V0DS

µPD4481162, 4481182, 4481322, 4481362

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

µPD4481162, 4481182, 4481322, 4481362

ZEROSB is a trademark of NEC Electronics Corporation.

The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
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appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
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Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
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customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

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