Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagrams
- Electrical Specifications
- Package Drawing
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MOS INTEGRATED CIRCUIT
PD4482163, 4482183, 4482323, 4482363
8M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
DOUBLE CYCLE DESELECT
Document No. M14904EJ3V0DS00 (3rd edition)
Date Published December 2002 NS CP(K)
Printed in Japan
DATA SHEET
The mark
#
#
#
# shows major revised points.
The mark shows major revised points.
2000
Description
The
PD4482163 is a 524,288-word by 16-bit, the PD4482183 is a 524,288-word by 18-bit, PD4482323 is a 262,144-
word by 32-bit and the
PD4482363 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS
technology using Full-CMOS six-transistor memory cell.
The
PD4482163, PD4482183, PD4482323 and PD4482363 integrates unique synchronous peripheral circuitry, 2-
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The
PD4482163, PD4482183, PD4482323 and PD4482363 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State ("Sleep"). In
the "Sleep" state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The
PD4482163, PD4482183, PD4482323 and PD4482363 are packaged in 100-pin PLASTIC LQFP with a 1.4
mm package thickness for high density and low capacitive loading.
Features
Single 3.3 V power supply
Synchronous operation
Operating temperature : T
A
= 0 to 70
C (-A44, -A50, -A60)
T
A
=
-40 to +85 C (-A44Y, -A50Y, -A60Y)
Internally self-timed write control
Burst read / write : Interleaved burst and linear burst sequence
Fully registered inputs and outputs for pipelined operation
Double-Cycle deselect timing
All registers triggered off positive clock edge
3.3 V LVTTL Compatible : All inputs and outputs
Fast clock access time : 2.8 ns (225 MHz), 3.1 ns (200 MHz), 3.5 ns (167 MHz)
Asynchronous output enable : /G
Burst sequence selectable : MODE
Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
Separate byte write enable : /BW1 to /BW4, /BWE (
PD4482323, PD4482363)
/BW1, /BW2, /BWE (
PD4482163, PD4482183)
Global write enable : /GW
Three chip enables for easy depth expansion
Common I/O using three state outputs
2
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Ordering Information
Part number
Access
Clock
Core Supply
I/O Interface
Operating
Package
Time
Frequency
Voltage
Temperature
ns
MHz
V
C
PD4482163GF-A44
2.8
225
3.3 0.165
3.3 V LVTTL
0 to 70
100-pin PLASTIC
PD4482163GF-A50
3.1
200
LQFP (14
20)
PD4482163GF-A60
3.5
167
PD4482183GF-A44
2.8
225
PD4482183GF-A50
3.1
200
PD4482183GF-A60
3.5
167
PD4482323GF-A44
2.8
225
PD4482323GF-A50
3.1
200
PD4482323GF-A60
3.5
167
PD4482363GF-A44
2.8
225
PD4482363GF-A50
3.1
200
PD4482363GF-A60
3.5
167
PD4482163GF-A44Y
2.8
225
-40 to +85
PD4482163GF-A50Y
3.1
200
PD4482163GF-A60Y
3.5
167
PD4482183GF-A44Y
2.8
225
PD4482183GF-A50Y
3.1
200
PD4482183GF-A60Y
3.5
167
PD4482323GF-A44Y
2.8
225
PD4482323GF-A50Y
3.1
200
PD4482323GF-A60Y
3.5
167
PD4482363GF-A44Y
2.8
225
PD4482363GF-A50Y
3.1
200
PD4482363GF-A60Y
3.5
167
3
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Pin Configurations
/
indicates active low signal.
100-pin PLASTIC LQFP (14 x 20)
[
PD4482163GF, PD4482183GF]
Marking Side
NC
NC
NC
V
DD
Q
V
SS
Q
NC
NC
I/O9
I/O10
V
SS
Q
V
DD
Q
I/O11
I/O12
NC
V
DD
NC
V
SS
I/O13
I/O14
V
DD
Q
V
SS
Q
I/O15
I/O16
I/OP2, NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
V
DD
Q
V
SS
Q
NC
I/OP1, NC
I/O8
I/O7
V
SS
Q
V
DD
Q
I/O6
I/O5
V
SS
NC
V
DD
ZZ
I/O4
I/O3
V
DD
Q
V
SS
Q
I/O2
I/O1
NC
NC
V
SS
Q
V
DD
Q
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
NC
NC
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
4
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Pin Identification (
PD4482163GF, PD4482183GF)
Symbol
Pin No.
Description
A0 to A18
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48,
49, 50, 43, 80
Synchronous Address Input
I/O1 to I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22, 23
Synchronous Data In,
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
74
Synchronous Data In (Parity),
I/OP2, NC
Note
24
Synchronous / Asynchronous Data Out (Parity)
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE,CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BW1, /BW2, /BWE
93, 94, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 51, 52, 53,
56, 57, 66, 75, 78, 79, 95, 96
No Connection
Note NC (No Connection) is used in the
PD4482163GF.
I/OP1 and I/OP2 are used in the
PD4482183GF.
5
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
100-pin PLASTIC LQFP (14 x 20)
[
PD4482323GF, PD4482363GF]
Marking Side
I/OP3, NC
I/O17
I/O18
V
DD
Q
V
SS
Q
I/O19
I/O20
I/O21
I/O22
V
SS
Q
V
DD
Q
I/O23
I/O24
NC
V
DD
NC
V
SS
I/O25
I/O26
V
DD
Q
V
SS
Q
I/O27
I/O28
I/O29
I/O30
V
SS
Q
V
DD
Q
I/O31
I/O32
I/OP4, NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/OP2, NC
I/O16
I/O15
V
DD
Q
V
SS
Q
I/O14
I/O13
I/O12
I/O11
V
SS
Q
V
DD
Q
I/O10
I/O9
V
SS
NC
V
DD
ZZ
I/O8
I/O7
V
DD
Q
V
SS
Q
I/O6
I/O5
I/O4
I/O3
V
SS
Q
V
DD
Q
I/O2
I/O1
I/OP1, NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6
A7
/CE
CE2
/BW4
/BW3
/BW2
/BW1
/CE2
V
DD
V
SS
CLK
/GW
/BWE
/G
/AC
/AP
/ADV
A8
A9
MODE
A5
A4
A3
A2
A1
A0
NC
NC
V
SS
V
DD
NC
A17
A10
A11
A12
A13
A14
A15
A16
Remark Refer to Package Drawing for the 1-pin index mark.
6
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Pin Identification (
PD4482323GF, PD4482363GF)
Symbol
Pin No.
Description
A0 to A17
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
Synchronous Address Input
I/O1 to I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74,
75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23,
24, 25, 28, 29
Synchronous Data In,
Synchronous / Asynchronous Data Out
I/OP1, NC
Note
51
Synchronous Data In (Parity),
I/OP2, NC
Note
80
Synchronous / Asynchronous Data Out (Parity)
I/OP3, NC
Note
1
I/OP4, NC
Note
30
/ADV
83
Synchronous Burst Address Advance Input
/AP
84
Synchronous Address Status Processor Input
/AC
85
Synchronous Address Status Controller Input
/CE, CE2, /CE2
98, 97, 92
Synchronous Chip Enable Input
/BWE1 to /BWE4, /BWE 93, 94, 95, 96, 87
Synchronous Byte Write Enable Input
/GW
88
Synchronous Global Write Input
/G
86
Asynchronous Output Enable Input
CLK
89
Clock Input
MODE
31
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
ZZ
64
Asynchronous Power Down State Input
V
DD
15, 41, 65, 91
Power Supply
V
SS
17, 40, 67, 90
Ground
V
DD
Q
4, 11, 20, 27, 54, 61, 70, 77
Output Buffer Power Supply
V
SS
Q
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Ground
NC
14, 16, 38, 39, 42, 66
No Connection
Note NC (No Connection) is used in the
PD4482323GF.
I/OP1 to I/OP4 are used in the
PD4482363GF.
7
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Block Diagrams
[
PD4482163,
PD4482183]
Address
Registers
Binary
Counter
and Logic
CLR
Q0
Q1
Byte 1
Write Register
Byte 1
Write Driver
8/9
Byte 2
Write Register
Byte 2
Write Driver
8/9
Enable
Register
Row and Column
Memory cell array
1,024 rows
512
16 columns
(8,388,608 bits)
512
18 columns
(9,437,184 bits)
Output
Registers
Output
Buffers
Input
Registers
16/18
17
19
A0, A1
A1'
A0'
16/18
2
16/18
A0 to A18
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O16
I/OP1 to I/OP2
ZZ
Power Down Control
Decoders
19
Burst Sequence
[
PD4482163, PD4482183]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
8
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
[
PD4482323, PD4482363]
Address
Registers
Binary
Counter
and Logic
CLR
Q0
Q1
Byte 1
Write Register
Byte 1
Write Driver
8/9
Byte 2
Write Register
Byte 2
Write Driver
8/9
Byte 3
Write Register
Byte 3
Write Driver
8/9
Byte 4
Write Register
Byte 4
Write Driver
8/9
Enable
Register
Row and Column
Memory cell array
1,024 rows
256
32 columns
(8,388,608 bits)
256
36 columns
(9,437,184 bits)
Output
Registers
Output
Buffers
Input
Registers
32/36
16
18
A0, A1
A1'
A0'
32/36
4
32/36
A0 to A17
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BW3
/BW4
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O32
I/OP1 to I/OP4
ZZ
Power Down Control
Decoders
18
[
PD4482323, PD4482363]
Interleaved Burst Sequence Table (MODE = V
DD
)
External Address
A17 to A2, A1, A0
1st Burst Address
A17 to A2, A1, /A0
2nd Burst Address
A17 to A2, /A1, A0
3rd Burst Address
A17 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = V
SS
)
External Address
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
1st Burst Address
A17 to A2, 0, 1
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
2nd Burst Address
A17 to A2, 1, 0
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
3rd Burst Address
A17 to A2, 1, 1
A17 to A2, 0, 0
A17 to A2, 0, 1
A17 to A2, 1, 0
9
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Asynchronous Truth Table
Operation
/G
I/O
Read Cycle
L
Dout
Read Cycle
H
High-Z
Write Cycle
High-Z, Din
Deselected
High-Z
Remark
: don't care
Synchronous Truth Table
Operation
/CE
CE2
/CE2
/AP
/AC
/ADV
/WRITE
CLK
Address
Deselected
Note
H
L
L
H
None
Deselected
Note
L
L
L
L
H
None
Deselected
Note
L
H
L
L
H
None
Deselected
Note
L
L
H
L
L
H
None
Deselected
Note
L
H
H
L
L
H
None
Read Cycle / Begin Burst
L
H
L
L
L
H
External
Read Cycle / Begin Burst
L
H
L
H
L
H
L
H
External
Read Cycle / Continue Burst
H
H
L
H
L
H
Next
Read Cycle / Continue Burst
H
H
L
H
L
H
Next
Read Cycle / Suspend Burst
H
H
H
H
L
H
Current
Read Cycle / Suspend Burst
H
H
H
H
L
H
Current
Write Cycle / Begin Burst
L
H
L
H
L
L
L
H
External
Write Cycle / Continue Burst
H
H
L
L
L
H
Next
Write Cycle / Continue Burst
H
H
L
L
L
H
Next
Write Cycle / Suspend Burst
H
H
H
L
L
H
Current
Write Cycle / Suspend Burst
H
H
H
L
L
H
Current
Note Deselect status is held until new "Begin Burst" entry.
Remarks 1.
: don't care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [
PD4482163, PD4482183]
/BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. [
PD4482323, PD4482363]
10
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Partial Truth Table for Write Enables
[
PD4482163,
PD4482183]
Operation
/GW
/BWE
/BW1
/BW2
Read Cycle
H
H
Read Cycle
H
L
H
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
H
L
L
H
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
H
L
H
L
Write Cycle / All Bytes
H
L
L
L
Write Cycle / All Bytes
L
Remark
: don't care
[
PD4482323,
PD4482363]
Operation
/GW
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
H
H
Read Cycle
H
L
H
H
H
H
Write Cycle / Byte 1 (I/O [1:8], I/OP1)
H
L
L
H
H
H
Write Cycle / Byte 2 (I/O [9:16], I/OP2)
H
L
H
L
H
H
Write Cycle / Byte 3 (I/O [17:24], I/OP3)
H
L
H
H
L
H
Write Cycle / Byte 4 (I/O [25:32], I/OP4)
H
L
H
H
H
L
Write Cycle / All Bytes
H
L
L
L
L
L
Write Cycle / All Bytes
L
Remark
: don't care
Pass-Through Truth Table
Previous Cycle
Present Cycle
Next Cycle
Operation
Add
/WRITE
I/O
Operation
Add
/CEs /WRITE
/G
I/O
Operation
Write Cycle
Ak
L
Dn(Ak)
Read Cycle
Am
L
H
L
Q1(Ak)
Read Q1(Am)
(Begin Burst)
Deselected
-
H
High-Z
No Carry Over from
Previous Cycle
Remarks 1.
: don't care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [
PD4482163, PD4482183]
/BW1 to /BW4 and /GW are HIGH, and /BWE is LOW. [
PD4482323, PD4482363]
/CEs = L means /CE is LOW, /CE2 is LOW and CE2 is HIGH.
/CEs = H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW.
ZZ (Sleep) Truth Table
ZZ
Chip Status
0.2 V
Active
Open
Active
V
DD
- 0.2 V
Sleep
11
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Notes
Supply voltage
V
DD
0.5
+4.0
V
Output supply voltage
V
DD
Q
0.5
V
DD
V
Input voltage
V
IN
0.5
V
DD
+ 0.5
V
1, 2
Input / Output voltage
V
I/O
0.5
V
DD
Q
+ 0.5
V
1, 2
Operating ambient temperature
T
A
-A44, -A50, -A60
0
70
C
-A44Y, -A50Y, -A60Y
40
+85
Storage temperature
T
stg
55
+125
C
Notes 1. 2.0 V (MIN.) (Pulse width : 2 ns)
2. V
DD
Q + 2.3 V (MAX.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply voltage
V
DD
3.135
3.3
3.465
V
Output supply voltage
V
DD
Q
3.135
3.3
3.465
V
High level input voltage
V
IH
2.0
V
DD
Q
+ 0.3
V
Low level input voltage
V
IL
0.3
Note
+0.8
V
Note 0.8 V (MIN.) (Pulse Width : 2 ns)
12
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Note
Input leakage current
I
LI
V
IN
(except ZZ, MODE) = 0 V to V
DD
2
+2
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
DD
Q, Outputs are disabled
2
+2
A
Operating supply current
I
DD
Device selected, Cycle = MAX.
-A44
440
mA
V
IN
V
IL
or V
IN
V
IH
, I
I/O
= 0 mA
-A44Y
-A50
400
-A50Y
-A60
320
-A60Y
I
DD1
Suspend cycle, Cycle = MAX.
180
/AC, /AP, /ADV, /GW, /BWEs
V
IH
,
V
IN
V
IL
or V
IN
V
IH
, I
I/O
= 0 mA
Standby supply current
I
SB
Device deselected, Cycle = 0 MHz
30
mA
V
IN
V
IL
or V
IN
V
IH
, All inputs are static
I
SB1
Device deselected, Cycle = 0 MHz
15
V
IN
0.2 V or V
IN
V
DD
0.2 V,
V
I/O
0.2 V, All inputs are static
I
SB2
Device deselected, Cycle = MAX.
130
V
IN
V
IL
or V
IN
V
IH
Power down supply current
I
SBZZ
ZZ
V
DD
0.2 V, V
I/O
V
DD
Q + 0.2 V
15
mA
High level output voltage
V
OH
I
OH
=
4.0 mA
2.4
V
Low level output voltage
V
OL
I
OL
= +8.0 mA
0.4
V
Capacitance (T
A =
25
C, f = 1MHz)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
6.0
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
8.0
pF
Clock Input capacitance
C
clk
V
clk
= 0 V
6.0
pF
Remark These parameters are periodically sampled and not 100% tested.
13
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
Input waveform (Rise / Fall time = 1 ns (20 to 80%))
Test ponts
V
SS
3.0 V
1.5 V
1.5 V
Output waveform
Test points
1.5 V
1.5 V
Output load condition
C
L
: 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
V
T
= +1.5 V
I/O (Output)
50
Z
O
= 50
C
L
Remark C
L
includes capacitance's of the probe and jig, and stray capacitances.
14
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Read and Write Cycle
Parameter
Symbol
-A44
-A50
-A60
Unit
Note
-A44Y
-A50Y
-A60Y
(225 MHz)
(200 MHz)
(167 MHz)
Standard
Alias
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Cycle time
TKHKH
TCYC
4.4
5.0
6.0
ns
Clock access time
TKHQV
TCD
2.8
3.1
3.5
ns
Output enable access time
TGLQV
TOE
2.8
3.1
3.5
ns
Clock high to output active
TKHQX1
TDC1
0
0
0
ns
Clock high to output change
TKHQX2
TDC2
1.5
1.5
1.5
ns
Output enable to output active
TGLQX
TOLZ
0
0
0
ns
Output disable to output High-Z
TGHQZ
TOHZ
0
2.8
0
3.1
0
3.5
ns
Clock high to output High-Z
TKHQZ
TCZ
1.5
2.8
1.5
3.1
1.5
3.5
ns
Clock high pulse width
TKHKL
TCH
1.8
2.0
2.0
ns
Clock low pulse width
TKLKH
TCL
1.8
2.0
2.0
ns
Setup times
Address
TAVKH
TAS
1.4
1.5
1.5
ns
Address status
TADSVKH
TSS
Data in
TDVKH
TDS
Write enable
TWVKH
TWS
Address advance
TADVVKH
Chip enable
TEVKH
Hold times
Address
TKHAX
TAH
0.4
0.5
0.5
ns
Address status
TKHADSX
TSH
Data in
TKHDX
TDH
Write enable
TKHWX
TWH
Address advance
TKHADVX
Chip enable
TKHEX
Power down entry time
TZZE
TZZE
8.8
10.0
12.0
ns
Power down recovery time
TZZR
TZZR
8.8
10.0
12.0
ns
15
Data S
h
e
e
t
M1
49
04E
J
3
V
0
DS
PD4482163,
4482183, 4482323, 4482363
TKHKH
TKLKH
TKHAX
TWVKH
TKHWX
TKHEX
TGLQV
TGLQX
TKHQX2
TKHQZ
Q1(A1)
Q1(A2)
Q2(A2)
Q3(A2)
Q4(A2)
Q1(A2)
A1
A2
A3
CLK
/AP
/AC
Address
/ADV
/CEs
Note1
/G
Data In
/BWE
/BWs
TGHQZ
TKHQV
TKHKL
TKHADSX
TADSVKH
TAVKH
TEVKH
TADSVKH
TKHADSX
TADVVKH
TKHADVX
TWVKH
TKHWX
/GW
Data Out
READ CYCLE
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
Notes 1.
Note2
Outputs are disabled within two clock cycles after deselect.
2.
Q1(A3)
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
High-Z
High-Z
High-Z
3. If /GW is set to low level or /BWE is set to low level and one of /BW1 to /BW4 is set to low level,
Q1(A3) is not output.
Note3
Note3
16
Data S
h
e
e
t
M1
49
04E
J
3
V
0
DS
PD4482163,
4482183, 4482323, 4482363
TKHKH
TAVKH
TKHAX
TEVKH
TKHEX
D1(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
TKHKL
TKLKH
A1
A2
A3
TDVKH
TKHDX
TKHADSX
TWVKH
TKHWX
CLK
/AP
/AC
Address
/ADV
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TADVVKH
TWVKH
TKHADVX
TKHWX
TADSVKH TKHADSX
TADSVKH
WRITE CYCLE
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
TGHQZ
High-Z
High-Z
17
Data S
h
e
e
t
M1
49
04E
J
3
V
0
DS
PD4482163,
4482183, 4482323, 4482363
TKHKH
TKLKH
TKHKL
TAVKH
TEVKH
TKHEX
TKHQV
TGLQX
Q1(A1)
Q1(A2)
Q1(A3)
Q2(A3)
Q3(A3)
A3
A2
A1
TGHQZ
TKHQX1
TDVKH
TKHDX
D1(A2)
TADSVKH TKHADSX
TKHAX
TADSVKH TKHADSX
CLK
/AP
/AC
Address
/ADV
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TWVKH
TKHWX
TWVKH
TKHWX
Q4(A3)
TADVVKH
TKHADVX
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
READ / WRITE CYCLE
High-Z
High-Z
High-Z
High-Z
High-Z
18
Data S
h
e
e
t
M1
49
04E
J
3
V
0
DS
PD4482163,
4482183, 4482323, 4482363
TKHKH
TKLKH
TKHKL
TAVKH
TEVKH
TKHEX
TGHQZ
Q1(A1)
Q1(A2)
Q1(A3)
Q1(A4)
A3
A2
TDVKH TKHDX
TKHAX
TADSVKH TKHADSX
CLK
/AC
Address
/CEs
Note2
/G
Data In
/BWE
Note1
/BWs
/GW
Note1
Data Out
TWVKH
Notes
2.
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1 to /BW4 LOW.
1.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
SINGLE READ / WRITE CYCLE
A4
A5
A6
A7
A1
A8
A9
TWVKH
TKHWX
Q1(A7)
Q1(A8)
Q1(A9)
D1(A5)
D1(A6)
D1(A7)
TGLQX
TKHQV
TGLQV
TKHQZ
Remark /AP is HIGH and /ADV is don't care.
TKHWX
Note3
3. Outputs are disabled within two clock cycles after deselect.
High-Z
High-Z
High-Z
High-Z
Note4
Note4
4. If /GW is set to low level or /BWE is set to low level and one of /BW1 to /BW4 is set to low level,
Q1(A9) is not output.
19
Data S
h
e
e
t
M1
49
04E
J
3
V
0
DS
PD4482163,
4482183, 4482323, 4482363
TKHKH
ZZ
TKLKH
A1
A2
TZZE
TZZR
Power Down (I
SBZZ
) State
Q1(A2)
Q1(A1)
TKHKL
CLK
/AP
/AC
Address
/ADV
/CEs
/G
/BWE
/BWs
/GW
Data Out
POWER DOWN (ZZ) CYCLE
High-Z
High-Z
20
Data S
h
e
e
t
M1
49
04E
J
3
V
0
DS
PD4482163,
4482183, 4482323, 4482363
TKHKH
Data Out
TKHKL
TKLKH
A1
A2
Power Down State (I
SB1
)
Note
Q1(A1)
Q1(A2)
Data In
CLK
/AP
/AC
Address
/ADV
/CEs
/G
/BWE
/BWs
/GW
STOP CLOCK CYCLE
Note V
IN
0.2 V or V
IN
V
DD
-
0.2 V, V
I/O
0.2 V
High-Z
High-Z
High-Z
High-Z
21
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Package Drawing
100-PIN PLASTIC LQFP (14x20)
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
22.0
0.2
20.0
0.2
0.65 (T.P.)
0.575
J
16.0
0.2
K
C
14.0
0.2
I
0.13
1.0
0.2
L
0.5
0.2
F
0.825
N
P
Q
0.10
1.4
0.125
0.075
S100GF-65-8ET-1
S
1.7 MAX.
H
0.32
+
0.08
-
0.07
M
0.17
+
0.06
-
0.05
R
3
+
7
-
3
M
80
81
51
50
30
31
100
1
S
S
N
J
detail of lead end
C
D
A
B
R
K
M
L
P
I
S
Q
G
F
H
22
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the
PD4482163, 4482183, 4482323 and 4482363.
Types of Surface Mount Devices
PD4482163GF : 100-pin PLASTIC LQFP (14 x 20)
PD4482183GF : 100-pin PLASTIC LQFP (14 x 20)
PD4482323GF : 100-pin PLASTIC LQFP (14 x 20)
PD4482363GF : 100-pin PLASTIC LQFP (14 x 20)
23
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
Revision History
Edition/
Page
Type of
Location
Description
Date
This
Previous
revision
(Previous edition
This edition)
edition
edition
3rd edition/
Throughout Throughout Modification
-
Preliminary Data Sheet
Data Sheet
Dec. 2002
Addition
-
Extended operating temperature products
(T
A
=
-40 to +85 C)
24
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
[MEMO]
25
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
[MEMO]
26
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
[MEMO]
27
Data Sheet M14904EJ3V0DS
PD4482163, 4482183, 4482323, 4482363
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD4482163, 4482183, 4482323, 4482363
The information in this document is current as of December, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
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redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
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support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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(Note)
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(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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