Document Outline
- COVER
- Features
- Ordering Information
- Pin Configurations
- Block Diagram
- 1. Initialization
- 2. Partial Refresh
- 2.1 Standby Mode
- 2.2 Density Switching
- 2.3 Standby Mode Status Transition
- 2.4 Addresses for Which Partial Refresh Is Supported
- 3. Page Read Operation
- 3.1 Features of Page Read Operation
- 3.2 Page Length
- 3.3 Page-Corresponding Addresses
- 3.4 Page Start Address
- 3.5 Page Direction
- 3.6 Interrupt during Page Read Operation
- 3.7 When page read is not used
- 4. Mode Register Settings
- 4.1 Mode Register Setting Method
- 4.2 Cautions for Setting Mode Register
- 5. Electrical Specifications
- 6. Timing Charts
- 7. Package Drawing
- 8. Recommended Soldering Conditions
- 9. Revision History
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
2001
Document No. M15867EJ5V0DS00 (5th edition)
Date Published August 2002 NS CP (K)
Printed in Japan
MOS INTEGRATED CIRCUIT
PD4664312-X
64M-BIT CMOS MOBILE SPECIFIED RAM
4M-WORD BY 16-BIT
EXTENDED TEMPERATURE OPERATION
PRELIMINARY DATA SHEET
The mark shows major revised points.
Description
The
PD4664312-X is a high speed, low power, 67,108,864 bits (4,194,304 words by 16 bits) CMOS Mobile
Specified RAM featuring Low Power Static RAM compatible function and pin configuration.
The
PD4664312-X is fabricated with advanced CMOS technology using one-transistor memory cell.
The
PD4664312-X is packed in 93-pin TAPE FBGA.
Features
4,194,304 words by 16 bits organization
Fast access time: 65, 75 ns (MAX.)
Fast page access time: 18, 25 ns (MAX.)
Byte data control: /LB (I/O0 to I/O7), /UB (I/O8 to I/O15)
Low voltage operation: 2.7 to 3.1 V (-B65X)
2.7 to 3.1 V (Chip), 1.65 to 2.1 V (I/O) (-BE75X)
Operating ambient temperature: T
A
= 25 to +85 C
Output Enable input for easy application
Chip Enable input: /CS pin
Standby Mode input: MODE pin
Standby Mode1: Normal standby (Memory cell data hold valid)
Standby Mode2: Density of memory cell data hold is variable
PD4664312
Access
Operating supply
Operating
Supply current
time
voltage
ambient
At operating
At standby
A (MAX.)
ns (MAX.)
V
temperature
mA (MAX.)
Density of data hold
Chip
I/O
C
64M bits 16M bits 8M bits 4M bits 0M bit
-B65X
65
2.7 to 3.1
25 to +85
45
100
60
50
45
10
-BE75X
Note
75
2.7 to 3.1 1.65 to 2.1
40
Note Under development
Preliminary Data Sheet M15867EJ5V0DS
2
PD4664312-X
Ordering Information
Part number
Package
Access time
Operating supply voltage
Operating
ns (MAX.)
V
temperature
Chip
I/O
C
PD4664312F9-B65X-CR2
93-pin TAPE FBGA (12 x 9)
65
2.7 to 3.1
25 to +85
PD4664312F9-BE75X-CR2
Note
75
2.7 to 3.1
1.65 to 2.1
Note Under development
Preliminary Data Sheet M15867EJ5V0DS
3
PD4664312-X
Pin Configurations
/xxx indicates active low signal.
93-pin TAPE FBGA (12 x 9)
[
PD4664312F9-B65X-CR2 ]
Top View
GND
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
NC
NC
I/O10
NC
/WE
V
CC
A16
I/O11
NC
NC
A12
I/O6
I/O13
A9
A15
A19
I/O14
/CS
I/O15
I/O1
A1
A2
A4
A10
NC
I/O2
A0
A3
MODE
A20
A14
/LB
NC
NC
/UB
I/O3
A21
NC
GND
A
B
C
D
E
F
G
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
K
L
J
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L K J H G F E D C B A
M
B C D E F G H J K L M
10
9
8
7
6
5
4
3
2
1
A
Top View
Bottom View
N
P
N P
NC
NC
NC
NC
N
P
NC
NC
NC
NC
NC
NC
NC
NC
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
A0 to A21
: Address inputs
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
MODE
: Standby mode
/WE
: Write enable
/OE
: Output enable
/LB, /UB
: Byte data select
V
CC
: Power supply
GND
: Ground
NC
Note
: No Connection
Preliminary Data Sheet M15867EJ5V0DS
4
PD4664312-X
93-pin TAPE FBGA (12 x 9)
[
PD4664312F9-BE75X-CR2 ]
Top View
GND
I/O9
I/O5
A7
/OE
I/O7
I/O4
I/O0
A6
A18
A11
A8
A5
I/O8
I/O12
A13
A17
NC
NC
I/O10
NC
/WE
V
CC
A16
I/O11
NC
NC
A12
I/O6
I/O13
A9
A15
A19
I/O14
/CS
I/O15
I/O1
A1
A2
A4
A10
V
CC
Q
I/O2
A0
A3
MODE
A20
A14
/LB
NC
NC
/UB
I/O3
A21
NC
GND
A
B
C
D
E
F
G
H
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
M
K
L
J
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
L K J H G F E D C B A
M
B C D E F G H J K L M
10
9
8
7
6
5
4
3
2
1
A
Top View
Bottom View
N
P
N P
NC
NC
NC
NC
N
P
NC
NC
NC
NC
NC
NC
NC
NC
Note Some signals can be applied because this pin is not internally connected.
Remarks Refer to Package Drawing for the index mark.
A0 to A21
: Address inputs
I/O0 to I/O15 : Data inputs / outputs
/CS
: Chip Select
MODE
: Standby mode
/WE
: Write enable
/OE
: Output enable
/LB, /UB
: Byte data select
V
CC
: Power supply
V
CC
Q
: Input / Output power supply
GND
: Ground
NC
Note
: No Connection
Preliminary Data Sheet M15867EJ5V0DS
5
PD4664312-X
Block Diagram
A0
A21
I/O8 to I/O15
/WE
/OE
/UB
/LB
I/O0 to I/O7
V
CC
V
CC
Q
GND
MODE
Refresh
counter
Refresh
control
Standby mode control
Address buffer
Address
buffer
Row
decoder
Memory cell array
67,108,864 bits
Input data
controller
Sense amplifier /
Switching circuit
Column decoder
Output data
controller
/CS
Remark V
CC
Q is the input / output power supply for -BE75X.
Preliminary Data Sheet M15867EJ5V0DS
6
PD4664312-X
Truth Table
/CS
MODE
/OE
/WE
/LB
/UB
Mode
I/O
Supply
I/O0 to I/O7
I/O8 to I/O15
current
H
H
Not selected (Standby Mode 1)
High-Z
High-Z
I
SB1
H
H
H
Not selected (Standby Mode 1)
High-Z
High-Z
L
Not selected (Standby Mode 2)
Note
High-Z
High-Z
I
SB2
L
H
H
H
Output disable
High-Z
High-Z
I
CCA
L
H
L
L
Word read
D
OUT
D
OUT
L
H
Lower byte read
D
OUT
High-Z
H
L
Upper byte read
High-Z
D
OUT
H
L
L
L
Word write
D
IN
D
IN
L
H
Lower byte write
D
IN
High-Z
H
L
Upper byte write
High-Z
D
IN
Note MODE pin must be fixed to high level except Standby Mode 2. (refer to 2.3 Standby Mode Status Transition).
Remark
: V
IH
or V
IL
, H: V
IH
, L: V
IL
Preliminary Data Sheet M15867EJ5V0DS
7
PD4664312-X
CONTENTS
1. Initialization .................................................................................................................................................................... 8
2. Partial Refresh ............................................................................................................................................................... 9
2.1 Standby Mode........................................................................................................................................................... 9
2.2 Density Switching...................................................................................................................................................... 9
2.3 Standby Mode Status Transition............................................................................................................................... 9
2.4 Addresses for Which Partial Refresh Is Supported ................................................................................................ 10
3. Page Read Operation .................................................................................................................................................. 11
3.1 Features of Page Read Operation.......................................................................................................................... 11
3.2 Page Length ........................................................................................................................................................... 11
3.3 Page-Corresponding Addresses............................................................................................................................. 11
3.4 Page Start Address................................................................................................................................................. 11
3.5 Page Direction ........................................................................................................................................................ 11
3.6 Interrupt during Page Read Operation.................................................................................................................... 11
3.7 When page read is not used................................................................................................................................... 11
4. Mode Register Settings................................................................................................................................................ 12
4.1 Mode Register Setting Method ............................................................................................................................... 12
4.2 Cautions for Setting Mode Register ........................................................................................................................ 13
5. Electrical Specifications ............................................................................................................................................... 14
6. Timing Charts............................................................................................................................................................... 20
7. Package Drawing......................................................................................................................................................... 30
8. Recommended Soldering Conditions .......................................................................................................................... 31
9. Revision History ........................................................................................................................................................... 32
Preliminary Data Sheet M15867EJ5V0DS
8
PD4664312-X
1. Initialization
Initialize the
PD4664312-X at power application using the following sequence to stabilize internal circuits.
(1) Following power application, make MODE high level after fixing MODE to low level for the period of t
VHMH
. Make
/CS high level before making MODE high level.
(2) /CS and MODE are fixed to high level for the period of t
MHCL
.
Normal operation is possible after the completion of initialization.
Figure1-1. Initialization Timing Chart
/CS (Input)
V
CC
MODE (Input)
t
MHCL
Initialization
t
CHMH
t
VHMH
V
CC
(MIN.)
Normal Operation
Cautions 1. Make MODE low level when starting the power supply.
2. t
VHMH
is specified from when the power supply voltage reaches the prescribed minimum value (V
CC
(MIN.)).
Preliminary Data Sheet M15867EJ5V0DS
9
PD4664312-X
2. Partial Refresh
2.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 64M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
2.2 Density Switching
In Standby Mode 2, the densities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M bit.
The density for performing refresh can be set with the mode register. Once the refresh density has been set in the
mode register, these settings are retained until they are set again, while applying the power supply. However, the mode
register setting will become undefined if the power is turned off, so set the mode register again after power application.
(For how to perform mode register settings, refer to section 4. Mode Register Settings.)
2.3 Standby Mode Status Transition
In Standby Mode 1, MODE and /CS are high level, or MODE, /LB and /UB are high level. In Standby Mode 2, MODE is
low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as after
applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to 16M bits,
8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal operation from
Standby Mode 2.
For the timing charts, refer to Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit
Timing Chart, Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart.
Preliminary Data Sheet M15867EJ5V0DS
10
PD4664312-X
Figure 2-1. Standby Mode State Machine
Power On
Active
MODE = V
IH
MODE = V
IL
MODE = V
IL
/CS = V
IL
,
MODE = V
IH
Standby
Mode 1
Standby Mode 2
(16M bits / 8M bits
/ 4M bits)
/CS = V
IL
Initial State
Initialization
Standby Mode 2
(Data not held)
/CS = V
IL
,
MODE = V
IH
MODE = V
IL
MODE = V
IL
MODE = V
IH
,
/CS = V
IH
or
/LB, /UB = V
IH
2.4 Addresses for Which Partial Refresh Is Supported
Data hold density
Correspondence address
16M bits
000000H to 0FFFFFH
8M bits
000000H to 07FFFFH
4M bits
000000H to 03FFFFH
Preliminary Data Sheet M15867EJ5V0DS
11
PD4664312-X
3. Page Read Operation
3.1 Features of Page Read Operation
Features
8 Words Mode
Page length
8 words
Page read-corresponding addresses
A2, A1, A0
Page read start address
Don't care
Page direction
Don't care
Interrupt during page read operation
Enabled
Note
Note An interrupt is output when /CS = H or in case A3 or a higher address changes.
3.2 Page Length
8 words is supported as the page lengths.
3.3 Page-Corresponding Addresses
The page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and A0 during page read
operation.
3.4 Page Start Address
Since random page read is supported, any address (A2, A1, A0) can be used as the page read start address.
3.5 Page Direction
Since random page read is possible, there is not restriction on the page direction.
3.6 Interrupt during Page Read Operation
When generating an interrupt during page read, either make /CS high level or change A3 and higher addresses.
3.7 When page read is not used
Since random page read is supported, even when not using page read, random access is possible as usual.
Preliminary Data Sheet M15867EJ5V0DS
12
PD4664312-X
4. Mode Register Settings
The partial refresh density can be set using the mode register. Since the initial value of the mode register at power
application is undefined, be sure to set the mode register after initialization at power application. When setting the
density of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for re-
setup.) However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not
necessary to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to
set the mode register.
4.1 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads of
the highest address (3FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two
write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
Table 4-1. shows the commands and command sequences.
Table 4-1. Command sequence
Command sequence
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
(Read cycle)
(Read cycle)
(Write cycle)
(Write cycle)
Partial refresh density
Address
Data
Address
Data
Address
Data
Address
Data
16M bits
3FFFFFH
3FFFFFH
3FFFFFH
00H
3FFFFFH
04H
8M bits
3FFFFFH
3FFFFFH
3FFFFFH
00H
3FFFFFH
05H
4M bits
3FFFFFH
3FFFFFH
3FFFFFH
00H
3FFFFFH
06H
0M bit
3FFFFFH
3FFFFFH
3FFFFFH
00H
3FFFFFH
07H
4th bus cycle (Write cycle)
I/O
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register setting
0
0
0
0
0
0
0
0
0
0
0
0
0
PL
PD
Page length
1
8 words
I/O1 I/O0
Density
Partial refresh
0
0
16M bits
density
0
1
8M bits
1
0
4M bits
1
1
0M bit
Preliminary Data Sheet M15867EJ5V0DS
13
PD4664312-X
4.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CS and /OE, toggle /CS at every
cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CS at the first and second read cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register is not performed correctly.
When the highest address (3FFFFFH) is read consecutively three or more times, the mode register setting entries are
not performed correctly. (Immediately after the highest address is read, the setting of the mode register is not performed
correctly.) Perform the setting of the mode register after power application or after accessing other than the highest
address.
Once the refresh density has been set in the mode register, these settings are retained until they are set again, while
applying the power supply. However, the mode register setting will become undefined if the power is turned off, so set
the mode register again after power application.
For the timing chart and flow chart, refer to Figure 6-12. Mode Register Setting Timing Chart, Figure 6-13. Mode
Register Setting Flow Chart.
Preliminary Data Sheet M15867EJ5V0DS
14
PD4664312-X
5. Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol Condition
Rating
Unit
-B65X
-BE75X
Supply voltage
V
CC
0.5
Note
to +4.0
0.5
Note
to +4.0
V
Input / Output supply voltage
V
CC
Q
0.5
Note
to +4.0
V
Input / Output voltage
V
T
0.5
Note
to V
CC
+ 0.4 (4.0 V MAX.) 0.5
Note
to V
CC
Q + 0.4 (4.0 V MAX.)
V
Operating ambient temperature
T
A
25 to +85
25 to +85
C
Storage temperature
T
stg
55 to +125
55 to +125
C
Note 1.0 V (MIN.) (Pulse width: 30 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
-B65X
-BE75X
Unit
MIN.
MAX.
MIN.
MAX.
Supply voltage
V
CC
2.7
3.1
2.7
3.1
V
Input / Output supply voltage
V
CC
Q
1.65
2.1
V
High level input voltage
V
IH
0.8V
CC
V
CC
+0.3
0.8V
CC
Q
V
CC
Q+0.3
V
Low level input voltage
V
IL
0.3
Note
0.2V
CC
0.3
Note
0.2V
CC
Q
V
Operating ambient temperature
T
A
25
+85
25
+85
C
Note 0.5 V (MIN.) (Pulse width: 30 ns)
Capacitance (T
A
= 25
C, f = 1 MHz)
Parameter
Symbol
Test condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
V
IN
= 0 V
8
pF
Input / Output capacitance
C
I/O
V
I/O
= 0 V
10
pF
Remarks 1. V
IN
: Input voltage, V
I/O
: Input / Output voltage
2. These parameters are not 100% tested.
Preliminary Data Sheet M15867EJ5V0DS
15
PD4664312-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
Density of
-B65X
Unit
data hold
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
, /CS = V
IH
or
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA
/CS = V
IL
, Minimum cycle time,
45
mA
I
I/O
= 0 mA
Standby supply current
I
SB1
/CS
V
CC
- 0.2 V,
64M bits
60
100
A
MODE
V
CC
- 0.2 V
I
SB2
/CS
V
CC
- 0.2 V,
16M bits
50
60
MODE
0.2 V
8M bits
45
50
4M bits
40
45
0M bit
10
High level output voltage
V
OH
I
OH
= 0.5 mA
0.8V
CC
V
Low level output voltage
V
OL
I
OL
= 1 mA
0.2V
CC
V
Remark V
IN
: Input voltage, V
I/O
: Input / Output voltage
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
Density of
-BE75X
Unit
data hold
MIN.
TYP.
MAX.
Input leakage current
I
LI
V
IN
= 0 V to V
CC
Q
1.0
+1.0
A
I/O leakage current
I
LO
V
I/O
= 0 V to V
CC
Q, /CS = V
IH
or
1.0
+1.0
A
/WE = V
IL
or /OE = V
IH
Operating supply current
I
CCA
/CS = V
IL
, Minimum cycle time,
40
mA
I
I/O
= 0 mA
Standby supply current
I
SB1
/CS
V
CC
- 0.2 V,
64M bits
60
100
A
MODE
V
CC
- 0.2 V
I
SB2
/CS
V
CC
- 0.2 V,
16M bits
50
60
MODE
0.2 V
8M bits
45
50
4M bits
40
45
0M bit
10
High level output voltage
V
OH
I
OH
= 0.5 mA
0.8V
CC
Q
V
Low level output voltage
V
OL
I
OL
= 1 mA
0.2V
CC
Q
V
Remark V
IN
: Input voltage, V
I/O
: Input / Output voltage
Preliminary Data Sheet M15867EJ5V0DS
16
PD4664312-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ -B65X ]
Input Waveform (Rise and Fall Time
5 ns)
Test points
0.2Vcc
0.8Vcc
Vcc / 2
Vcc / 2
Vcc
GND
5ns
Output Waveform
Test points
Vcc / 2
Vcc / 2
[ -BE75X ]
Input Waveform (Rise and Fall Time
5 ns)
Test points
0.2VccQ
0.8VccQ
VccQ / 2
VccQ / 2
VccQ
GND
5ns
Output Waveform
Test points
VccQ / 2
VccQ / 2
Output Load
AC characteristics directed with the note should be measured with the output load shown in Figure 5-1, Figure 5-2
.
Figure 5-1.
Figure 5-2.
[ -B65X ]
[ -BE75X ]
C
L
: 30 pF
C
L
: 30 pF
5 pF (t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
, t
BHZ
)
5 pF (t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
, t
BHZ
)
I/O (Output)
50
Z
O
= 50
C
L
V
CC
/ 2
I/O (Output)
50
Z
O
= 50
C
L
V
CC
Q
/ 2
Preliminary Data Sheet M15867EJ5V0DS
17
PD4664312-X
Read Cycle
Parameter
Symbol
-B65X
-BE75X
Unit Note
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
65
75
ns
1
Address access time
t
AA
65
75
ns
/CS access time
t
ACS
65
75
ns
/OE to output valid
t
OE
45
50
ns
/LB, /UB to output valid
t
BA
65
75
ns
Output hold from address change
t
OH
5
5
ns
Page read cycle time
t
PRC
18
25
ns
Page access time
t
PAA
18
25
ns
/CS to output in low impedance
t
CLZ
10
10
ns
2
/OE to output in low impedance
t
OLZ
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
5
5
ns
/CS to output in high impedance
t
CHZ
25
25
ns
/OE to output in high impedance
t
OHZ
25
25
ns
/LB, /UB to output in high impedance
t
BHZ
25
25
ns
Address set to /OE low level
t
ASO
0
0
ns
/OE high level to address hold
t
OHAH
5
5
ns
/CS high level to address hold
t
CHAH
0
0
ns
3
/LB, /UB high level to address hold
t
BHAH
0
0
ns
3, 4
/CS low level to /OE low level
t
CLOL
0
10,000
0
10,000
ns
5
/OE low level to /CS high level
t
OLCH
45
45
ns
/CS high level pulse width
t
CP
10
10
ns
/LB, /UB high level pulse width
t
BP
10
10
ns
/OE high level pulse width
t
OP
2
10,000
2
10,000
ns
5
Notes 1. Output load: 30 pF
2. Output load: 5 pF
3. When t
ASO
| t
CHAH
|, | t
BHAH
|, t
CHAH
and t
BHAH
(MIN.) are 15 ns.
t
CHAH
, t
BHAH
t
ASO
/LB, /UB, /CS (Input)
Address (Input)
/OE (Input)
4. t
BHAH
is specified from when both /LB and /UB become high level.
5. t
CLOL
and t
OP
(MAX.) are applied while /CS is being hold at low level.
Preliminary Data Sheet M15867EJ5V0DS
18
PD4664312-X
Write Cycle
Parameter
Symbol
-B65X
-BE75X
Unit Note
MIN.
MAX.
MIN.
MAX.
Write cycle time
t
WC
65
75
ns
/CS to end of write
t
CW
55
60
ns
Address valid to end of write
t
AW
55
60
ns
/LB, /UB to end of write
t
BW
55
60
ns
Write pulse width
t
WP
50
55
ns
Write recovery time
t
WR
0
0
ns
/CS pulse width
t
CP
10
10
ns
/LB, /UB high level pulse width
t
BP
10
10
ns
/WE high level pulse width
t
WHP
10
10
ns
Address setup time
t
AS
0
0
ns
/OE high level to address hold
t
OHAH
5
5
ns
/CS high level to address hold
t
CHAH
0
0
ns
1
/LB, /UB high level to address hold
t
BHAH
0
0
ns
1, 2
Data valid to end of write
t
DW
30
35
ns
Data hold time
t
DH
0
0
ns
/OE high level to /WE set
t
OES
0
10,000
0
10,000
ns
3
/WE high level to /OE set
t
OEH
10
10,000
10
10,000
ns
Notes 1. When t
AS
| t
CHAH
|, | t
BHAH
| and t
CP
18 ns, t
CHAH
and t
BHAH
(MIN.) are 15 ns.
t
CHAH
, t
BHAH
t
AS
/LB, /UB, /CS (Input)
Address (Input)
/WE (Input)
2. t
BHAH
is specified from when both /LB and /UB become high level.
3. t
OES
and t
OEH
(MAX.) are applied while /CS is being hold at low level.
Preliminary Data Sheet M15867EJ5V0DS
19
PD4664312-X
Initialization
Parameter
Symbol
MIN.
MAX.
Unit Note
Power application to MODE low level hold
t
VHMH
50
s
/CS high level to MODE high level
t
CHMH
0
ns
Following power application
t
MHCL
200
s
MODE high level hold to /CS low level
Standby Mode 2 Entry / Exit
Parameter
Symbol
MIN.
MAX.
Unit Note
Standby mode 2 entry
t
CHML
0
ns
/CS high level to MODE low level
Standby mode 2 exit to normal operation
t
MHCL1
30
ns
1
MODE high level to /CS low level
Standby mode 2 exit to normal operation
t
MHCL2
200
s
2
MODE high level to /CS low level
Notes 1. This is the time it takes to return to normal operation from Standby Mode 2 (data hold: 16M bits / 8M bits / 4M
bits).
2. This is the time it takes to return to normal operation from Standby Mode 2 (data not held).
Preliminary Data Sheet M15867EJ5V0DS
20
PD4664312-X
6. Timing Charts
Figure 6-1. Read Cycle Timing Chart 1 (/CS Controlled)
/CS (Input)
Address (Input)
Data Out
Q2
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
Data Out
Q1
t
RC
t
ACS
t
ACS
t
CP
A1
A2
A3
t
CP
t
CLZ
t
CLZ
t
CHZ
t
CHZ
t
CHAH
t
CHAH
/LB, /UB (Input)
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-2. Read Cycle Timing Chart 2 (/OE Controlled)
/CS (Input)
Address (Input)
Data Out Q2
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
t
ASO
Data Out Q1
t
OE
t
RC
t
AA
t
ASO
t
OE
t
ASO
t
OP
t
OP
A1
A2
A3
t
OHZ
t
OLZ
t
OHZ
t
OLZ
t
OHAH
t
OHAH
t
AA
/LB, /UB (Input)
t
BHAH
t
BHAH
Remark In read cycle, MODE and /WE should be fixed to high level.
Preliminary Data Sheet M15867EJ5V0DS
21
PD4664312-X
Figure 6-3. Read Cycle Timing Chart 3 (/CS, /OE Controlled)
/CS (Input)
Address (Input)
Data Out Q2
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
Data Out Q1
t
RC
t
ACS
t
AA
A1
A2
A3
t
CLZ
t
OE
t
OHZ
t
CHZ
t
OHAH
t
CHAH
/LB, /UB (Input)
t
CLOL
t
OLZ
t
OHZ
t
OHAH
t
ASO
t
OLZ
t
OE
t
BHAH
t
BHAH
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-4. Read Cycle Timing Chart 4 (Address Controlled)
/CS (Input)
Address (Input)
Data Out
Q2
I/O (Output)
t
RC
/OE (Input)
Data Out
Q1
t
AA
A1
A2
A3
t
RC
t
AA
t
OH
t
OH
t
OH
/LB, /UB (Input)
Remark In read cycle, MODE and /WE should be fixed to high level.
Preliminary Data Sheet M15867EJ5V0DS
22
PD4664312-X
Figure 6-5. Read Cycle Timing Chart 5 (/LB, /UB Controlled)
/CS (Input)
Address (Input)
I/O (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
t
RC
A1
A2
A3
t
BHAH
t
BHAH
/LB, /UB (Input)
t
BA
t
BHZ
Data Out
Q1
t
BLZ
t
BA
t
BHZ
Data Out
Q2
t
BLZ
t
BP
t
BP
Remark In read cycle, MODE and /WE should be fixed to high level.
Figure 6-6. Page Read Cycle Timing Chart
I/O (Output)
Address
(A3 to A21) (Input)
Page Address
(A0 to A2) (Input)
/CS (Input)
/OE (Input)
t
PRC
t
PRC
t
PRC
t
RC
t
PAA
t
OH
t
PAA
t
OH
t
PAA
t
OH
t
ACS
t
OE
t
OH
A
N+1
A
N+2
A
N+3
A
N+7
Q
N
Q
N+1
Q
N+2
Q
N+3
Q
N+7
t
CHZ
t
OHZ
A
N
t
PAA
t
OH
t
PRC
t
PAA
t
OH
t
PRC
t
PAA
t
OH
t
PRC
t
PAA
t
OH
Q
N+4
Q
N+5
Q
N+6
A
N+4
A
N+5
A
N+6
t
PRC
High-Z
Remarks 1. In read cycle, MODE and /WE should be fixed to high level.
2. /LB and /UB are low level.
Preliminary Data Sheet M15867EJ5V0DS
23
PD4664312-X
Figure 6-7. Write Cycle Timing Chart 1 (/CS Controlled)
t
WC
t
AS
t
WC
t
AS
t
AS
A1
A2
A3
t
CW
t
CW
t
WR
t
WR
t
CP
t
CP
/CS (Input)
Address (Input)
/WE (Input)
/LB, /UB (Input)
Data In D2
Data In D1
t
DW
t
DH
t
DW
t
DH
/OE (Input)
t
ASO
t
OHAH
t
OES
t
OEH
I/O (Input)
High-Z
High-Z
High-Z
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
24
PD4664312-X
Figure 6-8. Write Cycle Timing Chart 2 (/WE Controlled)
Data In D2
t
WC
t
AS
Data In D1
t
WC
t
AS
t
WHP
A1
A2
A3
t
CW
t
WR
t
CW
t
DW
t
DH
t
DW
t
DH
t
WP
t
WP
/OE (Input)
t
CP
t
ASO
t
OHAH
t
OES
t
OEH
t
BHAH
t
BHAH
t
WR
t
CP
t
CHAH
t
CHAH
/CS (Input)
Address (Input)
I/O (Input)
High-Z
High-Z
High-Z
/WE (Input)
/LB, /UB (Input)
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
25
PD4664312-X
Figure 6-9. Write Cycle Timing Chart 3 (/WE Controlled)
t
WC
t
AS
t
WC
t
AS
t
ASO
A1
A2
A3
t
WR
t
WR
/OE (Input)
t
OHAH
t
OES
t
OEH
t
WHP
t
AW
t
AW
t
DW
t
DH
t
DW
t
DH
t
WP
t
WP
t
BHAH
t
BHAH
/CS (Input)
Address (Input)
Data In D2
I/O (Input)
High-Z
High-Z
High-Z
/WE (Input)
Data In D1
/LB, /UB (Input)
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
26
PD4664312-X
Figure 6-10. Write Cycle Timing Chart 4 (/LB, /UB Controlled)
t
WC
t
AS
t
WC
t
AS
A1
A2
A3
t
WR
t
WR
t
DW
t
DH
t
DW
t
DH
t
BW
t
BW
t
BP
t
BP
t
ASO
/OE (Input)
t
OHAH
t
OES
t
OEH
/CS (Input)
Address (Input)
Data In D2
I/O (Input)
High-Z
High-Z
High-Z
/WE (Input)
Data In D1
/LB, /UB (Input)
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
27
PD4664312-X
Figure 6-11. Write Cycle Timing Chart 5 (/LB, /UB Independent Controlled)
t
WC
t
AS
t
WC
t
AS
A1
A2
A3
t
WR
t
WR
t
DW
t
DH
t
DW
t
DH
t
BW
t
BW
t
ASO
/OE (Input)
t
OHAH
t
OES
t
OEH
t
BP
/CS (Input)
Address (Input)
Data In D2
I/O0 to I/O7 (Input)
High-Z
High-Z
High-Z
High-Z
/WE (Input)
Data In
D1
/LB (Input)
/UB (Input)
I/O8 to I/O15 (Input)
Cautions 1. During address transition, at least one of pins /CS and /WE, or both of /LB and /UB pins should be
inactivated.
2. Do not input data to the I/O pins while they are in the output state.
3. In write cycle, MODE and /OE should be fixed to high level.
Remark Write operation is done during the overlap time of a low level /CS, /WE, /LB and/or /UB.
Preliminary Data Sheet M15867EJ5V0DS
28
PD4664312-X
Figure 6-12. Mode Register Setting Timing Chart
/LB, /UB (Input)
/WE (Input)
/CS (Input)
Address (Input)
/OE (Input)
I/O (Input)
t
RC
t
RC
t
WC
t
WC
3FFFFFH
t
WP
t
WR
t
WP
t
WR
t
DW
t
DH
t
DW
t
DH
3FFFFFH
3FFFFFH
3FFFFFH
xxxxH
xxxxH
Mode Register Setting
High-Z
High-Z
High-Z
Figure 6-13. Mode Register Setting Flow Chart
Start
End
Address= 3FFFFFH
Read with toggled the /CS, /OE
Address = 3FFFFFH
Write
Data = 00H?
No
Mode register setting exit
Fail
Address = 3FFFFFH
Write
Data = xxH?
No
Note
Note xxH = 04H, 05H, 06H, 07H
No
No
No
No
Address= 3FFFFFH
Read with toggled the /CS, /OE
Preliminary Data Sheet M15867EJ5V0DS
29
PD4664312-X
Figure 6-14. Standby Mode 2 (data hold: 16M bits / 8M bits / 4M bits) Entry / Exit Timing Chart
/CS (Input)
t
CHML
t
MHCL1
MODE (Input)
Standby
mode 1
Standby mode 2
(Data hold: 16M bits / 8M bits / 4M bits)
Figure 6-15. Standby Mode 2 (data not held) Entry / Exit Timing Chart
/CS (Input)
t
CHML
t
MHCL2
MODE (Input)
Standby
mode 1
Standby mode 2
(Data not held)
Preliminary Data Sheet M15867EJ5V0DS
30
PD4664312-X
7. Package Drawing
A
S
B
10
9
8
7
6
5
4
3
2
1
C B A
D
E
F
G
H
J
K
L
M
N
P
ZD
ZE
A
A1
A2
INDEX MARK
e
y
S
y1
S
ITEM
MILLIMETERS
D
E
w
e
A
A1
A2
b
x
y
y1
ZD
ZE
9.0
0.1
12.0
0.1
1.14
0.08
0.1
0.2
0.9
0.8
0.2
1.3
0.1
0.8
0.40
0.05
0.16
0.05
93-PIN TAPE FBGA (12x9)
P93F9-80-CR2
S
w
B
S
w
A
S
x
b
A B
M
E
D
Preliminary Data Sheet M15867EJ5V0DS
31
PD4664312-X
8. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
PD4664312-X.
Type of Surface Mount Device
PD4664312F9-CR2: 93-pin TAPE FBGA (12 x 9)
Preliminary Data Sheet M15867EJ5V0DS
32
PD4664312-X
9. Revision History
Edition/
Page
Type of
Location
Description
Date
This
Previous
revision
(Previous edition
This edition)
edition
edition
5th edition/
Throughout Throughout
Deletion
Class
-C75X, -C85X, -E85X, -E10X,
Aug. 2002
-BE85X, -CE80X, -CE90X
Modification Supply Voltage (Chip)
2.6 to 3.1 V
2.7 to 3.1 V
p.1
p.1
Deletion
Features
Fast access time: 80, 85, 90, 100 ns
Fast page access time: 30, 35 ns
pp.1, 15
pp.1, 15
Modification Operating supply current
-BE75X: TBD
40 mA
p.17
pp.17, 18
Addition
Read Cycle
t
OP
(MIN.): 2ns
p.20
p.22
Modification Figure 6-2
Timing charts are modified.
p.21
p.23
Modification Figure 6-3
Timing charts are modified.
Preliminary Data Sheet M15867EJ5V0DS
33
PD4664312-X
[ MEMO ]
Preliminary Data Sheet M15867EJ5V0DS
34
PD4664312-X
[ MEMO ]
Preliminary Data Sheet M15867EJ5V0DS
35
PD4664312-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD4664312-X
M8E 00. 4
The information in this document is current as of August, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
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NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
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Customers must check the quality grade of each semiconductor product before using it in a particular
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Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
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