Document Outline
- COVER
- DESCRIPTION
- FEATURES
- PIN NAMES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN FUNCTIONS
- TRUTH TABLE 1 (COUNTER BLOCK)
- TRUTH TABLE 2 (LATCH & OUTPUT BLOCKS)
- 1. DESCRIPTION OF OPERATIONS
- 2. OPERATING PRECAUTIONS
- ABSOLUTE MAXIMUM RATINGS
- DC CHARACTERISTICS
- AC CHARACTERISTICS
- Sample Application Circuits
- RECOMMENDED SOLDERING CONDITIONS
- PACKAGE DRAWINGS
DESCRIPTION
The
PD4704 is 8-bit up/down counters for extension of the
PD4702 incremental encoder counter. They perform
an up/down-count using an 8-bit width with a
PD4702 carry or borrow signal as input. In addition, a carry output
and borrow output are also provided for further extension of the count width, enabling extension to be performed
in 8-bit units.
FEATURES
8-bit up/down counter for extension of
PD4702
Count data output controllable (latch and 3-state output)
Extension carry and borrow outputs
CMOS, single +5 V power supply
PIN NAMES
Up
: Up-count input
Down
: Down-count input
Reset
: Counter reset input
STB
: Latch strobe signal input
OE
: Output control signal input
CD
0-7
: Count data outputs
Carry
: Carry pulse output
Borrow : Borrow pulse output
ORDERING INFORMATION
MOS INTEGRATED CIRCUIT
PD4704
EXTENSION 8-BIT UP/DOWN COUNTER
CMOS INTEGRATED CIRCUITS
Part Number
Package
PD4704C
20-pin plastic DIP
(300 mil)
PD4704G
20-pin plastic SOP
(300 mil)
PIN CONFIGURATION (Top View)
1
2
3
4
5
6
7
8
9
10
Reset
A
B
NC
CD
0
CD
1
CD
2
CD
3
NC
V
SS
V
DD
Carry
Borrow
STB
OE
CD
7
CD
6
CD
5
CD
4
NC
20
19
18
17
16
15
14
13
12
11
Document No.
IC-3305A (2nd edition)
(O. D. No.
IC-8762B)
Date Published April 1997 P
Printed in Japan
1993
DATA SHEET
2
PD4704
BLOCK DIAGRAM
Pin Name
Input/Output
Up
Input
Down
D
0 to 7
Output
(3-state)
Carry
Output
Borrow
Output
RESET
Input
(Schmitt)
OE
Input
STB
Input
V
DD
GND
Function
Up-count & down-count signal input pins
Count is performed on rise of signal.
Count data output pins. Activated when OE is "L", high impedance outputs when OE
is "H".
8-bit counter carry signal output pin (active-low)
8-bit counter borrow signal output pin (active-low)
8-bit counter reset signal output pin
Counter is reset when this pin is "H".
Count data output control signal input pin
Counter data output latch signal. Data is latched on the fall of STB, and is held while
STB = "L".
Power supply input pin
Ground pin
PIN FUNCTIONS
Reset
A
B
Phase
Discrimination
Edge Detection
8-Bit Up/Down Counter
8-Bit Latch
3-State Output
Carry
Borrow
STB
OE
CD
07
3
PD4704
TRUTH TABLE 1 (COUNTER BLOCK)
UP
DOWN
RESET
Carry
Borrow
Remarks
H
Reset
H
H
Reset
H
L
Down-count
H
L
Up-count
L
L
Disabled (count undefined)
L
L
Disabled (count undefined)
H
L
L
H
L
Borrow output when count = 00
H
L
H
L
L
H
Carry output when count = 0FF
H
TRUTH TABLE 2 (LATCH & OUTPUT BLOCKS)
STB
OE
CD
0
to CD
7
H
Output disable (3-state)
L
Output enable
H
Data through (count value load)
L
Data latch (count value retention)
: H or L
: H or L
4
PD4704
1.
DESCRIPTION OF OPERATIONS
(1)
Count operation
The
PD4704 is designed as 8-bit up/down counter for extension of the
PD4702. The first-stage Carry output
is connected to the UP input of the
PD4704, and similarly, the Borrow output is connected to the DOWN input. A
count is executed on the rising edge of the UP input or DOWN input.
If the
PD4704 is to be used alone, without being connected to the
PD4702, either UP or the DOWN must be "H".
If a count pulse is input to UP or DOWN while the other is "L", the count value may change.
(2)
Latch operation
An R-S flip-flop is inserted in the latch circuit input as shown in Fig. 1, and when STB is changed from "H" to "L"
while the UP or DOWN input is "L", the internal latch signal STB' remains at "H" until the end of the count operation.
Therefore, latching is not performed during a count operation. If STB changes from "H" to "L" t
SUDSTB1
(40 ns) or
more after the falling edge of UP or DOWN, the post-count data is latched, and if STB changes from "H" to "L" within
t
SUDSTB2
(10 ns) after the falling edge of UP or DOWN, then conversely, the pre-count data is latched.
Caution is required since, when UP or DOWN is "L" (during a count operation), the latch operation is kept waiting
even if STB is changed from "H" to "L", and therefore if a reset is executed the latch contents will also be reset (see
Figs. 2 and 3).
Fig. 1 STB Input Circuit
From UP/DOWN Circuit
STB'
STB
Count Clock
5
PD4704
UP/DOWN
STB
t
SUDSTB1
t
SUDSTB2
If STB changes from "H" to "L" and a reset is
executed in this period, the latch is also reset.
Post-count value latched
Pre-count value latched
Either pre- or post-count value latched
UP/DOWN
STB
RESET
t
SUDSTB1
t
DUDCD
Fig. 2 Relation Between STB Timing and Counter Value
Fig. 3 STB and RESET Timing
(3)
Carry & borrow outputs
If the counter performs an up-count operation when the count value is 0FF
H
, an active-low pulse is output to the
Carry output (the pulse width is virtually the same as the UP or DOWN pulse L period). Similarly, if the counter
performs a down-count operation when the count value is 00
H
, an active-low pulse is output to the Borrow output.
A Borrow pulse is also output if a down-count operation is performed while RESET is "H" (during a reset), and
therefore, when a
PD4704 is added, a reset must be executed at the same time.
6
PD4704
2.
OPERATING PRECAUTIONS
As the
PD4704 incorporates an 8-bit counter, a large transient current flows in the case of a count value which
changes all the bits (such as 00
H
0FF
H
or 7F
H
080
H
). This will cause misoperation unless the impedance of the
power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1
F)
be connected between V
DD
and V
SS
right next to the IC as shown in Fig. 4.
Fig. 4 Decoupling Capacitor
V
DD
V
SS
+5 V
C
C : 0.1 uF tantalum electrolytic laminated
ceramic capacitor, etc.
PD4704
7
PD4704
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
C, V
SS
= 0 V)
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
V
DD
0.5 to +7.0
V
Input voltage
V
I
1.0 to V
DD
+1.0
V
Output voltage
V
O
0.5 to V
DD
+0.5
V
Operating temperature
T
opt
40 to +85
C
Storage temperature
T
stg
65 to +150
C
Permissible loss
P
D
500 (DIP)
200 (SOP)
mW
DC CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= +5 V
10 %)
PARAMETER
SYMBOL
TEST CONDITIONS
RATING
UNIT
MIN.
MAX.
Input voltage low
V
IL
0.8
V
Input voltage high
V
IH
Reset
2.6
V
V
IH
Other than the above
2.2
V
Output voltage low
V
OL
I
OL
= 12 mA
0.45
V
Output voltage high
V
OH
I
OH
= 4 mA
V
DD
0.8
V
Static consumption current
I
DD
V
I
= V
DD
, V
SS
50
A
Input current
I
I
V
I
= V
DD
, V
SS
1.0
1.0
A
3-state output leak current
I
OFF
10
10
A
Dynamic consumption current
I
DD dyn
f
IN
= 16 MHz, C
L
= 50 pF
12
mA
Hysteresis voltage
V
H
Reset
0.2
V
AC CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= +5 V
10 %)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
Cycle
t
CYCT
f
in
= 16 MHz
60
ns
Up
Input pulse width
t
PWUDL
25
ns
Down
t
PWUDH
35
ns
Setup time
t
SRSUD
0
ns
Up/down switchover setupt time
t
SUDM
100
ns
Reset time
t
DRSCD
60
ns
Output delay
t
DUDCD
70
ns
CD
0 to 7
Output delay
t
DOECD
50
ns
Output delay
t
DSTBCD
50
ns
Float time
t
FOECD
40
ns
Carry
Output delay
t
DUDCB1
50
ns
Borrow
t
DUDCB2
100
ns
Output pulse width
t
PWCB
30
ns
RESET
Reset pulse width
t
PWRS
40
ns
STB
Setting time
t
SUDSTB1
40
ns
t
SUDSTB2
10
ns
8
PD4704
AC Timings
Fig. 1 Up/Down Signal Input Timing
UP/DOWN
t
CYCT
t
PWUDL
t
PWUDH
t
SUDM
t
CYCT
t
PWUDL
t
PWUDH
Fig. 2 Count Data Output Timing
UP/DOWN
RESET
t
PWRS
t
SRSUD
t
DRSCD
t
DUDCD
t
DOECD
Hi-Z
t
SUDSTB1
t
DSTBCD
t
DSTBCD
t
FOECD
Hi-Z
CD
0
CD
7
OE
STB
Fig. 3 Carry/Borrow Signal Output Timing
UP/DOWN
Carry
Borrow
t
DUDCB1
t
DUDCB2
t
PWCB
t
DUDCB1
t
DUDCB2
t
PWCB
Fig. 4 Strobe Signal Output Timing
UP/DOWN
STB
t
SUDSTB1
t
SUDSTB2
9
PD4704
Consumption Current Measurement Circuit
AC Test Input Waveform
A
B
STB
OE
D
7
D
1
D
0
C
L
C
L
C
L
V
DD
2.6 V
0.8 V
STB input connected to V
DD
or OE input connected to V
SS
.
Load on all outputs, C
L
= 50 pF.
Measurement Conditions
A, B inputs
f
IN
= 16 MHz
3 state output
V
IH
V
IL
V
IH
= 2.6 V (RESET input)
V
IH
= 2.2 V (inputs other than RESET)
V
IL
= 0.8 V
Timing measurement is performed at 1.5 V.
OE
t
DOECD
Output
1.5 V
t
DFOECD
V
OH
0 V
V
DD
V
OL
1.5 V
1.5 V
90 %
10 %
Output
Output
R = 1 k
C = 50 pF
V
DD
R
R
C
C
10
PD4704
PD4702
PD4704
Sample Application Circuits
16-bit counter
Data Bus
Incremental Rotary Encoder
8
8
8
RESET
CS
L
CS
H
A
B
STB
OE
Carry
Borrow
D
0
D
7
R
UP
Down
STB
OE
D
0
D
7
R
The application circuits and their parameters are for references only and are not intended for use in actual design-in's.
11
PD4704
RECOMMENDED SOLDERING CONDITIONS
The following conditions (see table below) must be met when soldering this product.
Please consult with our sales offices in case other soldering process is used, or in case soldering is done under
different conditions.
TYPES OF SURFACE MOUNT DEVICE
For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (IEI-1207).
PD4704G
Soldering process
Soldering conditions
Symbol
Infrared ray reflow
Peak package's surface temperature: 235
C or below,
IR35-00-2
Reflow time: 30 seconds or below (210
C or higher),
Number of reflow process: 2, Exposure limit*: None
VPS
Peak package's surface temperature: 215
C or below,
VP15-00-2
Reflow time: 40 seconds or below (200
C or higher),
Number of reflow process: 2, Exposure limit*: None
Wave soldering
Solder temperature: 260
C or below,
WS60-00-1
Flow time: 10 seconds or below,
Number of flow process: 1, Exposure limit*: None
Partial heating method
Terminal temperature: 300
C or below,
q
q
Flow time: 10 seconds or below,
Exposure limit*: None
*
Exposure limit before soldering after dry-pack package is opened.
Storage conditions: 25
C and relative humidity at 65 % or less.
Note Do not apply more than a single process at once, except for "Partial heating method".
TYPES OF THROUGH HOLE MOUNT DEVICE
PD4704C
Soldering process
Soldering conditions
Symbol
Wave soldering
Solder temperature: 260
C or below,
Flow time: 10 seconds or below
REFERENCE
Dcodument name
Document No.
NEC semiconductor device reliability/quality control system
IEI-1212
Quality grade on NEC semiconductor devices
IEI-1209
Semiconductor device mounting technology manual
IEI-1207
Semiconductor device package manual
IEI-1213
Guide to quality assurance for semiconductor devices
MEI-1202
Semiconductor selection guide
MF-1134
12
PD4704
20PIN PLASTIC DIP (300 mil)
ITEM
MILLIMETERS
INCHES
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
P20C-100-300A,C-1
N
0.25
0.01
R
0~15
0~15
A
25.40 MAX.
1.000 MAX.
B
1.27 MAX.
0.050 MAX.
F
1.1 MIN.
0.043 MIN.
G
3.50.3
0.1380.012
J
5.08 MAX.
0.200 MAX.
K
7.62 (T.P.)
0.300 (T.P.)
C
2.54 (T.P.)
0.100 (T.P.)
D
0.500.10
0.020+0.004
0.005
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
L
6.4
0.252
M
0.25
0.010+0.004
0.003
+0.10
0.05
2) ltem "K" to center of leads when formed parallel.
M
R
M
I
H
G
F
D
N
C
B
K
P
0.9 MIN.
0.035 MIN.
1
10
20
11
P
L
A
J
13
PD4704
20 PIN PLASTIC SOP (300 mil)
ITEM
MILLIMETERS
INCHES
A
B
C
E
F
G
H
I
J
13.00 MAX.
1.27 (T.P.)
1.8 MAX.
1.55
7.70.3
0.78 MAX.
0.12
1.1
5.6
M
0.10.1
N
0.512 MAX.
0.031 MAX.
0.0040.004
0.071 MAX.
0.061
0.3030.012
0.220
0.043
0.005
0.050 (T.P.)
P20GM-50-300B, C-4
P
3
3
+7
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
D
0.40
0.016
+0.10
0.05
K
0.20
0.008
+0.10
0.05
L
0.60.2
0.024
0.10
3
+7
3
0.004
+0.008
0.009
+0.004
0.002
+0.004
0.003
A
C
D
G
P
detail of lead end
F
E
B
H
I
L
K
M
J
N
M
1
10
11
20
14
PD4704
[MEMO]
15
PD4704
[MEMO]
PD4704
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
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