Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATION
- BLOCK DIAGRAM
- PIN FUNCTION
- ELECTRICAL CHARACTERISTICS
- FUNCTION SPECIFICATIONS
- FUNCTION OUTLINE
- MODE DESCRIPTION
- PACKAGE DRAWINGS
- RECOMMENDED SOLDERING CONDITIONS
1995
DATA SHEET
The
PD4991A is a CMOS integrated circuit that has the ability to input/output 4-bit parallel time data and calendar
data to/from a microcomputer and includes an alarm function.
Its reference oscillation frequency is 32.768 kHz. Hour, minute, second, year, month, day, and date data is stored
internally.
The
PD4991A consumes 30 % less power than the
PD4991.
FEATURES:
Time (hour, minute, and second) and calendar (leap year, year, month, day, and date) counters
Leap year can be automatically identified or set
12- and 24-hour modes selectable
4-bit parallel input/output in BCD data format
Alarm function (hour, minute, second, month, day, date)
One of 0.1, 1.0, 10, 30, and 60-s interval timer outputs selectable
One of 2048, 1024, 64, 16, 1 Hz, 1-pulse output, and H
L output selectable as alarm coincidence output
Upward compatible with
PD4991
Low power consumption: 2
A typ. (V
DD
= 2.4 V)
ORDERING INFORMATION:
Part Number
Package
PD4991ACX
18-pin plastic DIP (300 mil)
PD4991AGS
20-pin plastic SOP (300 mil)
PD4991A
MOS INTEGRATED CIRCUIT
4-BIT PARALLEL I/O CALENDAR CLOCK
Document No. IC-3309 (1st edition)
(O.D. No. IC-7892A)
Date Published March 1997 P
Printed in Japan
1993
PD4991A
2
PIN CONFIGURATION (Top View)
1
CS
1
2
TP
1
3
TP
2
4
A
0
5
A
1
6
A
2
7
A
3
8
OE
9
V
SS
18 V
DD
17 X
IN
16 X
OUT
15 CS
2
14 D
3
13 D
2
12 D
1
11 D
0
10 WE
PD4991ACX
PD4991AGS
1
CS
1
2
TP
1
3
TP
2
4
A
0
5
NC
6
A
1
7
A
2
8
A
3
9
OE
10
V
SS
20 V
DD
19 X
IN
18 X
OUT
17 CS
2
16 D
3
15 NC
14 D
2
13 D
1
12 D
0
11 WE
PD4991A
3
BLOCK DIAGRAM
MPX
X
IN
X
OUT
OSC
1/2
15
15stage Binary Divider
TIMING PULSE GENERATOR
SEC.
MIN.
HOUR
WEEK
DAY
MONTH
YEAR
TIME COUNTER
COMPARATOR
ALARM
CONTROL REGISTER 2
CONTROL REGISTER 1
MODE REGISTER
CLOCK STOP
CLOCK WAIT
CS
1
CS
2
OE
WE
DATA BUS
CONTROLLER
D
3
D
2
D
1
D
0
ADDRESS BUS
CONTROLLER
A
3
A
2
A
1
A
0
ADDRESS
DECODER
TP
1
TP
2
Nch OPEN DRAIN
DATA BUS
PD4991A
4
PIN FUNCTION
WE ..................... Write control pin (input).
The contents of the data bus are written to an address specified by the address bus at the
rising edge of WE.
OE ..................... Read control pin (input).
While OE = "L" level, the contents specified by the address bus are read to the data bus.
A
3
to A
0
.............. Address bus pins (input).
These pins specify an internal address of the
PD4991A.
D
3
to D
0
............. Data bus pin (I/O).
These pins constitute a bidirectional bus.
CS
1
, CS
2
........... Chip select pins (input).
When CS
1
= "L" and CS
2
= "H", data can be transferred between the
PD4991A and the CPU.
TP
1
.................... Timing pulse pin (output) (N-ch open-drain).
Outputs an alarm coincidence signal.
TP
2
.................... Timing pulse pin (output) (N-ch open-drain).
Outputs an interval timer signal.
X
IN
...................... Crystal oscillation signal pin (input).
Inverter input for oscillation.
X
OUT
................... Crystal oscillation signal pin (output).
Inverter output for oscillation.
V
DD
..................... Positive power supply pin.
V
SS
..................... GND pin.
PD4991A
5
ABSOLUTE MAXIMUM RATINGS (V
SS
= 0 V)
PARAMETER
SYMBOL
RATINGS
UNIT
Supply Voltage
V
PP
0.3 ~ 7.0
V
Input Voltage Range
V
IN
0.3 ~ V
PP
+ 0.3
V
Output Pin Breakdown Voltage
V
OUT
7.0
V
Low-Level Output Current
I
OUT
30
mA
(N-ch open-drain)
Operating Ambient Temperature
T
opt
40 ~ +85
C
Storage Temperature
T
stg
65 ~ +125
C
ELECTRICAL CHARACTERISTICS
(V
SS
= 0 V, f = 32.768 kHz, C
G
= C
D
= 20 pF, C
i
= 20 k
, T
a
= 40 to +85
C)
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT
CONDITIONS
Operating Voltage Range
V
DD
2.0
5.5
V
High-level Input Voltage
V
IH
0.7 V
DD
V
DD
V
Low-level Input Voltage
V
IL
V
SS
0.3 V
DD
V
Current Consumption *
I
DD
5
14
A
V
DD
= 3.6 V, V
IN
= V
SS
, T
a
= 40 ~ +70
C
Current Consumption *
I
DD
10
A
V
DD
= 3.0 V, V
IN
= V
SS
, T
a
= 40 ~ +70
C
Current Consumption *
I
DD
2
6
A
V
DD
= 2.4 V, V
IN
= V
SS
, T
a
= 40 ~ +70
C
High-Level Input Leakage Current
I
LIH
+1.0
A
V
DD
= 5.5 V, V
IN
= V
DD
Low-Level Input Leakage Current
I
LIL
1.0
A
V
DD
= 5.5 V, V
IN
= V
SS
High-Level Output Voltage
V
OH
2.4
V
I
OH
= 1.0 mA
Low-Level Output Voltage
V
OL1
0.4
V
I
OL
= 2.0 mA
Low-Level Output Voltage
V
OL2
0.4
V
I
OL
= 1.0 mA (Nch Open Drain)
High-Level Leakage Current
I
LOH
1.0
A
TP
out
= V
DD
(Nch Open Drain)
* If V
IN
pins are not V
SS
, Current Consumption increase in value.
AC CHARACTERISTICS
Write cycle (Unless otherwise specified, V
DD
= 5 V
10 %, T
a
= 40 to +85
C)
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT
CONDITIONS
Cycle Time
t
WC
150
CS-WE Reset Time
t
CW
120
Address-WE Reset Time
t
AW
120
Address-WE Setup Time
t
AS
0
Write Pulse Width
t
WP
90
ns
Address Hold Time
t
WR
20
Input Data Setup Time
t
DW
50
Input Data Hold Time
t
DH
0
WE-Output Floating Time
t
WHZ
50
PD4991A
6
Write Cycle (V
DD
= 2.7 to 3.6 V, T
a
= 40 to +85
C)
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT
CONDITIONS
Cycle Time
t
WC
210
CS-WE Reset Time
t
CW
170
Address-WE Reset Time
t
AW
170
Address-WE Setup Time
t
AS
0
Write Pulse Width
t
WP
30
ns
Address Hold Time
t
WR
20
Input Data Setup Time
t
DW
100
Input Data Hold Time
t
DH
0
WE-Output Floating Time
t
WHZ
70
PD4991A
7
Write cycle timing 1
Write cycle timing 2 (OE = V
IL
)
CS
OE
ADDRESS
WE
D
OUT
D
IN
t
WC
t
AW
t
CW
t
WP
t
WR
t
AS
t
OHZ
t
DW
t
DH
CS
ADDRESS
WE
D
OUT
D
IN
t
WC
t
AW
t
CW
t
WP
t
WR
t
AS
t
WHZ
t
DW
t
DH
t
OW
PD4991A
8
READ CYCLE (Unless otherwise specified, V
DD
= 5 V
10 %, T
a
= 40 to +85
C)
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT
CONDITIONS
Cycle Time
t
RC
150
Address Access Time
t
AA
150
CS-Access Time
t
ACS
150
OE-Output Delay Time
t
OE
75
OE-Output Delay Time
t
OLZ
5
ns
OE-Output Delay Time
t
OHZ
50
Output Hold Time
t
OH
15
CS-Output Set Time
t
CLZ
0
CS-Output Floating Time
t
CHZ
5
Read Cycle (V
DD
= 2.7 to 3.6 V, T
a
= 40 to +85
C)
PARAMETER
SYMBOL MIN.
TYP.
MAX.
UNIT
CONDITIONS
Cycle Time
t
RC
210
Address Access Time
t
AA
210
CS-Access Time
t
ACS
210
OE-Output Delay Time
t
OE
110
OE-Output Delay Time
t
OLZ
10
ns
OE-Output Delay Time
t
OHZ
70
Output Hold Time
t
OH
20
CS-Output Setup Time
t
CLZ
15
CS-Output Floating Time
t
CHZ
10
PD4991A
9
Read cycle timing 1
Read cycle timing 2
D
OUT
CS
ADDRESS
OE
t
ACS
t
CHZ
Output Data
t
OHZ
t
CLZ
t
RC
OE
ADDRESS
CS
D
OUT
t
RC
t
AA
t
OH
t
OE
t
OLZ
Output Data
PD4991A
10
FUNCTION SPECIFICATIONS
Reference frequency (X'tal OSC) ........... 32.768 kHz
Data format .............................................. BCD format
Data function
Year, month, day, date, hour, minute, and second counters
Leap year and months are automatically identified.
Leap year is identified every 4 years and can be set to any year.
Year is set in 2 digits.
Hour can be displayed in 12- or 24-hour mode.
Data input/output (D
3
, D
2
, D
1
, D
0
)
4-bit parallel input/output format
Data is written by WE signal and read by OE signal.
Function mode selection
With ADDRESS = "F
H
" (A
3
, A
2
, A
1
, A
0
= 1, 1, 1, 1), a mode is selected by DATA (D
3
, D
2
, D
1
, D
0
) input, and set
by input of WE signal.
A function is selected by ADDRESS input.
Timing pulse outputs (TP
1
, TP
2
)
TP
1
... Alarm coincidence signal.
One of the following is selectable:
2048 Hz
1024 Hz
64 Hz
16 Hz
1 Hz
1 pulse output (H
L)
TP
2
... Interval timer signal output.
One of the following is selectable:
60 s
30 s
10 s
1 s
0.1 s
Chip select (CS
1
, CS
2
)
When CS
1
= "H" or CS
2
= "L," all inputs except X
IN
are disabled (non-select).
When CS
1
= "L" and CS
2
= "H," all inputs are selected.
PD4991A
11
FUNCTION OUTLINE
The
PD4991A has the following three modes:
1
BASIC TIME MODE
In this mode, data can be written and read between the timer counter and the CPU. Moreover, control
registers 1 and 2 can be specified by a command*.
2
ALARM SET & TP
1
CONTROL MODE
In this mode, data is set to the alarm register, the function of TP
1
is set, and control registers 1 and 2 are
specified by a command*.
3
ALARM SET & TP
2
CONTROL MODE
In this mode, data is set to the alarm register, the function of TP
2
is set, the 12- or 24-hour mode is selected,
leap year identification function is set, and control registers 1 and 2 are specified by a command*.
* Control registers 1 and 2 are commonly used in all the modes.
To select a mode, write mode data to ADDRESS = "F
H
." Once a mode has been set, it is retained until a new
mode is set.
Table 1 shows the correspondence between modes and mode data.
PD4991A
12
Table 1 Correspondence between Mode Data and Modes
ADDRESS = (1, 1, 1, 1)
DATA
FUNCTION
MSB
LSB
0
*
0
0
BASIC TIME MODE
0
*
0
1
ALARM SET & TP
1
CONTROL MODE
0
*
1
0
ALARM SET & TP
2
CONTROL MODE
0
*
1
1
BASIC TIME MODE
1
*
*
*
Inhibited
* Irrelevant. This bit is ignored.
Note: The difference between mode (0, *, 0, 0) and mode (0, *, 1, 1) is that stages
10 to 15 of the 15-stage divider circuit are reset in the former mode when
the division stage reset command (
30 ADJ. RESET) is executed, and all
the stages of the divider circuit are reset in the latter mode.
Other commands are commonly used in both modes.
PD4991A
13
MODE DESCRIPTION
1.
BASIC TIME MODE (MODE = 0 * 0 0 B)
Thirteen types of counters are provided: 10-year, 1-year, 10-month, 1-month, 10-day, 1-day, date, 10-hour, 1-
hour, 10-minute, 1-minute, 10-second, and 1-second.
Date codes are 00H through 06H (0000 through 0110B).
(Correspondence between dates and date codes can be freely specified by the user.)
If leap year identification function is not used, the last day of February is always the 28th.
The addresses corresponding to the respective digits are shown in Table 2 Address Correspondence 1.
Specifications of control registers 1 and 2 are commonly applied to each mode. Tables 3 and 4 show correspondences
of data 1 and 2. Refer to these data correspondence tables when setting other modes.
Table 2 Address Correspondence 1
BASIC TIME MODE (MODE = 0, *, 0, 0)
DATA
FUNCTION
MSB
LSB
0
0
0
0
1-second digit
R/W
0
0
0
1
10-second digit
R/W
0
0
1
0
1-minute digit
R/W
0
0
1
1
10-minute digit
R/W
0
1
0
0
1-hour digit
R/W
0
1
0
1
10-hour digit
R/W
0
1
1
0
Date digit
R/W
0
1
1
1
1-day digit
R/W
1
0
0
0
10-day digit
R/W
1
0
0
1
1-month digit
R/W
1
0
1
0
10-month digit
R/W
1
0
1
1
1-year digit
R/W
1
1
0
0
10-year digit
R/W
1
1
0
1
CONTROL REGISTER 1
W/O
1
1
1
0
CONTROL REGISTER 2
R/W
1
1
1
1
MODE REGISTER
W/O
R/W : READ AND WRITE
W/O : WRITE ONLY
Note
The second most-significant bit of the data for the 10-hour digit serves as
an AM/PM flag in the 12-hour mode (AM = 0/PM = 1).
PD4991A
14
Table 3 Data Correspondence Table 1
CONTROL REGISTER1 (TIME COUNTER CONTROL)
ADDRESS = (1, 1, 0, 1)
D3
D2
D1
D0
W/O
0
NOP
RUN
NOP
NOP
1
CLOCK WAIT
*4
CLOCK STOP
*3
ADJUST (+/)30 s
*1
RESET
*2
*1. ADJUST (+/)30 s
Second digit
00 to 29
00 (second)
30 to 59
00 (second) + 1 (minute)
The BUSY flag remains set until a carry occurs.
In MODE (0, *, 0, 0), stages 10 to 15 of the 15-stage divider are reset.
In MODE (0, *, 1, 1), all the stages of the 15-stage divider are reset.
*2. RESET
In MODE (0, *, 0, 0), stages 10 to 15 of the 15-stage divider are reset.
In MODE (0, *, 1, 1), all the stages of the 15-stage divider are reset.
*3. CLOCK STOP
This command is used to write time.
To set time, execute the CLOCK RESET command and then the CLOCK STOP command. Then write
the time data. If the data is written without the clock stopped, the correct value may not be set.
*4. CLOCK WAIT
This command is used to read time.
When 1 is written to this bit, the clock is stopped. If the CLOCK RUN command is executed within 0.5
second, no delay in respect to the actual time occurs.
Table 4 Data Correspondence Table 2
CONTROL REGISTER2 (TP
1
/TP
2
CONTROL)
ADDRESS = (1, 1, 1, 0)
D3
D2
D1
D0
ALARM setting
Alarm coincidence
Output status
0
forced output flag
(TP
1
)
0: ENABLE
0: RESET
0: ENABLE
W/O
1: DISABLE
1: SET
1: DISABLE
1
INTERVAL CLOCK
INTERVAL COUNTER
Output status
(TP
2
)
0: RUN
0: NOP
0: ENABLE
1: CLK STOP
1: RESET
1: DISABLE
BUSY flag
Alarm coincidence flag
Interval flag
R/O
*
0: OFF
0: OFF
0: OFF
1: ON
1: ON
1: ON
*: Don't Care
R/O : READ ONLY
W/O : WRITE ONLY
PD4991A
15
2.
ALARM SET & TP
1
CONTROL MODE (MODE = 0 * 0 1)
ALARM SET & TP
2
CONTROL MODE (MODE = 0 * 1 0)
(1) Setting time to alarm register
The alarm register consists of a total of 44 bits with 4 bits each of 10-month digit, 1-month digit, 10-day digit,
1-day digit, date digit, 10-hour digit, 1-hour digit, 10-minute digit, 1-minute digit, 10-second digit, and 1-
second digit.
Manipulating alarm register
When "F
H
" is set to a certain digit of the alarm register, the digit is regarded as indicating an alarm
coincidence, which occurs when the value of the alarm register coincides with the contents of the time
counter, regardless of the data of the time counter.
If "F
H
" is set to all the digits, alarm coincidence occurs regardless of the data of the time counter. The
addresses corresponding to the respective digits are shown in Table 5 Address Correspondence Table
2.
Tables 6 and 7 Data Correspondence Tables 3 and 4 show the function control of TP
1
/TP
2
.
Example: An alarm coincidence occurs for 1 second at 54 minutes 32 seconds of every hour.
Digit
10-month 1-month
10-day
1-day
Date
10-hour
1-hour
10-minute 1-minute 10-second 1-second
Code
F
H
F
H
F
H
F
H
F
H
F
H
F
H
5
H
4
H
3
H
2
H
Example: An alarm coincidence occurs at 10 to 19 minites of every hour.
Digit
10-month 1-month
10-day
1-day
Date
10-hour
1-hour
10-minute 1-minute 10-second 1-second
Code
F
H
F
H
F
H
F
H
F
H
F
H
F
H
1
H
F
H
F
H
F
H
PD4991A
16
Table 5 Address Correspondence Table 2
ALARM SET & TP
1
CONTROL MODE (MODE = 0, *, 0, 1)
ALARM SET & TP
2
CONTROL MODE (MODE = 0, *, 1, 0)
ADDRESS
FUNCTION
MSB
LSB
0
0
0
0
1-second digit
R/W
0
0
0
1
10-second digit
R/W
0
0
1
0
1-minute digit
R/W
0
0
1
1
10-minute digit
R/W
0
1
0
0
1-hour digit
R/W
0
1
0
1
10-hour digit
R/W
0
1
1
0
Date digit
R/W
0
1
1
1
1-day digit
R/W
1
0
0
0
10-day digit
R/W
1
0
0
1
1-month digit
R/W
1
0
1
0
10-month digit
R/W
1
0
1
1
TP
1
/TP
2
FUNCTION CONTROL
*1
W/O
1
1
0
0
Leap year/12.24 HOUR SELECT
*2
R/W
1
1
0
1
CONTROL REGISTER1
W/O
1
1
1
0
CONTROL REGISTER2
R/W
1
1
1
1
MODE REGISTER
W/O
*: Don't Care. This bit is ignored.
R/W : READ AND WRITE
W/O : WRITE ONLY
*1. TP
1
FUNCTION CONTROL is performed in MODE (0, *, 0, 1).
TP
2
FUNCTION CONTROL is performed in MODE (0, *, 1, 0).
*2. The leap year counter is in MODE (0, *, 0, 1).
The 12/24 HOUR SELECT is in MODE (0, *, 1, 0).
PD4991A
17
Table 6 Data Correspondence Table 3
TP
1
FUNCTION CONTROL
(MODE = 0, *, 0, 1 ADDRESS = 1, 0, 1, 1)
DATA
FUNCTION
MSB
LSB
*
0
0
0
2048 Hz
W/O
*
0
0
1
1024 Hz
W/O
*
0
1
0
64 Hz
W/O
*
0
1
1
16 Hz
W/O
*
1
0
0
1 Hz
W/O
*
1
0
1
1-pulse output
W/O
*
1
1
0
"H"
"L"
W/O
*
1
1
1
BUSY
W/O
0
*
*
*
Alarm coincidence flag reset automatically
W/O
1
*
*
*
Alarm coincidence flag not reset automatically
W/O
W/O: WRITE ONLY
*: Don't Care
Table 7 Data Correspondence Table 4
TP
2
FUNCTION CONTROL
(MODE = 0, *, 1, 0 ADDRESS = 1, 0, 1, 1)
DATA
FUNCTION
MSB
LSB
*
0
0
0
0.1-s interval
W/O
*
0
0
1
1-s interval
W/O
*
0
1
0
10-s interval
W/O
*
0
1
1
30-s interval
W/O
*
1
0
0
60-s interval
W/O
0
1
1
1
BUSY
W/O
0
*
*
*
REPEAT
W/O
1
*
*
*
1 SHOT
W/O
W/O: WRITE ONLY
*: Don't Care
PD4991A
18
(2) Selecting 12-/24-hour mode
In the 12-hour mode, the second significant bit of the data for the 10-hour digit are used as an AM/PM flag.
AM = 00**
PM = 01**
Select the 12- or 24-hour mode before setting the time. Note that, if the mode is selected after the time has
been set, the data of the time counter is lost.
Table 8 Data Correspondence Table 5 shows how the 12- or 24-hour mode is selected.
Table 8 Data Correspondence Table 5
Leap year, 12-/24-hour mode selection
(MODE = 0, *, 1, 0 ADDRESS = 1, 1, 0, 0)
D3
D2
D1
D0
1: 24-hour mode
Leap Year
R/W
0: 12-hour mode
0: Valid
*
*
1: Invalid
*: Don't Care
Example:
In 12-hour mode
10-hour digit
1-hour digit
Hexadecimal
AM 8
0000
1000
08H
PM 8
0100
1000
48H
AM12
0001
0010
12H
PM12
0101
0010
52H
Notes on the use of the 12-hour mode
When writing AM12, write the lower digit and then the higher digit (i.e., write "2" to the 1-hour digit, and then
write "1" to the 10-hour digit); otherwise, PM12 may be set.
(3) Setting leap year counter
When a digit of year is written, the
PD4991A automatically sets the leap year counter.
Years are based on the Christian Era, and a leap year occurs every 4 years.
The user can directly write data to the leap year counter.
However, to do so, write the year counter first. If the leap year counter is written and then the year counter
is written, the leap year counter is automatically reset.
The leap year is identified when the value of the leap year counter is **00B.
The leap year counter can be set independently of the year counter.
The leap year counter is incremented in synchronization with the 1-year digit counter.
Table 9 Data Correspondence Table 6 shows how the leap year is identified.
PD4991A
19
Table 9 Data Correspondence Table 6
Leap year counter
(MODE = 0, *, 0, 1, ADDRESS = 1, 1, 0, 0)
D3
D2
D1
D0
R/W
*
*
Leap year counter (leap year = 0, 0)
*: Don't Care
Example
10-year
1-year
Leap year
digit
digit
counter
0 0 1 0
0 1 0 1
* * * *
Write 3 to 10-year digit
0 0 1 1
0 1 0 1
* * 1 1
Write 6 to 1-year digit
0 0 1 1
0 1 1 0
Incremented
* * 0 0
(Year 36 is a leap year
Write 4 to 10-year digit
0 1 0 0
0 1 1 0
leap year counter = 00H)
* * 1 0
(Year 46 is not a leap year
Write **00B to the leap year counter
0 1 0 0
0 1 1 0
leap year counter = 00H)
* * 0 0
3.
TIMING PULSE
TP1
The signal output from the TP
1
pin is the alarm coincidence signal. The output waveform is selected from 2048
Hz, 1024 Hz, 64 Hz, 16 Hz, 1 Hz, 1-pulse output, and "H"
"L", depending on the contents set to the TP
1
CONTROL REGISTER.
1-puse output
One pulse is output when the value of the alarm register coincides with the contents of the time counter.
Fig. 1 1-Pulse Output Waveform
.
.
Alarm coincidence
30.5 s
PD4991A
20
"H"
"L" output
The output signal of TP
1
goes from "H" to "L" when the value of the alarm register coincides with the contents
of the time counter.
Fig. 2 "H"
"L" Output Waveform
Alarm coincidence
Alarm coincidence flag, auto RESET
When the value of the alarm register coincides with the contents of the time counter, a signal is output to the
TP
1
pin.
This signal remains output until the value of the alarm register does not coincide with the time counter contents.
Fig. 3 TP
1
Output Waveform (with AUTO RESET)
2048 Hz
1 Hz
~
1 pulse
Alarm coincidence
Alarm coincidence
"H"
"L"
Alarm coincidence
30.5 s
T
T
PD4991A
21
Fig. 4 TP
1
Output Waveform (without AUTO RESET)
Without RESET of the alarm coincidence flag
2048 Hz
1 Hz
~
1 pulse
Alarm coincidence
Another alarm coincidence
Alarm coincidence
Another alarm coincidence
"H"
"L"
Alarm coincidence
Another alarm coincidence
30.5 s
Figs. 5 and 6 show examples of applications using TP
1
.
Fig. 5 TP
1
Output Status (AUTO RESET mode)
TP
1
2048 Hz
1 Hz
~
"H"
"L"
1 pulse
ALARM ENABLE
Alarm coincidence flag reset
Output status enable
Alarm coincidence
Alarm does not
coincide
Alarm coincidence
flag set
Alarm coincidence
Alarm does not
coincide
Output status
disabled
Alarm
coincidence
Alarm
coincidence
flag set
Alarm does not
coincide
Alarm
coincidence
flag ON
Alarm
coincidence
flag OFF
Alarm
coincidence
flag ON
Alarm
coincidence
flag OFF
Alarm
coincidence
flag ON
30.5 s
PD4991A
22
Fig. 6 TP
1
Output Status (without AUTO RESET)
TP
2
SET (MODE = 0 * 1 1 B)
The TP
2
pin outputs an interval timer signal.
This signal is cyclically output.
The cycle at which the interval timer signal is output can be selected between 0.1 s, 1 s, 10 s, 30 s, and 60 s,
depending on the contents indicated by the TP
2
CONTROL REGISTER. Note, however, that the 0.1-s cycle
does not last exactly for 0.1 second, but that five 0.1-s cycles are equivalent to one 0.5 second.
If
30 s ADJ, RESET is executed in mode (0, *, 1, 1), an error occurs in the cycle.
Fig. 7 TP
2
Output Waveform
REPEAT output
1-shot output
T
T
T
START
30.5 s
T
T
30.5 s
START
T
30.5 s
TP
1
2048 Hz
1 Hz
~
"H"
"L"
1 pulse
ALARM ENABLE
Alarm coincidence flag reset
Output status enabled
Alarm coincidence
Alarm does not
coincide
Alarm coincidence
flag reset
Alarm coincidence
flag set
Alarm
coincidence
flag ON
Alarm
coincidence
flag OFF
Alarm
coincidence
flag ON
30.5 s
Alarm coincidence
Alarm does not
coincide
Output status
disabled
Output status
enabled
PD4991A
23
BUSY output
The BUSY signal can be output to the TP
1
and TP
2
pins.
When output of the BUSY signal is specified, only the BUSY signal is output to the TP
1
and TP
2
pins.
The contents of the CONTROL REGISTER 2 are not affected, however.
Fig. 8 BUSY Output Waveform
Fig. 9 shows an example of an application using TP
2
.
Fig. 9 TP
2
Output Status
1 pulse
REPEAT
Output status
ENABLE
TP
2
30.5 s
RESET & RUN
T
T
t
1
t
2
T
T
30.5 s
Interval
CLK STOP
RUN
RESET & RUN
Interval
CLK STOP
RUN
RESET
RESET
30.5 s
t
1
+ t
2
= T
T
TP
2
flag ON
Note When the output status is disabled, the signal goes "H" regardless of the status of TP
2
.
BUSY
BUSY signal
1st digit carry
1st digit carry
457.7 s
BUSY flag
OFF
BUSY flag
ON
BUSY flag
ON
TP
1
or TP
2
Output DISABLE SET
30.5 s
PD4991A
24
.
.
Oscillation characteristics
Figs. 11 and 12 show the frequency stability when the ambient temperature (T
a
) and supply voltage (V
DD
) are
changed with a crystal of crystal impedance C
1
= 20 k
and a circuit shown in Fig. 10.
The stability and day difference are calculated by the following expressions:
Stability =
f f
reference value
10
6
(ppm)
f
reference value
Note
f
reference value
in Fig. 12 is the measured frequency when
V
DD
= 3.5 V.
1
1
Day difference =
TP1 specified
measured
2
number of division stage
60 seconds
60 minutes
frequency
fequency
24 hours (sec)
Note
The number of division stages = 11 at 2048 Hz.
Fig. 10 Oscillation Characteristics Measuring Circuit
Fig. 11 Frequency Stability
Fig. 12 Frequency Stability
vs. Temperature Characteristics
vs. Supply Voltage Characteristics
TP1
V
DD
V
SS
C
R
X
IN
C
G
X
OUT
C
D
X'
tal
In constant temperature bath
R
C
X'
tal
: 10 k
: Tantalum capacitor (10 F)
: MX-38T
(Nippon Denpa Kogyo)
8.4
4.2
0
4.2
8.4
12.7
16.9
Day difference
(sec)
97.7
48.8
0
48.4
97.7
146.5
195.3
Stability
(ppm)
2048.2
2048.1
2048.0
2047.9
2047.8
2047.7
2047.6
Frequency
(Hz)
2047.5
2048.3
40
20
0
40
60
80 (
C)
C
D
= C
G
= 10 pF
20 pF
30 pF
Temperature
V
DD
= 5.0 V
30
10
20 30
50
70
10
1.73
1.30
0.86
0.43
0
0.43
0.86
1.30
Day difference (sec)
20
15
10
5
0
5
10
15
Frequency stability (ppm)
2
4
5
6
3
C
P
= 20 pF
C
G
= 10 pF
C
G
= 20 pF
C
G
= 30 pF
Supply voltage
V
DD
(V)
PD4991A
25
Fig. 13 Dynamic Current Consumption Characteristics
Differences between
PD4991 and
PD4991A
The
PD4991A improves on the characteristics of the
PD4991. These two products differ as follows:
1.
Specifications
PARAMETER
SYMBOL
PD4991
PD4991A
REMARKS
Current Consumption
I
DD
20
A MAX.
14
A MAX.
V
DD
= 3.6 V
Current Consumption
I
DD
15
A MAX.
--
V
DD
= 3.0 V
Current Consumption
I
DD
--
6
A MAX.
V
DD
= 2.4 V
Input Data Setup Time
t
DW
0 ns MIN.
50 ns MIN.
Specifications differ
Input Data Hold Time
t
DH
0 ns MIN.
0 ns MIN.
Specifications differ
25
20
15
10
5
0
1.0
2.0
3.0
4.0
5.0
6.0
Supply voltage V
DD
(V)
Dynamic current consumption I
DD
( A)
PD4991
PD4991A
C
G
= C
D
= 20 pF
T
a
= 25
C
PD4991A
26
AC Timing of
PD4991
2.
Function
PARAMETER
PD4991
PD4991A
Valid Range of
30 s ADJUST
1-second to 1-minute digits
All digits
(no carry to 10-minute digit)
BUSY Flag when
30 s ADJUST
Not BUSY
BUSY until all digits are carried
D
3
bit of CONTROL REGISTER 1
NOP
CLOCK WAIT
CLOCK WAIT Bit and CLOCK STOP Bit
Both bits inhibit input of clock to the clock counter (1 Hz) and subsequently stop the clock. The CLOCK STOP
bit is used to set the time to the clock (be sure to stop the clock when setting it). The CLOCK WAIT bit is used
to prevent the CPU from reading wrong data in case counting takes place when the time is read (the time can
also be read without the CLOCK WAIT bit but with the BUSY signal or by performing two reads). If the clock
is run within 0.5 second after stopping the clock or placed in the wait state, no delay in respect to the actual
time occurs.
AC Timing of
PD4991A
WE or CS
D
0
~ D
3
t
DW
t
DH
50%
50%
WE or CS
D
0
~ D
3
t
DW
t
DH
50%
PD4991A
27
Example of an Application Circuit
The application circuits and their parameters are for references only and are not intended for use in actual
design-in's.
D
3
D
2
D
1
D
0
Data bus
A
3
A
2
A
1
A
0
Address bus
A
3
A
2
A
1
A
0
ADDRESS
DECODER
WE
WR
OE
RD
V
DD
C
1SS53
Ni-Cd
3.6 V
+5 V
V
SS
GND
15 k
4.7 k
1 k
510
2SA1175
2SC2785
1SS53
PD4991A
D
0
D
1
D
2
D
3
CS
2
X
IN
X
OUT
TP
1
TP
2
POWER
FAIL
C
G
= 20 ~ 30 pF
C
D
= 20 pF
32.768
kHz
10 k
+5 V
C: ceramic capacitor or tantalum capacitor
(0.1 F to 10 F)
10 k
+5 V
CS
1
PD4991A
28
18PIN PLASTIC DIP (300 mil)
ITEM MILLIMETERS
INCHES
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
P18C-100-300A,C-1
N
0.25
0.01
P
1.0 MIN.
0.039 MIN.
R
0~15
0~15
A
22.86 MAX.
0.900 MAX.
B
1.27 MAX.
0.050 MAX.
F
1.2 MIN.
0.047 MIN.
G
3.50.3
0.1380.012
J
5.08 MAX.
0.200 MAX.
K
7.62 (T.P.)
0.300 (T.P.)
C
2.54 (T.P.)
0.100 (T.P.)
D
0.500.10
0.020 +0.004
0.005
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
L
6.4
0.252
M
0.25
0.010 +0.004
0.003
+0.10
0.05
2) ltem "K" to center of leads when formed parallel.
M
R
M
P
I
H
G
F
D
N
C
B
1
9
18
10
A
L
K
J
PD4991A
29
20 PIN PLASTIC SOP (300 mil)
ITEM MILLIMETERS
INCHES
A
B
C
E
F
G
H
I
J
13.00 MAX.
1.27 (T.P.)
1.8 MAX.
1.55
7.70.3
0.78 MAX.
0.12
1.1
5.6
M
0.10.1
N
0.512 MAX.
0.031 MAX.
0.0040.004
0.071 MAX.
0.061
0.3030.012
0.220
0.043
0.005
0.050 (T.P.)
P20GM-50-300B, C-4
P
3
3
+7
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
D
0.40
0.016
+0.10
0.05
K
0.20
0.008
+0.10
0.05
L
0.60.2
0.024
0.10
3
+7
3
0.004
+0.008
0.009
+0.004
0.002
+0.004
0.003
A
C
D
G
P
detail of lead end
F
E
B
H
I
L
K
M
J
N
M
1
10
11
20
PD4991A
30
RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when soldering this product. Please consult with our sales offices when using
other soldering process or under different conditions.
Type of Surface Mounting Device
PD4991 AGS
Soldering process
Soldering conditions
Symbols
Infrared ray reflow
Peak temperature of package surface: 235
C or below,
IR35-00-2
Reflow time: 30 seconds or less (210
C or higher),
Number of reflow process: 2, Exposure limit*: None
VPS
Peak temperature of package surface: 215
C or below,
VP15-00-2
Reflow time: 40 seconds or less (200
C or higher),
Number of reflow process: 2, Exposure limit*: None
Wave soldering
Soldering temperature: 260
C or below
WS60-00-1
Flow time: 10 seconds or less, Number of reflow process: 1,
Exposure limit*: None
Partial heating
Pin temperature: 300
C or below,
--
method
Time: 10 seconds or below (per side of leads)
*
Exposure limit before soldering after dry-pack is opened.
Storage condition: 25
C and relative humidity at 65 % or less.
Caution Do not apply more than a single process once, except for "Partial heating method."
Type of Through-Hole Device
PD4991 ACX
Soldering process
Soldering conditions
Wave soldering
Soldering temperature: 260
C or below
PD4991A
31
[MEMO]
PD4991A
32
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
[MEMO]
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