Document Outline

• COVER
• FEATURES
• APPLICATION
• ORDERING INFORMATION
• BLOCK DIAGRAM
• PERIPHERAL CONNECTION
• PIN CONFIGURATION (TOP VIEW)
• PIN LIST
• 1. PIN FUNCTION
  • 1.1 Video Input Interface
  • 1.2 Video Output Interface
  • 1.3 Audio Input Interface
  • 1.4 Audio Input/output Interface
  • 1.5 Stream Input Interface
  • 1.6 Stream Output Interface
  • 1.7 SDRAM Interface
  • 1.8 Host CPU Interface
    • 1.8.1 Parallel bus interface
    • 1.8.2 Serial bus interface
  • 1.9 Clock, Reset
  • 1.10 N-Wire
  • 1.11 GPIO
  • 1.12 Power Supply
  • 1.13 Recommended Connections of Unused Pins
• 2. FEATURE OVERVIEW
  • 2.1 Video
    • 2.1.1 Encoding
    • 2.1.2 Transcoding
    • 2.1.3 Input/output processing
  • 2.2 Audio
    • 2.2.1 Encoding
    • 2.2.2 Transcoding (DEMUX, MUX)
    • 2.2.3 Input/output processing
  • 2.3 MPEG System Processing
    • 2.3.1 System time clock
    • 2.3.2 Multiplex
    • 2.3.3 De-multiplex
    • 2.3.4 Transcode
  • 2.4 Stream Interface
    • 2.4.1 Parallel steam data interface
    • 2.4.2 Serial stream data interface
  • 2.5 Host CPU Interface
  • 2.6 SDRAM Interface
  • 2.7 Memory Connection Diagram
  • 2.8 Memory Map
• 3. SYSTEM INTERFACE REGISTER
  • 3.1 Register Mapping (General Mapping)
  • 3.2 Register Functions
    • 3.2.1 Common register
    • 3.2.2 Data transfer register
    • 3.2.3 Internal CPU interrupt register
    • 3.2.4 Interrupt mask register
    • 3.2.5 Download interrupt register
    • 3.2.6 Interrupt register
    • 3.2.7 Reset register
    • 3.2.8 ROM access cycle register
    • 3.2.9 Port setup register
• 4. SYSTEM INTERFACE PROCEDURE
  • 4.1 Outline
  • 4.2 Firmware Download
    • 4.2.1 Host CPU to instruction RAM of internal CPU
    • 4.2.2 External ROM to instruction RAM of internal CPU
    • 4.2.3 Host CPU to SDRAM
    • 4.2.4 External ROM to SDRAM
  • 4.3 SDRAM Write during Executing
  • 4.4 SDRAM Read during Executing
  • 4.5 SDRAM Initialization
  • 4.6 Operation Mode Setting by Changing Firmware
  • 4.7 Transfer Ending
  • 4.8 Transfer Error Handling
    • 4.8.1 Transfer error handling 1
    • 4.8.2 Transfer error handling 2
    • 4.8.3 Transfer error handling 3
• 5. EXAMPLE FOR COMMON REGISTER USAGE
  • 5.1 Register Map Example
  • 5.2 Example of the Common Register Which A Firmware Defines
    • 5.2.1 COMCODE: Command code register
    • 5.2.2 ESTS: Status register
• 6. ELECTRICAL CHARACTERISTICS
• 7. PACKAGE DRAWING
• 8. RECOMMENDED SOLDERING CONDITIONS