Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- PIN CONFIGURATION (Top View)
- BLOCK DIAGRAM
- 1. PROGRAM COUNTER (PC) ......... 10 BITS
- 2. STACK POINTER (SP) ......... 2 BITS
- 3. PROGRAM MEMORY (ROM) ......... 1002 STEPS x 10 BITS
- 4. DATA MEMORY (RAM) ......... 32 WORDS x 5 BITS
- 5. DATA POINTER (R0)
- 6. ACCUMULATOR (A) ......... 4 BITS
- 7. ARITHMETIC LOGIC UNIT (ALU) ......... 4 BITS
- 8. FLAGS
- 9. SYSTEM CLOCK GENERATOR
- 10. TIMER
- 11. PIN FUNCTIONS
- 11.1 KI/O Pin (P0)
- 11.2 KI/O Pull-Down Resistor Configuration
- 11.3 KI Pin (P12)
- 11.4 KI Pull-Down Resistor Configuration
- 11.5 S-OUT Pin
- 11.6 S-IN Pin (D0 bit of P1)
- 12. PORT REGISTER (Px)
- 13. CONTROL REGISTER (P1)
- 14. STANDBY FUNCTION (HALT INSTRUCTION)
- 14.1 STOP Mode (Oscillation stop HALT instruction)
- 14.2 HALT Mode (Oscillation continue HALT instruction)
- 14.3 Standby Release Conditions
- 15. AC PIN (ALL CLEAR PIN)
- 16. MASK OPTIONS (PLA DATA)
- 17. WRITING, READING, AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
- 17.1 Operation Mode When Writing, Reading, and Verifying Program Memory
- 17.2 Program Memory Writing Procedure
- 17.3 Program Memory Reading Procedure
- 18. INSTRUCTION SET
- 19. APPLICATION CIRCUIT EXAMPLE
- 20. ELECTRICAL SPECIFICATIONS
- 21. PACKAGE DRAWINGS
- 22. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A. uPD612x SERIES PRODUCT LIST
- APPENDIX B. DEVELOPMENT TOOLS
DATA SHEET
MOS INTEGRATED CIRCUIT
PD61P24
DESCRIPTION
The
PD61P24 is a 4-bit single-chip microcontroller for infrared remote controllers for TVs, VCRs, stereos, cassette
decks, air conditioners, etc.
As the
PD61P24 is user-programmable, it is ideal for evaluation of programs running in a
PD6124A or 6600A,
and for small-scale production of such systems.
The functions of the
PD61P24 are described in detail in the following User's Manual. Be sure to read this
manual before designing your system.
PD612X Series User's Manual: IEP-1083
FEATURES
Transmitter for programmable infrared remote control-
ler
19 types of instructions
Instruction execution time: 17.6
s (with 455-kHz ce-
ramic resonator)
On-chip one-time PROM: 1002
10 bits
Data memory (RAM) capacity : 32
5 bits
9-bit programmable timer: 1 channel
I/O pins (K
I/O
): 8 pins
Input pins (K
I
): 4 pins
Serial input pins (S-IN): 1 pin
Transmission-in-progress indication pin (S-OUT): 1
pin
Transmit carrier frequency (REM)
f
OSC
/12, f
OSC
/8
Standby operation (HALT/STOP mode)
Low power consumption
Current consumption in STOP mode (T
A
= 25
C)
1
A MAX.
Low-voltage operation: V
DD
= 2.2 to 5.5 V
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR REMOTE CONTROL TRANSMISSION
The information in this document is subject to change without notice.
The mark shows major revised points.
Document No. U12629EJ4V0DS00 (4th edition)
Previous No. IC-2876
Date Published July 1997 N
Printed in Japan
Caution To use the NEC transmission format, ask NEC to supply the custom code.
Do no use R
0
when using a register as an operand of the branch instruction.
1997
PD61P24
2
ORDERING INFORMATION
Part Number
Package
PD61P24CS
20-pin plastic shrink DIP (300 mil)
PD61P24GS
20-pin plastic SOP (300 mil)
PIN CONFIGURATION (Top View)
(1) Normal operating mode
(2) PROM programming mode
K
K
S-IN
S-OUT
REM
V
OSC-OUT
OSC-IN
V
AC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
K
K
K
K
K
K
K
K
K
K
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I0
I1
I2
I3
I/O1
I/O0
DD
SS
1
2
3
4
5
6
7
8
D1
D0
V
PP
(Open)
(Open)
V
DD
(Open)
CLK
20
19
18
17
16
15
14
13
D2
D3
D4
D5
D6
D7
MD0
MD1
9
V
SS
12 MD2
10
(L)
11 MD3
Caution Round brackets ( ) indicate the pins not used in the PROM programming mode.
L
: Connect each of these pins to GND via a resistor (470
).
Open: Leave these pins open.
PD61P24
3
BLOCK DIAGRAM
I0 I3
K -K
L
H
32
5 bits
AC
K
I/O0
-K
I/O7
S-IN
REM
S-OUT
OSC-IN
OSC-OUT
MOD
10 bits
OSC
ROM
D.P.
ROM
D.P.
PC(H)
M
P
X
ADD
DEC
M
P
X
RAM
RAM
CNTL
(H)
CNTL
(L)
SP
TIMER
(L)
TIMER
(H)
ACC
KEY
IN
KEY
OUT(H)
KEY
OUT(L)
ALU
Watchdog
timer
function
PC(L)
One-Time
PROM
(L)
One-Time
PROM
(H)
1002
10 bits
PD61P24
4
1.
PROGRAM COUNTER (PC) ......... 10 BITS
The program counter (PC) is a binary counter, which holds the address information for the program memory.
Figure 1-1. Program Counter Organization
PC
7
PC
6
PC
5
PC
4
PC
3
PC
2
PC
1
PC
0
PC
8
PC
9
PC
Normally, the program counter contents are automatically incremented each time an instruction is executed,
according to the number of instruction bytes.
When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination.
Immediate data or the data memory contents are loaded to all or some bits of the PC.
When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack
memory. Then, a value needed for each jump instruction will be loaded.
When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded
into the PC.
When "all clear" is input or on reset, the PC contents are cleared to "000H".
2.
STACK POINTER (SP) ......... 2 BITS
This 2-bit register holds the start address information for the stack area. The stack area is shared with the data
memory.
The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when
the return instruction (RET) is executed.
The stack pointer is cleared to "00B" after reset or "all clear" is input, and indicates the highest address FH for
the data memory as the stack area.
The figure below shows the relationship for the stack pointer and the data memory area.
R
C
Data memory
R
D
R
E
R
F
(SP)
11B
10B
01B
00B
If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset
signal will be generated.
PD61P24
5
3.
PROGRAM MEMORY (ROM) ......... 1002 STEPS
10 BITS
The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter.
Program and table data are stored in the program memory.
Figure 3-1. Program Memory Map
Test program
area
000H
0FFH
100H
1FFH
200H
2FFH
300H
3E9H
3EAH
3FFH
4.
DATA MEMORY (RAM) ......... 32 WORDS
5 BITS
The data memory is a RAM of 32 words
5 bits. The data memory stores processing data. In some cases, the
data memory is processed in 8-bit units. R
0
may be used as the data pointer for the ROM.
After power application, the RAM will be undefined. The RAM retains the previous data on reset.
Figure 4-1. Data Memory Organization
1
R
0
0
R
F
R
B
R
C
SP3
SP2
SP1
SP0
.
.
.
.
.
.
Caution Avoid using the RAM areas R
D
, R
E
, and R
F
in a CALL routine as much as possible because these
areas are also used as stack memory areas (to prevent program hang-up in case the value of the
SP is destroyed due to some reason such as noise).
When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer
checking in the main routine.
PD61P24
6
5.
DATA POINTER (R
0
)
R
0
(R
10
, R
00
) for the data memory can serve as the data pointer for the ROM.
R
0
specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified
by the control register.
Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address
to the data pointer.
On reset or "all clear" is input, it becomes undefined.
Figure 5-1. Data Pointer Organization
AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
AD
8
AD
9
Control registers
(P )
1
R
0
R
10
R
00
6.
ACCUMULATOR (A) ......... 4 BITS
The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation.
On reset or "all clear" is input, it becomes undefined.
Figure 6-1. Accumulator Organization
A
0
A
1
A
2
A
3
A
7.
ARITHMETIC LOGIC UNIT (ALU) ......... 4 BITS
The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic
operations.
8.
FLAGS
(1) Status flag
When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition
specified by the STTS instruction, the status flag (F) is set (to 1).
On reset or "all clear" is input, it becomes undefined.
(2) Carry flag
When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from
the MSB for the accumulator, the carry flag (C) is set (to 1).
The carry flag (C) is also set (to 1), if the contents for the accumulator are "FH", when the SCAF instruction
is executed.
On reset or "all clear" is input, it becomes undefined.
PD61P24
7
9.
SYSTEM CLOCK GENERATOR
The system clock generator consists of a resonator, which uses a ceramic resonator (400kHz to 500kHz).
Figure 9-1. System Clock Generator
STOP mode
System clock
OSC-OUT
OSC-IN
In the STOP mode (oscillation stop HALT instruction), the oscillator in the system clock generator stops its
operation, and the system clock is stopped.
PD61P24
8
10. TIMER
The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve
as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output
validity.
The 9-bit down counter is decremented (1) every 8/f
OSC
(s) in synchronization with the machine cycle, after
starting down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped,
the signal indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for
the timer operation completion, the standby (HALT) condition is released and the next instruction will be executed.
If the next instruction again sets the value of the down counter, down counting continues without any error (the carrier
output of the REM pin is not affected).
Set the down count time according to the following calculation; (set value (HEX) + 1)
8/f
OSC
. Setting the value
to the timer is done by the timer manipulation instruction.
When the down counter is operating, the remote control transmission carrier can be output to the REM pin.
Whether or not to output the carrier can be selected by the MSB for the timer register block. Set "1", when outputting
the carrier, or "0", when not outputting the carrier.
If all the down counter bits become "0", when outputting the carrier, the carrier output will be stopped. When
not outputting the carrier, the REM pin output will become low level.
A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the S-
OUT pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output
to the REM pin.
If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating,
the oscillation stop mode is initiated after down counting is stopped (after 0).
Timer operation STOP/RUN is controlled by the control register (P
1
). (Refer to 13. CONTROL REGISTER (P
1
).)
At reset (all clear) time, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are cleared to
000H.
Caution Because the timer clock is not synchronized with the carrier output, the pulse width may be
shortened at the beginning and end of the carrier output.
Figure 10-1. Timer Block Organization
S-OUT
REM
Carrier
(fosc/12, fosc/8)
Selected by control register
Clear
Set by timer mainpulation instruction
9-bit down counter
Zero detection circuit
D of control register P
(Timer RUN/STOP)
2
1
1/0
MSB
fosc/8
PD61P24
9
11. PIN FUNCTIONS
11.1
K
I/O
Pin (P
0
)
This is the 8-bit I/O pin for key-scan output. When the control register (P
1
) is set for the input port, the port can
be used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the V
SS
level inside the LSI.
At reset (all cleared), the value of I/O mode and output latch becomes undefined.
Figure 11-1. K
I/O
Pin Organization
K
I/O7
K
I/O6
K
I/O5
K
I/O4
K
I/O3
K
I/O2
K
I/O1
K
I/O0
P
0
P
10
P
00
(P )
Control register
1
11.2
K
I/O
Pull-Down Resistor Configuration
V
DD
V
SS
CMOS
N-ch
Pin
Pull-down resistor
Input signal
Output signal
Input/output selection
N-ch
P-ch
R
When K
I/O
is set to the input mode, pull-down resistor R is turned on.
PD61P24
10
11.3
K
I
Pin (P
12
)
This is the 4-bit pin for key input. All of these pins are pulled down to the V
SS
level by PLA data.
Figure 11-2. K
I
Pin Organization
K
I3
K
I2
K
I1
K
I0
P
2
11.4
K
I
Pull-Down Resistor Configuration
V
DD
V
SS
N-ch
V
SS
Pin
Input signal
PLA K
I
pull-down
resistor switch
Pull-down
resistor
P-ch
When the pull-down resistor switch is turned on (set 1) by PLA data, pull-down resistor R is turned on.
PD61P24
11
11.5
S-OUT Pin
By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that
communication is in progress.
The S-OUT pin is CMOS output.
The S-OUT pin goes high on reset.
11.6
S-IN Pin (D
0
bit of P
1
)
To input serial data, use the S-IN pin. When control register (P
1
) is set to serial input mode, the S-IN pin is
connected as an input to the LSB of the accumulator; the S-IN pin is pulled down to the V
SS
level within the LSI.
In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied to the
LSB of the accumulator.
If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no
through current flows internally. When the RL A instruction is executed, the MSB is copied to the LSB.
At reset (all cleared), the S-IN pin goes into a high-impedance state.
Figure 11-3. Configuration of the S-IN Pin
A
3
A
2
A
1
A
0
CY
Control register
S-IN
PD61P24
12
12. PORT REGISTER (P
)
K
I/O
, K
I
, and the control register are handled as port registers.
The table below shows the relations between the port registers and pins.
Table 12-1. Relations between Port Registers and Pins
Pin
Input Mode
Output Mode
Name
Read
Write
Read
Write
On Reset
K
I/O
Pin status
Output latch
Pin status
Output latch
Undefined [input mode, output latch]
K
I
Pin status
Input mode
S-IN
Pin status is read by RL A instruction when D
0
of P
1
register = 1.
High impedance (D
0
of P
1
register = 0)
P
10
P
11
P
12
P
00
P
01
P
02
K
I/O7-4
K
I/O3-0
P
0
P
1
P
2
Control register (H)
Control register (L)
K
I3-0
P
1
(H)
P
0
(L)
PD61P24
13
13. CONTROL REGISTER (P
1
)
The control register contains of 10 bits. The controllable items are shown in Table 13-1.
Table 13-1. Control Register (P
1
)
Bit
D
9
Name
Test mode
Be sure to set 0.
0
1
Set
Value
Timer
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
HALT
D.P.
AD
MOD
K
I/O
9
D.P.
AD
8
RL A
A
CC
0
STOP
NOP
f /8
AD =0
9
AD =0
8
OSC
IN
RUN
OSC
STOP
f /12
AD =1
9
AD =1
8
OSC
OUT
A
3
S-IN
D
0 ..........................
Specifies data to be input to A
0
when the accumulator is shifted to the left.
0: A
3
, 1:S-IN
D
1 ..........................
Specifies the status of K
I/O
, as follows:
0: input mode, 1: output mode
D
2 ..........................
Specifies the status of the timer, as follows:
0: Count stop, 1: Count execution
D
3 ..........................
Specifies the carrier frequency output from the REM pin.
0: f
OSC
/8, 1: f
OSC
/12
D
4
, D
5 .................
Specify the high-order 2 bits of the ROM data pointer.
D
6 ..........................
Determines what happen to the oscillation circuit when the HALT instruction is executed.
0: Oscillation does not stop
1: Oscillation stops (STOP mode)
D
7 ..........................
Be sure to set this bit to 0.
D
8
, D
9 .................
These bits specify test modes. Be sure to set them to 0.
Remark
D
0
= D
8
= D
9
= 0 on reset, and the other bits are undefined.
PD61P24
14
14. STANDBY FUNCTION (HALT INSTRUCTION)
The
PD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,
when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).
In the standby mode, the program execution stops. However, the contents of the internal registers and the data
memory are all retained.
14.1
STOP Mode (Oscillation stop HALT instruction)
In the STOP mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops.
Therefore, operations requiring the system clock will stop.
If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode
will be initiated, after the timer count down operation is completed.
14.2
HALT Mode (Oscillation continue HALT instruction)
The CPU stops its operation, until the HALT release condition is satisfied.
The system clock operation continues in this mode.
14.3
Standby Release Conditions
(1) S-IN input
(2) K
I/O
input
(3) K
I
input
(4) Timer count down operation completion
Remark
Either high level or low level can be specified for setting a release condition by input.
Table 14-1. Standby Mode Releasing Condition
D
3
0/1
0
Releasing condition:
0
1
Timer
0
1
0
0
K
0
0
S-IN
D
2
D
1
D
0
Releasing
Condition
1
0
1
0
I/O
K
I
Remarks
Released when 0.
Valid only in the IN mode.
When RL A is selected, the standby mode is
always released.
3
"0"Low level detection
"1"High level detection
PD61P24
15
15. AC PIN (ALL CLEAR PIN)
Internal part of the CPU including the program counter can be reset by setting the AC pin to the low level.
Watchdog Timer Function
A power-on reset function and a CR watchdog timer function, that can be controlled by program, can be realized
by connecting a 0.1
F capacitor across the AC pin and the V
SS
.
V
DD
0.1 F
0.1 F
V
V
DD
V
thL
t
Charge mode
Charge start instruction
Execute HALT instruction
immediately before NOP.
(Charge for 0.4 ms or more)
Discharge mode
Charge-discharge
pattern
Discharge start instruction
Discharge starts after the NOP
instruction execution.
(Discharge time is about 5 ms from V
DD
to V
thL
)
The pattern must be
controlled by the program,
in such a manner that
the C charge level will not
go below V
thL
.
Caution When the watchdog timer function is not used, switch to charging mode by executing a NOP
instruction immediately before a HALT instruction at the beginning of the program. (Be sure to
connect the capacitor.)
PD61P24
16
16. MASK OPTIONS (PLA DATA)
The following items are fixed by mask option:
K
I
, S-IN pin pull-down resistor provided
Carrier duty selection (1/3) at f
OSC
/12
Hang-up detection provided
<1> K
I/O
ALL
The system is reset when the hang-up detection K
I/O
ALL switch is set to ON ("1") by PLA data and if the
K
I/O
pins are in the input mode in the oscillation stop HALT mode or if even one of the K
I/O
pins is low.
To use a pin as a key source of the switch, turn ON the switch with PLA data.
Figure 16-1. Hang-up Detection K
I/O
ALL Configuration Diagram
V
DD
To RESET circuit
PLA hang-up
detection
K
I/O
ALL switch
K output signal
I/O0
K output signal
I/O1
K output signal
I/O2
K output signal
I/O3
K output signal
I/O4
K output signal
I/O5
K input/output selection
I/O
K output signal
I/O6
K output signal
I/O7
<2> HALT release condition specification (S-IN, K
I/O
, K
I
)
The system is reset if S-IN and K
I/O
are used in the HALT mode when S-IN and K
I/O
are specified by PLA data
not to be used ("1"). K
I
is used ("0").
PD61P24
17
BIT Assignment by Switch Selection
0
1
2
7
6
5
4
Address
Note
K
I3
K
I2
K
I1
K
I0
3
2
1
0
MSB
LSB
KI
pull-down resistor
Corresponding
Portion
Hang-up detection
Duty
S-IN
0
1
(Provided)
1
(Provided)
1
(Provided)
1
(Provided)
0
0
0
0
0
0
Duty
1
(1/3 duty)
S-IN
pull-down
resistor
1
(Provided)
1
(Detection
provided)
1
(Unused)
1
(Unused)
0
(Used)
K
I/O
ALL
HALT
S-IN
HALT
K
I/O
HALT
K
I
0
PD61P24
18
17. WRITING, READING, AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)
To write, read, or verify the PROM, set the PROM mode and use the pins shown in Table 17-1. No address input
pin is used. To update the address, the clock signal input from the CLK pin is used.
Table 17-1. Pins Used to Write, Read, and Verify Program Memory
Symbol
Function
V
PP
Applies program voltage (12.5 V)
CLK
Inputs clock to update address
MD0-MD3
Selects operation mode
D0-D7
Inputs/outputs 8-bit data
V
DD
Applies supply voltage (6 V)
17.1 Operation Mode When Writing, Reading, and Verifying Program Memory
The
PD61P24 enters the program memory write, read, or verify mode if +6 V is applied to the V
DD
pin and +12.5
V is applied to the V
PP
pin after the reset status has been held a certain time (V
DD
= 5 V, AC = low level).
In this mode, the operation modes listed in Table 17-2 can be selected by using the MD0 through MD3 pins.
Any input pins not used for writing, reading, or verifying the program memory must be open or connected to GND
via a pull-down resistor (470
).
Table 17-2. Operating Mode When Writing, Reading, and Verifying Program Memory
Specifies Operation Mode
Operation Mode
V
PP
V
DD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Clears program memory address to 0
L
H
H
H
Write mode
L
L
H
H
Read and verify modes
H
H
H
Program inhibit mode
: don't care (L or H)
PD61P24
19
17.2 Program Memory Writing Procedure
The program memory is written at high speed in the following procedure.
(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low.
(2) Supply 5 V to the V
DD
pin. Keep the V
PP
pin low.
(3) Wait for 10
s, and supply 5 V to the V
PP
pin.
(4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins.
(5) Supply 6 V to V
DD
and 12.5 V to V
PP
.
(6) Set the program inhibit mode.
(7) Write data in the 1-ms write mode.
(8) Set the program inhibit mode.
(9) Set the verify mode. If the data has been correctly written, proceed to (10). If not, repeat (7) through (9).
(10) Additional writing of (Number of times data has been written in (7) through (9): X)
1 ms
(11) Set the program inhibit mode.
(12) Input a pulse four times to the CLK pin to update the program memory address (+1).
(13) Repeat (7) through (12) until the data is written to the last address.
(14) Set the mode in which the program memory address is cleared to 0.
(15) Change the voltage on the V
DD
and V
PP
pins to 5 V.
(16) Turn off power supply.
Program memory writing steps (2) through (12) are illustrated below.
Write
Verify
Additional write
Address
increment
Repeat X times
MD3
MD2
MD1
MD0
D0-D7
CLK
GND
V
DD
V
DD
V
DD
+1
GND
V
DD
V
PP
V
PP
Data input
Data output
Data input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Reset
PD61P24
20
17.3 Program Memory Reading Procedure
(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low.
(2) Supply 5 V to the V
DD
pin. Keep the V
PP
pin low.
(3) Wait for 10
s, and supply 5 V to the V
PP
pin.
(4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins.
(5) Supply 6 V to V
DD
and 12.5 V to V
PP
.
(6) Set the program inhibit mode.
(7) Set the verify mode. If a clock pulse is input to the CLK pin, the data of one address is output each time the
pulse has been input to the CLK pin four times.
(8) Set the program inhibit mode.
(9) Set the mode in which the program memory address is cleared to 0.
(10) Change the voltage on the V
DD
and V
PP
pins to 5 V.
(11) Turn off power supply.
Program memory reading steps (2) through (9) are illustrated below.
Hi-Z
Hi-Z
" L "
MD3
MD2
MD1
MD0
D0-D7
CLK
GND
V
DD
V
DD
V
PP
V
PP
V
DD
GND
V
DD
+1
Reset
Data output
Data output
PD61P24
21
18. INSTRUCTION SET
Accumulator Manipulation Instructions
ANL
ANL
ANL
ANL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
INC
RL
D00
E00
A00
D10
D30
D31
E10
E30
E31
A10
A30
A31
A13
F13
R
10
R
11
R
12
R
1F
R
00
R
01
R
0F
R
r
A, R
r
A, @R
0
H
A, @R
0
L
A, #data
A, R
r
A, @R
0
H
A, @R
0
L
A, #data
A, R
r
A, @R
0
H
A, @R
0
L
A, #data
A
A
D01
E01
A01
D02
E02
A02
D0F
E0F
A0F
D20
E20
A20
D21
E21
A21
D2F
E2F
A2F
Input/Output Instructions
P
A,
P ,
A,
A,
A,
IN
OUT
ANL
ORL
XRL
F19
219
D19
E19
A19
P
P
11
P
P
P
A
P
P
P
P
P
P
P
F18
218
D18
E18
A18
P
10
F1A
21A
D1A
E1A
A1Z
P
12
F39
239
D39
E39
A39
P
01
F38
238
D38
E38
A38
P
00
F3A
23A
D3A
E3A
A3A
02
P
OUT
319
P
P
1
P
P
#data
318
P
0
31A
P
2
P
1P
and P
0P
operate in pair format
Data Transfer Instructions
MOV
MOV
F00
F10
F01
F02
F0F
F20
F21
F2F
A, R
A, @R H
r
0
R
10
R
11
R
12
R
1F
R
00
R
01
R
0F
R
r
MOV
F30
A, @R H
0
MOV
F31
A, #data
MOV
MOV
300
301
302
30F
R , #data
R , @R
r
r
R
0
R
1
R
2
R
F
R
r
320
321
322
32F
MOV
R , A
r
200
201
202
20F
220
221
22F
0
R
1r
and R
0r
operate in pair format
PD61P24
22
Branch Instructions
R
r
R
0
R
1
R
2
R
F
JMP0
JC
JC
JNC
JNC
JF
JF
JNF
JNF
addr
addr
Rr
Note
addr
addr
addr
411
611
631
711
731
Rr
Note
Rr
Note
Rr
Note
601
621
701
721
602
622
702
722
60F
62F
70F
72F
Pair register
JMP0
Rr
Note
401
402
40F
Note
r = 1 through F
r = 0 canot be used.
Subroutine Instructions
addr
CALL0
RET
411
P
1
P
P
312
412
P
0
Timer/Counter Manipulation Instructions
A,
T ,
T,
T,
MOV
MOV
MOV
MOV
F1F
21F
T
1
T
t
T
A
#data
@R
t
0
31F
33F
T
0-1
T
0
t
F3F
23F
Other Instructions
HALT #data
STTS R
STTS #data
SCAF
NOP
00
R
111
131
D13
000
01
R
02
R
0F
R
120
121
122
12F
0r
PD61P24
23
19. APPLICATION CIRCUIT EXAMPLE
V
DD
V
DD
Key matrix
Mode select switch
Infrared LED
SE303 series
SE313
SE307-C
SE1003-C
Transmission
indication
2SC3616, 3618
2SD1615, 1616
2SC2001
3.0 V
47 F
+
100 pF
100 pF
0.1 F
K
I/O1
K
I/O0
S-IN
1
2
3
4
5
6
7
8
9
10
K
I/O2
K
I/O3
S-OUT
REM
V
DD
OSC-OUT
OSC-IN
V
SS
AC
K
I/O4
K
I/O5
K
I/O6
K
I/O7
K
I0
K
I1
K
I2
K
I3
PD61P24
20
19
18
17
16
15
14
13
12
11
Caution The ceramic resonator start up capacitor value must be determined, by taking the voltage level and
the oscillation start up characteristics for the ceramic resonator into consideration.
PD61P24
24
20. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25
C)
Parameter
Symbol
Ratings
Unit
Supply Voltage
V
DD
7.0
V
Input Voltage
V
IN
0.3 to V
DD
+ 0.3
V
Operating Ambient Temperature
T
A
20 to +75
C
Storage Temperature
T
stg
40 to +125
C
Caution
Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality
of the product may be degraded. The absolute maximum rating therefore specifies the upper or
lower limit of the value at which the product can be used without physical damages. Be sure to
use the product(s) within the ratings.
Recommended Operating Range (T
A
= 25
C)
Parameter
Symbol
MIN.
TYP.
MAX.
Unit
Supply Voltage
V
DD
2.2
5.5
V
Oscillation Frequency
f
OSC
400
500
kHz
PD61P24
25
DC Characteristics (V
DD
= 3.0 V, f
OSC
= 455 kHz, T
A
= 25
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Supply Voltage
V
DD
2.2
5.5
V
Current Consumption 1
I
DD1
f
OSC
= 455 kHz
0.3
1.5
mA
Current Consumption 2
I
DD2
f
OSC
= STOP
1.0
A
REM High Level Output Current
I
OH1
V
O
= 1.0 V
5
8
15
mA
REM Low Level Output Current
I
OL1
V
O
= 0.3 V
0.5
1.5
2.5
mA
S-OUT High Level Output Current
I
OH2
V
O
= 2.7 V
0.3
1.0
2.0
mA
S-OUT Low Level Output Current
I
OL2
V
O
= 0.3 V
1
1.5
2.5
mA
KI High Level Input Current
I
IH1
V
I
= 3.0 V
10
30
A
KI High Level Input Current
I
IH1'
V
I
= 3.0 V, without pull-down resistor
0.2
A
KI Low Level Input Current
I
IL1
V
I
= 0 V
0.2
A
KI/O High Level Input Current
I
IH2
V
I
= 3.0 V
10
30
A
KI/O High Level Input Current
I
IH2'
V
I
= 3.0 V, without pull-down resistor
0.2
A
KI/O Low Level Input Current
I
IL2
V
I
= 0 V
0.2
A
KI/O High Level Output Current
I
OH3
V
0
= 2.5 V
1.5
2.0
4.0
mA
KI/O Low Level Output Current
I
OL3
V
0
= 2.1 V
25
50
100
A
S-IN High Level Input Current
I
IH3
V
I
= 3.0 V
6
15
A
S-IN High Level Input Current
I
IH3'
V
I
= 3.0 V, without pull-down resistor
0.2
A
S-IN Low Level Input Current
I
IL3
V
I
= 0 V
0.2
A
KI High Level Input Voltage
V
IH1
2.1
3.0
V
KI Low Level Input Voltage
V
IL1
V
I
= 3.0 V
0
0.9
V
KI/O High Level Input Voltage
V
IH2
1.3
3.0
V
KI/O Low Level Input Voltage
V
IL2
0
0.4
V
S-IN High Level Input Voltage
I
IH3
1.1
3.0
V
S-IN Low Level Input Voltage
I
IL3
0
0.4
V
AC Pull-Up Resistor
R
1
V
I
= 0 V
0.3
3.0
k
AC Pull-Down Resistor
R
2
V
I
= 2.7 V
150
400
1500
k
AC High Level Input Voltage
V
IH4
1.8
3.0
V
AC Low Level Input Voltage
V
IL4
0
1.2
V
PD61P24
26
DC Programming Characteristics (T
A
= 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High-level input voltage
V
IH1
Other than CLK
0.7 V
DD
V
DD
V
V
IH2
CLK
V
DD
0.5
V
DD
V
Low-level input voltage
V
IL1
Other than CLK
0
0.3 V
DD
V
V
IL2
CLK
0
0.4
V
Input leakage current
I
LI
V
IN
= V
IL
or V
IH
10
A
High-level output voltage
V
OH
I
OH
= 1 mA
V
DD
1.0
V
Low-level output voltage
V
OL
I
OL
= 1.6 mA
0.4
V
V
DD
supply current
I
DD
30
mA
V
PP
supply current
I
PP
MD0 = V
IL
, MD1 = V
IH
30
mA
Cautions 1. Keep V
PP
to within +13.5 V including the overshoot.
2. Apply V
DD
before V
PP
, and turn it off after V
PP
.
AC Programming Characteristics (T
A
= 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.5 V)
Parameter
Symbol
Note 1
Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
Note 2
(vs. MD0
)
t
AS
t
AS
2
s
MD1 setup time (vs. MD0
)
t
M1S
t
OES
2
s
Data setup time (vs. MD0
)
t
DS
t
DS
2
s
Address hold time
Note 2
(vs. MD0
)
t
AH
t
AH
2
s
Data hold time (vs. MD0
)
t
DH
t
DH
2
s
MD0
data output float delay time
t
DF
t
DF
0
130
ns
V
PP
setup time (vs. MD3
)
t
VPS
t
VPS
2
s
V
DD
setup time (vs. MD3
)
t
VDS
t
VCS
2
s
Initial program pulse width
t
PW
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
OPW
t
OPW
0.95
21.0
ms
MD0 setup time (vs. MD1
)
t
M0S
t
CES
2
s
MD0
data output delay time
t
DV
t
DV
MD0 = MD1 = V
IL
1
s
MD1 hold time (vs. MD0
)
t
M1H
t
OEH
t
M1H
+ t
M1R
50
s
2
s
MD1 recovery time (vs. MD0
)
t
M1R
t
OR
2
s
Program counter reset time
t
PCR
--
10
s
CLK input high-, low-level widths
t
XH
, t
XL
--
0.125
s
CLK input frequency
f
X
--
4.19
MHz
Initial mode set time
t
I
--
2
s
MD3 setup time (vs. MD1
)
t
M3S
--
2
s
MD3 hold time (vs. MD1
)
t
M3H
--
2
s
MD3 setup time (vs. MD0
)
t
M3SR
--
On reading program memory
2
s
Address
Note 2
data output delay time
t
DAD
t
ACC
On reading program memory
2
s
Address
Note 2
data output hold time
t
HAD
t
OH
On reading program memory
0
130
ns
MD3 hold time (vs. MD0
)
t
M3HR
--
On reading program memory
2
s
MD3
data output float delay time
t
DFR
--
On reading program memory
2
s
Reset setup time
t
RES
10
s
Notes 1. Corresponding symbols of
PD27C256A (the
PD27C256A is a maintenance product).
2. The internal address signal is incremented by one at the falling edge of CLK input at the third clock.
PD61P24
27
PROGRAM MEMORY WRITE TIMING
PROGRAM MEMORY READ TIMING
V
PP
V
PP
V
DD
GND
V
DD
+1
V
DD
V
DD
GND
CLK
D0-D7
MD0
MD1
MD2
MD3
t
RES
t
VPS
t
VDS
t
XH
t
XL
t
AS
t
AH
t
DH
t
DS
t
OPW
t
DF
t
DV
t
M0S
t
M1R
t
OH
t
DS
t
PW
t
I
t
M3H
t
M1H
t
M1S
t
PCR
t
M3S
Data input
Data output
Data input
Data input
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data output
Data output
t
M3SR
t
PCR
t
DV
t
I
t
XL
t
DAD
t
HAD
t
VDS
t
VPS
t
XH
t
M3HR
t
DFR
" L "
V
PP
V
PP
V
DD
GND
V
DD
+1
V
DD
V
DD
GND
CLK
D0-D7
MD0
MD1
MD2
MD3
t
RES
Hi-Z
Hi-Z
PD61P24
28
21. PACKAGE DRAWINGS
20 PIN PLASTIC SOP (300 mil)
ITEM MILLIMETERS INCHES
A
B
C
E
F
G
H
I
J
13.00 MAX.
1.27 (T.P.)
1.8 MAX.
1.55
7.70.3
0.78 MAX.
0.12
1.1
5.6
M
0.10.1
N
0.512 MAX.
0.031 MAX.
0.0040.004
0.071 MAX.
0.061
0.3030.012
0.220
0.043
0.005
0.050 (T.P.)
P20GM-50-300B, C-4
P
3
3
+7
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
D 0.40
0.016
+0.10
0.05
K 0.20
0.008
+0.10
0.05
L 0.60.2 0.024
0.10
3
+7
3
0.004
+0.008
0.009
+0.004
0.002
+0.004
0.003
A
C
D
G
P
detail of lead end
F
E
B
H
I
L
K
M
J
N
M
1
10
11
20
PD61P24
29
20PIN PLASTIC SHRINK DIP (300 mil)
ITEM
MILLIMETERS
INCHES
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
P20C-70-300B-1
N
0.17
0.007
R
0~15
0~15
A
19.57 MAX.
0.771 MAX.
B
1.78 MAX.
0.070 MAX.
F
0.85 MIN.
0.033 MIN.
G
3.20.3
0.1260.012
J
5.08 MAX.
0.200 MAX.
K
7.62 (T.P.)
0.300 (T.P.)
C
1.778 (T.P.)
0.070 (T.P.)
D
0.500.10
0.020+0.004
0.005
H
0.51 MIN.
0.020 MIN.
I
4.31 MAX.
0.170 MAX.
L
6.5
0.256
M
0.25
0.010+0.004
0.003
+0.10
0.05
2) ltem "K" to center of leads when formed parallel.
M
R
M
I
H
G
F
D
N
C
B
K
1
10
20
11
A
L
J
PD61P24
30
22. RECOMMENDED SOLDERING CONDITIONS
It is recommended that
PD6124A and 6600A be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document, Semiconductor Device
Mounting Technology Manual (C10535E).
For other soldering methods and conditions, consult NEC.
Table 22-1. Soldering Conditions of Surface-Mount Type
PD61P24GS: 20-pin plastic SOP (300 mil)
Soldering Method
Soldering Conditions
Partial Heating
Pin temperature: 300
C max., time: 3 seconds max. (per device side)
Table 22-2. Soldering Conditions of Through-Hole Type
PD61P24CS: 20-pin plastic shrink DIP (300 mil)
Soldering Method
Soldering Conditions
Wave Soldering (Only for pin part)
Solder bath temperature: 260
C max., time: 10 seconds max.
Partial Heating
Pin temperature: 300
C max., time: 3 seconds max. (per pin)
Caution When soldering this product using of wave soldering, exercise care that the solder does not come
in direct contact with the package.
PD61P24
31
APPENDIX A.
PD612
SERIES PRODUCT LIST
Part Number
PD6124A
PD6600A
PD61P24
PD6125A
PD6126A
Item
ROM capacity
1002
10 bits
512
10 bits
1002
10 bits
1002
10 bits
(mask ROM)
(mask ROM)
(one-time PROM)
(mask ROM)
RAM capacity
32
5 bits
I/O pin
8 pins (K
I/O0-7
)
12 pins
16 pins (K
I/O0-7
,
(K
I/O0-7
, I/O
00-03
)
I/O
00-03
, I/O
10-13
)
S-IN pin
Provided
Current consumption
2
A
1
A
(f
OSC
= STOP) (MAX.)
S-IN high-level input
30
A
15
A
current (MAX.)
Transmission carrier frequency
f
OSC
/12, f
OSC
/8
Low-voltage detection
Provided
None
(reset) function
Mask option
Provided
None (fixed)
Provided
Supply voltage
V
DD
= 2.2 to 5.5 V V
DD
= 2.2 to 3.6 V V
DD
= 2.2 to 5.5 V V
DD
= 2.0 to 6.0 V
Package
20-pin plastic SOP (300 mil)
24-pin plastic
28-pin plastic
20-pin plastic shrink DIP (300 mil)
SOP (300 mil)
SOP (375 mil)
24-pin plastic
shrink DIP
(300 mil)
PD61P24
32
APPENDIX B. DEVELOPMENT TOOLS
The following tools are available for program development using the
PD61P24.
Document
Document No.
PS612X Series Emulator
--
Note 1
PS61P24 Assembler
--
Note 1
PROM Programmer
AF-9703
Note 2, 3
AF-9704
Note 2, 3
AF-9705
Note 3
AF-9706
Note 3
PD61P24 Program Adapter
AF9807B
Note 3
Notes 1. These are products from I.C Corp. For details, consult I.C Corp.
I.C Corp.
6th Barnet Gotanda Bldg.
1-9-5 Higashi-Gotanda, Shinagawa-ku, Tokyo 141
Tel. 03-3447-3793
Fax. 03-3440-5606
2. Not available.
3. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd.
Ando Electric Co., Ltd.
4-19-7 Kamata, Ota-ku, Tokyo 144
Tel. 0120-40-0211(toll-free)
Caution Use a writing program after assembling the program, convert the HEX file to a ROM file by using
the PROM utility program "UPDPROM" (refer to AS612X Assembler User's Manual(IEM-1016)).
PD61P24
33
[MEMO]
PD61P24
34
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD61P24
35
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J96. 8
PD61P24
36
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
[MEMO]
PDF 
ZIP