Document Outline

COVER
DESCRIPTION
FEATURES
APPLICATION
ORDERING INFORMATION
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
LIST OF FUNCTIONS
1. PIN FUNCTIONS
- 1.1 List of Pin Functions
- 1.2 Pin Input/Output Circuits
- 1.3 Recommended Connection of Unused Pins
2. INTERNAL CPU FUNCTIONS
- 2.1 Program Counter (PC): 10 Bits
- 2.2 Stack Pointer (SP): 1 Bit
- 2.3 Address Stack Register (ASR (RF)): 10 Bits
- 2.4 Program Memory (ROM): 512 steps x 10 bits
- 2.5 Data Memory (RAM): 32 x 4 Bits
- 2.6 Data Pointer (DP): 10 Bits
- 2.7 Accumulator (A): 4 Bits
- 2.8 Arithmetic and Logic Unit (ALU): 4 Bits
- 2.9 Flags
  - 2.9.1 Status flag (F)
  - 2.9.2 Carry flag (CY)
3. PORT REGISTERS (PX)
- 3.1 KI/O Port (P0)
- 3.2 KI Port/Special Ports (P1)
  - 3.2.1 KI port (P11: bits 4 to 7 of P1)
  - 3.2.2 S0 port (bit 2 of P1)
  - 3.2.3 S1/LED# (bit 3 of P1)
- 3.3 Control Register 0 (P3)
- 3.4 Control Register 1 (P4)
4. TIMER
- 4.1 Timer Configuration
- 4.2 Timer Operation
- 4.3 Carrier Output
- 4.4 Software Control of Timer Output
5. STANDBY FUNCTION
- 5.1 Outline of Standby Function
- 5.2 Standby Mode Setting and Release
- 5.3 Standby Mode Release Timing
6. RESET# PIN
7. POC CIRCUIT (MASK OPTION)
- 7.1 Functions of POC Circuit
- 7.2 Oscillation Check at Low Supply Voltage
8. SYSTEM CLOCK OSCILLATOR
9. INSTRUCTION SET
- 9.1 Machine Language Output by Assembler
- 9.2 Circuit Symbol Description
- 9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table
- 9.4 Accumulator Operation Instructions
- 9.5 Input/Output Instructions
- 9.6 Data Transfer Instruction
- 9.7 Branch Instructions
- 9.8 Subroutine Instructions
- 9.9 Timer Operation Instructions
- 9.10 Others
10. ASSEMBLER RESERVED WORDS
- 10.1 Mask Option Directives
  - 10.1.1 OPTION and ENDOP directives
  - 10.1.2 Mask option definition directive
11. ELECTRICAL SPECIFICATIONS
12. CHARACTERISTICS CURVES (REFERENCE VALUES)
13. APPLICATION CIRCUIT EXAMPLE
14. PACKAGE DRAWINGS
15. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. DEVELOPMENT TOOLS
APPENDIX B. FUNCTIONAL COMPARISON BETWEEN uPD62A AND OTHER SUBSERIES
APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT

1999

DATA SHEET

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR INFRARED REMOTE CONTROL TRANSMISSION

DESCRIPTION

Due to its low-voltage 2.0 V operation, on-chip carrier generator for infrared remote control transmission, standby

release function through key entry, and programmable timer, the

PD62A is ideal for infrared remote control

transmitters.

For the

PD62A, the one-time PROM product

PD6P4B has been made available for program evaluation or

small-scale production.

FEATURES

· Program memory (ROM): 512

10 bits

· Data memory (RAM): 32

4 bits

· On-chip carrier generator for infrared remote control

· 9-bit programmable timer:

1 channel

· Command execution time:

s (when operating at f

= 8 MHz: ceramic oscillation)

· Stack levels:

1 (Stack RAM is also available for data memory RF.)

· I/O pins (K

I/O

· Input pins (K

· Sense input pin (S

)

· S

/LED pin (I/O): When in output mode, this is the remote control transmission display pin.

· Power supply voltage:

= 2.0 to 3.6 V

· Operating ambient temperature: T

= 40 to +85°C

· Oscillator frequency:

= 2.4 to 8 MHz

· POC (Power On Clear) circuit (Mask option)

APPLICATION

Infrared remote control transmitter (for AV and household electrical appliances)

MOS INTEGRATED CIRCUIT

PD62A

Document No. U14474EJ1V0DS00 (1st edition)
Date Published November 1999 N CP(K)
Printed in Japan

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.

PD62A

Data Sheet U14474EJ1V0DS00

BLOCK DIAGRAM

-K

I/O0

-K

I/O7

, S

/LED

Port K

I/O

Port S

ROM

RAM

System
control

Carrier
generator

9-bit
timer

CPU
core

RESET

OUT

GND

REM

/LED

LIST OF FUNCTIONS

Item

PD62A

PD6P4B

ROM capacity

512

10 bits

1002

10 bits

Mask ROM

One-time PROM

RAM capacity

4 bits

Stack

1 level (RAM also used as RF)

I/O pins

· Key input (K

· Key I/O (K

I/O

· Key extended input (S

, S

· Remote control transmission display output (LED): 1 (alternately functions as S

pin)

Number of keys

· 32 keys

· 48 keys (when extended by key extension input)

· 96 keys (when extended by key extension input and diode)

Clock frequency

Ceramic oscillation

· f

= 2.4 to 8 MHz

Instruction execution time

s (f

= 8 MHz)

Carrier frequency

/8, f

/16, f

/64, f

/96, f

/128, f

/192, no carrier (high level)

Timer

9-bit programmable timer: 1 channel

POC circuit

Mask option

Internal

Supply voltage

= 2.0 to 3.6 V

= 2.2 to 3.6 V (f

= 2.4 to 4 MHz)

= 2.7 to 3.6 V (f

= 4 to 8 MHz)

Operating ambient temperature

= 40 to +85

Package

· 20-pin plastic SSOP (300 mils)

· 20-pin plastic SOP (300 mils)

· 20-pin plastic SSOP (300 mils)

PD62A

Data Sheet U14474EJ1V0DS00

TABLE OF CONTENTS

1. PIN FUNCTIONS ..........................................................................................................................

1.1

List of Pin Functions .........................................................................................................................

1.2

Pin Input/Output Circuits ..................................................................................................................

1.3

Recommended Connection of Unused Pins ...................................................................................

2. INTERNAL CPU FUNCTIONS .....................................................................................................

2.1

Program Counter (PC) ......................................................................................................................

2.2

Stack Pointer (SP) .............................................................................................................................

2.3

Address Stack Register (ASR (RF)) .................................................................................................

2.4

Program Memory (ROM) ................................................................................................................... 10

2.5

Data Memory (RAM) .......................................................................................................................... 10

2.6

Data Pointer (DP) ............................................................................................................................... 11

2.7

Accumulator (A) ................................................................................................................................ 11

2.8

Arithmetic and Logic Unit (ALU) ...................................................................................................... 12

2.9

Flags ................................................................................................................................................... 12

2.9.1

Status flag (F) .......................................................................................................................... 12

2.9.2

Carry flag (CY) ........................................................................................................................ 13

3. PORT REGISTERS (PX) .............................................................................................................. 14

3.1

I/O

Port (P0) ....................................................................................................................................... 15

3.2

Port/Special Ports (P1) ................................................................................................................. 16

3.2.1

port (P

: bits 4 to 7 of P1) .................................................................................................. 16

3.2.2

port (bit 2 of P1) .................................................................................................................. 16

3.2.3

/LED (bit 3 of P1) ................................................................................................................. 16

3.3

Control Register 0 (P3) ..................................................................................................................... 17

3.4

Control Register 1 (P4) ..................................................................................................................... 18

4. TIMER ........................................................................................................................................... 19

4.1

Timer Configuration .......................................................................................................................... 19

4.2

Timer Operation ................................................................................................................................. 20

4.3

Carrier Output .................................................................................................................................... 21

4.4

Software Control of Timer Output ................................................................................................... 21

5. STANDBY FUNCTION ................................................................................................................. 22

5.1

Outline of Standby Function ............................................................................................................ 22

5.2

Standby Mode Setting and Release ................................................................................................. 23

5.3

Standby Mode Release Timing ........................................................................................................ 24

6. RESET PIN ................................................................................................................................... 26

7. POC CIRCUIT (MASK OPTION) .................................................................................................. 27

7.1

Functions of POC Circuit .................................................................................................................. 28

7.2

Oscillation Check at Low Supply Voltage ....................................................................................... 28

8. SYSTEM CLOCK OSCILLATOR ................................................................................................. 29

PD62A

Data Sheet U14474EJ1V0DS00

9. INSTRUCTION SET ...................................................................................................................... 30

9.1

Machine Language Output by Assembler ....................................................................................... 30

9.2

Circuit Symbol Description .............................................................................................................. 31

9.3

Mnemonic to/from Machine Language (Assembler Output) Contrast Table ...............................

9.4

Accumulator Operation Instructions ............................................................................................... 36

9.5

Input/Output Instructions ................................................................................................................. 39

9.6

Data Transfer Instruction .................................................................................................................. 40

9.7

Branch Instructions .......................................................................................................................... 42

9.8

Subroutine Instructions .................................................................................................................... 43

9.9

Timer Operation Instructions ........................................................................................................... 44

9.10 Others ................................................................................................................................................. 45

10. ASSEMBLER RESERVED WORDS .......................................................................................... 47

10.1 Mask Option Directives .................................................................................................................... 47

10.1.1 OPTION and ENDOP directives ............................................................................................. 47

10.1.2 Mask option definition directive ............................................................................................... 47

11. ELECTRICAL SPECIFICATIONS .............................................................................................. 48

12. CHARACTERISTIC CURVES (REFERENCE VALUES) ........................................................... 52

13. APPLICATION CIRCUIT EXAMPLE .......................................................................................... 53

14. PACKAGE DRAWINGS ............................................................................................................. 54

15. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 55

APPENDIX A. DEVELOPMENT TOOLS ......................................................................................... 56

APPENDIX B. FUNCTIONAL COMPARISON BETWEEN

PD62A AND OTHER SUBSERIES ... 57

APPENDIX C. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 58

PD62A

Data Sheet U14474EJ1V0DS00

1. PIN FUNCTIONS

1.1 List of Pin Functions

Pin No.

Symbol

Function

After Format

After Reset

I/O0

to K

I/O7

CMOS

High-level output

push-pull

Note 1

15 to 20

High-impedance

(OFF mode)

/LED

CMOS push-pull

High-level output

(LED)

REM

CMOS push-pull

Low-level output

OUT

Low level

(oscillation stopped)

GND

RESET

11 to 14

to K

Note 2

Input (low-level)

Notes 1. Be aware that the drive capability of the low-level output side is held low.

2. In order to prevent malfunction, be sure to input a low level to more than one of pins K

to K

when

reset is released (when the RESET pin changes from low level to high level, or POC is released due

to supply voltage startup).

8-bit input/output port

Input/output can be specified in 8-bit units.

In input mode, a pull-down resistor is added.

In output mode, these pins can be used as the key scan

output of the key matrix.

Input port

Can also be used as the key return input of the key

matrix.

In input mode, the use of a pull-down resistor for the S

and S

ports can be specified by software in 2-bit units.

If input mode is canceled by software, this pin is placed

in OFF mode and enters the high-impedance state.

Input/output port

In input mode (S

), this pin can also be used as the key

return input of the key matrix.

The use of a pull-down resistor for the S

and S

ports

can be specified by software in 2-bit units.

In output mode (LED), it becomes the remote control

transmission display output (active low). When the

remote control carrier is output from the REM output, this

pin outputs a low level from the LED output synchronously

with the REM signal.

Infrared remote control transmission output.

The output is active high.

Carrier frequency: f

/8, f

/64, f

/96, high-level, f

/16,

/128, f

/192 (software supporting)

Power supply

These pins are connected to system clock ceramic

resonators.

Ground

Normally, this pin is the system reset input. By inputting

a low level, the CPU can be reset. When resetting with

the POC circuit (mask option) a low level is output. A

pull-up resistor is connected to this pin.

4-bit input port

These pins can be used as the key return input of the key

matrix.

The use of a pull-down resistor can be specified by

software in 4-bit units.

PD62A

Data Sheet U14474EJ1V0DS00

2. INTERNAL CPU FUNCTIONS

2.1 Program Counter (PC): 10 Bits

This is a binary counter that holds the address information of the program memory.

Figure 2-1. Program Counter Configuration

PC9

PC0

PC8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

The program counter contains the address of the instruction that should be executed next. Normally, the counter

contents are automatically incremented in accordance with the instruction length (byte count) each time an

instruction is executed.

However, when executing JUMP instructions (JMP, JC, JNC, JF, JNF), the program counter contains the jump

destination address written in the operand.

When executing the subroutine call instruction (CALL), the call destination address written in the operand is

entered in the PC after the PC contents at the time are saved in the address stack register (ASR). If the return

instruction (RET) is executed after the CALL instruction is executed, the address saved in the ASR is restored to

the PC.

When reset, the value of the program counter becomes "000H".

2.2 Stack Pointer (SP): 1 Bit

This is a 1-bit register which holds the status of the address stack register.

The stack pointer contents are incremented when the call instruction (CALL) is executed; they are decremented

when the return instruction (RET) is executed.

When reset, the stack pointer contents are cleared to 0.

When the stack pointer overflows (stack level 2 or more) or underflows, the CPU is hung up and a system reset

signal is generated, and the PC becomes "000H".

As no instruction is available to set a value directly for the stack pointer, it is not possible to operate the pointer

by means of a program.

2.3 Address Stack Register (ASR (RF)): 10 Bits

The address stack register saves the return address of the program after a subroutine call instruction is executed.

The low-order 8 bits are configured as RAM that is also used as the data memory RF. The register holds the

ASR value even after RET is executed.

When reset, it holds the previous data (undefined on power application).

Caution If RF is accessed as data memory, the high-order 2 bits of the ASR become undefined.

Figure 2-2. Address Stack Register Configuration

ASR9

ASR8

ASR7

ASR6

ASR5

ASR4

ASR3

ASR2

ASR1

ASR0

ASR

PD62A

Data Sheet U14474EJ1V0DS00

Figure 2-4. Data Memory Configuration

DP (refer to 2.6 Data Pointer (DP))

ASR (refer to 2.3 Address Stack Register (ASR (RF)))

(high-order 4 bits) R

(low-order 4 bits)

2.6 Data Pointer (DP): 10 Bits

The ROM data table can be referenced by setting the ROM address in the data pointer to call the ROM contents.

The low-order 8 bits of the ROM address are specified by R0 of the data memory; and the high-order 2 bits by

bits 4 and 5 of the P3 register (CR0).

When reset, the pointer contents become "000H".

Figure 2-5. Data Pointer Configuration

2.7 Accumulator (A): 4 Bits

The accumulator, which is a register consisting of 4 bits, plays a leading role in performing various operations.

When reset, the accumulator contents become undefined.

Figure 2-6. Accumulator Configuration

PD62A

Data Sheet U14474EJ1V0DS00

2.8 Arithmetic and Logic Unit (ALU): 4 Bits

The arithmetic and logic unit (ALU), which is an arithmetic circuit consisting of 4 bits, executes simple

manipulations with priority given to logical operations.

2.9 Flags

2.9.1 Status flag (F)

Pin and timer statuses can be checked by executing the STTS instruction to check the status flag.

The status flag is set (to 1) in the following cases.

· If the condition specified with the operand is met when the STTS instruction has been executed

· When standby mode is canceled.

· When the cancelation condition is met at the point of executing the HALT instruction. (In this case, the system

is not placed in standby mode.)

Conversely, the status flag is cleared (to 0) in the following cases:

· If the condition specified with the operand is not met when the STTS instruction has been executed.

· When the status flag has been set (to 1), the HALT instruction executed, but the cancelation condition is not

met at the point of executing the HALT instruction. (In this case, the system is not placed in standby mode.)

Table 2-1. Conditions for Status Flag (F) to Be Set by STTS Instruction

Operand Value of STTS Instruction

Condition for Status Flag (F) to Be Set

High level input to at least one of K

pins.

High level input to at least one of K

pins.

High level input to at least one of K

pins.

The down counter of the timer is 0.

Any combination of b

[The following condition is added in addition to the above.]

, and b

above.

High level input to at least one of S

and S

pins.

PD62A

Data Sheet U14474EJ1V0DS00

3.1 K

I/O

Port (P0)

The K

I/O

port is an 8-bit input/output port for key scan output.

Input/output mode is set by bit 1 of the P4 register.

If a read instruction is executed, the pin state can be read in input mode, whereas the output latch contents can

be read in output mode.

If the write instruction is executed, data can be written to the output latch regardless of input or output mode.

When reset, the port is placed in output mode; and the value of the output latch (P0) becomes 1111 1111B.

The K

I/O

port includes a pull-down resistor, allowing pull-down in input mode only.

Caution If a key is double-pressed, a high-level output and a low-level output may coincide at the

I/O

port. To avoid this, the low-level output current of the K

I/O

port is held low. Therefore, be

careful when using the K

I/O

port for purposes other than key scan output.

The K

I/O

port is so designed that, even when connected directly to V

, within the normal supply

voltage range (V

= 2.0 to 3.6 V), no problem may occur.

Table 3-2. K

I/O

Port (P0)

Bit

Name

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

to b

: Read:

In input mode, the K

I/O

pin's state is read.

In output mode, the K

I/O

pin's output latch contents are read.

Write:

Data is written to the K

I/O

pin's output latch regardless of input or output mode.

PD62A

Data Sheet U14474EJ1V0DS00

3.2 K

Port/Special Ports (P1)

3.2.1 K

port (P

: bits 4 to 7 of P1)

The K

port is a 4-bit input port for key entry.

The pin status can be read at this port.

Software can be used to set whether to connect a pull-down resistor at the K

port in 4-bit units by means of bit

5 of the P4 register.

When reset, a pull-down resistor is connected.

Table 3-3. K

/Special Port Register (P1)

Bit

Name

/LED

(Fixed to 1)

In input mode, the status of the S

pin is read (Read only).

In OFF mode, this bit is fixed to 1.

The status of the S

/LED pin is read regardless of input/output mode (Read only).

to b

The status of the K

pin is read (Read only).

Caution In order to prevent malfunction, be sure to input a low level to more than one of pins K

to K

when reset is released (when the RESET pin changes from low level to high level, or POC is

released due to supply voltage startup).

3.2.2 S

port (bit 2 of P1)

The S

port is the input/OFF mode port.

The pin status can be read by setting this port to input mode with bit 0 of the P4 register.

In input mode, software can be used to set whether to connect a pull-down resistor at the S

and S

/LED ports

in 2-bit units by means of bit 4 of the P4 register.

If input mode is canceled (set to OFF mode), the pin becomes high-impedance, but the through current is stopped

from flowing internally. In OFF mode, "1" can be read regardless of the pin status.

When reset, this port is set to OFF mode and becomes high-impedance.

3.2.3 S

/LED (bit 3 of P1)

The S

/LED port is an input/output port.

This port is set input or output mode by means of bit 2 of the P4 register. The pin status can be read in both

input and output mode.

In input mode, software can be used to set whether to connect a pull-down resistor at the S

and S

/LED ports

in 2-bit units by means of bit 4 of the P4 register.

In output mode, the pull-down resistor is automatically disconnected, and this port becomes the remote control

transmission display pin (refer to 4. TIMER).

When reset, this port is placed in output mode, and a high level is output.

PD62A

Data Sheet U14474EJ1V0DS00

3.3 Control Register 0 (P3)

Control register 0 consists of 8 bits. The contents that can be controlled are as shown below.

When reset, this register becomes 0000 0011B.

Table 3-4. Control Register 0 (P3)

Bit

Name

DP (Data pointer) TCTL

CARY

MOD

Set

Fixed

1/1

Refer to Table 3-5.

value

to 0

1/2

OFF

After reset

and b

: These bits specify the carrier frequency and duty ratio of the REM output.

This bit specifies the availability of the carrier of the frequency specified by b

and b

"0" = ON (with carrier); "1" = OFF (without carrier; high level)

This bit changes the carrier frequency and the timer clock's frequency division ratio.

"0" = 1/1 (carrier frequency: the specified value of b

and b

; timer clock: f

/64)

"1" = 1/2 (carrier frequency: half of the specified value of b

and b

; timer clock: f

/128)

Table 3-5. Timer Clock and Carrier Frequency Settings

Timer Clock

Carrier Frequency (Duty Ratio)

/64

/8 (Duty 1/2)

/64 (Duty 1/2)

/96 (Duty 1/2)

/96 (Duty 1/3)

Without carrier (high level)

/128

/16 (Duty 1/2)

/128 (Duty 1/2)

/192 (Duty 1/2)

/192 (Duty 1/3)

Without carrier (high level)

and b

: These bits specify the high-order 2 bits (DP

and DP

) of the ROM data pointer.

Remark

: don't care

PD62A

Data Sheet U14474EJ1V0DS00

3.4 Control Register 1 (P4)

Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.

When reset, this register becomes 0010 0110B.

Table 3-6. Control Register 1 (P4)

Bit

Name

/LED

I/O

Pull-down Pull-down

mode

Set

Fixed

OFF

Fixed

OFF

value

to 0

to "0"

LED

OUT

After reset

: Specifies the input mode of the S

port. "0" = OFF mode (high impedance); "1" = IN (input mode).

: Specifies the I/O mode of the K

I/O

port.

"0" = IN (input mode); "1" = OUT (output mode).

: Specifies the I/O mode of the S

/LED port. "0" = S

(input mode); "1" = LED (output mode).

: Specifies the connection of a pull-down resistor in S

port input mode. "0" = OFF (not connected);

"1" = ON (connected)

: Specifies the connections of a pull-down resistor in K

port. "0" = OFF (not connected);

"1" = ON (connected).

Remark In output mode or in OFF mode, all the pull-down resistors are automatically disconnected.

PD62A

Data Sheet U14474EJ1V0DS00

4.2 Timer Operation

The timer starts (counting down) when a value other than 0 is set for the down counter with a timer operation

instruction. The timer operation instructions for making the timer start operation are shown below:

MOV T0, A

MOV T1, A

MOV T, #data10

MOV T, @R0

The down counter is decremented (1) in the cycle of 64/f

or 128/f

Note

. If the value of the down counter becomes

0, the zero-detection circuit generates the timer operation end signal to stop the timer operation. At this time, if

the timer is in HALT mode (HALT #

101B) waiting for the timer to stop its operation, the HALT mode is canceled

and the instruction following the HALT instruction is executed. The output of the timer operation end signal is

continued while the down counter is 0 and the timer is stopped. There is the following relational expression between

the timer's time and the down counter's set value.

Timer time = (Set value + 1)

64/f

(or 128/f

Note

)

Note This becomes 128/f

if bit 3 of the control register is set (to 1).

By setting 1 for the flag (t

) which enables the timer output, the timer can output its operation status from the

/LED pin and the REM pin. The REM pin can also output the carrier while the timer is in operation.

Table 4-1. Timer Output (at t

= 1)

/LED Pin

REM Pin

Timer operating

H (or carrier output

Note

)

Timer halting

Note The carrier output results if bit 2 of control register 0 is cleared (to 0).

Figure 4-2. Timer Output (When Carrier Is Not Output)

Timer value: (set value + 1)

64/f

(or 128/f

)

LED

REM

PD62A

Data Sheet U14474EJ1V0DS00

4.3 Carrier Output

The carrier for remote-controlled transmission can be output from the REM pin by clearing (to 0) bit 2 of control

As shown in Figure 4-3, in the case where the timer stops when the carrier is at a high level, the carrier continues

to be output until its next fall and then stops due to the function of the carrier synchronous circuit. When the timer

starts operation, however, the high-level width of the first carrier may be shorter than the specified width.

Figure 4-3. Timer Output (When Carrier Is Output)

Timer value: (Set value+1)

64/f

(or 128/f

)

LED

REM (at low-level start)

REM (at high-level start)

Note 1

Note 2

Notes 1. Error when the REM output ends: Lead by "the carrier's low-level width" to lag by "the carrier's high-

level width"

2. Error of the carrier's high-level width: 0 to "the carrier's high-level width"

4.4 Software Control of Timer Output

The timer output can be controlled by software. As shown in Figure 4-4, a pulse with a minimum width of 1-

instruction cycle (64/f

) can be output.

Figure 4-4. Pulse Output of 1-Instruction Cycle Width

MOV T, #0000000000B; low-level output from the REM pin

MOV T, #1000000000B; high-level output from the REM pin

MOV T, #0000000000B; low-level output from the REM pin

64/f

LED

REM

...

PD62A

Data Sheet U14474EJ1V0DS00

5. STANDBY FUNCTION

5.1 Outline of Standby Function

To save current consumption, two types of standby modes, HALT mode and STOP mode, are made available.

In STOP mode, the system clock stops oscillation. At this time, the X

and X

OUT

pins are fixed at a low level.

In HALT mode, CPU operation halts, while the system clock continues oscillating. When in HALT mode, the

timer (including REM output and LED output) operates.

In either STOP mode or HALT mode, the statuses of the data memory, accumulator, and port register, etc.

immediately before the standby mode was set are retained. Therefore, make sure to set the port status for the system

so that the current consumption of the whole system is suppressed before the standby mode is set.

Table 5-1. Statuses During Standby Mode

STOP Mode

HALT Mode

Setting instruction

HALT instruction

Clock oscillation circuit

Oscillation stopped

Oscillation continues

CPU

· Operation halted

Data memory

· Immediately preceding status retained

Operation

Accumulator

· Immediately preceding status retained

statuses

Flag

· 0 (When 1, the flag is not placed in the standby mode.)

· Immediately preceding status retained

Port register

· Immediately preceding status retained

Timer

· Operation halted

· Operable

(The count value is reset to "0")

Cautions 1. Write the NOP instruction as the first instruction after STOP mode is canceled.

2. When standby mode is canceled, the status flag (F) is set (to 1).

3. If, at the point the standby mode has been set, its cancelation condition is met, then the

system is not placed in the standby mode. However, the status flag (F) is set (1).

PD62A

Data Sheet U14474EJ1V0DS00

5.2 Standby Mode Setting and Release

The standby mode is set with the HALT #b

B instruction for both STOP mode and HALT mode. For the

standby mode to be set, the status flag (F) is required to have been cleared (to 0).

The standby mode is released by the release condition specified by the reset (RESET input; POC) or the HALT

instruction operand. If the standby mode is released, the status flag (F) is set (to 1).

Even when the HALT instruction is executed in a state in which the status flag (F) has been set (to 1), the standby

mode is not set. If the release condition is not met at this time, the status flag is cleared (to 0). If the release condition

is met, the status flag remains set (to 1).

Even in the case when the release condition has already been met at the point that the HALT instruction is

executed, the standby mode is not set. Here, also, the status flag (F) is set (to 1).

Caution Depending on the status of the status flag (F), the HALT instruction may not be executed. Be

careful about this. For example, when setting HALT mode after checking the key status with

the STTS instruction, because the system does not enter HALT mode as long as the status flag

(F) remains set (to 1), sometimes an unintended operation is performed. In this case, the

intended operation can be realized by executing the STTS instruction immediately after the

timer setting to clear (to 0) the status flag.

Example

STTS

#03H

;To check the K

pin status.

MOV

T, #0xxH

;To set the timer

STTS

#05H

;To clear the status flag

(During this time, be sure not to execute an instruction that may set the status flag.)

HALT

#05H

;To set HALT mode

Table 5-2. Addresses Executed After Standby Mode Release

Release Condition

Address Executed After Release

Reset

0 address

Release condition shown in Table 5-3

The address following the HALT instruction

...

PD62A

Data Sheet U14474EJ1V0DS00

Table 5-3. Standby Mode Settings (HALT #b

B) and Release Conditions

Operand Value of

HALT Instruction

Setting Mode

Setting Precondition

Release Condition

STOP

All K

I/O

pins are high-level output.

High level input to at least one

of K

pins.

STOP

All K

I/O

pins are high-level output.

High level input to at least one

of K

pins.

STOP

Note 1

The K

I/O0

pin is high-level output.

High level input to at least one

of K

pins.

Any combination of

STOP

[The following condition is added in addition to the above.]

above

High level input to at least one

of S

and S

pins

Note 2

0/1

HALT

When the timer's down counter is 0

Notes 1. When setting HALT #

110B, configure a key matrix by using the K

I/O0

pin and the K

pin so that an

internal reset takes effect at the time of program hang-up.

2. At least one of the S

and S

pins (the pin used for releasing standby) must be in input mode. (Note

that an internal reset does not take effect even when both pins are in output mode.)

Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value

other than that above or when the precondition has not been satisfied when executing the

HALT instruction.

2. If STOP mode is set when the timer's down counter is not 0 (timer operating), the system

is placed in STOP mode only after all the 10 bits of the timer's down counter and the timer

output permit flag are cleared to 0.

3. Write the NOP instruction as the first instruction after STOP mode is released.

5.3 Standby Mode Release Timing

(1) STOP mode release timing

Figure 5-1. STOP Mode Cancelation by Release Condition

Caution When a release condition is established in the STOP mode, the device is released from the STOP

mode, and goes into a wait state. At this time, if the release condition is not held, the device

goes into STOP mode again after the wait time has elapsed. Therefore, when releasing the STOP

mode, it is necessary to hold the release condition longer than the wait time.

Wait

(52/f

)

HALT mode

Operating

mode

STOP mode

Oscillation

stopped

Oscillation

Operating

mode

Oscillation

HALT instruction

(STOP mode)

Standby
release signal

Clock

: Oscillation growth time

PD62A

Data Sheet U14474EJ1V0DS00

6. RESET PIN

The system reset takes effect by inputting a low level to the RESET pin.

While the RESET pin is at low level, the system clock oscillator is stopped and the X

and X

OUT

pins are fixed

to GND.

If the RESET pin is raised from low level to high level, it executes the program from the 0 address after counting

246 to 694 of the system clock (f

Figure 6-1. Reset Operation by RESET Input

The RESET pin outputs a low level when the POC circuit (mask option) is in operation.

Caution When connecting a reset IC to the RESET pin, be sure to connect an IC of the N-ch open drain

output type.

Table 6-1. Hardware Statuses After Reset

· RESET Input During Operation

· RESET Input in Standby Mode

Hardware

· Reset by Internal POC Circuit During Operation · Reset by Internal POC Circuit in Standby

· Reset by Other Factors

Note 1

Mode

PC (10 bits)

000H

SP (1 bit)

Data

R0 = DP

000H

memory

R1-RF

Undefined

Previous status retained

Accumulator (A)

Undefined

Status flag (F)

Carry flag (CY)

Timer (10 bits)

000H

Port register

FFH

Note 2

Control register P3

03H

26H

Notes 1. The following resets are available.

· Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy

the precondition)

· Reset when executing the RLZ instruction (when A = 0)

· Reset by stack pointer's overflow or underflow

2. Refers to the value based on the K

pin status.

In order to prevent malfunction, be sure to input a low level to more than one of pins K

to K

when

reset is released (when the RESET pin changes from low level to high level, or POC is released due

to supply voltage startup).

Wait

(246 to 694)/f

HALT mode

Oscillation

stopped

Operating mode or
standby mode

RESET

0 address start

: Oscillation growth time

Operating

mode

PD62A

Data Sheet U14474EJ1V0DS00

7. POC CIRCUIT (MASK OPTION)

The POC circuit monitors the power supply voltage and applies an internal reset in the microcontroller when the

battery is replaced, etc. If the application circuit satisfies the following conditions, the POC circuit can be

incorporated by the mask option.

· High reliability is not required.

· Clock frequency f

= 2.4 to 8 MHz

· Operating ambient temperature T

= 40 to +85°C

Cautions 1. The one-time PROM product (

PD6P4B) already contains the POC circuit.

2. There are cases in which the POC circuit cannot detect a low power supply voltage of less

than 1 ms. Therefore, if the power supply voltage has become low for a period of less than

1 ms, the POC circuit may malfunction because it does not generate an internal reset signal.

3. Clock oscillation is stopped by the resonator due to low power supply voltage before the

POC circuit generates the internal reset signal. In this case, malfunction may result, for

example when the power supply voltage is recovered after the oscillation is stopped. This

type of phenomenon takes place because the POC circuit does not generate an internal reset

signal (because the power supply voltage recovers before the low power supply voltage is

detected) even though the clock has stopped. If, by any chance, a malfunction has taken

place, remove the battery for a short time and put it back. In most cases, normal operation

will be resumed.

4. If the application circuit does not satisfy the conditions above, design the application circuit

so that the reset takes effect without failure within the power supply voltage range by means

of an external reset circuit.

5. In order to prevent malfunction, be sure to input a low level to more than one of pins K

when reset is released (when the RESET pin changes from low level to high level, or POC

is released due to supply voltage startup).

Remarks 1. It is recommended that the POC circuit be incorporated when the application circuit is an infrared

remote-control transmitter for household appliances.

2. Even when a POC circuit is incorporated, the externally input RESET is valid with the OR condition;

therefore, the POC circuit and the RESET input can be used at the same time. However, if the

POC circuit detects a low power supply voltage, the RESET pin will be forced to low level; therefore,

use an N-ch open drain output or NPN open collector output for the external reset circuit.

PD62A

Data Sheet U14474EJ1V0DS00

7.1 Functions of POC Circuit

The POC circuit has the following functions:

· Generating an internal reset signal when V

POC

· Canceling an internal reset signal when V

> V

POC

Here, V

: power supply voltage, V

POC

: POC-detected voltage.

Notes 1. In reality, oscillation stabilization wait time must elapse before the circuit is switched to operating

mode. The oscillation stabilization wait time is about 252/f

to 700/f

(about 70 to 190

s: when f

= 3.64 MHz).

2. For the POC circuit to generate an internal reset signal when the power supply voltage has fallen,

it is necessary for the power supply voltage to be kept less than the V

POC

for a period of 1 ms or more.

Therefore, in reality, there is a time lag of up to 1 ms until the reset takes effect.

3. The POC-detected voltage (V

POC

) varies between about 1.7 to 2.0 V; thus, the reset may be canceled

at a power supply voltage smaller than the assured range (V

= 2.0 to 3.6 V). However, as long as

the conditions for operating the POC circuit are met, the actual lowest operating power supply voltage

becomes lower than the POC-detected voltage. Therefore, there is no malfunction occurring due to

the shortage of power supply voltage. However, malfunction for such reasons as the clock not

oscillating due to low power supply voltage may occur (refer to Cautions 3. in 7. POC CIRCUIT).

7.2 Oscillation Check at Low Supply Voltage

A reliable reset operation can be expected of the POC circuit if it satisfies the condition that the clock can oscillate

even at low power supply voltage (the oscillation start voltage of the resonator being even lower than the POC-

detected voltage). Whether this condition is met or not can be checked by measuring the oscillation status on a

product which actually contains a POC circuit, as follows.

<1> Connect a storage oscilloscope to the X

OUT

pin so that the oscillation status can be measured.

<2> Connect a power supply whose output voltage can be varied and then gradually raise the power supply

voltage V

from 0 V (making sure to avoid V

> 3.6 V).

At first (during V

< 1.7 V (approx.)), the X

OUT

pin is 0 V regardless of the V

. However, at the point that V

reaches the POC-detected voltage (V

POC

= 1.85 V (TYP.)), the voltage of the X

OUT

pin jumps to about 0.5 V

Maintain this power supply voltage for a while to measure the waveform of the X

OUT

pin. If, by any chance, the

oscillation start voltage of the resonator is lower than the POC-detected voltage, the growing oscillation of the X

OUT

pin can be confirmed within several ms after the V

has reached the V

POC

3.6 V

2.0 V

POC

1.7 V (approx.)

0 V

Internal reset signal

Reset

Operating ambient temperature T

= 40 to +85

Clock frequency f

= 2.4 to 8 MHz

POC-detected voltage V

POC

= 1.85 V (TYP.)

Note 3

Operating mode

Reset

Note 2

Note 1

PD62A

Data Sheet U14474EJ1V0DS00

9.3 Mnemonic to/from Machine Language (Assembler Output) Contrast Table

Accumulator Operation Instructions

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

ANL

A, R0n

FBEn

(A)

(Rmn)

m = 0, 1

n = 0 to F

A, R1n

FAEn

· Rmn

A, @R0H

FAF0

(A)

((P13), (R0))

7-4

· ROM

A, @R0L

FBF0

(A)

((P13), (R0))

3-0

· ROM

A, #data4

FBF1

data4

(A)

data4

· data4

ORL

A, R0n

FDEn

(A)

(Rmn)

m = 0, 1

n = 0 to F

A, R1n

FCEn

A, @R0H

FCF0

(A)

((P13), (R0))

7-4

A, @R0L

FDF0

(A)

((P13), (R0))

3-0

A, #data4

FDF1

data4

(A)

data4

XRL

A, R0n

F5En

(A)

(Rmn)

m = 0, 1

n = 0 to F

A, R1n

F4En

· Rmn

A, @R0H

F4F0

(A)

((P13), (R0))

7-4

· ROM

A, @R0L

F5F0

(A)

((P13), (R0))

3-0

· ROM

A, #data4

F5F1

data4

(A)

data4

· data4

INC

F4F3

(A)

(A) + 1

if (A) = 0

else CY

FCF3

n+1

)

), (A

)

RLZ

FEF3

if A = 0

reset

else (A

n+1

)

), (A

)

PD62A

Data Sheet U14474EJ1V0DS00

Input/output Instructions

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

A, P0n

FFF8 + n

(A)

(Pmn)

m = 0, 1

n = 0, 1, 3, 4

A, P1n

FEF8 + n

OUT

P0n, A

E5F8 + n

(Pmn)

(A)

m = 0, 1

n = 0, 1, 3, 4

P1n, A

E4F8 + n

ANL

A, P0n

FBF8 + n

(A)

(Pmn) m = 0, 1 n = 0, 1, 3, 4

A, P1n

FAF8 + n

· Pmn

ORL

A, P0n

FDF8 + n

(A)

(Pmn) m = 0, 1 n = 0, 1, 3, 4

A, P1n

FCF8 + n

XRL

A, P0n

F5F8 + n

(A)

(Pmn) m = 0, 1 n = 0, 1, 3, 4

A, P1n

F4F8 + n

· Pmn

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

OUT

Pn, #data8 E6F8 + n

data8

(Pn)

data8

n = 0, 1, 3, 4

Remark

Pn: P1n to P0n are dealt with in pairs.

Data Transfer Instruction

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

MOV

A, R0n

FFEn

(A)

(Rmn)

m = 0, 1

n = 0 to F

A, R1n

FEEn

A, @R0H

FEF0

(A)

((P13), (R0))

7-4

A, @R0L

FFF0

(A)

((P13), (R0))

3-0

A, #data4

FFF1

data4

(A)

data4

R0n, A

E5En

(Rmn)

(A)

m = 0, 1

n = 0 to F

R1n, A

E4En

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

MOV

Rn, #data8

E6En

data8

(R1n-R0n)

data8

n = 0 to F

Rn, @R0

E7En

(R1n-R0n)

((P13), (R0)) n = 1 to F

Remark

Rn: R1n to R0n are dealt with in pairs.

PD62A

Data Sheet U14474EJ1V0DS00

Branch Instructions

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

JMP

addr (Page 0)

E8F1

addr

addr (Page 1)

E9F1

addr

addr (Page 0)

ECF1

addr

if CY = 1

addr

addr (Page 1)

EAF1

addr

else PC

PC + 2

JNC

addr (Page 0)

EDF1

addr

if CY = 0

addr

addr (Page 1)

EBF1

addr

else PC

PC + 2

addr (Page 0)

EEF1

addr

if F = 1

addr

addr (Page 1)

F0F1

addr

else PC

PC + 2

JNF

addr (Page 0)

EFF1

addr

if F = 0

addr

addr (Page 1)

F1F1

addr

else PC

PC + 2

Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.

Subroutine Instructions

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

CALL

addr (Page 0)

E6F2

E8F1

addr

SP + 1, ASR

PC, PC

addr

addr (Page 1)

E6F2

E9F1

addr

RET

E8F2

ASR, SP

SP 1

Caution 0 and 1, which refer to PAGE0 and 1, are not written when describing mnemonics.

Timer Operation Instructions

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

MOV

A, T0

FFFF

(A)

(Tn)

n = 0, 1

A, T1

FEFF

T0, A

E5FF

(Tn)

(A)

n = 0, 1

T1, A

F4FF

(T) n

Mnemonic

Operand

Instruction Code

Operation

Instruction

1st Word

2nd Word

3rd Word

Length

Cycle

MOV

T, #data10

E6FF

data10

(T)

data10

T, @R0

F4FF

(T)

((P13), (R0))

PD62A

Data Sheet U14474EJ1V0DS00

9.4 Accumulator Operation Instructions

ANL A, R0n

ANL A, R1n

<1> Instruction code:

1 0 1 R

0 R

<2> Cycle count:

<3> Function:

(A)

(Rmn)

m = 0, 1

n = 0 to F

· Rmn

The accumulator contents and the register Rmn contents are ANDed and the results are entered in the

accumulator.

ANL A, @R0H

ANL A, @R0L

<1> Instruction code:

1 1 0 1 0/1 1 0 0 0 0

<2> Cycle count:

<3> Function:

(A)

((P13), (R0))

7-4

(in the case of ANL A, @R0H)

· ROM

(A)

((P13), (R0))

3-0

(in the case of ANL A, @R0L)

· ROM

The accumulator contents and the program memory contents specified with the control register P13 and

-R

are ANDed and the results are entered in the accumulator.

If H is specified, b

, b

, and b

take effect. If L is specified, b

, b

, and b

take effect.

· Program memory (ROM) organization

Valid bits at the time of accumulator operation

ANL A, #data4

<1> Instruction code:

1 1 0 1 1 1 0 0 0 1

0 0 0 0 0 0 d

<2> Cycle count:

<3> Function:

(A)

data4

· data4

The accumulator contents and the immediate data are ANDed and the results are entered in the

accumulator.

PD62A

Data Sheet U14474EJ1V0DS00

ORL A, R0n

ORL A, R1n

<1> Instruction code:

1 1 1 0 R

0 R

<2> Cycle count:

<3> Function:

(A)

(Rmn)

m = 0, 1

n = 0 to F

The accumulator contents and the register Rmn contents are ORed and the results are entered in the

accumulator.

ORL A, @R0H

ORL A, @R0L

<1> Instruction code:

1 1 1 0 0/1 1 0 0 0 0

<2> Cycle count:

<3> Function:

(A)

(P13), (R0))

7-4

(in the case of ORL A, @R0H)

(A)

(P13), (R0))

3-0

(in the case of ORL A, @R0L)

The accumulator contents and the program memory contents specified with the control register P13 and

-R

are ORed and the results are entered in the accumulator.

If H is specified, b

, b

, and b

take effect. If L is specified, b

, b

, and b

take effect.

ORL A, #data4

<1> Instruction code:

1 1 1 0 1 1 0 0 0 1

0 0 0 0 0 0 d

<2> Cycle count:

<3> Function:

(A)

data4

The accumulator contents and the immediate data are exclusive-ORed and the results are entered in

the accumulator.

XRL A, R0n

XRL A, R1n

<1> Instruction code:

1 0 1 0 R

0 R

<2> Cycle count:

<3> Function:

(A)

(Rmn)

m = 0, 1

n = 0 to F

· Rmn

The accumulator contents and the register Rmn contents are ORed and the results are entered in the

accumulator.

PD62A

Data Sheet U14474EJ1V0DS00

XRL A, @R0H

XRL A, @R0L

<1> Instruction code:

1 0 1 0 0/1 1 0 0 0 0

<2> Cycle count:

<3> Function:

(A)

((P13), (R0))

7-4

(in the case of XRL A, @R0H)

· ROM

(A)

((P13), (R0))

3-0

(in the case of XRL A, @R0L)

· ROM

The accumulator contents and the program memory contents specified with the control register P13 and

-R

are exclusive-ORed and the results are entered in the accumulator.

If H is specified, b

, b

, and b

take effect. If L is specified, b

, b

, and b

take effect.

XRL A, #data4

<1> Instruction code:

1 0 1 0 1 1 0 0 0 1

0 0 0 0 0 0 d

<2> Cycle count:

<3> Function:

(A)

data4

· data4

The accumulator contents and the immediate data are exclusive-ORed and the results are entered in

the accumulator.

INC A

<1> Instruction code:

1 0 1 0 0 1 0 0 1 1

<2> Cycle count:

<3> Function:

(A)

(A) + 1

A = 0

else

The accumulator contents are incremented (+1).

RL A

<1> Instruction code:

1 1 1 0 0 1 0 0 1 1

<2> Cycle count:

<3> Function:

n + 1

)

(An), (A

)

The accumulator contents are rotated anticlockwise bit by bit.

RLZ A

<1> Instruction code:

1 1 1 1 0 1 0 0 1 1

<2> Cycle count:

<3> Function:

A = 0

reset

else

n + 1

)

(An), (A

)

The accumulator contents are rotated anticlockwise bit by bit.

If A = 0H at the time of command execution, an internal reset takes effect.

PD62A

Data Sheet U14474EJ1V0DS00

9.5 Input/Output Instructions

IN A, P0n

IN A, P1n

<1> Instruction code:

1 1 1 1 P

1 1 P

<2> Cycle count:

<3> Function:

(A)

(Pmn)

m = 0, 1

n = 0, 1, 3, 4

The port Pmn data is loaded (read) onto the accumulator.

OUT P0n, A

OUT P1n, A

<1> Instruction code:

0 0 1 0 P

1 1 P

<2> Cycle count:

<3> Function:

(Pmn)

(A)

m = 0, 1

n = 0, 1, 3, 4

The accumulator contents are transferred to port Pmn to be latched.

ANL A, P0n

ANL A, P1n

<1> Instruction code:

1 1 0 1 P

1 1 P

<2> Cycle count:

<3> Function:

(A)

(Pmn)

m = 0, 1

n = 0, 1, 3, 4

· Pmn

The accumulator contents and the port Pmn contents are ANDed and the results are entered in the

accumulator.

ORL A, P0n

ORL A, P1n

<1> Instruction code:

1 1 1 0 P

1 1 P

<2> Cycle count:

<3> Function:

(A)

(Pmn)

m = 0, 1

n = 0, 1, 3, 4

The accumulator contents and the port Pmn contents are ORed and the results are entered in the

accumulator.

XRL A, P0n

XRL A, P1n

<1> Instruction code:

1 0 1 0 P

1 1 P

<2> Cycle count:

<3> Function:

(A)

(Pmn)

m = 0, 1

n = 0, 1, 3, 4

· Pmn

The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered

in the accumulator.

PD62A

Data Sheet U14474EJ1V0DS00

OUT Pn, #data8

<1> Instruction code:

0 0 1 1 0 1 1 P

0 d

<2> Cycle count:

<3> Function:

(Pn)

data8

n = 0, 1, 3, 4

The immediate data is transferred to port Pn. In this case, port Pn refers to P

-P

operating in pairs.

9.6 Data Transfer Instruction

MOV A, R0n

MOV A, R1n

<1> Instruction code:

1 1 1 1 R

0 R

<2> Cycle count:

<3> Function:

(A)

(Rmn)

m = 0, 1

n = 0 to F

The register Rmn contents are transferred to the accumulator.

MOV A, @R0H

<1> Instruction code:

1 1 1 1 0 1 0 0 0 0

<2> Cycle count:

<3> Function:

(A)

((P13), (R0))

7-4

The high-order 4 bits (b

) of the program memory specified with control register P13 and register

pair R

-R

are transferred to the accumulator. b

is ignored.

MOV A, @R0L

<1> Instruction code:

1 1 1 1 1 1 0 0 0 0

<2> Cycle count:

<3> Function:

(A)

((P13), (R0))

3-0

The low-order 4 bits (b

) of the program memory specified with control register P13 and register

pair R

-R

are transferred to the accumulator. b

is ignored.

· Program memory (ROM) contents

MOV A, #data4

<1> Instruction code:

1 1 1 1 1 1 0 0 0 1

0 0 0 0 0 0 d

<2> Cycle count:

<3> Function:

(A)

data4

The immediate data is transferred to the accumulator.

PD62A

Data Sheet U14474EJ1V0DS00

MOV R0n, A

MOV R1n, A

<1> Instruction code:

0 0 1 0 R

0 R

<2> Cycle count:

<3> Function:

(Rmn)

(A)

m = 0, 1

n = 0 to F

The accumulator contents are transferred to register Rmn.

MOV Rn, #data8

<1> Instruction code:

0 0 1 1 0 0 R

0 d

<2> Cycle count:

<3> Function:

(R1n-R0n)

data8

n = 0 to F

The immediate data is transferred to the register. Using this instruction, registers operate as register

pairs.

The pair combinations are as follows:

: R

- R

: R

- R

: R

- R

: R

- R

Lower column

Higher column

MOV Rn, @R0

<1> Instruction code:

0 0 1 1 1 0 R

<2> Cycle count:

<3> Function:

(R1n-R0n)

((P13), R0))

n = 1 to F

The program memory contents specified with control register P13 and register pair R

-R

are

transferred to register pair R1n-R0n. The program memory consists of 10 bits and has the following

state after the transfer to the register.

@R0

R1n

R0n

Program memory

The high-order 2 bits of the program memory address is specified with the control register (P13).

PD62A

Data Sheet U14474EJ1V0DS00

9.7 Branch Instructions

The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically

performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as

follows.

PD62A (ROM: 0.5 K steps):

page 0

PD6P4B (PROM: 1 K steps) :

page 0

JMP addr

<1> Instruction code: page 0

0 1 0 0 0 1 0 0 0 1

; page 1

0 1 0 0 1 1 0 0 0 1

<2> Cycle count:

<3> Function:

addr

The 10 bits (PC

9-0

) of the program counter are replaced directly by the specified address addr (a

JC addr

<1> Instruction code: page 0

0 1 1 0 0 1 0 0 0 1

; page 1

0 1 0 1 0 1 0 0 0 1

<2> Cycle count:

<3> Function:

CY = 1

addr

else

PC + 2

If the carry flag CY is set (to 1), a jump is made to the address specified with addr (a

to a

JNC addr

<1> Instruction code: page 0

0 1 1 0 1 1 0 0 0 1

; page 1

0 1 0 1 1 1 0 0 0 1

<2> Cycle count:

<3> Function:

CY = 0

addr

else

PC + 2

If the carry flag CY is cleared (to 0), a jump is made to the address specified with addr (a

to a

JF addr

<1> Instruction code: page 0

0 1 1 1 0 1 0 0 0 1

; page 1

1 0 0 0 0 1 0 0 0 1

<2> Cycle count:

<3> Function:

F = 1

addr

else

PC + 2

If the status flag F is set (to 1), a jump is made to the address specified with addr (a

to a

JNF addr

<1> Instruction code: page 0

0 1 1 1 1 1 0 0 0 1

; page 1

1 0 0 0 1 1 0 0 0 1

<2> Cycle count:

<3> Function:

F = 0

addr

else

PC + 2

If the status flag F is cleared (to 0), a jump is made to the address specified with addr (a

to a

PD62A

Data Sheet U14474EJ1V0DS00

9.8 Subroutine Instructions

The program memory consists of pages in steps of 1K (000H to 3FFH). However, as the assembler automatically

performs page optimization, it is unnecessary to designate pages. The pages allowed for each product are as

follows.

PD62A (ROM: 0.5 K steps):

page 0

PD6P4B (PROM: 1 K steps): page 0

CALL addr

<1> Instruction code:

0 0 1 1 0 1 0 0 1 0

page 0

0 1 0 0 0 1 0 0 0 1

; page 1

0 1 0 0 1 1 0 0 0 1

<2> Cycle count:

<3> Function:

SP + 1

ASR

addr

The stack pointer value is incremented (+1) and the program counter value is saved in the address stack

to a

) is entered in the program counter.

If a carry is generated when the stack pointer value is incremented (+1), an internal reset takes effect.

RET

<1> Instruction code:

0 1 0 0 0 1 0 0 1 0

<2> Cycle count:

<3> Function:

ASR

SP 1

The value saved in the address stack register is restored to the program counter. Then, the stack

pointer is decremented (1) .

If a borrow is generated when the stack pointer value is decremented (1), an internal reset takes effect.

PD62A

Data Sheet U14474EJ1V0DS00

9.9 Timer Operation Instructions

MOV A, T0

MOV A, T1

<1> Instruction code:

1 1 1 1 0/1 1 1 1 1 1

<2> Cycle count:

<3> Function:

(A)

(Tn)

n = 0, 1

The timer Tn contents are transferred to the accumulator. T1 corresponds to (t

, t

); T0 corresponds

to (t

, t

Can be set with

MOV T, #data10
MOV T, @R0

MOV T0, A

MOV T1, A

<1> Instruction code:

0 0 1 0 0/1 1 1 1 1 1

<2> Cycle count:

<3> Function:

(Tn)

(A)

n = 0, 1

The accumulator contents are transferred to the timer register Tn. T1 corresponds to (t

, t

); T0

corresponds to (t

, t

). After executing this instruction, if data is transferred to T1, t

becomes

0; if data is transferred to T0, t

becomes 0.

MOV T, #data10

<1> Instruction code:

0 0 1 1 0 1 1 1 1 1

<2> Cycle count:

<3> Function:

(T)

data10

The immediate data is transferred to the timer register T (t

-t

Remark The timer time is set with (set value + 1)

64/f

or 128/f

PD62A

Data Sheet U14474EJ1V0DS00

MOV T, @R0

<1> Instruction code:

0 0 1 1 1 1 1 1 1 1

<2> Cycle count:

<3> Function:

(T)

((P13), (R0))

The program memory contents are transferred to the timer register T (t

to t

) specified with the control

-R

The program memory, which consists of 10 bits, is placed in the following state after being transferred

to the register.

Program memory

Timer

The high-order 2 bits of the program memory address are specified with the control register (P13).

Caution When setting a timer value in the program memory, be sure to use the DT directive.

9.10 Others

HALT #data4

<1> Instruction code:

0 0 0 1 0 1 0 0 0 1

0 0 0 0 0 0 d

<2> Cycle count:

<3> Function:

Standby mode

Places the CPU in standby mode.

The condition for having the standby mode (HALT/STOP mode) canceled is specified with the immediate

data.

STTS R0n

<1> Instruction code:

0 0 0 1 1 0 R

<2> Cycle count:

<3> Function:

If statuses match

else

n = 0 to F

The S

, S

, K

I/O

, K

, and TIMER statuses are compared with the register R

contents. If at least one

of the statuses coincides with the bits that have been set, the status flag F is set (to 1).

If none of them coincide, the status flag F is cleared (to 0).

PD62A

Data Sheet U14474EJ1V0DS00

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= +25°C)

Parameter

Symbol

Conditions

Rating

Unit

Power supply voltage

0.3 to +3.8

Input voltage

I/O

, K

, S

, RESET

0.3 to V

+0.3

Output voltage

0.3 to V

+0.3

Output current, high

Note

REM

Peak value

rms

LED

Peak value

7.5

rms

One K

I/O

Peak value

13.5

rms

Total of LED and K

I/O

pins

Peak value

rms

Output current, low

Note

REM

Peak value

7.5

rms

LED

Peak value

7.5

rms

Operating ambient

40 to +85

°C

temperature

Storage temperature

stg

65 to +150

°C

Note The rms value should be calculated as follows: [rms value] = [Peak value]

Duty.

Caution Product quality may suffer if the absolute rating is exceeded even momentarily for any

parameter. That is, the absolute maxumum ratings are rated values at which the product is on

the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure the absolute maximum ratings are not exceeded.

Recommended Power Supply Voltage Range (T

= 40 to +85°C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power supply voltage

= 2.4 to 8 MHz

2.0

3.0

3.6

PD62A

Data Sheet U14474EJ1V0DS00

DC Characteristics (T

= 40 to +85°C, V

= 2.0 to 3.6 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, high

IH1

RESET

0.8 V

IH2

I/O

0.7 V

IH3

, S

0.65 V

Input voltage, low

IL1

RESET

0.2 V

IL2

I/O

0.3 V

IL3

, S

0.15 V

Input leakage current,

LIH1

high

= V

, pull-down resistor not incorporated

LIH2

, S

= V

, pull-down resistor not incorporated

Input leakage current,

LIL1

= 0 V

low

LIL2

I/O

= 0 V

LIL3

, S

= 0 V

Output voltage, high

OH1

REM, LED, K

I/O

= 0.3 mA

0.8 V

Output voltage, low

OL1

REM, LED

= 0.3 mA

0.3

OL2

I/O

= 15

0.4

Output current, high

OH1

REM

= 3.0 V, V

= 1.0 V

OH2

I/O

= 3.0 V, V

= 2.2 V

2.5

Output current, low

OL1

I/O

= 3.0 V, V

= 0.4 V

= 3.0 V, V

= 2.2 V

100

390

On-chip pull-up resistor

RESET

100

On-chip pull-down

RESET

2.5

resistor

, S

150

300

I/O

130

250

500

Data retention power

DDDR

In STOP mode

0.9

3.6

supply voltage

Supply current

Note

DD1

Operating

= 8.0 MHz, V

= 3 V

10%

0.8

1.6

mode

= 4.0 MHz, V

= 3 V

10%

0.7

1.4

DD2

HALT mode

= 8.0 MHz, V

= 3 V

10%

0.75

1.5

= 4.0 MHz, V

= 3 V

10%

0.65

1.3

DD3

STOP mode

= 3 V

10%, When POC circuit

1.9

9.0

incorporated by mask option

= 3 V

10%, T

= 25°C,

1.9

5.0

When POC circuit incorporated

by mask option

Note The current flowing to the on-chip pull-up resistors is not included.

PD62A

Data Sheet U14474EJ1V0DS00

AC Characteristics (T

= 40 to +85°C, V

= 2.0 to 3.6 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Instruction execution time t

7.9

, S

high-level width

When releasing

In HALT mode

standby mode

In STOP mode

Note

RESET low-level width

RSL

Note 10 + 52/f

+ oscillation growth time

Remark t

= 64/f

: System clock oscillation frequency)

POC Circuit (mask option

Note 1

) (T

= 40 to +85°C)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

POC-detected voltage

Note 2

POC

1.85

2.0

Notes 1. Operates effectively under the conditions of f

= 2.4 to 8 MHz.

2. Refers to the voltage at which the POC circuit cancels an internal reset. If V

POC

< V

, the internal

reset is released.

From the time of V

POC

until the internal reset takes effect, a delay of up to 1 ms occurs. When

the period of V

POC

lasts less than 1 ms, the internal reset may not take effect.

System Clock Oscillator Characteristics (T

= 40 to +85°C, V

= 2.0 to 3.6 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Oscillation frequency

2.4

3.64

8.0

MHz

(ceramic resonator)

PD62A

Data Sheet U14474EJ1V0DS00

12. CHARACTERISTICS CURVES (REFERENCE VALUES)

r supply current I

[mA]

Power supply voltage V

[V]

vs V

(fx = 4 MHz)

= 25

1.5

2.5

3.6

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Operating mode

HALT mode

1.5

2.5

3.6

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

r supply current I

[mA]

Power supply voltage V

[V]

vs V

(fx = 8 MHz)

= 25

Operating mode

HALT mode

w-le

l output current I

[mA]

Low-level output voltage V

[V]

vs V

(REM, LED)

= 25

C, V

= 3.0 V)

High-le

l output current I

[mA]

High-level output voltage V

[V]

vs V

(REM, LED, K

I/O

)

= 25

C, V

= 3.0 V)

500

450

400

350

300

250

200

150

100

w-le

l output current I

[ A]

Low-level output voltage V

[V]

vs V

I/O

)

= 25

C, V

= 3.0 V)

PD62A

Data Sheet U14474EJ1V0DS00

15. RECOMMENDED SOLDERING CONDITIONS

The

PD62A should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales representa-

tives.

Table 15-1. Surface Mounting Type Soldering Conditions

PD62AMC-

×××

-5A4: 20-pin plastic SSOP (300 mils)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C; Time: 30 seconds max. (at 210

C or higher);

IR35-00-3

Count: three times or less

VPS

Package peak temperature: 215

C; Time: 40 seconds. max. (at 200

C or higher);

VP15-00-3

Count: Three times or less

Wave soldering

Solder bath temperature: 260

C max.; Time: 10 seconds max.; Count: once;

WS60-00-1

Preheating temperature: 120

C max. (package surface temperature)

Partial heating

Pin temperature: 300

C or less; Time: 3 seconds max. (per pin row)

Caution Do not use different soldering methods together (except for partial heating).

PD62A

Data Sheet U14474EJ1V0DS00

Item

PD62A

PD63A

PD64

PD6134

PD6600A

ROM capacity

512

10 bits

768

10 bits

1002

10 bits 1002

10 bits

512

10 bits

RAM capacity

4 bits

5 bits

Stack

1 level (also used as RF of RAM)

3 levels
(also used for RAM)

Key matrix

6 = 48 keys

4 = 32 keys

(S-IN) input

Read by P

Read by left shift
instruction

/LED (S-OUT)

I/O (standby release function available)

Output

Clock frequency

Ceramic oscillation

· f

= 2.4 to

· f

= 2.4 to 8 MHz

· f

= 300 kHz to 1 MHz · f

= 400 to 500 kHz

8 MHz

· f

= 2.4 to 4 MHz

· f

= 300 to 500 kHz

(with POC circuit)

Timer

Clock

/64, f

/128

/8, f

/16

Count start

Writing count value

Writing count value
and P1 register value

Carrier

Frequency

· f

/8, f

/64, f

/96 (timer clock: f

/64)

· f

, f

/8, f

/12

· f

/8, f

/12

· f

/16, f

/128, f

/192 (timer clock: f

/128)

(timer clock: f

/8)

· No carrier

· f

/2, f

/16, f

/24

(timer clock: f

/16)

· No carrier

Output start

Synchronized with timer

Asynchronized
with timer

Instruction execution time

s (f

= 8 MHz)

s (f

= 1 MHz)

s (f

= 500 kHz)

Relative branch instruction

None

Provided

Left shift instruction

None

Provided

"MOV Rn, @RO" instruction

n = 1 to F

n = 0 to F

Standby mode

HALT mode for timer only.

HALT/STOP mode

(HALT instruction)

STOP mode for only releasing K

set by P1 register

I/O

high-level output or K

I/O0

high-level output)

value

Relationship between HALT

HALT instruction not executed when F = 1

HALT instruction

instruction execution and

executed regardless

status flag (F)

of status of F

Reset function by charging/

None

Provided

discharging capacitor

POC circuit

Mask option

Provided (low-voltage

Low level output to RESET pin on detection

detection circuit)
Low level output to
S-OUT pin on detection

Mask option

POC circuit only (set by software in circuits other than POC circuit)

· Pull-down resistor
· Variable duty
· Runaway detection

Supply voltage

= 2.0 to 3.6 V V

= 1.8 to 3.6 V

= 2.2 to 3.6 V

Operating temperature

· T

= 40 to

· T

= 40 to +85

= 20 to +70

+85

· T

= 20 to +70

C (with POC circuit)

Package

· 20-pin plastic · 20-pin plastic · 20-pin plastic SOP

· 20-pin plastic SOP

SSOP

SOP

· 20-pin plastic SSOP

· 20-pin plastic shrink
DIP

One-time PROM model

PD6P4B

PD61P34B

PD61P24

APPENDIX B. FUNCTIONAL COMPARISON BETWEEN

PD62A AND OTHER SUBSERIES

PD62A

Data Sheet U14474EJ1V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and trans-

ported in an anti-static container, static shielding bag or conductive material. All test and

measurement tools including work bench and floor should be grounded. The operator should be

grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar

precautions need to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input

levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered to have a

possibility of being an output pin. All handling related to the unused pins must be judged device

by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until

the reset signal is received. Reset operation must be executed immediately after power-on for

devices having reset function.

PD62A

Data Sheet U14474EJ1V0DS00

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J99.1

PD62A

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States

and/or other countries.

PC/AT and PC DOS are trademarks of International Business Machines Corporation.

M7 98.8

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD62AMC

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD62AMC