Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- 1. PIN FUNCTIONS
- 2. INPUT SIGNAL FORMAT
- 2.1 Supplying Clock to CLK even outside Sample Data Interval
- 2.1.1 Serial data input (Pin 1 is Low or Open)
- 2.2 Supplying Clock to CLK only during Sample Data Interval
- 2.2.1 Inputting serial data (Pin 1 Low or Open)
- 2.2.2 Inputting parallel data (Pin 1 High)
- 3. USAGE CAUTIONS
- 4. ELECTRICAL CHARACTERISTICS
- 5. APPLICATION CIRCUIT EXAMPLE
- 6. MEASURING CIRCUIT EXAMPLE
- 7. PACKAGE DRAWINGS
- 8. RECOMMENDED SOLDERING CONDITIONS
DATA SHEET
MOS INTEGRATED CIRCUIT
PD6376
AUDIO 2-CHANNEL 16-BIT D/A CONVERTER
The
PD6376 is an audio 2-channel 16-bit D/A converter.
The
PD6376 has low sound quality deterioration by employing the resistor string configuration and 0-point offset,
and low power consumption by using the CMOS process. It operates on a single 5-V power supply, and it is pin-
compatible with the
PD6372 when Pin 1 is low level or open.
FEATURES
Single 5-V power supply
CMOS structure
On-chip output operational amplifier circuit
On-chip 0-point offset circuit
Resistor string configuration
8 f
S
(2 ch
400 kHz) supported
On-chip 2-channel DAC
L-R in-phase output
ORDERING INFORMATION
Part Number Package
PD6376GS 16-pin plastic SOP (300 mil)
The information in this document is subject to change without notice.
The mark
shows major revised points.
Document No. S12799EJ5V0DS00 (5th edition)
(Previous No. IC-2531)
Date Published December 1997 N
Printed in Japan
1991
PD6376
2
BLOCK DIAGRAM
13
14
15
16
1
2
3
4
5
12
7
8
9
6
11
10
LRCK/WDCK
LRSEL/RSI
SI/LSI
CLK
D.GND
NC
A.GND
R.REF
R.OUT
L.OUT
L.REF
Analog power supply block
Digital power supply block
MAIN DAC
MAIN DAC
SUB DAC
SHIFT REGISTER
LATCH
TIMING
GENERATOR
SUB DAC
D.V
DD
A.V
DD
4/8 f
S
SEL
PD6376
3
PIN CONFIGURATION (Top View)
16-Pin Plastic SOP (300 mil)
1
2
3
4
5
6
7
8
CLK
SI/LSI
LRSEL/RSI
LRCK/WDCK
A.GND
L.OUT
L.REF
R.REF
16
15
14
13
12
11
10
9
4/8 f
S
SEL
D.GND
NC
D.V
DD
A.GND
R.OUT
A.V
DD
A.V
DD
PD6376
4
1. PIN FUNCTIONS
Pin No.
Symbol
Name
I/O
Function
1
4/8 f
S
SEL
Input
When this pin is Low or leaves Open, L-ch data and R-ch
data is input in time-division from Pin 15.
When this pin is High, L-ch data is input from Pin 15, and
R-ch data is input from Pin 14.
(Pulled down in IC with 100-k
resistor)
2
D.GND
Digital GND
GND pin of logic block
3
NC
Non Connection
Not connected to internal chip
4
D.V
DD
Digital V
DD
Power supply pin to logic block
5
A.GND
Analog GND
GND pin to analog block
6
R.OUT
R-ch OUTPUT
Output
Right analog signal output pin
7
A.V
DD
Analog V
DD
Power supply pin to analog block
8
A.V
DD
Analog V
DD
9
R.REF
R-ch Voltage Reference
Reference voltage pin. Normally connected to A. GND
10
L.REF
L-ch Voltage Reference
through via capacitor to lower impedance
11
L.OUT
L-ch OUTPUT
Output
Left analog signal output pin
12
A.GND
Analog GND
GND pin of analog block
13
LRCK/WDCK
Left/Right Clock
Input
When Pin 1 is Low or leaves Open:
WORD Clock
Functions as L-R judgment signal input pin.
When Pin 1 is High:
Functions as input data word judgment signal input pin.
14
LRSEL/RSI
Left/Right Selection
Input
When Pin 1 is Low or leaves Open:
R-ch Series Input
Functions as pin to select L-R polarity for LRCK signal.
When LRCK signal is High, set LRSEL pin to Low to input
L-ch data; When LRCK signal is LOW, set LRSEL pin to
High to input L-ch data.
When Pin 1 is High:
Functions as R-ch serial data input pin.
15
SI/LSI
Series Input
Input
When Pin 1 is Low or Open:
L-ch Series Input
Functions as L-ch and R-ch serial data input pin
alternately.
When Pin 1 is High:
Functions as L-ch serial data input pin.
16
CLK
CLOCK
Input
Input pin for read clock of serial input data
PD6376
5
2. INPUT SIGNAL FORMAT
Input data must be input as 2's complement, MSB first.
2's complement is a method of expressing both positive numbers and negative numbers as binary numbers. See
the table below.
2's Complement
Decimal Number
L.OUT, R.OUT Pin Voltage TYP. (V)
(MSB)
(LSB)
(Reference Values)
Note
0111
1111
1111
1111
+32767
2.6
0111
1111
1111
1110
+32766
0000
0000
0000
0001
+1
0000
0000
0000
0000
0
1.6
1111
1111
1111
1111
1
1000
0000
0000
0001
32767
1000
0000
0000
0000
32768
0.6
Note When A.V
DD
= 5.0 V
Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature.
Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of
CLK.
CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same
as 1 clock cycle.
PD6376
6
2.1 Supplying Clock to CLK even outside Sample Data Interval
2.1.1 Serial data input (Pin 1 is Low or Open)
Synchronize the reverse timing of LRCK with the falling edge of CLK upon completion of LSB input (Point A in Figure
2-1).
Figure 2-1 Timing Chart for Serial Data Input
A
A
Interval of 1 sample data
LSB
CLK
SI
LRCK
16
1
2
3
4
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
MSB
2.1.2. Inputting parallel data (Pin 1 is High)
Synchronize the timing of the falling edge of WDCK with the falling edge of CLK upon completion of LSB input of
data (LSI, RSI) (Point A in Figure 2-2.).
Figure 2-2 Parallel Data Input Timing Chart
A
A
LSB
CLK
LSI
RSI
WDCK
16
1
2
3
4
1
2
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
MSB
LSB
16
1
2
3
4
1
2
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
MSB
PD6376
7
2.2 Supplying Clock to CLK only during Sample Data Interval
The analog outputs of the L.OUT and R.OUT pins are updated after the input of 4.5 clocks following data input.
(See 4. ELECTRICAL CHARACTERISTICS, Timing Charts 1 and 2.)
2.2.1 Inputting serial data (Pin 1 Low or Open)
Place the LRCK reverse timing between the falling edge of CLK at LSB input completion (Point A in Figure 2-3)
and the next MSB input start time (Point B in Figure 2-3) (so as to include Points A and B).
Figure 2-3 Timing Chart of Serial Data Input
A
A
B
B
1-sample data interval
LRCK reverse interval
LRCK reverse interval
LSB
CLK
SI
LRCK
16
1
2
3
4
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
MSB
2.2.2 Inputting parallel data (Pin 1 High)
Place the WDCK falling edge timing between the falling edge of CLK at LSB input completion (Point A in Figure
2-4) and the next MSB input start time (Point B in Figure 2-4) (so as to include Points A and B).
Place the WDCK rising edge timing between the third falling edge of CLK from MSB input completion (Point C in
Figure 2-4) and the falling edge of CLK upon LSB input start (Point D in Figure 2-4) (so as to include Points C and
D).
Figure 2-4 Timing Chart of Parallel Data Input
A
A
B
B
C
D
WDCK falling
edge interval
WDCK falling
edge interval
WDCK rising edge interval
LSB
CLK
LSI
RSI
WDCK
16
1
2
3
4
1
2
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
MSB
LSB
16
1
2
3
4
1
2
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
MSB
PD6376
8
3. USAGE CAUTIONS
Insertion of a muting circuit in the next stage after the
PD6376 is recommended.
If no muting circuit is inserted in the next stage, shock noise may be generated when power is applied.
PD6376
9
4. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (T
A
= 25
C)
Parameter
Symbol
Rating
Unit
Supply voltage
V
DD
0.3 to +7.0
V
Output pin voltage
V
OUT
0.3 to V
DD
+0.3
V
Logic input voltage
V
IN
0.3 to V
DD
+0.3
V
Operating ambient temperature
T
A
20 to +75
C
Storage temperature
T
stg
40 to +125
C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the device
reliability may be impaired. The absolute maximum ratings are values that may physically
damage the product. Be sure to use the product within the ratings.
Recommended Operating Range
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Supply voltage
V
DD
4.5
5.0
5.5
V
Logic input voltage (High)
V
IH
0.7V
DD
V
DD
V
Logic input voltage (Low)
V
IL
0
0.3V
DD
V
Operating temperature range
T
A
20
+25
+75
C
Output load resistance
R
L
R.OUT or L.OUT pin
5
k
Conversion frequency
f
S
400
kHz
Clock frequency
f
CLK
10
MHz
Clock pulse width
f
SCK
40
ns
SI, LRCK set time
t
DC
12
ns
SI, LRCK hold time
t
CD
12
ns
Electrical Characteristics (T
A
= 25
C, V
DD
= +5 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Resolution
RES
16
Bit
Total harmonic distortion 1
THD
1
f
IN
= 1 kHz, 0 dB
0.04
0.09
%
Total harmonic distortion 2
THD
2
f
IN
= 1 kHz, 20 dB
0.1
0.3
%
Full-scale output voltage
V
FS
2.0
2.3
V
p-p
Cross talk
C.T
0 dB per channel, f
IN
= 1 kHz
85
95
dB
S/N ratio
S/N
JIS-A
96
dB
Dynamic range
D.R
f
IN
= 1 kHz, 60 dB
92
dB
Circuit current
I
DD
f
IN
= 1 kHz, 0 dB
6.0
12
mA
PD6376
10
TIMING CHART 1
When Pin 1 is Low or Open (serial input)
4.5 clocks
LSB
CLK
SI
LRCK
LRCK
L.OUT
R.OUT
16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
N
Note
N
1
2
3
4
5
6
7
8
9 10 11
MSB
(R-ch)
(R-ch)
(L-ch)
(L-ch)
N 1
N 1
Analog output update
Note When the LRCK signal is High, set the LRSEL pin to Low to input L-ch data. When the LRCK signal is Low, set the LRSEL pin to High to input L-ch data.
t
SCK
t
SCK
CLK
SI
t
CD
t
DC
CLK
LRCK
t
DC
t
CD
PD6376
11
TIMING CHART 2
When Pin 1 is High (parallel input)
t
SCK
t
SCK
CLK
SI
t
CD
t
DC
CLK
WDCK
t
DC
t
CD
4.5 clocks
LSB
CLK
LSI
RSI
WDCK
L.OUT
R.OUT
16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
N
1
2
3
4
5
6
7
8
9 10 11
MSB
N1
N
LSB
16
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MSB
LSB
N
N + 1
1
2
3
4
5
6
7
8
9 10 11
MSB
N1
N
Analog output update
PD6376
12
Typical Characteristics (T
A
= 25
C)
Note 20 kHz low-pass filter: 298BLR-010N (Toko) used
THD vs. Frequency Characteristics
THD vs. V
DD
Characteristics
1.0
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
0.1
0.2 0.3 0.5
1
Frequency f (kHz)
(20 dB)
Note
f
S
= 88.2 kHz
V
DD
= 5.0 V
Note
f
S
= 88.2 kHz
f
IN
= 1 kHz, 0 dB
(Full Scale)
THD (%)
2 3
5
10
20
Voltage Gain vs. Frequency Characteristics
0
5
10
0.1
0.2 0.3 0.5
1
Frequency f (kHz)
Note f
S
= 88.2 kHz
V
DD
= 5.0 V
Voltage Gain (dB)
2 3
5
10
20
THD vs. R
L
Characteristics
10
1.0
0.1
0.01
100
1 k
10 k
100 k
Load Resistance R
L
(
)
Note
f
S
= 88.2 kHz
f
IN
= 1 kHz, 0 dB
V
DD
= 5.0 V
THD (%)
1 M
1.0
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
0
3.0
4.0
5.0
6.0
7.0
V
DD
(V)
THD (%)
THD vs. V
OUT
Characteristics
Note
f
S
= 88.2 kHz
f
IN
= 1 kHz
V
DD
= 5.0 V
10.0
5.0
3.0
2.0
1.0
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
60
50
40
30
20
10
0
V
OUT
(dB)
THD (%)
PD6376
13
5. APPLICATION CIRCUIT EXAMPLE
(1) f
S
to 4 f
S
mode (L/R data serial input mode)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16 15 14 13 12 11 10
9
384 f
S
LRCK
SI
CLK
+5 V
+5 V
+5 V
+5 V
+5 V
+5 V
+10 V
+10 V
OP Amp.
OP Amp.
Note
+5 V
+
+
+
+
+
+
+
0.1 F
0.1 F
47 F
47 F
10 F
1/2
2/2
22 F
22 F
L-ch
OUT
R-ch
OUT
100 k
100 k
100 k
100 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
+
10 F
1000 pF
1000 pF
1000 pF
1000 pF
NPC
SM5807
PD6376GS
Note Assuming secondary active LPF (Gain: K = 2, quality factor: Q = 1, cutoff frequency: f
C
.
=. 30 kHz)
oversampling, the attenuation characteristics are moderate. If oversampling is not performed, use
a high-order filter.
Remark Operational amplifier (OP Amp.):
PC4558
(2) 8 f
S
mode (L/R data parallel input mode)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
384 f
S
LRCK
SI
CLK
+5 V
+5 V
+5 V
+5 V
+10 V
+10 V
Note
+5 V
+5 V
+
+
+
+
+
+
+
0.1 F
0.1 F
47 F 47 F
10 F
22 F
22 F
L-ch
OUT
R-ch
OUT
100 k
100 k
100 k
100 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
5.6 k
+
10 F
1000 pF
1000 pF
1000 pF
1000 pF
NPC
SM5813
9
16 15 14 13 12 11 10
1
2
3
4
5
6
7
8
PD6376GS
OP Amp.
1/2
OP Amp.
2/2
Note Secondary active LPF (K = 2, Q = 1, f
C
.
=. 30 kHz)
Remark Operational amplifier (OP Amp.):
PC4558
PD6376
14
6. MEASURING CIRCUIT EXAMPLE
+5 V
+
+
+
47 F
47 F
47 F
100 F
100 F
100 F
0.1 F
0.1 F
+
+
+
+
2/2
OP Amp.
2/2
5.6 k
5.6 k
5.6 k
3.6 k
3.6 k
5.6 k
V
DD
PD6376
Sampling frequency f
S
= 88.2 kHz
3.6 k
3.6 k
100 k
200
L
R
100 F
+
100 k
200
+
Anritsu
MG22A
LRCK
9
8
7
6
5
4
3
2
1
10
11
12
13
14
15
16
SI
CLK
LPF
LPF
V
REF
298BLR-010N (TOKO)
298BLR-010N (TOKO)
(+2.5 V)
h.p.
339 A
(30 kHz
LPF ON)
OP Amp.
1/2
PD6376
15
7. PACKAGE DRAWINGS
16 PIN PLASTIC SOP (300 mil)
ITEM
MILLIMETERS
INCHES
A
B
C
E
F
G
H
I
J
10.46 MAX.
1.27 (T.P.)
1.8 MAX.
1.55
7.70.3
0.78 MAX.
0.12
1.1
5.6
M
0.10.1
N
0.412 MAX.
0.031 MAX.
0.0040.004
0.071 MAX.
0.061
0.3030.012
0.220
0.043
0.005
0.050 (T.P.)
P16GM-50-300B-4
P
3
3
+7
NOTE
Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
D
0.40
0.016
+0.10
0.05
K
0.20
0.008
+0.10
0.05
L
0.60.2
0.024
0.10
3
+7
3
0.004
+0.008
0.009
+0.004
0.002
+0.004
0.003
A
C
D
G
P
detail of lead end
F
E
B
H
I
L
K
M
M
1
8
9
16
J
N
PD6376
16
8. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when performing soldering for the
PD6376.
For more detailed information, refer to the information document Semiconductor Device Mounting Technology
Manual (C10535E).
For soldering methods and conditions other than the recommended conditions, please consult with an NEC sales
representative.
Surface Mount Type Soldering Conditions
PD6376GS: 16-pin Plastic SOP (300 mil)
Soldering Process
Soldering Conditions
Symbol
Infrared reflow
Peak package temperature: 230
C, Time: 30 seconds max. (at 210
C or higher),
IR30-00-1
Count: Once
VPS
Peak package temperature: 215
C, Time: 40 seconds max. (at 200
C or higher),
VP-15-00-1
Count: Once
Pin Partial heating
Pin temperature: 300
C or less, Time: 3 seconds max. (per pin row)
Caution Do not use different soldering methods together (except for pin partial heating).
PD6376
17
[MEMO]
PD6376
18
[MEMO]
PD6376
19
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
2
PD6376
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
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