Document Outline

COVER
FEATURES
APPLICATIONS
ORDERING INFORMATION
PIN CONFIGURATION
PIN NAMES
INTERNAL BLOCK DIAGRAM
1. DIFFERENCES AMONG PRODUCTS
2. PIN FUNCTIONS
- 2.1 Port Pins
- 2.2 Non-port Pins
- 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
3. FUNCTION BLOCKS
- 3.1 Internal Units
  - 3.1.1 CPU
  - 3.1.2 Bus control unit (BCU)
  - 3.1.3 ROM
  - 3.1.4 RAM
  - 3.1.5 Ports
  - 3.1.6 Interrupt controller (INTC)
  - 3.1.7 Clock generator (CG)
  - 3.1.8 Real-time pulse unit (RPU)
  - 3.1.9 Serial interface (SIO)
  - 3.1.10 Pulse width modulation (PWM)
  - 3.1.11 A/D converter (ADC)
  - 3.1.12 D/A converter (DAC)
4. CPU FUNCTIONS
5. BUS CONTROL FUNCTIONS
6. INTERRUPT/EXCEPTION HANDLING FUNCTION
7. CLOCK GENERATION FUNCTION
8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
9. SERIAL INTERFACE FUNCTIONS (SIO)
- 9.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
- 9.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
- 9.3 Baud Rate Generators 0 to 2 (BRG0 to BRG2)
10. PWM UNIT
11. A/D CONVERTER
12. D/A CONVERTER
13. PORT FUNCTIONS
14. RESET FUNCTION
15. INSTRUCTION SET
16. ELECTRICAL SPECIFICATIONS
17. PACKAGE DRAWINGS
18. RECOMMENDED SOLDERING CONDITIONS

1998

DATA SHEET

PD703003A, 703004A, 703025A

MOS INTEGRATED CIRCUIT

The

PD703003A, 703004A, 703025A are members of the V850 Family

of 32-bit single-chip microcontrollers

designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU

core, ROM, RAM, interrupt controller, real-time pulse unit, a serial interface, an A/D converter, a D/A converter, and

PWM signal units.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

V853 User's Manual, Hardware:

U10913E

V850 Family User's Manual, Architecture: U10243E

FEATURES

· Number of instructions: 74

· Minimum instruction execution time: 30 ns (@ 33-MHz operation)

· General-purpose registers: 32 bits

32 registers

· Instruction set optimized for control applications

On-chip memory

ROM: 256 Kbytes (

PD703025A)

128 Kbytes (

PD703003A)

96 Kbytes (

PD703004A)

RAM:

8 Kbytes (

PD703025A)

4 Kbytes (

PD703003A, 703004A)

· Advanced on-chip interrupt controller

· Real-time pulse unit suitable for control operations

· Powerful serial interface (on-chip dedicated baud rate generator)

· On-chip clock generator

· 10-bit resolution A/D converter: 8 channels

· 8-bit resolution D/A converter: 2 channels

· 8/9/10/12-bit resolution PWM: 2 channels

· Power saving functions

APPLICATIONS

· AV: Camcorders, VCRs, etc.

· Office equipment: PPCs, LBPs, printers, etc.

· Industrial equipment: Motor controllers, NC machine tools, etc.

· Communications equipment: Mobile telephones, etc.

V853

32/16-BIT SINGLE-CHIP MICROCONTROLLER

Document No. U13188EJ2V0DS00 (2nd edition)
Date Published August 1999 N CP(K)
Printed in Japan

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.

The mark shows major revised points.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

ORDERING INFORMATION

Part Number

Package

Maximum

Internal Internal

Operating

ROM

RAM

Frequency (MHz) (bytes)

(bytes)

PD703003AGC-25-xxx-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

128 K

4 K

PD703003AGC-33-xxx-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

128 K

4 K

PD703004AGC-25-xxx-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

96 K

4 K

PD703004AGC-33-xxx-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

96 K

4 K

PD703025AGC-25-xxx-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

256 K

8 K

PD703025AGC-33-xxx-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

256 K

8 K

Remark xxx indicates ROM code suffix.

PIN CONFIGURATION

· 100-Pin Plastic LQFP (fine pitch) (14

14 mm)

PD703003AGC-xx-xxx-8EU

PD703004AGC-xx-xxx-8EU

PD703025AGC-xx-xxx-8EU

Caution Connect the IC (Internally Connected) pin directly to V

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

ANO0

ANO1

REF2

REF3

P07/INTP113/ADTRG

P06/INTP112

P05/INTP111

P04/INTP110

P03/TI11

P02/TCLR11

P01/TO111

P00/TO110

P117/INTP143

P116/INTP142

P115/INTP141

P114/INTP140

P113/TI14

P112/TCLR14

P111/TO141

P31/TO131

P32/TCLR13

P33/TI13

P34/INTP130

P35/INTP131/SO3

P36/INTP132/SI3

P37/INTP133/SCK3

P63/A19

P62/A18

P61/A17

P60/A16

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P90/LBEN

P91/UBEN

P92/R/W

P93/DSTB

P94/ASTB

P95/HLDAK

P96/HLDRQ

WAIT

MODE

RESET

/CKSEL

CLKOUT

P110/TO140

P30/TO130

P27/SCK1

P26/RXD1/SI1

P25/TXD1/SO1

P24/SCK0

P23/RXD0/SI0

P22/TXD0/SO0

P21/PWM1

P20/PWM0

NMI

P17/INTP123/SCK2

P16/INTP122/SI2

P15/INTP121/SO2

P14/INTP120

P13/TI12

P12/TCLR12

P11/TO121

P10/TO120

REF1

P77/ANI7

P76/ANI6

100

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

PIN NAMES

A16 to A19:

Address Bus

P30 to P37:

Port3

AD0 to AD15:

Address/Data Bus

P40 to P47:

Port4

ADTRG:

AD Trigger Input

P50 to P57:

Port5

ANI0 to ANI7:

Analog Input

P60 to P63:

Port6

ANO0, ANO1:

Analog Output

P70 to P77:

Port7

ASTB:

Address Strobe

P90 to P96:

Port9

Analog Power Supply

P110 to P117:

Port11

REF1

to AV

REF3

Analog Reference Voltage

PWM0, PWM1:

Pulse Width Modulation

Analog Ground

RESET:

Reset

Power Supply for Clock Generator

R/W:

Read/Write Status

Ground for Clock Generator

RXD0, RXD1:

Receive Data

CKSEL:

Clock Select

SCK0 to SCK3:

Serial Clock

CLKOUT:

Clock Output

SI0 to SI3:

Serial Input

DSTB:

Data Strobe

SO0 to SO3:

Serial Output

HLDAK:

Hold Acknowledge

TO110, TO111,:

Timer Output

HLDRQ:

Hold Request

TO120, TO121,

IC:

Internally Connected

TO130, TO131,

INTP110 to INTP113,: Interrupt Request from Peripherals

TO140, TO141

INTP120 to INTP123,

TCLR11 to TCLR14: Timer Clear

INTP130 to INTP133,

TI11 to TI14:

Timer Input

INTP140 to INTP143

TXD0, TXD1:

Transmit Data

LBEN:

Lower Byte Enable

UBEN:

Upper Byte Enable

MODE:

Mode

WAIT:

Wait

NMI:

Non-maskable Interrupt Request

X1, X2:

Crystal

P00 to P07:

Port0

Power Supply

P10 to P17:

Port1

Ground

P20 to P27:

Port2

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

INTERNAL BLOCK DIAGRAM

Notes 1.

PD703003A:

128 Kbytes

PD703004A:

96 Kbytes

PD703025A:

256 Kbytes

PD703003A, 703004A: 4 Kbytes

PD703025A:

8 Kbytes

NMI

TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141

INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143

TCLR11 to TCLR14

TI11 to TI14

INTC

RPU

SIO

Mask ROM

RAM

Note 2

Note 1

CPU

32-bit

barrel shifter

System
register

General

32 bits

ALU

Multiplier

Port

P110 to P117

P90 to P96

P70 to P77

P60 to P63

P50 to P57

P40 to P47

P30 to P37

P20 to P27

P10 to P17

P00 to P07

BCU

Instruction

queue

ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A19
AD0 to AD15

HLDRQ
HLDAK

CLKOUT

MODE

RESET

UART0/CSI0

BRG0

UART1/CSI1

BRG1

CSI2

BRG2

CSI3

PWM

SO0/TXD0

SI0/RXD0

SCK0

SO1/TXD1

SI1/RXD1

SCK1

SO2

SI2

SCK2

SO3

SI3

SCK3

PWM0, PWM1

A/D

converter

ANI0 to ANI7

REF1

ADTRG

D/A

converter

ANO0, ANO1

REF2

, AV

REF3

CKSEL

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

CONTENTS

DIFFERENCES AMONG PRODUCTS ............................................................................................

PIN FUNCTIONS ..............................................................................................................................

2.1

Port Pins ................................................................................................................................................

2.2

Non-port Pins ........................................................................................................................................

2.3

Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................

FUNCTION BLOCKS .......................................................................................................................

3.1

Internal Units .........................................................................................................................................

CPU FUNCTIONS ............................................................................................................................

BUS CONTROL FUNCTIONS .........................................................................................................

INTERRUPT/EXCEPTION HANDLING FUNCTION ........................................................................

CLOCK GENERATION FUNCTION ................................................................................................

TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) ........................................................

SERIAL INTERFACE FUNCTIONS (SIO) .......................................................................................

9.1

Asynchronous Serial Interfaces 0, 1 (UART0, UART1) ......................................................................

9.2

Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) ..................................................................................

9.3

Baud Rate Generators 0 to 2 (BRG0 to BRG2) ...................................................................................

10. PWM UNIT .......................................................................................................................................

11. A/D CONVERTER ............................................................................................................................

12. D/A CONVERTER ............................................................................................................................

13. PORT FUNCTIONS ..........................................................................................................................

14. RESET FUNCTION ..........................................................................................................................

15. INSTRUCTION SET .........................................................................................................................

16. ELECTRICAL SPECIFICATIONS ....................................................................................................

17. PACKAGE DRAWINGS ...................................................................................................................

18. RECOMMENDED SOLDERING CONDITIONS ...............................................................................

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

1. DIFFERENCES AMONG PRODUCTS

Item

PD703003

PD703003A

PD703004A

PD703025A

PD70F3003

PD70F3003A

PD70F3025A

Internal ROM

Mask ROM

Flash memory

128 Kbytes

96 Kbytes

256 Kbytes 128 Kbytes

256 Kbytes

Internal RAM

4 Kbytes

8 Kbytes

4 Kbytes

8 Kbytes

Operation Normal

Single-chip Implemented

mode

operation

mode

ROM-less

Implemented Not implemented

mode

Flash memory

Not implemented

Implemented

programming mode

Not implemented

Implemented

Value of CKC register when reset 00H

MODE = 0: 03H

00H

MODE = 0: 03H

MODE = 1: 00H

Electrical specifications

Power consumption levels vary (see specific product's data sheet).

Others

Depending on the products, noise tolerance and noise emission will vary due to the

differences in circuit scale and mask layout.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

2. PIN FUNCTIONS

2.1 Port Pins

(1/2)

Pin Name

I/O

Function

Alternate Function

P00

I/O

Port 0

TO110

P01

8-bit input/output port

TO111

P02

Input/output can be specified in 1-bit units

TCLR11

P03

TI11

P04

INTP110

P05

INTP111

P06

INTP112

P07

INTP113/ADTRG

P10

I/O

Port 1

TO120

P11

8-bit input/output port

TO121

P12

Input/output can be specified in 1-bit units

TCLR12

P13

TI12

P14

INTP120

P15

INTP121/SO2

P16

INTP122/SI2

P17

INTP123/SCK2

P20

I/O

Port 2

PWM0

P21

8-bit input/output port

PWM1

P22

Input/output can be specified in 1-bit units

TXD0/SO0

P23

RXD0/SI0

P24

SCK0

P25

TXD1/SO1

P26

RXD1/SI1

P27

SCK1

P30

I/O

Port 3

TO130

P31

8-bit input/output port

TO131

P32

Input/output can be specified in 1-bit units

TCLR13

P33

TI13

P34

INTP130

P35

INTP131/SO3

P36

INTP132/SI3

P37

INTP133/SCK3

P40 to P47

I/O

Port 4

AD0 to AD7

8-bit input/output port

Input/output can be specified in 1-bit units

P50 to P57

I/O

Port 5

AD8 to AD15

8-bit input/output port

Input/output can be specified in 1-bit units

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

2.2 Non-port Pins

(1/2)

Pin Name

I/O

Function

Alternate Function

TO110

Output

Pulse signal output from timers 11 to 14

P00

TO111

P01

TO120

P10

TO121

P11

TO130

P30

TO131

P31

TO140

P110

TO141

P111

TCLR11

Input

External clear signal input for timers 11 to 14

P02

TCLR12

P12

TCLR13

P32

TCLR14

P112

TI11

Input

External count clock input for timers 11 to 14

P03

TI12

P13

TI13

P33

TI14

P113

INTP110

Input

External maskable interrupt request input, also used as external capture

P04

INTP111

trigger input for timer 11

P05

INTP112

P06

INTP113

P07/ADTRG

INTP120

Input

External maskable interrupt request input, also used as external capture

P14

INTP121

trigger input for timer 12

P15/SO2

INTP122

P16/SI2

INTP123

P17/SCK2

INTP130

Input

External maskable interrupt request input, also used as external capture

P34

INTP131

trigger input for timer 13

P35/SO3

INTP132

P36/SI3

INTP133

P37/SCK3

INTP140

Input

External maskable interrupt request input, also used as external capture

P114

INTP141

trigger input for timer 14

P115

INTP142

P116

INTP143

P117

SO0

Output

Serial transmit data output (3-wire) for CSI0 to CSI3

P22/TXD0

SO1

P25/TXD1

SO2

P15/INTP121

SO3

P35/INTP131

SI0

Input

Serial receive data input (3-wire) for CSI0 to CSI3

P23/RXD0

SI1

P26/RXD1

SI2

P16/INTP122

SI3

P36/INTP132

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(2/2)

Pin Name

I/O

Function

Alternate Function

SCK0

I/O

Serial clock I/O (3-wire) for CSI0 to CSI3

P24

SCK1

P27

SCK2

P17/INTP123

SCK3

P37/INTP133

TXD0

Output

Serial transmit data output for UART0 and UART1

P22/SO0

TXD1

P25/SO1

RXD0

Input

Serial receive data input for UART0 and UART1

P23/SI0

RXD1

P26/SI1

PWM0

Output

PWM pulse signal output

P20

PWM1

P21

AD0 to AD7

I/O

16-bit multiplexed address/data bus for external memory expansion

P40 to P47

AD8 to AD15

P50 to P57

A16 to A19

Output

High-order address bus used for external memory expansion

P60 to P63

LBEN

Output

External data bus's low-order byte enable signal output

P90

UBEN

External data bus's high-order byte enable signal output

P91

R/W

Output

External read/write status output

P92

DSTB

External data strobe signal output

P93

ASTB

External address strobe signal output

P94

HLDAK

Output

Bus hold acknowledge output

P95

HLDRQ

Input

Bus hold request input

P96

ANI0 to ANI7

Input

Analog input to A/D converter

P70 to P77

ANO0, ANO1

Output

Analog output to D/A converter

NMI

Input

Non-maskable interrupt request input

CLKOUT

Output

System clock output

CKSEL

Input

Input for specifying clock generator's operation mode

WAIT

Input

Control signal input for inserting wait in bus cycle

MODE

Input

Operation mode specification

RESET

Input

System reset input

Input

Resonator connection for system clock. Input is via X1 when using an

external clock.

ADTRG

Input

A/D converter external trigger input

P07/INTP113

REF1

Input

Reference voltage input for A/D converter

REF2

Input

Reference voltage input for D/A converter

REF3

Positive power supply for A/D converter

Ground potential for A/D converter

Positive power supply for on-chip clock generator

CKSEL

Ground potential for on-chip clock generator

Positive power supply

Ground potential

Internally connected pin. Connect directly to V

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.

Figure 2-1 illustrates the various circuit types using partially abridged diagrams.

When connecting to V

or V

via a resistor, a resistance value in the range of 1 to 10 k

is recommended.

Table 2-1. Types of Pin Input/Output Circuits (1/2)

Pin Name

Input/Output Circuit Type

Recommended Connection of Unused Pins

P00/TO110, P01/TO111

Input: Independently connect to V

or V

via a resistor.

P02/TCLR11, P03/TI11,

Output: Leave open.

P04/INTP110 to P07/INTP113/ADTRG

P10/TO120, P11/TO121

P12/TCLR12, P13/TI12

P14/INTP120

P15/INTP121/SO2

P16/INTP122/SI2

P17/INTP123/SCK2

P20/PWM0, P21/PWM1

P22/TXD0/SO0

P23/RXD0/SI0, P24/SCK0

P25/TXD1/SO1

P26/RXD1/SI1, P27/SCK1

P30/TO130, P31/TO131

P32/TCLR13, P33/TI13

P34/INTP130

P35/INTP131/SO3

10-A

P36/INTP132/SI3

P37/INTP133/SCK3

P40/AD0 to P47/AD7

P50/AD8 to P57/AD15

P60/A16 to P63/A19

P70/ANI0 to P77/ANI7

Connect directly to V

P90/LBEN

Input: Independently connect to V

or V

via a resistor.

P91/UBEN

Output: Leave open.

P92/R/W

P93/DSTB

P94/ASTB

P95/HLDAK

P96/HLDRQ

P110/TO140, P111/TO141

P112/TCLR14, P113/TI14

P114/INTP140 to P117/INTP143

ANO0, ANO1

Leave open.

NMI

Connect directly to V

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

3. FUNCTION BLOCKS

3.1 Internal Units

3.1.1 CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic

operations, data transfers, and almost all other instruction processing.

Other dedicated on-chip hardware, such as a multiplier (16 bits

16 bits) and a barrel shifter (32 bits) help accelerate

processing of complex instructions.

3.1.2 Bus control unit (BCU)

The BCU starts the required bus cycle based on the physical address obtained by the CPU. When an instruction

is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a

prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal

instruction queue.

3.1.3 ROM

ROM is mapped to the address space starting at 00000000H. The MODE pin can be used to select an access

enable/disable setting. ROM can be accessed by the CPU in one clock cycle when an instruction is fetched.

3.1.4 RAM

RAM is mapped to the address space starting at FFFFE000H. RAM can be accessed by the CPU in one clock

cycle when data accessed.

3.1.5 Ports

Various port pin and control pin functions can be selected for the 75 pins (port 0 to port 11) comprising I/O ports

(of which eight pins comprise an input-only port).

3.1.6 Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP110 to INTP113, INTP120 to INTP123, INTP130

to INTP133, and INTP140 to INTP143) from on-chip peripheral hardware and external hardware. Eight interrupt

priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for

interrupt sources.

3.1.7 Clock generator (CG)

An on-chip PLL enables the CPU operating clock to be supplied to resonators connected to pins X1 and X2 at 5

frequency, 1

frequency, and 1/2

frequency. It can also be connected to an external clock instead of to a resonator.

3.1.8 Real-time pulse unit (RPU)

The RPU includes a four-channel 16-bit timer/event counter and a one-channel 16-bit interval timer, which enables

measurement of pulse intervals and frequency as well as programmable pulse output.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

3.1.9 Serial interface (SIO)

Four channels comprise two kinds of serial interfaces: an asynchronous serial interface (UART) and a clocked

serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other two

channels are fixed as CSI.

For UART, data is transferred via the TXD and RXD pins. The baud rate is determined by the on-chip baud rate

generator. For CSI, data is transferred via the SO, SI, and SCK pins. The baud rate can be determined by the on-

chip baud rate generator or it can be supplied from an external source.

One of the two CSI-fixed channels is used as the serial clock output, and serial output is sent via an N-ch open

drain output.

3.1.10 Pulse width modulation (PWM)

There are two channels of selectable 8/9/10/12-bit resolution PWM signal outputs. When a low pass filter is

externally connected, PWM output can be used as D/A converter output. This is suitable for actuator control

applications, such as in motors.

3.1.11 A/D converter (ADC)

This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using

the successive approximation method.

3.1.12 D/A converter (DAC)

This is an 8-bit resolution D/A converter that includes two channels. It converts using the R-2R conversion method.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

6. INTERRUPT/EXCEPTION HANDLING FUNCTION

The features of the interrupt/exception handling function are shown below.

· Interrupts

· Non-maskable interrupt: 1 source

· Maskable interrupt: 32 sources

· 8-level programmable priority control

· Multiple interrupt control based on priority levels

· Mask specification for each maskable interrupt request

· Noise elimination, edge detection, and valid edge specification for external interrupt requests

· Exceptions

· Software exceptions: 32 sources

· Exception trap: 1 source (invalid instruction code exception)

The configuration of the interrupt/exception handling function is shown below.

Figure 6-1. Block Diagram of Maskable Interrupt

RPU

Selector

210

2103

210

1032

210

2103

210

INTM1

INTM2

INTM3

INTM4

SIO

INTCSI0

INTOV11

Internal bus

XXMKn (interrupt mask flag)

ISPR

Handler
address

generator

CPU

PSW

Interrupt

request

Interrupt

request

acknowledge

HALT mode

release signal

XXPRn (priority controller)

OVIF11
OVIF12
OVIF13
OVIF14

P11IF0
P11IF1
P11IF2
P11IF3
P12IF0
P12IF1
P12IF2
P12IF3
P13IF0
P13IF1
P13IF2
P13IF3
P14IF0
P14IF1
P14IF2
P14IF3

CSIF0
CSIF1
CSIF2
CSIF3
SEIF0
SRIF0

STIF0
SEIF1

SRIF1

STIF1

ADIF

CMIF4

INTOV12
INTOV13
INTOV14

INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
INTP120/INTCC120
INTP121/INTCC121
INTP122/INTCC122
INTP123/INTCC123
INTP130/INTCC130
INTP131/INTCC131
INTP132/INTCC132
INTP133/INTCC133
INTP140/INTCC140
INTP141/INTCC141
INTP142/INTCC142
INTP143/INTCC143

INTCM4

INTAD

INTCSI1
INTCSI2
INTCSI3
INTSER0
INTSR0
INTST0
INTSER1
INTSR1
INTST1

A/D converter

INTP110

INTP111

INTP112

INTP113

INTP120

INTP121

INTP122

INTP123

INTP130

INTP131

INTP132

INTP133

INTP140

INTP141

INTP142

INTP143

XX: Name of peripheral unit (OV, P11 to P14, CM, CS, SE, SR, ST, AD)

n: Peripheral unit number (none, or 0 to 4, 11 to 14)

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Interrupt/exception sources are shown in Table 6-1.

Table 6-1. List of Interrupts (1/2)

Interrupt/Exception Source

Default Exception

Handler

Restored

Type

Category

Name

Control

Trigger Source

Unit

Priority

Code

Address

Maskable

Interrupt

INTCSI2

CSIC2

CSI2 transmission/reception completion

SIO

01F0H

000001F0H

nextPC

Interrupt

INTCSI3

CSIC3

CSI3 transmission/reception completion

SIO

0200H

00000200H

nextPC

Interrupt

INTSER0

SEIC0

UART0 reception error

SIO

0210H

00000210H

nextPC

Interrupt

INTSR0

SRIC0

UART0 reception completion

SIO

0220H

00000220H

nextPC

Interrupt

INTST0

STIC0

UART0 transmission completion

SIO

0230H

00000230H

nextPC

Interrupt

INTSER1

SEIC1

UART1 reception error

SIO

0240H

00000240H

nextPC

Interrupt

INTSR1

SRIC1

UART1 reception completion

SIO

0250H

00000250H

nextPC

Interrupt

INTST1

STIC1

UART1 transmission completion

SIO

0260H

00000260H

nextPC

Interrupt

INTAD

ADIC

A/D conversion completion

ADC

0270H

00000270H

nextPC

Remarks 1. Default priority: Default priority is the priority order when several maskable interrupt requests

are generated at the same time. The highest priority is 0.

Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception

handling is started. However, if an interrupt occurs during execution of the DIVH

(divide) instruction, the restored PC value is the PC value of the current instruction

(DIVH).

2. The invalid instruction execution address can be obtained using restored PC-4 when an invalid

instruction code exception occurs.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

7. CLOCK GENERATION FUNCTION

The features of the clock generation function are shown below.

· Multiplier function using PLL clock synthesizer

· Clock sources

· Oscillation via resonator connection (PLL mode): f

, 2

· External clock (PLL mode): f

, 2

· External clock (direct mode): f

= 2

· Power saving control

· HALT mode

· IDLE mode

· Software STOP mode

· Clock output inhibit mode

The configuration of the clock generation function is shown below.

Figure 7-1. Block Diagram of Clock Generation Function

Remark

Internal system clock frequency

: Frequency of external oscillator or external clock

CKSEL

)

CLKOUT

CPU, internal peripheral I/O

Clock generator

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)

The features of the timer/counter functions are shown below.

· Measurement of pulse interval and frequency, programmable pulse output

· 16-bit measurements enabled

· Generates a variety of pulse patterns (interval pulse, one-shot pulse, etc.)

· Timer 1

· 16-bit timer/event counter

· Count clock sources: two types (selection of an internal system clock division, external pulse input)

· Capture/compare (shared) registers: 16

· Count clear pins: TCLR11 to TCLR14

· Interrupt sources: 20 types

· External pulse outputs: 8

· Timer 4

· 16-bit interval timer

· Count clock: selectable from an internal system clock division

· Compare register: 1

· Interrupt source: 1

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

The configurations of the respective timer/counter functions are shown below.

Figure 8-1. Block Diagram of Timer 1 (16-bit timer/event counter)

Notes 1. Internal count clock

2. External count clock

3. Priority to reset

Remark

: Internal system clock

n = 1 to 4

Figure 8-2. Block Diagram of Timer 4 (16-bit interval timer)

Note Internal count clock

Remark

: Internal system clock

TM4 (16-bit)

CM4

Clear and start

INTCM4

Note

m
m/32

/2
/4
/16
/32

m
m/4
m/8
m/32

/2
/4

TCLR1n

TI1n

INTP1n0

INTP1n1

INTP1n2

INTP1n3

Note 2

Note 1

Clear and start

TM1n (16 bits)

CC1n0

CC1n1

CC1n2

CC1n3

INTOV1n

INTCC1n0
INTCC1n1

Note3

INTCC1n2
INTCC1n3

TO1n0

TO1n1

Edge

detection

Clear and

start

Edge detection

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

9. SERIAL INTERFACE FUNCTIONS (SIO)

Two types and six channels of serial interfaces are provided.

Up to four channels may be used at the same time.

(1) Asynchronous serial interfaces 0, 1 (UART0, UART1): 2 channels

(2) Clocked serial interfaces 0 to 3 (CSI0 to CSI3): 4 channels

Caution UART0 and CSI0 use the same alternate function pin, as do UART1 and CSI1. Either one can be

selected via a register (ASIM00, ASIM10).

9.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)

The features of asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below.

· Transfer rate

150 bps to 76800 bps (with

= 33-MHz operation, using baud rate generator)

110 bps to 307200 bps (with

= 20-MHz operation, using baud rate generator)

Maximum 1031 Kbps (with

= 33-MHz operation, using

/2)

· Full duplex communications: Receive buffer (RXBn) incorporated

· Two-pin configuration

TXDn: output pin for transmit data

RXDn: input pin for receive data

· Reception error detection function

· Parity error

· Framing error

· Overrun error

· Three types of interrupt sources

· Reception error interrupt (INTSERn)

· Reception completion interrupt (INTSRn)

· Transmission completion interrupt (INTSTn)

· The character length of transmit and receive data is specified via the ASIMn0, ASIMn1 registers

· Character length: 7 or 8 bits, or 9 bits (if using expansion bit)

· Parity function: even, odd, zero, or no parity

· Transmission stop bits: 1 or 2 bits

· On-chip baud rate generator

Remark n = 0, 1

: Internal system clock

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

11. A/D CONVERTER

The features of the A/D converter are shown below.

· Analog inputs: 8 channels

· On-chip 10-bit A/D converter

· On-chip A/D conversion result registers (ADCR0 to ADCR7)

10 bits

8 registers

· A/D conversion trigger modes

A/D trigger mode

Timer trigger mode

External trigger mode

· Sequential conversion method

The configuration of the A/D converter is shown below.

Figure 11-1. Block Diagram of A/D Converter

Internal bus

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

INTAD

Controller

ADM0 (8)

ADM1 (8)

ADCR0

SAR (10)

Voltage comparator

Tap selector

ADCR1

ADCR2

ADCR3

ADCR4

ADCR5

ADCR6

ADCR7

R/2

Series resistor string

Sample & hold circuit

REF1

R/2

INTCC110
INTCC111
INTCC112

Noise

elimination

Edge

detection

INTCC113

ADTRG

Input circuit

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

15. INSTRUCTION SET

· How to read instruction set tables

Table 15-1. Symbols Used to Indicate Operands

Symbol

Description

reg1

General registers (r0 to r31): used as source registers

reg2

General registers (r0 to r31): mainly used as destination registers

Element pointer (r30)

bit#3

3-bit data used to specify bit number

immX

X bits immediate

dispX

X bits displaced

regID

System register number

vector

5-bit data used to specify trap vector (00H to 1FH)

cccc

4-bit data used to indicate condition code

Indicates the instruction group. Instructions are listed in these tables according to their respective groups.

Indicates the mnemonic abbreviation for the instruction.

Indicates the instruction's operands (see Table 15-1).

Indicates the instruction binary code. The binary codes for 32-bit
instructions are shown in two levels (see Table 15-2).

Indicates instruction operation (see Table 15-3).

Indicates flag operations
(see Table 15-4).

Mnemonic

Operand

Opcode

Operation

Flags

SAT

Instruction

Group

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Table 15-2. Symbols Used to Indicate Opcodes

Symbol

Description

1-bit data of code specifying reg1 or regID

1-bit data of code specifying reg2

1 bit of displaced data

1 bit of immediate data

cccc

4-bit data used to indicate condition code

bbb

3-bit data used to specify bit number

Table 15-3. Symbols Used to Indicate Operations

Symbol

Description

Assign

GR [ ]

General register

SR [ ]

System register

zero-extend (n)

Zero-extend n up until word length

sign-extend (n)

Sign-extend n up until word length

load-memory (a, b)

Read data having size b from address a

store-memory (a, b, c)

Replace data b at address a with data having size c

load-memory-bit (a, b)

Read bit b from address a

store-memory-bit (a, b, c)

Write c to bit b from address a

saturated (n)

Execute saturation processing for n (n = complement to 2)

Calculation of n:

When n

7FFFFFFFH, result is 7FFFFFFFH.

When n

80000000H, result is 80000000H.

result

Result is indicated by flag operations

Byte

Byte (8 bits)

Halfword

Half word (16 bits)

Word

Word (32 bits)

Add

Subtract

Bit linkage

Multiply

Divide

AND

Logical AND

Logical OR

XOR

Exclusive OR

NOT

Logical NOT

logically shift left by

Logical shift left

logically shift right by

Logical shift right

arithmetically shift right by

Arithmetic shift right

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Table 15-4. Flag Operations

Identifier

Description

(Blank)

No change

Clear to zero

Set or clear according to result

Restore previously saved value(s)

Table 15-5. Condition Codes

Condition Name (cond)

Condition Code (cccc)

Conditional Expression

Description

0000

OV = 1

Overflow

1000

OV = 0

No overflow

C/L

0001

CY = 1

Carry

Lower (Less than)

NC/NL

1001

CY = 0

No carry

No lower (Greater than or equal)

Z/E

0010

Z = 1

Zero

Equal

NZ/NE

1010

Z = 0

Not zero

Not equal

0011

(CY OR Z) = 1

Not higher (Less than or equal)

1011

(CY OR Z) = 0

Higher (Greater than)

0100

S = 1

Negative

1100

S = 0

Positive

0101

Always (unconditional)

1101

SAT = 1

Saturated

0110

(S XOR OV) = 1

Less than signed

1110

(S XOR OV) = 0

Greater than or equal signed

0111

((S XOR OV) OR Z) = 1

Less than or equal signed

1111

((S XOR OV) OR Z) = 0

Greater than signed

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Instruction Set List

Instruction Mnemonic

Operand

Opcode

Operation

Flags

Group

CY OV S

SAT

Load/store

SLD.B

disp7[ep], reg2

r r r r r 0 1 1 0 d d d d d d d adr

ep + zero-extend (disp7)

instructions

GR[reg2]

sign-extend (Load-memory (adr, Byte))

SLD.H

disp8[ep], reg2

r r r r r 1 0 0 0 d d d d d d d adr

ep + zero-extend (disp8)

Note 1 GR[reg2]

sign-extend (Load-memory (adr, Halfword))

SLD.W

disp8[ep], reg2

r r r r r 1 0 1 0 d d d d d d 0 adr

ep + zero-extend (disp8)

Note 2 GR[reg2]

Load-memory (adr, Word)

LD.B

disp16[reg1], reg2

r r r r r 1 1 1 0 0 0 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d d GR[reg2]

sign-extend (Load-memory (adr, Byte))

LD.H

disp16[reg1], reg2

r r r r r 1 1 1 0 0 1 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d 0 GR[reg2]

sign-extend (Load-memory (adr, Halfword))

Note 3

LD.W

disp16[reg1], reg2

r r r r r 1 1 1 0 0 1 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d 1 GR[reg2]

Load-memory (adr, Word)

Note 3

SST.B

reg2, disp7[ep]

r r r r r 0 1 1 1 d d d d d d d adr

ep + zero-extend (disp7)

Store-memory (adr, GR[reg2], Byte)

SST.H

reg2, disp8[ep]

r r r r r 1 0 0 1 d d d d d d d adr

ep + zero-extend (disp8)

Note 1 Store-memory (adr, GR[reg2], Halfword)

SST.W

reg2, disp8[ep]

r r r r r 1 0 1 0 d d d d d d 1 adr

ep + zero-extend (disp8)

Note 2 Store-memory (adr, GR[reg2], Word)

ST.B

reg2, disp16[reg1]

r r r r r 1 1 1 0 1 0 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d d Store-memory (adr, GR[reg2], Byte)

ST.H

reg2, disp16[reg1]

r r r r r 1 1 1 0 1 1 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d 0 Store-memory (adr, GR[reg2], Halfword)

Note 3

ST.W

reg2, disp16[reg1]

r r r r r 1 1 1 0 1 1 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d 1 Store-memory (adr, GR[reg2], Word)

Note 3

Arithmetic MOV

reg1, reg2

r r r r r 0 0 0 0 0 0 RRRRR GR[reg2]

GR[reg1]

operation

MOV

imm5, reg2

r r r r r 0 1 0 0 0 0 i i i i i

GR[reg2]

sign-extend (imm5)

instructions

MOVHI

imm16, reg1, reg2

r r r r r 1 1 0 0 1 0 RRRRR GR[reg2]

GR[reg1] + (imm16 || 0

)

i i i i i i i i i i i i i i i i

MOVEA

imm16, reg1, reg2

r r r r r 1 1 0 0 0 1 RRRRR GR[reg2]

GR[reg1] + sign-extend (imm16)

i i i i i i i i i i i i i i i i

ADD

reg1, reg2

r r r r r 0 0 1 1 1 0 RRRRR GR[reg2]

GR[reg2] + GR[reg1]

× × × ×

ADD

imm5, reg2

r r r r r 0 1 0 0 1 0 i i i i i

GR[reg2]

GR[reg2] + sign-extend (imm5)

× × × ×

ADDI

imm16, reg1, reg2

r r r r r 1 1 0 0 0 0 RRRRR GR[reg2]

GR[reg1] + sign-extend (imm16)

× × × ×

i i i i i i i i i i i i i i i i

SUB

reg1, reg2

r r r r r 0 0 1 1 0 1 RRRRR GR[reg2]

GR[reg2] GR[reg1]

× × × ×

SUBR

reg1, reg2

r r r r r 0 0 1 1 0 0 RRRRR GR[reg2]

GR[reg1] GR[reg2]

× × × ×

Notes 1. ddddddd = high-order 7 bits of disp8

2. dddddd = high-order 6 bits of disp8

3. ddddddddddddddd = high-order 15 bits of disp16

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Instruction Mnemonic

Operand

Opcode

Operation

Flags

Group

CY OV S Z

SAT

Arithmetic MULH

reg1, reg2

r r r r r 0 0 0 1 1 1 RRRRR GR[reg2]

GR[reg2]

Note

GR[reg1]

Note

operation

(signed multiplication)

instructions

MULH

imm5, reg2

r r r r r 0 1 0 1 1 1 i i i i i

GR[reg2]

Note

sign-extend (imm5)

(signed multiplication)

MULHI

imm16, reg1, reg2

r r r r r 1 1 0 1 1 1 RRRRR GR[reg2]

GR[reg1]

Note

imm16

i i i i i i i i i i i i i i i i

(signed multiplication)

DIVH

reg1, reg2

r r r r r 0 0 0 0 1 0 RRRRR GR[reg2]

GR[reg2]

GR[reg1]

Note

(signed division)

× × ×

CMP

reg1, reg2

r r r r r 0 0 1 1 1 1 RRRRR result

GR[reg2] GR[reg1]

× × × ×

CMP

imm5, reg2

r r r r r 0 1 0 0 1 1 i i i i i

result

GR[reg2] sign-extend (imm5)

× × × ×

SETF

cccc, reg2

r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 then GR[reg2]

00000001H

else GR[reg2]

00000000H

Saturated SATADD reg1, reg2

r r r r r 0 0 0 1 1 0 RRRRR GR[reg2]

saturated (GR[reg2] + GR[reg1])

× × × × ×

operation

SATADD imm5, reg2

r r r r r 0 1 0 0 0 1 i i i i i

GR[reg2]

saturated (GR[reg2] + sign-extend (imm5))

× × × × ×

instructions

SATSUB reg1, reg2

r r r r r 0 0 0 1 0 1 RRRRR GR[reg2]

saturated (GR[reg2] GR[reg1])

× × × × ×

SATSUBI imm16, reg1, reg2

r r r r r 1 1 0 0 1 1 RRRRR GR[reg2]

saturated (GR[reg1] sign-extend (imm16))

× × × × ×

i i i i i i i i i i i i i i i i

SATSUBR reg1, reg2

r r r r r 0 0 0 1 0 0 RRRRR GR[reg2]

saturated (GR[reg1] GR[reg2])

× × × × ×

Logical

TST

reg1, reg2

r r r r r 0 0 1 0 1 1 RRRRR result

GR[reg2]AND GR[reg1]

× ×

operation

reg1, reg2

r r r r r 0 0 1 0 0 0 RRRRR GR[reg2]

GR[reg2]OR GR[reg1]

× ×

instruction

ORI

imm16, reg1, reg2

r r r r r 1 1 0 1 0 0 RRRRR GR[reg2]

GR[reg1]OR zero-extend (imm16)

× ×

i i i i i i i i i i i i i i i i

AND

reg1, reg2

r r r r r 0 0 1 0 1 0 RRRRR GR[reg2]

GR[reg2]AND GR[reg1]

× ×

ANDI

imm16, reg1, reg2

r r r r r 1 1 0 1 1 0 RRRRR GR[reg2]

GR[reg1]AND zero-extend (imm16)

0 0

i i i i i i i i i i i i i i i i

XOR

reg1, reg2

r r r r r 0 0 1 0 0 1 RRRRR GR[reg2]

GR[reg2]XOR GR[reg1]

× ×

XORI

imm16, reg1, reg2

r r r r r 1 1 0 1 0 1 RRRRR GR[reg2]

GR[reg1]XOR zero-extend (imm16)

× ×

i i i i i i i i i i i i i i i i

NOT

reg1, reg2

r r r r r 0 0 0 0 1 RRRRR

GR[reg2]

NOT (GR[reg1])

× ×

SHL

reg1, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

GR[reg2]logically shift left by GR[reg1]

× ×

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

SHL

imm5, reg2

r r r r r 0 1 0 1 1 0 i i i i i

GR[reg2]

GR[reg2]logically shift left by

× ×

zero-extend (imm5)

SHR

reg1, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

GR[reg2]logically shift right by GR[reg1]

× ×

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

SHR

imm5, reg2

r r r r r 0 1 0 1 0 0 i i i i i

GR[reg2]

GR[reg2]logically shift right by

× ×

zero-extend (imm5)

SAR

reg1, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

GR[reg2]arithmetically shift right by

× ×

0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

GR[reg1]

SAR

imm5, reg2

r r r r r 0 1 0 1 0 1 i i i i i

GR[reg2]

GR[reg2]arithmetically shift right by

× ×

zero-extend (imm5)

Note Only the low-order half word is valid.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Instruction Mnemonic

Operand

Opcode

Operation

Flags

Group

CY OV S

SAT

Branch

JMP

[reg1]

0 0 0 0 0 0 0 0 0 1 1 RRRRR PC

GR[reg1]

instructions

disp22

0 0 0 0 0 1 1 1 1 0 d d d d d d PC

PC + sign-extend (disp22)

d d d d d d d d d d d d d d d 0

Note 1

JARL

disp22, reg2

r r r r r 1 1 1 1 0 d d d d d d GR[reg2]

PC + 4

d d d d d d d d d d d d d d d 0 PC

PC + sign-extend (disp22)

Note 1

Bcond

disp9

d d d d d 1 0 1 1 d d d c c c c if conditions are satisfied

Note 2 then PC

PC + sign-extend (disp9)

Bit

SET1

bit#3, disp16[reg1] 0 0 b b b 1 1 1 1 1 0 RRRRR adr

GR[reg1] + sign-extend (disp16)

manipulation

d d d d d d d d d d d d d d d d Z flag

Not (Load-memory-bit (adr, bit#3))

instructions

Store-memory-bit (adr, bit#3, 1)

CLR1

bit#3, disp16[reg1] 1 0 b b b 1 1 1 1 1 0 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d d Z flag

Not (Load-memory-bit (adr, bit#3))

Store-memory-bit (adr, bit#3, 0)

NOT1

bit#3, disp16[reg1] 0 1 b b b 1 1 1 1 1 0 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d d Z flag

Not (Load-memory-bit (adr, bit#3))

Store-memory-bit (adr, bit#3, Z flag)

TST1

bit#3, disp16[reg1] 1 1 b b b 1 1 1 1 1 0 RRRRR adr

GR[reg1] + sign-extend (disp16)

d d d d d d d d d d d d d d d d Z flag

Not (Load-memory-bit (adr, bit#3))

Notes 1. ddddddddddddddddddddd = high-order 21 bits of disp22

2. dddddddd = high-order 8 bits of disp9

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Instruction Mnemonic

Operand

Opcode

Operation

Flags

Group

CY OV S Z

SAT

Special

LDSR

reg2, regID

r r r r r 1 1 1 1 1 1 RRRRR SR[regID]

GR[reg2]

regID = EIPC, FEPC

instructions

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

regID = EIPSW, FEPSW

Note

regID = PSW

× × × × ×

STSR

regID, reg2

r r r r r 1 1 1 1 1 1 RRRRR GR[reg2]

SR[regID]

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

TRAP

vector

0 0 0 0 0 1 1 1 1 1 1 i i i i i

EIPC

PC + 4 (restored PC)

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW

PSW

ECR.EICC

Interrupt code

PSW.EP

PSW.ID

00000040H (when vector is 00H to 0FH)

00000050H (when vector is 10H to 1FH)

RETI

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP = 1

R R R R

0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 then PC

EIPC

PSW

EIPSW

else if PSW.NP = 1

then PC

FEPC

PSW

FEPSW

else PC

EIPC

PSW

EIPSW

HALT

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stops

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID

0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt prohibit)

1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID

0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt enable)

NOP

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation, uses at least one clock

Note In this instruction, "reg2" is the mnemonic abbreviation for the source register, but the reg1 field is used for

the opcode. Consequently, this instruction differs from other instructions in the way the registers are

specified in the mnemonic description and opcode.

rrrrr = regID specification

RRRRR = reg2 specification

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

16. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Conditions

Rating

Unit

Power supply voltage

0.5 to +7.0

0.5 to V

+ 0.3

0.5 to +0.5

0.5 to V

+ 0.3

0.5 to +0.5

Input voltage

Note, V

= 5.0 V

10%

0.5 to V

+ 0.3

Clock input voltage

X1 pin, V

= 5.0 V

10%

0.5 to V

+ 1.0

Output current, low

Per pin

4.0

Total for all pins

100

Output current, high

Per pin

4.0

Total for all pins

100

Output voltage

= 5.0 V

10%

0.5 to V

+ 0.3

Analog input voltage

IAN

P70/ANI0 to P77/ANI7

> V

0.5 to V

+ 0.3

0.5 to AV

+ 0.3

Analog reference input voltage

REF

REF1

to AV

REF3

> V

0.5 to V

+ 0.3

0.5 to AV

+ 0.3

Operating ambient temperature

40 to +85

Storage temperature

stg

65 to +150

Note X1, P70/ANI0 to P77/ANI7, and AV

REF1

to AV

REF3

are excluded.

Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between

or V

and GND. However, open-drain pins and open collector pins can be directly

connected. A direct connection to an external circuit can be made to avoid conflicting output

from high-impedance pins if the external circuit is designed for the correct timing.

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions shown below for DC characteristics and AC characteristics are

within the range for normal operation and quality assurance.

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input capacitance

= 1 MHz

I/O capacitance

Unmeasured pins returned to 0 V.

Output capacitance

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Recommended Oscillator

(1)

PD703003A, 703004A

(a) Ceramic resonator connection (T

= 40 to +85

Manufacturer

Part Number

Oscillation

Recommended

Oscillation

Frequency

Circuit Constant

Voltage Range

Stabilization Time

(MHz)

C1 (pF)

C2 (pF)

Rd (

)

MIN. (V)

MAX. (V) (MAX.) T

OST

(ms)

Kyocera

KBR-3.0MS

3.0

4.5

5.5

0.24

Corporation

KBR-3.2MS

3.2

4.5

5.5

0.24

KBR-5.0MSA/MSB

5.0

680

4.5

5.5

0.14

KBR-5.0MKC

5.0

On-chip

680

4.5

5.5

0.14

KBR-5.0MKD

5.0

On-chip

680

4.5

5.5

0.14

KBR-5.0MKS

5.0

On-chip

680

4.5

5.5

0.14

PBRC5.00A

5.0

680

4.5

5.5

0.14

PBRC5.00B

5.0

On-chip

680

4.5

5.5

0.14

KBR-6.6MSA/MSB

6.6

4.5

5.5

0.10

KBR-6.6MKC

6.6

On-chip

4.5

5.5

0.10

KBR-6.6MKD

6.6

On-chip

4.5

5.5

0.10

KBR-6.6MKS

6.6

On-chip

4.5

5.5

0.10

PBRC6.60A

6.6

4.5

5.5

0.10

PBRC6.60B

6.6

On-chip

4.5

5.5

0.10

TDK

CCR5.0MC3

5.0

On-chip

4.5

5.5

0.18

FCR5.0MC5

5.0

On-chip

4.5

5.5

0.16

CCR6.6MC3

6.6

On-chip

4.5

5.5

0.17

Murata Mfg.

CSA3.20MG040

3.2

100

4.5

5.5

0.27

Co., Ltd.

CST3.20MGW040

3.2

On-chip

4.5

5.5

0.27

CSA5.00MG040

5.0

100

4.5

5.5

0.31

CST5.00MGW040

5.0

On-chip

4.5

5.5

0.31

CSA6.60MTZ040

6.6

100

4.5

5.5

0.30

CST6.60MTW040

6.6

On-chip

4.5

5.5

0.30

Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible.

2. Do not cross the wiring with the other signal lines in the broken-line area.

3. Sufficiently evaluate the matching between the

PD703003A, 703004A and the resonator.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

DC Characteristics (T

= 40 to +85

C, V

= 5.0 V

10%, V

= 0 V)

(1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, high

Except for X1 and pins listed in Note

2.2

+ 0.3

Note

0.8V

+ 0.3

Input voltage, low

Except for X1 and pins listed in Note

0.5

+0.8

Note

0.5

0.2V

Clock input voltage, high

0.8V

+ 0.5

Clock input voltage, low

0.5

+0.6

Schmitt-triggered input

Note, rising edge

3.0

Threshold voltage

Note, falling edge

2.0

Schmitt-triggered input hysteresis width V

Note

0.5

Output voltage, high

= 2.5 mA

0.7V

= 100

0.4

Output voltage, low

= 2.5 mA

0.45

Input leakage current, high

LIH

= V

Input leakage current, low

LIL

= 0 V

Output leakage current, high

LOH

= V

Output leakage current, low

LOL

= 0 V

Software pull-up resistor

P35/INTP131/SO3,

P36/INTP132/SI3,

P37/INTP133/SCK3

Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/

SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,

P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE

Remarks 1. TYP. values are reference values for when T

= 25

C and V

= 5.0 V.

= Internal system clock frequency

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

DC Characteristics (T

= 40 to +85

C, V

= 5.0 V

10%, V

= 0 V)

(2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power

PD703003A, When

DD1

Direct mode

Note

1.9

+ 5 2.1

+ 17

supply 703004A

operating

PLL mode

2.0

+ 7 2.2

+ 20

current

DD2

Direct mode

Note

1.2

+ 5 1.3

+ 13

HALT mode

PLL mode

1.3

+ 7 1.4

+ 15

DD3

Direct mode

Note

+ 300 10

+ 500

IDLE mode

PLL mode

0.1

+ 2 0.2

+ 3

DD4

STOP mode

PD703025A, When

DD1

Direct mode

Note

2.5

+ 2 2.8

+ 16.5

operating

PLL mode

2.6

+ 4 2.9

+19.5

DD2

Direct mode

Note

1.3

+ 5 1.4

+ 13

HALT mode

PLL mode

1.3

+ 10 1.4

+ 18

DD3

Direct mode

Note

+ 300 10

+ 500

IDLE mode

PLL mode

0.1

+ 2 0.2

+ 3

DD4

STOP mode

Note When using A/D converter:

= 5 to 33 MHz

When not using A/D converter:

= 0 to 33 MHz

Remarks 1. TYP. values are reference values for when T

= 25

C and V

= 5.0 V. The power supply current

does not include AV

REF1

to AV

REF3

or the current that flows across a software pull-up resistor.

= Internal system clock frequency

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

Data Retention Characteristics (T

= 40 to +85

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention voltage

DDDR

STOP mode

1.5

5.5

Data retention current

DDDR

= V

DDDR

+50

0.2V

DDDR

C < T

0.2V

DDDR

200

Power supply voltage rise time

RVD

200

Power supply voltage fall time

FVD

200

Power supply voltage hold time

HVD

(vs. STOP mode setting)

STOP mode release signal input time t

DREL

Note

Data retention high-level input voltage

IHDR

Note

0.9V

DDDR

Data retention low-level input voltage

ILDR

0.1V

DDDR

Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/

SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,

P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1

Remark

TYP. values are reference values for when T

= 25

C and V

= 5.0 V.

HVD

FVD

RVD

DREL

DDDR

RESET (input)

IHDR

NMI (input)

(Released at falling edge)

IHDR

ILDR

NMI (input)

(Released at rising edge)

STOP mode setting (fifth clock after PSC register is set)

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

AC Characteristics (T

= 40 to +85

C, V

= 5.0 V

10%, V

= 0 V)

AC test input waveform

(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/

SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/

TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14,

P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1

(b) Pins other than those listed in (a) above

AC test output test points

Load condition

Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert

a buffer or other element to reduce the device's load capacitance to below 50 pF.

Test points

2.2 V

0.8 V

2.2 V

0.8 V

2.4 V

0.4 V

Test points

2.2 V

0.8 V

2.2 V

0.8 V

Test points

0.8V

0.2V

0.8V

0.2V

0 V

= 50 pF

DUT

(Device under testing)

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(1) Clock timing

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

X1 input cycle

<1>

CYX

Direct mode

Note 1

PLL mode (PLL locked)

200

315

151

334

X1 input high-level width

<2>

WXH

Direct mode

PLL mode

X1 input low-level width

<3>

WXL

Direct mode

PLL mode

X1 input rise time

<4>

Direct mode

PLL mode

X1 input fall time

<5>

Direct mode

PLL mode

CPU operating frequency

Direct mode

Note 2

MHz

PLL mode

Note 3

MHz

CLKOUT output cycle

<6>

CYK

Note 4

CLKOUT input high-level width

<7>

WKH

0.5T 5

CLKOUT input low-level width

<8>

WKL

0.5T 5

CLKOUT input rise time

<9>

CLKOUT input fall time

<10> t

CLKOUT delay time

<11> t

DXK

Direct mode

Notes 1. When using A/D converter: 100 ns

When not using A/D converter: DC

2. When using A/D converter: 5 MHz

When not using A/D converter: 0 MHz

3. Free-running oscillation frequency

4. When using A/D converter: 200 ns

When not using A/D converter: DC

Remark

T = t

CYK

Parameter

Symbol

Conditions

TYP.

Unit

Free-running oscillation frequency

PLL mode

MHz

X1 (input)

CLKOUT (output)

<1>

<2>

<4>

<5>

<6>

<7>

<11>

<8>

<9>

<10>

<3>

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(2) Input waveform

(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/

SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/

SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

Input rise time

<12> t

IR2

Input fall time

<13> t

IF2

(b) Pins other than those listed in (a) above

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

Input rise time

<14> t

IR1

Input fall time

<15> t

IF1

2.2 V

<15>

<14>

0.8 V

2.2 V

0.8 V

2.4 V

0.4 V

Input signal

0.8V

0.2V

0.8V

0.2V

0 V

<13>

<12>

Input signal

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(3) Output waveform (other than CLKOUT)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

Output rise time

<16> t

Output fall time

<17> t

(4) Reset timing

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

RESET high-level width

<18> t

WRSH

500

RESET low-level width

<19> t

WRSL

When power supply is ON

500 + T

OST

500 + T

OST

and STOP mode has been

released

Other than when power

500

supply is ON and STOP

mode has been released

Remark

OST

: Oscillation stabilization time

0.8 V

<16>

<17>

2.2 V

0.8 V

Output signal

RESET (input)

<18>

<19>

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(5) Read timing (1/2)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

Address delay time from CLKOUT

<20> t

DKA

R/W, UBEN, LBEN delay time from CLKOUT

<78> t

DKA2

Address float delay time from CLKOUT

<21> t

FKA

ASTB delay time from CLKOUT

<22> t

DKST

DSTB delay time from CLKOUT

<23> t

DKD

Data input setup time (to CLKOUT

) <24> t

SIDK

Data input hold time (from CLKOUT

) <25> t

HKID

WAIT setup time (to CLKOUT

) <26> t

SWTK

WAIT hold time (from CLKOUT

) <27> t

HKWT

Address hold time (from CLKOUT

) <28> t

HKA

Address setup time (to ASTB

)

<29> t

SAST

+70

0.5T 10

C < T

0.5T 12

Address hold time (from ASTB

) <30> t

HSTA

0.5T 10

Address float delay time from DSTB

<31> t

FDA

Data input setup time (to address) <32> t

SAID

+70

(2 + n)T 22

C < T

(2 + n)T 25

Data input setup time (to DSTB

) <33> t

SDID

+70

(1 + n)T 20

C < T

(1 + n)T 24

DSTB

delay time from ASTB

<34> t

DSTD

0.5T 10

Data input hold time (from DSTB

) <35> t

HDID

Address output delay time from DSTB

<36> t

DDA

(1 + i)T

ASTB

delay time from DSTB

<37> t

DDSTH

0.5T 10

ASTB

delay time from DSTB

<38> t

DDSTL

(1.5 + i)T 10

DSTB low-level width

<39> t

WDL

+70

(1 + n)T 10

C < T

(1 + n)T 13

ASTB high-level width

<40> t

WSTH

T 10

WAIT setup time (to address)

<41> t

SAWT1

1, 40

+70

1.5T 20

1, 70

C < T

1.5T 24

<42> t

SAWT2

1, 40

+70

(1.5 + n)T 20

1, 70

C < T

(1.5 + n)T 24

WAIT hold time (from address)

<43> t

HAWT1

(0.5 + n)T

<44> t

HAWT2

(1.5 + n)T

WAIT setup time (to ASTB

)

<45> t

SSTWT1

1, 40

+70

T 18

1, 70

C < T

T 20

<46> t

SSTWT2

(1 + n)T 15

WAIT hold time (from ASTB

)

<47> t

HSTWT1

<48> t

HSTWT2

(1 + n)T

Remarks 1. T = t

CYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.

4. Maintain at least one of the two data input hold times, either t

HKID

(<25>) or t

HDID

(<35>).

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(6) Write timing (1/2)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

Address delay time from CLKOUT

<20> t

DKA

R/W, UBEN, LBEN delay time from CLKOUT

<78> t

DKA2

ASTB delay time from CLKOUT

<22> t

DKST

DSTB delay time from CLKOUT

<23> t

DKD

WAIT setup time (to CLKOUT

) <26> t

SWTK

WAIT hold time (from CLKOUT

) <27> t

HKWT

Address hold time (from CLKOUT

) <28> t

HKA

Address setup time (to ASTB

)

<29> t

SAST

+70

0.5T 10

C < T

0.5T 12

Address hold time (from ASTB

) <30> t

HSTA

0.5T 10

DSTB

delay time from ASTB

<34> t

DSTD

0.5T 10

ASTB

delay time from DSTB

<37> t

DDSTH

0.5T 10

DSTB low-level width

<39> t

WDL

+70

(1 + n)T 10

C < T

(1 + n)T 13

ASTB high-level width

<40> t

WSTH

T 10

WAIT setup time (to address)

<41> t

SAWT1

1, 40

+70

1.5T 20

1, 70

C < T

1.5T 24

<42> t

SAWT2

1, 40

+70

(1.5 + n)T 20

1, 70

C < T

(1.5 + n)T 24

WAIT hold time (from address)

<43> t

HAWT1

(0.5 + n)T

<44> t

HAWT2

(1.5 + n)T

WAIT setup time (to ASTB

)

<45> t

SSTWT1

1, 40

+70

T 18

1, 70

C < T

T 20

<46> t

SSTWT2

(1 + n)T 15

WAIT hold time (from ASTB

)

<47> t

HSTWT1

<48> t

HSTWT2

(1 + n)T

Data output delay time from

<49> t

DKOD

+70

CLKOUT

C < T

Data output delay time from DSTB

<50> t

DDOD

Data output hold time (from CLKOUT

) <51> t

HKOD

Data output setup time (to DSTB

) <52> t

SODD

(1 + n)T 15

Data output hold time (from DSTB

) <53> t

HDOD

T 10

Remarks 1. T = t

CYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(7) Bus hold timing (1/2)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Units

MIN.

MAX.

MIN.

MAX.

HLDRQ setup time (to CLKOUT

) <54> t

SHQK

HLDRQ hold time (from CLKOUT

) <55> t

HKHQ

HLDAK delay time from CLKOUT

<56> t

DKHA

HLDRQ high-level width

<57> t

WHQH

T + 10

HLDAK low-level width

<58> t

WHAL

+70

T 10

C < T

T 12

Bus float delay time from CLKOUT

<59> t

DKF

Bus output delay time from HLDAK

<60> t

DHAC

HLDAK

delay time from HLDRQ

<61> t

DHQHA1

(2n + 7.5)T + 20

HLDAK

delay time from HLDRQ

<62> t

DHQHA2

0.5T

1.5T + 20

0.5T

1.5T + 20

Remarks 1. T = t

CYK

2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may

vary when using the programmable wait insertion function.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(9) CSI timing (1/2)

(a) Master mode

(i)

Timing of CSI0 to CSI2

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67> t

CYSK1

Output

160

120

SCKn high-level width

<68> t

WSKH1

Output

0.5t

CYSK1

0.5t

CYSK1

SCKn low-level width

<69> t

WSKL1

Output

0.5t

CYSK1

0.5t

CYSK1

SIn setup time (to SCKn

)

<70> t

SSISK1

SIn hold time (from SCKn

)

<71> t

HSKSI1

SOn output delay time (from SCKn

) <72> t

DSKSO1

SOn output hold time (from SCKn

) <73> t

HSKSO1

0.5t

CYSK1

0.5t

CYSK1

Remark

n = 0 to 2

(ii) Timing of CSI3

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCK3 cycle

<67> t

CYSK3

Output

= 1.5 k

500

SCK3 high-level width

<68> t

WSKH3

Output

= 50 pF

0.5t

CYSK3

0.5t

CYSK3

SCK3 low-level width

<69> t

WSKL3

Output

0.5t

CYSK3

0.5t

CYSK3

SI3 setup time (to SCK3

)

<70> t

SSISK3

100

SI3 hold time (from SCK3

)

<71> t

HSKSI3

SO3 output delay time (from SCK3

) <72> t

DSKSO3

= 1.5 k

150

SO3 output hold time (from SCK3

) <73> t

HSKSO3

= 50 pF

0.5t

CYSK3

0.5t

CYSK3

Remark

is the load resistance and C

is the load capacitance of the output line for SCK3 and SO3.

(b) Slave mode

(i)

Timing of CSI0 to CSI2

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67> t

CYSK2

Input

160

120

SCKn high-level width

<68> t

WSKH2

Input

SCKn low-level width

<69> t

WSKL2

Input

SIn setup time (to SCKn

)

<70> t

SSISK2

SIn hold time (from SCKn

)

<71> t

HSKSI2

SOn output delay time (from SCKn

) <72> t

DSKSO2

SOn output hold time (from SCKn

) <73> t

HSKSO2

WSKH2

Remark

n = 0 to 2

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

(9) CSI timing (2/2)

(b) Slave mode

(ii) Timing of CSI3

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

SCK3 cycle

<67> t

CYSK4

Input

500

SCK3 high-level width

<68> t

WSKH4

Input

180

SCK3 low-level width

<69> t

WSKL4

Input

180

SI3 setup time (to SCK3

)

<70> t

SSISK4

100

SI3 hold time (from SCK3

)

<71> t

HSKSI4

SO3 output delay time (from SCK3

) <72> t

DSKSO4

= 1.5 k

150

SO3 output hold time (from SCK3

) <73> t

HSKSO4

= 50 pF

WSKH4

Remark

is the load resistance and C

is the load capacitance of the output line for SCK3 and SO3.

SCKn (I/O)

SIn (Input)

SOn (output)

<67>

<69>

<68>

<70>

<71>

<72>

<73>

Input data

Output data

Remarks 1. Broken lines indicate high impedance.

2. n = 0 to 3

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

A/D Converter Characteristics (T

= 40 to +85

C, V

= AV

= 5 V

10%, V

= AV

= 0 V)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

Resolution

bit

Total error

Note 1

4.5 V

REF1

0.4

%FSR

3.5 V

REF1

0.7

%FSR

Quantization error

1/2

LSB

Conversion time

CONV

4.5 V

REF1

CYK

3.5 V

REF1

CYK

Sampling time

SAMP

4.5 V

REF1

CYK

3.5 V

REF1

CYK

Zero scale error

Note 1

4.5 V

REF1

1.5

3.5

1.5

3.5

LSB

3.5 V

REF1

1.5

4.5

1.5

4.5

LSB

Full scale error

Note 1

4.5 V

REF1

1.5

2.5

1.5

2.5

LSB

3.5 V

REF1

1.5

4.5

1.5

4.5

LSB

Nonlinearity error

Note 1

4.5 V

REF1

1.5

2.5

1.5

2.5

LSB

3.5 V

REF1

1.5

4.5

1.5

4.5

LSB

Analog input

IAN

0.3

voltage

Note 2

+0.3

Reference voltage

REF1

3.5

REF1

current

REF1

1.2

3.0

1.2

3.0

power supply

2.3

6.0

2.3

6.0

current

Notes 1. Exclude quantization error.

2. When V

IAN

= 0, the conversion result becomes 000H.

When 0 < V

IAN

< AV

REF1

, conversion has 10-bit resolution.

When AV

REF1

IAN

, the conversion result becomes 3FFH.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

D/A Converter Characteristics (T

= 40 to +85

C, V

= AV

= 5 V

10%, V

= AV

= 0 V)

Parameter

Symbol

Conditions

25-MHz Version

33-MHz Version

Unit

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

Resolution

bit

Total error

Load condition: 2 M

, 30 pF

0.8

REF2

= V

REF3

= 0

Load condition: 2 M

, 30 pF

1.0

REF2

= 0.75V

REF3

= 0.25V

Load condition: 4 M

, 30 pF

0.6

REF2

= V

REF3

= 0

Load condition: 4 M

, 30 pF

0.8

REF2

= 0.75V

REF3

= 0.25V

Settling time

Load condition: 2 M

, 30 pF

Output resistance

REF2

input voltage

REF2

0.75V

REF3

input voltage

REF3

0.25V

REF2

to AV

REF3

AIREF

DACS0, DACS1 = 55H

resistance value

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

100 PIN PLASTIC LQFP (FINE PITCH) (14

14)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.

S100GC-50-8EU

1.00

0.039

14.00±0.20

0.551+0.009

0.008

1.60 MAX.

0.063 MAX.

0.50±0.20

0.020+0.008

0.009

+0.009

0.008

14.00±0.20

0.551+0.009

0.008

16.00±0.20

0.630±0.008

1.00

0.039

0.22

0.009±0.002

0.08

0.003

0.50 (T.P.)

0.020 (T.P.)

1.00±0.20

0.039+0.009

0.008

0.08

0.003

1.40±0.05

0.055±0.002

16.00±0.20

0.630±0.008

detail of lead end

0.17

0.007+0.001

0.003

+0.03

0.07

0.10±0.05

0.004±0.002

+0.05

0.04

100

17. PACKAGE DRAWINGS

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

18. RECOMMENDED SOLDERING CONDITIONS

The

PD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended

conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales represen-

tatives.

Table 18-1. Soldering Conditions

(1)

PD703003AGC-xx-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14

14 mm)

PD703004AGC-xx-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14

14 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

IR35-107-2

VPS

VP15-107-2

Partial heating

Note After opening a dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

(2)

PD703025AGC-xx-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14

14 mm)

Undefined

Package peak temperature: 235

C, Time: 30 sec. Max. (at 210

C or higher),

Count: two times or less, Exposure limit: 7 days

Note

(after that, prebake at

125

C for 10 hours)

Package peak temperature: 215

C, Time: 40 sec. Max. (at 200

C or higher),

Count: two times or less, Exposure limit: 7 days

Note

(after that, prebake at

125

C for 10 hours)

Pin temperature: 300

C Max., Time 3 sec. Max. (per pin row)

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

PD703003A, 703004A, 703025A

Data Sheet U13188EJ2V0DS00

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J99.1

PD703003A, 703004A, 703025A

RELATED DOCUMENTS

PD703003 Data Sheet (U12261E)

PD70F3003 Data Sheet (U12036E)

PD70F3003A, 70F3025A Data Sheet (U13189E)

V850 Family Instruction Table (U10229J)

Note

Note Japanese version

The related documents indicated in this publication may include preliminary versions. However, preliminary versions

are not marked as such.

V850 Family and V853 are trademarks of NEC Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.

Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98.8

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