MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD703014A, 703014AY, 703015A,

703015AY, 703017A, 703017AY

V850/SA1

32-/16-BIT SINGLE-CHIP MICROCONTROLLER

Document No. U14526EJ2V0DS00 (2nd edition)

The mark shows major revised points.

Date Published September 2000 N CP(K)
Printed in Japan

DATA SHEET

2000

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

DESCRIPTION

The

PD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY (V850/SA1) are 32-/16-bit single-

chip microcontrollers that include the CPU core of the V850 Family

, and peripheral functions such as ROM/RAM,

timer/counters, serial interfaces, an A/D converter, a timer, and a DMA controller.

In addition to its high real-time responsiveness and one-clock-pitch execution of instructions, the V850/SA1

includes a hardware multiplier for multiplication instructions, saturation instructions, and bit manipulation instructions,

all of which are instructions suited to digital servo control applications. As a real-time control system, this device

provides a high-level cost performance ideal for applications ranging from low-power camcorders and other AV

equipment to portable telephone equipment such as cellular phones and personal handyphone systems (PHS).

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

V850/SA1 User's Manual Hardware:

U12768E

V850 Family

User's Manual Architecture:

U10243E

FEATURES

{

Number of instructions: 74

{

Minimum instruction execution time:

59 ns (@ 17 MHz operation with main system clock (f

))

50 ns (@ 20 MHz operation with main system clock (f

))

30.5

s (@ 32.768 kHz operation with subsystem clock (f

))

{

General-purpose registers: 32 bits

32 registers

{

Instruction set:

Signed multiplication, saturation operations, 32-bit

shift instructions, bit manipulation instructions,

load/store instructions

{

Memory space:

16 MB linear address space

Memory block allocation function: 2 MB per block

{

External bus interface: 16-bit data bus

Address bus: Separate output enabled

{

Internal memory

Mask ROM: 64 KB (

PD703014A, 703014AY)

128 KB (

PD703015A, 703015AY)

256 KB (

PD703017A, 703017AY)

RAM: 4 KB

(

PD703014A, 703014AY, 703015A, 703015AY)

8 KB (

PD703017A, 703017AY)

{

Interrupts and exception

External: 8, internal: 23, exception: 1

{

I/O lines Total: 85

{

Timer/counters

16-bit timer:

2 channels

8-bit timer:

4 channels

{

Watch timer: 1 channel

{

Watchdog timer: 1 channel

{

Serial interface (SIO)

Asynchronous serial interface (UART)

Clocked serial interface (CSI)

C bus interface

(

PD703014AY, 703015AY, 703017AY)

{

A/D converter: 12 channels

{

DMA controller: 3 channels

{

RTP: 8 bits

1 channel or 4 bits

2 channels

{

Power-saving functions: HALT/IDLE/STOP modes

{

Packages: 100-pin plastic LQFP (14

14)

121-pin plastic FBGA (12

12)

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

APPLICATIONS

{

Low-power portable devices

Cellular phones, PHSs, and camcorders

ORDERING INFORMATION

Part Number

Package

Internal ROM

PD703014AGC-

×××

-8EU

PD703014AF1-

×××

-EA6

PD703014AYGC-

×××

-8EU

PD703014AYF1-

×××

-EA6

PD703015AGC-

×××

-8EU

PD703015AF1-

×××

-EA6

PD703015AYGC-

×××

-8EU

PD703015AYF1-

×××

-EA6

PD703017AGC-

×××

-8EU

PD703017AF1-

×××

-EA6

PD703017AYGC-

×××

-8EU

PD703017AYF1-

×××

-EA6

100-pin plastic LQFP (fine-pitch) (14

14)

121-pin plastic FBGA (12

12)

100-pin plastic LQFP (fine-pitch) (14

14)

121-pin plastic FBGA (12

12)

100-pin plastic LQFP (fine-pitch) (14

14)

121-pin plastic FBGA (12

12)

100-pin plastic LQFP (fine-pitch) (14

14)

121-pin plastic FBGA (12

12)

100-pin plastic LQFP (fine-pitch) (14

14)

121-pin plastic FBGA (12

12)

100-pin plastic LQFP (fine-pitch) (14

14)

121-pin plastic FBGA (12

12)

64 KB (Mask ROM)

128 KB (Mask ROM)

256 KB (Mask ROM)

Remark

×××

indicates ROM code suffix.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

PIN CONFIGURATION

100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

PD703014AGC-

×××

-8EU

PD703014AYGC-

×××

-8EU

PD703015AGC-

×××

-8EU

PD703015AYGC-

×××

-8EU

PD703017AGC-

×××

-8EU

PD703017AYGC-

×××

-8EU

Notes 1. Connect the IC pin directly to V

2. Applies to the

PD703014AY, 703015AY, and 703017AY only.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

100

P20/SI2

P15/SCK1/ASCK0

P14/SO1/TXD0

P13/SI1/RXD0

P12/SCK0/SCL

Note 2

P11/SO0

P10/SI0/SDA

Note 2

P07/INTP6

P06/INTP5/RTPTRG

P05/INTP4/ADTRG

P04/INTP3

P03/INTP2

P02/INTP1

P01/INTP0

P00/NMI

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P107/RTP7/A12

P110/A1

P111/A2

P112/A3

P113/A4

RESET

P114/XT1

XT2

CLKOUT

P120/WAIT

P90/LBEN/WRL

P91/UBEN

P92/R/W/WRH

P93/DSTB/RD

P94/ASTB

P95/HLDAK

P96/HLDRQ

P40/AD0

P41/AD1

P42/AD2

P43/AD3

P21/SO2

P22/SCK2

P23/RXD1

P24/TXD1

P25/ASCK1

P26/TI2/TO2
P27/TI3/TO3

P30/TI00
P31/TI01
P32/TI10
P33/TI11

P34/TO0/A13
P35/TO1/A14

P36/TI4/TO4/A15

P37/TI5/TO5

Note 1

P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9

P105/RTP5/A10
P106/RTP6/A11

P71/ANI1
P70/ANI0
AV

REF

P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV

P47/AD7
P46/AD6
P45/AD5
P44/AD4

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

121-pin plastic FBGA (12

×
×
×
×

12)

PD703014AF1-

×××

-EA6

PD703015AF1-

×××

-EA6

PD703017AF1-

×××

-EA6

PD703014AYF1-

×××

-EA6

PD703015AYF1-

×××

-EA6

PD703017AYF1-

×××

-EA6

Top View

Bottom View

N M L K J H G F E D C B A

A B C D E F G H J K L M N

Pin
Number

Pin Name

Pin
Number

Pin Name

Pin
Number

Pin Name

Pin
Number

Pin Name

Pin
Number

Pin Name

Pin
Number

Pin Name

P20

P83

G11

P60

K13

P15

P80

G12

P56

P104

B10

P75

D11

G13

P57

P105

P92

P13

B11

D12

P34

RESET

M10

P95

P11

B12

D13

P37

M11

P41

P06

B13

P71

P25

P35

M12

P45

P03

P22

H11

P55

M13

P44

P00

P23

P30

H12

P53

P90

P107

P81

E11

H13

P54

P120

P110

A10

P76

P24

E12

P64

Note

P93

P112

A11

P73

P07

E13

P65

Note

L10

P96

A12

P72

P04

P26

P100

L11

XT1

A13

P01

P27

J11

P52

L12

P21

P82

P33

J12

P50

L13

P14

P77

F11

P63

J13

P51

P106

CLKOUT

C10

P74

F12

P61

P101

P111

P91

P12

C11

F13

P62

P102

P113

N10

P94

P10

C12

P70

P31

P103

N11

P40

P05

C13

REF

P32

K11

P46

XT2

N12

P42

P02

P36

K12

P47

N13

P43

Note

Connect the IC pin directly to V

Remarks 1. Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic

LQFP.

2. Connect the D4 pin directly to V

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

PIN IDENTIFICATION

A1 to A21:

Address Bus

P90 to P96:

Port 9

AD0 to AD15:

Address/Data Bus

P100 to P107:

Port 10

ADTRG:

AD Trigger Input

P110 to P114:

Port 11

ANI0 to ANI11:

Analog Input

P120:

Port 12

ASCK0, ASCK1:

Asynchronous Serial Clock

RD:

Read

ASTB:

Address Strobe

RESET:

Reset

Analog V

RTP0 to RTP7:

Real-time Port

REF

Analog Reference Voltage

RTPTRG:

RTP Trigger

Analog V

R/W:

Read/Write Status

Power Supply for Bus Interface

RXD0, RXD1:

Receive Data

Ground for Bus Interface

SCK0 to SCK2:

Serial Clock

CLKOUT:

Clock Output

SCL

Note

Serial Clock

DSTB:

Data Strobe

SDA

Note

Serial Data

HLDAK:

Hold Acknowledge

SI0 to SI2:

Serial Input

HLDRQ:

Hold Request

SO0 to SO2:

Serial Output

IC:

Internally Connected

TI00, TI01, TI10, :

Timer Input

INTP0 to INTP6:

Interrupt Request From Peripherals

TI11, TI2 to TI5

LBEN:

Lower Byte Enable

TO0 to TO5:

Timer Output

NMI:

Non-maskable Interrupt Request

TXD0, TXD1:

Transmit Data

P00 to P07:

Port 0

UBEN:

Upper Byte Enable

P10 to P15:

Port 1

Power Supply

P20 to P27:

Port 2

Ground

P30 to P37:

Port 3

WAIT:

Wait

P40 to P47:

Port 4

WRH:

Write Strobe High Level Data

P50 to P57:

Port 5

WRL:

Write Strobe Low Level Data

P60 to P65:

Port 6

X1, X2:

Crystal for Main Clock

P70 to P77:

Port 7

XT1, XT2:

Crystal for Sub-clock

P80 to P83:

Port 8

Note

Applies to the

PD703014AY, 703015AY, and 703017AY only.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

INTERNAL BLOCK DIAGRAM

Notes 1.

PD703014A, 703014AY: 64 KB

PD703015A, 703015AY: 128 KB

PD703017A, 703017AY: 256 KB

PD703014A, 703014AY, 703015A, 703015AY: 4 KB

PD703017A, 703017AY: 8 KB

3. Applies to the

PD703014AY, 703015AY, and 703017AY only.

NMI

TI00, TI01,

TI10, TI11

TO0, TO1

SIO

TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5

SO0

SI0/SDA

Note 3

SCK0/SCL

Note 3

INTP0 to INTP6

INTC

CSI0/I

Note 3

SO1/TXD0

SI1/RXD0

SCK1/ASCK0

CSI1/UART0

SO2

SI2

SCK2

CSI2

TXD1

RXD1

ASCK1

Note 1

ALU

CPU

Mask
ROM

Note 2

RAM

HLDRQ (P96)
HLDAK (P95)

ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT

A1 to A12

A13 to A15 (P34 to P36)

A16 to A21 (P60 to P65)

AD0 to AD15

(P40 to P47, P50 to P57)

(P100 to P107, P110 to P113)

P120

P114

P110 to P113

P100 to P107

P90 to P96

P80 to P83

P70 to P77

P60 to P65

P50 to P57

P40 to P47

P30 to P37

P20 to P27

P10 to P15

P00 to P07

RTP0 to RTP7

RTPTRG

REF

ANI0 to ANI11

ADTRG

CLKOUT

XT1 (P114)

XT2

RESET

BCU

Timer/counters

16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM5

DMAC: 3 ch

Watch timer

Watchdog

timer

RTP

A/D

converter

UART1

32-bit

barrel shifter

System

registers

Multiplier

16 x 16 32

General registers

32 bits x 32

Instruction

queue

Port

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

CONTENTS

PIN FUNCTIONS.................................................................................................................................. 8

1.1

Port Pins..................................................................................................................................................... 8

1.2

Non-Port Pins........................................................................................................................................... 11

1.3

Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 14

ELECTRICAL SPECIFICATIONS...................................................................................................... 18

PACKAGE DRAWINGS..................................................................................................................... 42

RECOMMENDED SOLDERING CONDITIONS ............................................................................... 44

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

1. PIN FUNCTIONS

1.1 Port Pins

(1/3)

Pin Name

I/O

PULL

Function

Alternate Function

P00

NMI

P01

INTP0

P02

INTP1

P03

INTP2

P04

INTP3

P05

INTP4/ADTRG

P06

INTP5/RTPTRG

P07

I/O

Yes

Port 0

8-bit I/O port

Input/output can be specified in 1-bit units.

INTP6

P10

SI0/SDA

Note

P11

SO0

P12

SCK0/SCL

Note

P13

SI1/RXD0

P14

SO1/TXD0

P15

I/O

Yes

Port 1

6-bit I/O port

Input/output can be specified in 1-bit units.

SCK1/ASCK0

P20

SI2

P21

SO2

P22

SCK2

P23

RXD1

P24

TXD1

P25

ASCK1

P26

TI2/TO2

P27

I/O

Yes

Port 2

8-bit I/O port

Input/output can be specified in 1-bit units.

TI3/TO3

P30

TI00

P31

TI01

P32

TI10

P33

TI11

P34

TO0/A13

P35

TO1/A14

P36

TI4/TO4/A15

P37

I/O

Yes

Port 3

8-bit I/O port

Input/output can be specified in 1-bit units.

TI5/TO5

Note

Applies to the

PD703014AY, 703015AY, and 703017AY only.

Remark

PULL: On-chip pull-up resistor

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

(2/3)

Pin Name

I/O

PULL

Function

Alternate Function

P40

AD0

P41

AD1

P42

AD2

P43

AD3

P44

AD4

P45

AD5

P46

AD6

P47

I/O

Port 4

8-bit I/O port

Input/output can be specified in 1-bit units.

AD7

P50

AD8

P51

AD9

P52

AD10

P53

AD11

P54

AD12

P55

AD13

P56

AD14

P57

I/O

Port 5

8-bit I/O port

Input/output can be specified in 1-bit units.

AD15

P60

A16

P61

A17

P62

A18

P63

A19

P64

A20

P65

I/O

Port 6

6-bit I/O port

Input/output can be specified in 1-bit units.

A21

P70

ANI0

P71

ANI1

P72

ANI2

P73

ANI3

P74

ANI4

P75

ANI5

P76

ANI6

P77

Input

Port 7

8-bit input port

ANI7

P80

ANI8

P81

ANI9

P82

ANI10

P83

Input

Port 8

4-bit input port

ANI11

Remark

PULL: On-chip pull-up resistor

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

1.2 Non-Port Pins

(1/3)

Pin Name

I/O

PULL

Function

Alternate Function

A1 to A4

P110 to P113

A5 to A12

P100/RTP0 to

P107/RTP7

A13

P34/TO0

A14

P35/TI1

A15

Output

Yes

Low-order address bus used for external memory expansion

P36/TI4/TO4

A16 to A21

Output

High-order address bus used for external memory expansion

P60 to P65

AD0 to AD7

P40 to P47

AD8 to AD15

I/O

16-bit multiplexed address/data bus used for external memory

expansion

P50 to P57

ADTRG

Input

Yes

A/D converter external trigger input

P05/INTP4

ANI0 to ANI7

Input

P70 to P77

ANI8 to ANI11

Input

Analog input to A/D converter

P80 to P83

ASCK0

P15/SCK1

ASCK1

Input

Yes

Serial clock input for UART0 and UART1

P25

ASTB

Output

External address strobe signal output

P94

Positive power supply for A/D converter

REF

Input

Reference voltage input for A/D converter

Ground potential for A/D converter

Positive power supply for bus interface

Ground potential for bus interface

CLKOUT

Output

Internal system clock output

DSTB

Output

External data strobe signal output

P93/RD

HLDAK

Output

Bus hold acknowledge output

P95

HLDRQ

Input

Bus hold request input

P96

INTP0 to INTP3

External interrupt request input (analog noise elimination)

P01 to P04

INTP4

P05/ADTRG

INTP5

P06/RTPTRG

INTP6

Input

Yes

External interrupt request input (digital noise elimination)

P07

LBEN

Output

External data bus's low-order byte enable signal output

P90/WRL

NMI

Input

Yes

Non-maskable interrupt request input

P00

Output

Read strobe signal output

P93/DSTB

RESET

Input

System reset input

RTP0 to RTP7

Output

Yes

Real-time output port

P100/A5 to P107/A12

Remark

PULL: On-chip pull-up resistor

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

(2/3)

Pin Name

I/O

PULL

Function

Alternate Function

RTPTRG

Input

Yes

RTP external trigger input

P06/INTP5

R/W

Output

External read/write status output

P92/WRH

RXD0

P13/SI1

RXD1

Input

Yes

Serial receive data input for UART0 and UART1

P23

SCK0

P12

SCK1

P15/ASCK0

SCK2

Serial clock I/O (3-wire type) for CSI0 to CSI2

P22

SCL

C serial clock I/O

Note

P12/SCK0

SDA

I/O

Yes

C serial transmit/receive data I/O

Note

P10/SI0

SI0

P10

SI1

P13/RXD0

SI2

Input

Yes

Serial receive data input (3-wire type) for CSI0 to CSI2

P20

SO0

P11

SO1

P14/TXD0

SO2

Output

Yes

Serial transmit data output (3-wire type) for CSI0 to CSI2

P21

TI00

External capture trigger input and external count clock input

for TM0

P30

TI01

External capture trigger input for TM0

P31

TI10

External capture trigger input and external count clock input

for TM1

P32

TI11

External capture trigger input for TM1

P33

TI2

External count clock input for TM2

P26/TO2

TI3

External count clock input for TM3

P27/TO3

TI4

External count clock input for TM4

P36/TO4/A15

TI5

Input

Yes

External count clock input for TM5

P37/TO5

TO0, TO1

Pulse signal output for TM0 and TM1

P34/A13, P35/A14

TO2

Pulse signal output for TM2

P26/TI2

TO3

Pulse signal output for TM3

P27/TI3

TO4

Pulse signal output for TM4

P36/TI4/A15

TO5

Output

Yes

Pulse signal output for TM5

P37/TI5

TXD0

P14/SO1

TXD1

Output

Yes

Serial transmit data output for UART0 and UART1

P24

UBEN

Output

High-order byte enable signal output for external data bus

P91

Positive power supply pin

Ground potential

Note

Applies to the

PD703014AY, 703015AY, and 703017AY only.

Remark

PULL: On-chip pull-up resistor

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

1.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are show in Table 1-1. For

the input/output schematic circuit diagram of each type, refer to Figure 1-1.

Table 1-1. Types of Pin I/O Circuits (1/2)

Alternate Function

I/O Circuit Type

Recommended Connection of Unused Pins

P00

NMI

P01 to

P04

INTP0 to INTP3

P05

INTP4/ADTRG

P06

INTP5/RTPTRG

P07

INTP6

8-A

Input:

Connect to V

Output: Leave open

P10

SI0/SDA

Note

10-A

P11

SO0

P12

SCK0/SCL

Note

10-A

P13

SI1/RXD0

8-A

P14

SO1/TXD0

P15

SCK1/ASCK0

10-A

P20

SI2

8-A

P21

SO2

P22

SCK2

10-A

P23

RXD1

8-A

P24

TXD1

5-A

P25

ASCK1

P26, P27

TI2/TO2, TI3/TO3

P30, P31

TI00, TI01

P32, P33

TI10, TI11

8-A

P34, P35

TO0/A13, TO1/A14

5-A

P36

TI4/TO4/A15

P37

TI5/TO5

8-A

Input:

Connect to V

or V

Output: Leave open

P40 to

P47

AD0 to AD7

P50 to

P57

AD8 to AD15

P60 to

P65

A16 to A21

Input:

Connect to BV

or BV

Output: Leave open

P70 to

P77

ANI0 to ANI7

P80 to

P83

ANI8 to ANI11

Connect to AV

or AV

Note

Applies to the

PD703014AY, 703015AY, and 703017AY only.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25°C, V

= 0 V)

Parameter

Symbol

Conditions

Ratings

Unit

0.5 to +4.6

0.5 to +0.5

Supply voltage

0.5 to +0.5

Note 1

0.5 to V

+ 0.5

Note 4

Input voltage

Note 2

0.5 to BV

+ 0.5

Note 4

Clock input voltage

X1, XT1, V

= 2.7 to 3.6 V

0.5 to V

+ 1.0

Note 4

Analog input voltage

IAN

Note 3 (AV

)

0.5 to AV

+ 0.5

Note 4

Analog reference input voltage

REF

0.5 to AV

+ 0.5

Note 4

Per pin

4.0

Total for P00 to P07, P10 to P15, P20 to

P25

Total for P26, P27, P30 to P37, P100 to

P107, P110 to P113

Total for P40 to P47, P90 to P96, P120,

CLKOUT

Output current, low

Total for P50 to P57, P60 to P65

Per pin

4.0

Total for P00 to P07, P10 to P15, P20 to

P25

Total for P26, P27, P30 to P37, P100 to

P107, P110 to P113

Total for P40 to P47, P90 to P96, P120,

CLKOUT

Output current, high

Total for P50 to P57, P60 to P65

Note 1, V

= 2.7 to 3.6 V

0.5 to V

+ 0.5

Note 4

Output voltage

Note 2, BV

= 2.7 to 3.6 V

0.5 to BV

+ 0.5

Note 4

Operating ambient temperature

40 to +85

Storage temperature

stg

65 to +150

Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, RESET, and their alternate-function pins.

2. Ports 4, 5, 6, 9, CLKOUT, and their alternate-function pins.

3. Ports 7, 8, and their alternate-function pins.

4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.

Cautions

1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V

, V

and GND. Open-drain pins or open-collector pins, however, can be directly connected to

each other. Direct connection of the output pins between an IC product and an external

circuit is possible, if the output pins can be set to the high-impedance state and the output

timing of the external circuit is designed to avoid output conflict.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product

is on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions indicated for DC characteristics and AC characteristics represent

the quality assurance range during normal operation.

Capacitance (T

= 25°C, V

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

I/O capacitance

Output capacitance

= 1 MHz

Unmeasured pins returned to 0 V

Operating Conditions

Internal Operation Clock Frequency

Supply Voltage (V

)

Operating Ambient Temperature (T

)

2 MHz

17 MHz

2.7 to 3.6 V

40 to +85°C

2 MHz

20 MHz

3.0 to 3.6 V

40 to +85°C

= 32.768 kHz

2.7 to 3.6 V

40 to +85°C

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Recommended Oscillator

(1) Main system clock oscillator (T

= 40 to +85°C)

(a) Connection of ceramic resonator or crystal resonator

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 2.7 to 3.6 V

MHz

Oscillation frequency

= 3.0 to 3.6 V

MHz

Upon reset release

Oscillation stabilization time

Upon STOP mode release

Note

Note The TYP value differs depending on the setting of the oscillation stabilization time select register (OSTS).

Caution Ensure that the duty of oscillation waveform is between 45% and 55%.

Remarks 1.

Connect the oscillator as close as possible to the X1 and X2 pins.

Do not route the wiring near broken lines.

Sufficiently evaluate the matching between the oscillator and resonator.

(b) External clock input

High-speed CMOS inverter

External clock

Open

Cautions

1. Connect the high-speed CMOS inverter as close as possible to the X1 pin.

2. Sufficiently evaluate the matching between the

µ
µ
µ
µ

PD703014A, 703014AY, 703015A,

703015AY, 703017A, 703017AY and the high-speed CMOS inverter.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

(2) Subsystem clock oscillator (T

= 40 to +85°C)

(a) Connection of crystal resonator

XT1

XT2

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Oscillation frequency

32.768

kHz

Oscillation stabilization time

Remarks 1.

Connect the oscillator as close as possible to the XT1 and XT2 pins.

Do not route the wiring near broken lines.

Sufficiently evaluate the matching between the oscillator and resonator.

(b) External clock input

XT1

XT2

High-speed CMOS inverter

Cautions

1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin.

2. Sufficiently evaluate the matching between the

µ
µ
µ
µ

PD703014A, 703014AY, 703015A,

703015AY, 703017A, 703017AY and the high-speed CMOS inverter.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

DC Characteristics

(1) Operating conditions (T

= 40 to +85°C, V

= AV

= BV

= 2.7 to 3.6 V, V

= AV

= BV

= 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

IH1

Pins other than below

0.7V

IH2

Note 1

0.7AV

IH3

Note 2

0.75V

Input voltage, high

IH4

X1, XT1 (P114), XT2

0.8V

IL1

Pins other than below

0.3V

IL2

Note 1

0.3AV

IL3

Note 2

0.2V

Input voltage, low

IL4

X1, XT1 (P114), XT2

0.2V

OH1

Note 3

= 3 mA

0.8V

Output voltage, high

OH2

Note 4

= 1 mA

0.8V

OL1

Note 3

= 1.6 mA

0.4

OL2

Note 4

(Except pins

P10 and P12)

= 1.6 mA

0.4

Output voltage, low

OL3

P10, P12

= 3 mA

0.4

Pins other than below

Input leakage current, high

LIH

= V

= AV

= BV

X1, XT1, XT2

Pins other than below

Input leakage current, low

LIL

= 0 V

X1, XT1, XT2

Output leakage current, high

LOH

= V

= AV

= BV

Output leakage current, low

LOL

= 0 V

DD1

Normal

operation

= 17 MHz

All peripheral functions

operating

DD2

HALT mode

= 17 MHz

All peripheral functions

operating

DD3

IDLE mode

= 17 MHz

Watch timer operating

STOP mode (subsystem oscillator, watch

timer operating)

Supply current

Note 5

DD4

STOP mode (subsystem oscillator

stopped (XT1 = V

))

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

(1) Operating conditions (T

= 40 to +85°C, V

= AV

= BV

= 2.7 to 3.6 V, V

= AV

= BV

= 0 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

DD5

Subsystem clock normal operation mode

= 32.768 kHz (main system clock

stopped)

140

Supply current

Note 5

DD6

Subsystem clock IDLE mode

= 32.768 kHz (main system clock

stopped, watch timer operating)

Pull-up resistance

= 0 V

100

Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.

2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their

alternate-function pins.

3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.

4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternate-

function pins.

5. The TYP. value of V

is 3.3 V. The current consumed by the output buffer is not included.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

(2) Operating conditions (T

= 40 to +85°C, V

= AV

= BV

= 3.0 to 3.6 V, V

= AV

= BV

= 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

IH1

Pins other than below

0.7V

IH2

Note 1

0.7AV

IH3

Note 2

0.75V

Input voltage, high

IH4

X1, XT1 (P114), XT2

0.8V

IL1

Pins other than below

0.3V

IL2

Note 1

0.3AV

IL3

Note 2

0.2V

Input voltage, low

IL4

X1, X2, XT1 (P114), XT2

0.2V

OH1

Note 3

= 3 mA

0.8V

Output voltage, high

OH2

Note 4

= 1 mA

0.8V

OL1

Note 3

= 1.6 mA

0.4

OL2

Note 4

(Except pins

P10 and P12)

= 1.6 mA

0.4

Output voltage, low

OL3

P10, P12

= 3 mA

0.4

Pins other than below

Input leakage current, high

LIH

= V

= AV

= BV

X1, XT1, XT2

Pins other than below

Input leakage current, low

LIL

= 0 V

X1, XT1, XT2

Output leakage current, high

LOH

= V

Output leakage current, low

LOL

= 0 V

DD1

Normal

operation

= 20 MHz

All peripheral functions

operating

DD2

HALT mode

= 20 MHz

All peripheral functions

operating

DD3

IDLE mode

= 20 MHz

Watch timer operating

1.2

4.5

STOP mode (subsystem oscillator, watch

timer operating)

Supply current

Note 5

DD4

STOP mode (subsystem oscillator

stopped (XT1 = V

))

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

(2) Operating conditions (T

= 40 to +85°C, V

= AV

= BV

= 3.0 to 3.6 V, V

= AV

= BV

= 0 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

DD5

Subsystem clock normal operation mode

= 32.768 kHz (main system clock

stopped)

140

Supply current

Note 5

DD6

Subsystem clock IDLE mode

= 32.768 kHz (main system clock

stopped, watch timer operating)

Pull-up resistance

= 0 V

100

Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.

2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET and their

alternate-function pins.

3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.

4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternate-

function pins.

5. The TYP. value of V

is 3.3 V. The current consumed by the output buffer is not included.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Data Retention Characteristics (T

= 40 to +85°C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention voltage

DDDR

STOP mode

1.8

3.6

Data retention current

DDDR

[V]

Supply voltage rise time

RVD

200

Supply voltage fall time

FVD

200

Supply voltage hold time

(from STOP mode setting)

HVD

STOP release signal input time

DREL

Data retention high-level input voltage

IHDR

All input ports

IHn

DDDR

Data retention low-level input voltage

ILDR

All input ports

ILn

Remarks 1.

TYP. values are reference values for when T

= 25°C.

n = 1 to 4

Setting STOP mode

HVD

FVD

RESET

(input)

NMI, INTP0 to INTP3

(input)

NMI, INTP0 to INTP3 (input)

(when STOP mode is released

at rising edge)

RVD

DREL

DDDR

IHDR

ILDR

IHDR

Caution

Shifting to STOP mode and restoring from STOP mode must be performed at V

= 2.7 V min.

= 17 MHz) and V

= 3.0 V min. (f

= 20 MHz), respectively.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Clock Timing

(1) Operating conditions (T

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load

capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

X1 input cycle

58.8

XT1 input cycle

CYX

<1>

28.5

X1 input high-level width

26.4

XT1 input high-level width

WXH

<2>

12.8

X1 input low-level width

26.4

XT1 input low-level width

WXL

<3>

12.8

X1 input rise time

<4>

0.5 (t

CYX

WXH

WXL

)

X1 input fall time

<5>

0.5 (t

CYX

WXH

WXL

)

CLKOUT output cycle

CYK

<6>

58.8 ns

31.2

CLKOUT high-level width

WKH

<7>

0.4t

CYK

CLKOUT low-level width

WKL

<8>

0.4t

CYK

CLKOUT rise time

<9>

CLKOUT fall time

<10>

Remarks 1.

T = t

CYK

Ensure that the duty is between 45% and 55%.

(2) Operating conditions (T

= 40 to +85°C, V

= BV

= 3.0 to 3.6 V, V

= BV

= 0 V, Output pin load

capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

X1 input cycle

50.0

XT1 input cycle

CYX

<1>

28.5

X1 input high-level width

22.5

XT1 input high-level width

WXH

<2>

12.8

X1 input low-level width

22.5

XT1 input low-level width

WXL

<3>

12.8

X1 input rise time

<4>

0.5 (t

CYX

WXH

WXL

)

X1 input fall time

<5>

0.5 (t

CYX

WXH

WXL

)

CLKOUT output cycle

CYK

<6>

50.0 ns

31.2

CLKOUT high-level width

WKH

<7>

0.4t

CYK

CLKOUT low-level width

WKL

<8>

0.4t

CYK

CLKOUT rise time

<9>

CLKOUT fall time

<10>

Remarks 1.

T = t

CYK

Ensure that the duty is between 45% and 55%.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Clock Timing

X1, XT1 (input)

CLKOUT (output)

<2>

<4>

<5>

<1>

<3>

<7>

<9>

<10>

<8>

<6>

(1) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9

= 40 to +85

°
°
°
°

C, V

= BV

= 2.7 to 3.6 V, V

= BV

0 V, Output pin load capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Output rise time

<11>

Output fall time

<12>

(2) Timing of pins other than CLKOUT, ports 4, 5, 6, and 9

= 40 to +85

°
°
°
°

C, V

= BV

= 3.0 to 3.6 V, V

= BV

0 V, Output pin load capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Output rise time

<11>

Output fall time

<12>

0.8V

0.4 V

Output signal

<12>

<11>

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Bus Timing (CLKOUT Asynchronous)

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Address setup time (to ASTB

)

SAST

<13>

0.5T

Address hold time (from ASTB

)

HSTA

<14>

0.5T

Address float from DSTB

FDA

<15>

Data input setup time from address

SAID

<16>

(2 + n)T 25

Data input setup time from DSTB

SDID

<17>

(1 + n)T 25

Delay time from ASTB

to DSTB

DSTD

<18>

0.5T

Data input hold time (from DSTB

)

HDID

<19>

Address output time from DSTB

DDA

<20>

(1 + i)T 15

Delay time from DSTB

to ASTB

DDST1

<21>

0.5T 15

Delay time from DSTB

to ASTB

DDST2

<22>

(1.5 + i)T 15

DSTB low-level width

WDL

<23>

(1 + n)T 15

ASTB high-level width

WSTH

<24>

T 15

Data output time from DSTB

DDOD

<25>

Data output setup time (to DSTB

)

SODD

<26>

(1 + n)T 20

Data output hold time (from DSTB

)

HDOD

<27>

T 15

SAWT1

<28>

1.5T 25

WAIT setup time (to address)

SAWT2

<29>

(1.5 + n)T 25

HAWT1

<30>

(0.5 + n)T

WAIT hold time (from address)

HAWT2

<31>

(1.5 + n)T

SSTWT1

<32>

T 25

WAIT setup time (to ASTB

)

SSTWT2

<33>

(1 + n)T 25

HSTWT1

<34>

WAIT hold time (from ASTB

)

HSTWT2

<35>

(1 + n)T

HLDRQ high-level width

WHQH

<36>

T + 10

HLDAK low-level width

WHAL

<37>

T 15

Bus output delay time from HLDAK

DHAC

<38>

Delay time from HLDRQ

to HLDAK

DHQHA1

<39>

(2n + 7.5)T + 25

Delay time from HLDRQ

to HLDAK

DHQHA2

<40>

0.5T

1.5T + 25

Remarks 1.

T = 1/f

CPU

: CPU operation clock frequency)

n: Number of wait clocks inserted in the bus cycle.

The sampling timing changes when a programmable wait is inserted.

i: Number of idle states inserted after the read cycle (0 or 1).

The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from

X1.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Bus Timing (CLKOUT Synchronous)

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Delay time from CLKOUT

to address

DKA

<41>

Delay time from CLKOUT

to address

float

FKA

<42>

Delay time from CLKOUT

to ASTB

DKST

<43>

Delay time from CLKOUT

to DSTB

DKD

<44>

Data input setup time (to CLKOUT

)

SIDK

<45>

Data input hold time (from CLKOUT

)

HKID

<46>

Data output delay time from CLKOUT

DKOD

<47>

WAIT setup time (to CLKOUT

)

SWTK

<48>

WAIT hold time (from CLKOUT

)

HKWT

<49>

HLDRQ setup time (to CLKOUT

)

SHQK

<50>

HLDRQ hold time (from CLKOUT

)

HKHQ

<51>

Delay time from CLKOUT

to bus float

DKF

<52>

Delay time from CLKOUT

to HLDAK

DKHA

<53>

Remark

The values in the above specifications are values for when clocks with a 5:5 duty ratio are input from X1.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Reset/Interrupt Timing

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

RESET high-level width

WRSH

<54>

500

RESET low-level width

WRSL

<55>

500

NMI high-level width

WNIH

<56>

500

NMI low-level width

WNIL

<57>

500

n = 0 to 3 (analog noise
elimination)

500

INTPn high-level width

WITH

<58>

n = 4 to 6 (digital noise
elimination)

3T + 20

n = 0 to 3 (analog noise
elimination)

500

INTPn low-level width

WITL

<59>

n = 4 to 6 (digital noise
elimination)

3T + 20

Remark

T = 1/f

Reset

<54>

<55>

RESET (input)

Interrupt

<56>

<57>

NMI (input)

<58>

<59>

INTPn (input)

Remark n = 0 to 6

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

TIn Input Timing

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

TIn0, TIn1 high-level width

n = 0, 1

sam

+ 20

Note

TIn high-level width

TIHn

<60>

n = 2 to 5

3T + 20

TIn0, TIn1 low-level width

n = 0, 1

sam

+ 20

Note

TIn low-level width

TILn

<61>

n = 2 to 5

3T + 20

Note T

sam

(count clock cycle) can be selected from the following by setting the PRMn2 to PRMn0 bits of prescaler

mode register n, n1 (PRMn, PRMn1).

For n = 0 (TM0): T

sam

= 2T, 4T, 16T, 64T, 256T, or 1/INTWTI cycle

For n = 1 (TM1): T

sam

= 2T, 4T, 16T, 32T, 128T, or 256T cycle

However, when the TIn0 valid edge is selected as the count clock cycle, T

sam

= 2T.

Remark T = 1/f

<60>

<61>

Tln

Remark

n = 00, 01, 10, 11, 2 to 5

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

CSI Timing

(1) Master mode (T

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load capacitance:

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCKn cycle time

KCY1

<62>

400

SCKn high-/low-level width

KH1

, t

KL1

<63>

140

SIn setup time (to SCKn

)

SIK1

<64>

SIn hold time (from SCKn

)

KSI1

<65>

Delay time from SCKn

to SOn output

KSO1

<66>

Remark n = 0 to 2

(2) Slave mode (T

= 40 to +85°C, V

= BV

= 2.7 to 3.6 V, V

= BV

= 0 V, Output pin load capacitance:

= 50 pF)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCKn cycle time

KCY2

<62>

400

SCKn high-/low-level width

KH2

, t

KL2

<63>

140

SIn setup time (to SCKn

)

SIK2

<64>

SIn hold time (from SCKn

)

KSI2

<65>

Delay time from SCKn

to SOn output

KSO2

<66>

Remark n = 0 to 2

<65>

<66>

<64>

<62>

<63>

Remark n = 0 to 2

SCKn (I/O)

SIn (input)

SOn (output)

Input data

Output data

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

C Bus Mode (

µ
µ
µ
µ

PD703014AY, 703015AY, 703017AY only)

= 40 to +85°C, V

= 2.7 to 3.6 V, V

= 0 V)

Normal Mode

High-Speed Mode

Parameter

Symbol

MIN.

MAX.

MIN.

MAX.

Unit

SCL clock frequency

CLK

100

400

kHz

Bus-free time (between

stop/start conditions)

BUF

<70>

4.7

1.3

Hold time

Note 1

HD:STA

<71>

4.0

0.6

SCL clock low-level width

LOW

<72>

4.7

1.3

SCL clock high-level width

HIGH

<73>

4.0

0.6

Setup time for start/restart

conditions

SU:STA

<74>

4.7

0.6

CBUS

compatible

master

5.0

Data hold

time

C mode

HD:DAT

<75>

Note 2

0.9

Note 3

Data setup time

SU:DAT

<76>

250

100

Note 4

SDA and SCL signal rise

time

<77>

1000

20 + 0.1Cb

Note 5

300

SDA and SCL signal fall

time

<78>

300

20 + 0.1Cb

Note 5

300

Stop condition setup time

SU:STO

<79>

4.0

0.6

Capacitance load of each

bus line

400

Notes 1. At the start condition, the first clock pulse is generated after the hold time.

2. The system requires a minimum of 300 ns hold time internally for the SDA signal (at V

IHmin.

of SCL

signal) in order to occupy the undefined area at the falling edge of SCL.

3. If the system does not extend the SCL signal low hold time (t

LOW

), only the maximum data hold time (t

DAT

) needs to be satisfied.

4. The high-speed mode I

C bus can be used in the normal-mode I

C bus system. In this case, set the

high-speed mode I

C bus so that it meets the following conditions.

If the system does not extend the SCL signal's low state hold time:

DAT

250 ns

If the system extends the SCL signal's low state hold time:

Transmit the following data bit to the SDA line prior to the SCL line release (t

Rmax.

+ t

DAT

= 1000 +

250 = 1250 ns: Normal mode I

C bus specification).

5. Cb: Total capacitance of one bus line (unit: pF)

Remark The maximum operating frequency of the

PD703014AY, 703015AY, and 703017AY is 17 MHz.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

C Bus Mode (

µ
µ
µ
µ

PD703014AY, 703015AY, 703017AY only)

Restart
condition

Stop
condition

SCL (I/O)

SDA (I/O)

Stop
condition

Start
condition

<72>

<73>

<78> <77>

<71>

<77>

<78>

<75>

<76>

<74>

<71>

<79>

<70>

A/D Converter (T

= 40 to +85°C, V

= AV

REF

= 2.7 to 3.6 V, V

= AV

= 0 V, Output pin load

capacitance: C

= 50 pF)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

Note 1

0.8

%FSR

Conversion time

CONV

100

Zero-scale error

Note 1

0.4

%FSR

Full-scale error

Note 1

0.4

%FSR

Integral linearity error

Note 2

LSB

Differential linearity error

Note 2

LSB

Analog reference voltage

REF

2.7

3.6

Analog input voltage

IAN

REF

current

REF

360

500

Power supply current

Notes 1. Excluding quantization error (

0.05 %FSR)

2. Excluding quantization error (

0.5 LSB)

Remark LSB: Least Significant Bit

FSR: Full Scale Range

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

4. RECOMMENDED SOLDERING CONDITIONS

The

PD703014A, 703014AY, 703015A, 703015AY, 703017A, and 703017AY should be soldered and mounted

under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 4-1. Surface Mounting Type Soldering Conditions

(1)

µ
µ
µ
µ

PD703014AGC-

×××

-8EU: 100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD703014AYGC-

×××

-8EU: 100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD703015AGC-

×××

-8EU: 100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD703015AYGC-

×××

-8EU: 100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD703017AGC-

×××

-8EU: 100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD703017AYGC-

×××

-8EU: 100-pin plastic LQFP (fine-pitch) (14

×
×
×
×

14)

Soldering Method

Soldering Conditions

Recommended

Condition

Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Two times or less

Exposure limit: 7 days

Note

(after that, prebake at 125°C for 10 hours)

IR35-107-2

VPS

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: Two times or less

Exposure limit: 7 days

Note

(after that, prebake at 125°C for 10 hours)

VP15-107-2

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution

Do not use different soldering methods together (except for partial heating).

(2)

µ
µ
µ
µ

PD703014AF1-

×××

-EA6: 121-pin plastic FBGA (12

×
×
×
×

12)

µ
µ
µ
µ

PD703014AYF1-

×××

-EA6: 121-pin plastic FBGA (12

×
×
×
×

12)

µ
µ
µ
µ

PD703015AF1-

×××

-EA6: 121-pin plastic FBGA (12

×
×
×
×

12)

µ
µ
µ
µ

PD703015AYF1-

×××

-EA6: 121-pin plastic FBGA (12

×
×
×
×

12)

µ
µ
µ
µ

PD703017AF1-

×××

-EA6: 121-pin plastic FBGA (12

×
×
×
×

12)

µ
µ
µ
µ

PD703017AYF1-

×××

-EA6: 121-pin plastic FBGA (12

×
×
×
×

12)

Soldering Method

Soldering Conditions

Recommended

Condition

Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Two times or less

Exposure limit: 7 days

Note

(after that, prebake at 125°C for 10 hours)

IR35-107-2

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Caution

Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use

these components in an I

C system, provided that the system conforms to the I

C Standard

Specification as defined by Philips.

Reference document

Electrical Characteristics for Microcomputer (IEI-601)

Note

This document number is that of the Japanese version.

Related document

PD70F3017A, 70F3017AY Data Sheet (U14527E)

V850 Family and V850/SA1 are trademarks of NEC Corporation.

Data Sheet U14526EJ2V0DS00

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829

J00.7

µ
µ
µ
µ

PD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

M8E 00. 4

The information in this document is current as of June, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

Document Outline

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