Document Outline
- COVER
- FEATURES
- APPLICATIONS
- ORDERING INFORMATION
- PIN CONFIGURATION
- PIN NAMES
- INTERNAL BLOCK DIAGRAM
- 1. DIFFERENCES AMONG PRODUCTS
- 2. PIN FUNCTIONS
- 2.1 Port Pins
- 2.2 Non-Port Pins
- 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
- 3. ELECTRICAL SPECIFICATIONS
- 4. PACKAGE DRAWING
- 5. RECOMMENDED SOLDERING CONDITIONS
1998
DATA SHEET
PD703003A, 703004A, 703025A
MOS INTEGRATED CIRCUIT
The
PD703003A, 703004A, and 703025A are members of the V850 Family
TM
of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features including a 32-bit CPU
core, ROM, RAM, an interrupt controller, a real-time pulse unit, a serial interface, an A/D converter, a D/A converter,
and PWM.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
V853 User's Manual Hardware:
U10913E
V850 Family User's Manual Architecture:
U10243E
FEATURES
Number of instructions: 74
Minimum instruction execution time: 30 ns (@ 33 MHz operation)
General-purpose registers: 32 bits
32 registers
Instruction set optimized for control applications
On-chip memory
ROM: 256 KB (
PD703025A)
128 KB (
PD703003A)
96 KB (
PD703004A)
RAM:
8 KB (
PD703025A)
4 KB (
PD703003A, 703004A)
Advanced on-chip interrupt controller
Real-time pulse unit suitable for control operations
Powerful serial interface (on-chip dedicated baud rate generator)
On-chip clock generator
10-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
8-/9-/10-/12-bit resolution PWM: 2 channels
Power saving functions
APPLICATIONS
AV: Camcorders, VCRs, etc.
Office equipment: PPCs, LBPs, printers, etc.
Industrial equipment: Motor controllers, NC machine tools, etc.
Communications equipment: Mobile telephones, etc.
V853
TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Document No. U13188EJ4V0DS00 (4th edition)
Date Published July 2000 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark shows major revised points.
PD703003A, 703004A, 703025A
2
Data Sheet U13188EJ4V0DS00
ORDERING INFORMATION
Part Number
Package
Maximum
Internal Internal
Operating
ROM
RAM
Frequency (MHz) (Bytes)
(Bytes)
PD703003AGC-25-xxx-8EU
100-pin plastic LQFP (fine pitch) (14
14 mm)
25
128 K
4 K
PD703003AGC-33-xxx-8EU
100-pin plastic LQFP (fine pitch) (14
14 mm)
33
128 K
4 K
PD703004AGC-25-xxx-8EU
100-pin plastic LQFP (fine pitch) (14
14 mm)
25
96 K
4 K
PD703004AGC-33-xxx-8EU
100-pin plastic LQFP (fine pitch) (14
14 mm)
33
96 K
4 K
PD703025AGC-25-xxx-8EU
100-pin plastic LQFP (fine pitch) (14
14 mm)
25
256 K
8 K
PD703025AGC-33-xxx-8EU
100-pin plastic LQFP (fine pitch) (14
14 mm)
33
256 K
8 K
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION
100-pin plastic LQFP (fine pitch) (14
14 mm)
PD703003AGC-25-xxx-8EU
PD703004AGC-33-xxx-8EU
PD703003AGC-33-xxx-8EU
PD703025AGC-25-xxx-8EU
PD703004AGC-25-xxx-8EU
PD703025AGC-33-xxx-8EU
Caution Connect the IC (Internally Connected) pin directly to V
SS
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
ANO1
AV
REF2
AV
REF3
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141
P31/TO131
P32/TCLR13
P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
P62/A18
P61/A17
P60/A16
V
SS
V
DD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
V
SS
V
DD
P41/AD1
P40/AD0
P90/LBEN
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
WAIT
IC
MODE
RESET
CV
DD
/CKSEL
X2
X1
CV
SS
CLKOUT
V
SS
V
DD
P110/TO140
P30/TO130
P27/SCK1
P26/RXD1/SI1
P25/TXD1/SO1
P24/SCK0
P23/RXD0/SI0
P22/TXD0/SO0
P21/PWM1
P20/PWM0
NMI
V
DD
V
SS
P17/INTP123/SCK2
P16/INTP122/SI2
P15/INTP121/SO2
P14/INTP120
P13/TI12
P12/TCLR12
P11/TO121
P10/TO120
AV
DD
AV
SS
AV
REF1
P77/ANI7
P76/ANI6
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
3
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
PIN NAMES
A16 to A19:
Address Bus
P30 to P37:
Port 3
AD0 to AD15:
Address/Data Bus
P40 to P47:
Port 4
ADTRG:
AD Trigger Input
P50 to P57:
Port 5
ANI0 to ANI7:
Analog Input
P60 to P63:
Port 6
ANO0, ANO1:
Analog Output
P70 to P77:
Port 7
ASTB:
Address Strobe
P90 to P96:
Port 9
AV
DD
:
Analog Power Supply
P110 to P117:
Port 11
AV
REF1
to AV
REF3
:
Analog Reference Voltage
PWM0, PWM1:
Pulse Width Modulation
AV
SS
:
Analog Ground
RESET:
Reset
CV
DD
:
Power Supply for Clock Generator
R/W:
Read/Write Status
CV
SS
:
Ground for Clock Generator
RXD0, RXD1:
Receive Data
CKSEL:
Clock Select
SCK0 to SCK3:
Serial Clock
CLKOUT:
Clock Output
SI0 to SI3:
Serial Input
DSTB:
Data Strobe
SO0 to SO3:
Serial Output
HLDAK:
Hold Acknowledge
TO110, TO111,:
Timer Output
HLDRQ:
Hold Request
TO120, TO121,
IC:
Internally Connected
TO130, TO131,
INTP110 to INTP113,: Interrupt Request from Peripherals
TO140, TO141
INTP120 to INTP123,
TCLR11 to TCLR14: Timer Clear
INTP130 to INTP133,
TI11 to TI14:
Timer Input
INTP140 to INTP143
TXD0, TXD1:
Transmit Data
LBEN:
Lower Byte Enable
UBEN:
Upper Byte Enable
MODE:
Mode
WAIT:
Wait
NMI:
Non-maskable Interrupt Request
X1, X2:
Crystal
P00 to P07:
Port 0
V
DD
:
Power Supply
P10 to P17:
Port 1
V
SS
:
Ground
P20 to P27:
Port 2
PD703003A, 703004A, 703025A
4
Data Sheet U13188EJ4V0DS00
INTERNAL BLOCK DIAGRAM
Notes 1.
PD703003A:
128 KB
PD703004A:
96 KB
PD703025A:
256 KB
2.
PD703003A, 703004A: 4 KB
PD703025A:
8 KB
NMI
TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141
INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143
TCLR11 to TCLR14
TI11 to TI14
INTC
RPU
SIO
Mask ROM
RAM
Note 2
Note 1
CPU
PC
32-bit
barrel shifter
System
registers
General-purpose
registers
32 bits
32
ALU
Multiplier
16
16
32
Port
P110 to P117
P90 to P96
P70 to P77
P60 to P63
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P17
P00 to P07
CG
BCU
Instruction
queue
ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A19
AD0 to AD15
HLDRQ
HLDAK
CLKOUT
X1
X2
MODE
RESET
UART0/CSI0
BRG0
UART1/CSI1
BRG1
CSI2
BRG2
CSI3
PWM
SO0/TXD0
SI0/RXD0
SCK0
SO1/TXD1
SI1/RXD1
SCK1
SO2
SI2
SCK2
SO3
SI3
SCK3
PWM0, PWM1
A/D
converter
ANI0 to ANI7
AV
REF1
AV
SS
AV
DD
ADTRG
D/A
converter
ANO0, ANO1
AV
REF2
, AV
REF3
V
DD
V
SS
CV
DD
CV
SS
CKSEL
5
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
CONTENTS
1.
DIFFERENCES AMONG PRODUCTS ............................................................................................
6
2.
PIN FUNCTIONS ..............................................................................................................................
7
2.1
Port Pins ................................................................................................................................
7
2.2
Non-Port Pins ........................................................................................................................
9
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins ....................................
11
3.
ELECTRICAL SPECIFICATIONS ....................................................................................................
14
4.
PACKAGE DRAWING .....................................................................................................................
36
5.
RECOMMENDED SOLDERING CONDITIONS ...............................................................................
37
PD703003A, 703004A, 703025A
6
Data Sheet U13188EJ4V0DS00
1. DIFFERENCES AMONG PRODUCTS
Item
PD703003
PD703003A
PD703004A
PD703025A
PD70F3003
PD70F3003A
PD70F3025A
Internal ROM
Mask ROM
Flash memory
128 KB
96 KB
256 KB
128 KB
256 KB
Internal RAM
4 KB
8 KB
4 KB
8 KB
Operation Normal
Single-chip Implemented
mode
operation
mode
mode
ROM-less
Implemented Not implemented
Implemented Not implemented
mode
Flash memory
Not implemented
Implemented
programming mode
V
PP
pin
Not implemented
Implemented
Value of CKC register after reset
00H
MODE = 0: 03H
00H
MODE = 0: 03H
MODE = 1: 00H
MODE = 1: 00H
Electrical specifications
Power consumption levels vary (see specific product's data sheet).
Other
Depending on the products, noise tolerance and noise emission will vary due to the
differences in circuit scale and mask layout.
7
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
I/O
Function
Alternate Function
P00
I/O
Port 0
TO110
P01
8-bit I/O port
TO111
P02
Input/output can be specified in 1-bit units.
TCLR11
P03
TI11
P04
INTP110
P05
INTP111
P06
INTP112
P07
INTP113/ADTRG
P10
I/O
Port 1
TO120
P11
8-bit I/O port
TO121
P12
Input/output can be specified in 1-bit units.
TCLR12
P13
TI12
P14
INTP120
P15
INTP121/SO2
P16
INTP122/SI2
P17
INTP123/SCK2
P20
I/O
Port 2
PWM0
P21
8-bit I/O port
PWM1
P22
Input/output can be specified in 1-bit units.
TXD0/SO0
P23
RXD0/SI0
P24
SCK0
P25
TXD1/SO1
P26
RXD1/SI1
P27
SCK1
P30
I/O
Port 3
TO130
P31
8-bit I/O port
TO131
P32
Input/output can be specified in 1-bit units.
TCLR13
P33
TI13
P34
INTP130
P35
INTP131/SO3
P36
INTP132/SI3
P37
INTP133/SCK3
P40 to P47
I/O
Port 4
AD0 to AD7
8-bit I/O port
Input/output can be specified in 1-bit units.
P50 to P57
I/O
Port 5
AD8 to AD15
8-bit I/O port
Input/output can be specified in 1-bit units.
PD703003A, 703004A, 703025A
8
Data Sheet U13188EJ4V0DS00
(2/2)
Pin Name
I/O
Function
Alternate Function
P60 to P63
I/O
Port 6
A16 to A19
4-bit I/O port
Input/output can be specified in 1-bit units.
P70 to P77
Input
Port 7
ANI0 to ANI7
8-bit input port
P90
I/O
Port 9
LBEN
P91
7-bit I/O port
UBEN
P92
Input/output can be specified in 1-bit units.
R/W
P93
DSTB
P94
ASTB
P95
HLDAK
P96
HLDRQ
P110
I/O
Port 11
TO140
P111
8-bit I/O port
TO141
P112
Input/output can be specified in 1-bit units.
TCLR14
P113
TI14
P114
INTP140
P115
INTP141
P116
INTP142
P117
INTP143
9
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
2.2 Non-Port Pins
(1/2)
Pin Name
I/O
Function
Alternate Function
TO110
Output
Pulse signal output from timers 11 to 14
P00
TO111
P01
TO120
P10
TO121
P11
TO130
P30
TO131
P31
TO140
P110
TO141
P111
TCLR11
Input
External clear signal input for timers 11 to 14
P02
TCLR12
P12
TCLR13
P32
TCLR14
P112
TI11
Input
External count clock input for timers 11 to 14
P03
TI12
P13
TI13
P33
TI14
P113
INTP110
Input
External maskable interrupt request input, also used as external capture
P04
INTP111
trigger input for timer 11
P05
INTP112
P06
INTP113
P07/ADTRG
INTP120
Input
External maskable interrupt request input, also used as external capture
P14
INTP121
trigger input for timer 12
P15/SO2
INTP122
P16/SI2
INTP123
P17/SCK2
INTP130
Input
External maskable interrupt request input, also used as external capture
P34
INTP131
trigger input for timer 13
P35/SO3
INTP132
P36/SI3
INTP133
P37/SCK3
INTP140
Input
External maskable interrupt request input, also used as external capture
P114
INTP141
trigger input for timer 14
P115
INTP142
P116
INTP143
P117
SO0
Output
Serial transmit data output (3-wire) for CSI0 to CSI3
P22/TXD0
SO1
P25/TXD1
SO2
P15/INTP121
SO3
P35/INTP131
SI0
Input
Serial receive data input (3-wire) for CSI0 to CSI3
P23/RXD0
SI1
P26/RXD1
SI2
P16/INTP122
SI3
P36/INTP132
PD703003A, 703004A, 703025A
10
Data Sheet U13188EJ4V0DS00
(2/2)
Pin Name
I/O
Function
Alternate Function
SCK0
I/O
Serial clock I/O (3-wire) for CSI0 to CSI3
P24
SCK1
P27
SCK2
P17/INTP123
SCK3
P37/INTP133
TXD0
Output
Serial transmit data output for UART0 and UART1
P22/SO0
TXD1
P25/SO1
RXD0
Input
Serial receive data input for UART0 and UART1
P23/SI0
RXD1
P26/SI1
PWM0
Output
PWM pulse signal output
P20
PWM1
P21
AD0 to AD7
I/O
16-bit multiplexed address/data bus for external memory expansion
P40 to P47
AD8 to AD15
P50 to P57
A16 to A19
Output
Higher address bus used for external memory expansion
P60 to P63
LBEN
Output
External data bus's lower byte enable signal output
P90
UBEN
External data bus's higher byte enable signal output
P91
R/W
Output
External read/write status output
P92
DSTB
External data strobe signal output
P93
ASTB
External address strobe signal output
P94
HLDAK
Output
Bus hold acknowledge output
P95
HLDRQ
Input
Bus hold request input
P96
ANI0 to ANI7
Input
Analog input to A/D converter
P70 to P77
ANO0, ANO1
Output
Analog output from D/A converter
--
NMI
Input
Non-maskable interrupt request input
--
CLKOUT
Output
System clock output
--
CKSEL
Input
Input for specifying clock generator's operation mode
CV
DD
WAIT
Input
Control signal input for inserting wait in bus cycle
--
MODE
Input
Operation mode specification
--
RESET
Input
System reset input
--
X1
Input
Resonator connection for system clock. Input is via X1 when using an
--
X2
--
external clock.
--
ADTRG
Input
A/D converter external trigger input
P07/INTP113
AV
REF1
Input
Reference voltage input for A/D converter
--
AV
REF2
Input
Reference voltage input for D/A converter
--
AV
REF3
--
AV
DD
--
Positive power supply for A/D converter
--
AV
SS
--
Ground potential for A/D converter
--
CV
DD
--
Positive power supply for on-chip clock generator
CKSEL
CV
SS
--
Ground potential for on-chip clock generator
--
V
DD
--
Positive power supply
--
V
SS
--
Ground potential
--
IC
--
Internally connected pin (Connect directly to V
SS
)
--
11
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
Figure 2-1 illustrates the various circuit types using partially abridged diagrams.
When connecting to V
DD
or V
SS
via a resistor, a resistance value in the range of 1 to 10 k
is recommended.
Table 2-1. Types of Pin Input/Output Circuits (1/2)
Pin Name
Input/Output Circuit Type
Recommended Connection of Unused Pins
P00/TO110, P01/TO111
5
Input: Independently connect to V
DD
or V
SS
via a resistor.
P02/TCLR11, P03/TI11,
8
Output: Leave open.
P04/INTP110 to P07/INTP113/ADTRG
P10/TO120, P11/TO121
5
P12/TCLR12, P13/TI12
8
P14/INTP120
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
P20/PWM0, P21/PWM1
5
P22/TXD0/SO0
P23/RXD0/SI0, P24/SCK0
8
P25/TXD1/SO1
5
P26/RXD1/SI1, P27/SCK1
8
P30/TO130, P31/TO131
5
P32/TCLR13, P33/TI13
8
P34/INTP130
P35/INTP131/SO3
10-A
P36/INTP132/SI3
P37/INTP133/SCK3
P40/AD0 to P47/AD7
5
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7
9
Connect directly to V
SS
.
P90/LBEN
5
Input: Independently connect to V
DD
or V
SS
via a resistor.
P91/UBEN
Output: Leave open.
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
8
P114/INTP140 to P117/INTP143
ANO0, ANO1
12
Leave open.
NMI
2
Connect directly to V
SS
.
PD703003A, 703004A, 703025A
12
Data Sheet U13188EJ4V0DS00
Table 2-1. Types of Pin Input/Output Circuits (2/2)
Pin Name
Input/Output Circuit Type
Recommended Connection of Unused Pins
CLKOUT
3
Leave open.
WAIT
1
Connect directly to V
DD
.
MODE
2
--
RESET
CV
DD
/CKSEL
AV
REF1
to AV
REF3
, AV
SS
--
Connect directly to V
SS
.
AV
DD
--
Connect directly to V
DD
.
IC
--
Connect directly to V
SS
.
13
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
Figure 2-1. Pin Input/Output Circuits
Type 1
Type 2
Type 8
Type 3
P-ch
N-ch
IN
V
DD
IN
Schmitt-triggered input with hysteresis characteristics
P-ch
N-ch
V
DD
OUT
P-ch
N-ch
V
DD
IN/OUT
Data
Output
disable
Type 5
P-ch
N-ch
V
DD
IN/OUT
Data
Output
disable
Input
enable
IN
Comparator
+
V
REF
(threshold voltage)
P-ch
N-ch
Input enable
Type 9
Data
Output disable
P-ch
IN/OUT
V
DD
N-ch
P-ch
V
DD
Pull-up
enable
Open drain
Type 10-A
OUT
P-ch
N-ch
Analog output voltage
Type 12
PD703003A, 703004A, 703025A
14
Data Sheet U13188EJ4V0DS00
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25
C)
Parameter
Symbol
Conditions
Ratings
Unit
Power supply voltage
V
DD
V
DD
pin
0.5 to +7.0
V
CV
DD
CV
DD
pin
0.5 to V
DD
+ 0.3
V
CV
SS
CV
SS
pin
0.5 to +0.5
V
AV
DD
AV
DD
pin
0.5 to V
DD
+ 0.3
V
AV
SS
AV
SS
pin
0.5 to +0.5
V
Input voltage
V
I1
Note, V
DD
= 5.0 V
10%
0.5 to V
DD
+ 0.3
V
Clock input voltage
V
K
X1 pin, V
DD
= 5.0 V
10%
0.5 to V
DD
+ 1.0
V
Output current, low
I
OL
Per pin
4.0
mA
Total for all pins
100
mA
Output current, high
I
OH
Per pin
4.0
mA
Total for all pins
100
mA
Output voltage
V
O
V
DD
= 5.0 V
10%
0.5 to V
DD
+ 0.3
V
Analog input voltage
V
IAN
P70/ANI0 to P77/ANI7
AV
DD
> V
DD
0.5 to V
DD
+ 0.3
V
V
DD
AV
DD
0.5 to AV
DD
+ 0.3
V
Analog reference input voltage
AV
REF
AV
REF1
to AV
REF3
AV
DD
> V
DD
0.5 to V
DD
+ 0.3
V
V
DD
AV
DD
0.5 to AV
DD
+ 0.3
V
Operating ambient temperature
T
A
40 to +85
C
Storage temperature
T
stg
65 to +150
C
Note X1, P70/ANI0 to P77/ANI7, and AV
REF1
to AV
REF3
are excluded.
Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between
V
DD
or V
CC
and GND. However, open-drain pins and open collector pins can be directly
connected. A direct connection to an external circuit can be made to avoid conflicting output
from high-impedance pins if the external circuit is designed for the correct timing.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
Capacitance (T
A
= 25
C, V
DD
= V
SS
= 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
f
C
= 1 MHz
15
pF
I/O capacitance
C
IO
Unmeasured pins returned to 0 V.
15
pF
Output capacitance
C
O
15
pF
15
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
Operating Conditions
Operation Mode
Internal Operating
Operating Ambient
Power Supply
Clock Frequency (
)
Temperature (T
A
)
Voltage (V
DD
)
Direct mode, PLL mode
2 to 33 MHz
Note 1
40 to +85
C
5.0 V
10%
5 to 33 MHz
Note 2
40 to +85
C
5.0 V
10%
Notes 1. When not using A/D converter
2. When using A/D converter
Recommended Oscillator
(1) Ceramic resonator connection (T
A
= 40 to +85
C)
(a)
PD703003A, 703004A
Manufacturer
Part Number
Oscillation
Recommended
Oscillation
Oscillation
Frequency
Circuit Constant
Voltage Range
Stabilization Time
f
XX
(MHz)
C1 (pF)
C2 (pF)
Rd (
)
MIN. (V)
MAX. (V) (MAX.) T
OST
(ms)
Kyocera
KBR-5.0MSA/MSB
5.0
33
33
680
4.5
5.5
0.14
Corporation
KBR-5.0MKC
5.0
On-chip
On-chip
680
4.5
5.5
0.14
KBR-5.0MKD
5.0
On-chip
On-chip
680
4.5
5.5
0.14
KBR-5.0MKS
5.0
On-chip
On-chip
680
4.5
5.5
0.14
PBRC5.00A
5.0
33
33
680
4.5
5.5
0.14
PBRC5.00B
5.0
On-chip
On-chip
680
4.5
5.5
0.14
KBR-6.6MSA/MSB
6.6
33
33
--
4.5
5.5
0.10
KBR-6.6MKC
6.6
On-chip
On-chip
--
4.5
5.5
0.10
KBR-6.6MKD
6.6
On-chip
On-chip
--
4.5
5.5
0.10
KBR-6.6MKS
6.6
On-chip
On-chip
--
4.5
5.5
0.10
PBRC6.60A
6.6
33
33
--
4.5
5.5
0.10
PBRC6.60B
6.6
On-chip
On-chip
--
4.5
5.5
0.10
TDK
CCR5.0MC3
5.0
On-chip
On-chip
--
4.5
5.5
0.18
FCR5.0MC5
5.0
On-chip
On-chip
--
4.5
5.5
0.16
CCR6.6MC3
6.6
On-chip
On-chip
--
4.5
5.5
0.17
Murata Mfg.
CSA5.00MG040
5.0
100
100
--
4.5
5.5
0.31
Co., Ltd.
CST5.00MGW040
5.0
On-chip
On-chip
--
4.5
5.5
0.31
CSA6.60MTZ040
6.6
100
100
--
4.5
5.5
0.30
CST6.60MTW040
6.6
On-chip
On-chip
--
4.5
5.5
0.30
Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible.
2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines.
3. Sufficiently evaluate the matching between the
PD703003A or 703004A and the resonator.
X1
X2
C1
C2
Rd
PD703003A, 703004A, 703025A
16
Data Sheet U13188EJ4V0DS00
(b)
PD703025A
X1
X2
C1
C2
Rd
Manufacturer
Part Number
Oscillation
Recommended
Oscillation
Oscillation
Frequency
Circuit Constant
Voltage Range
Stabilization Time
f
XX
(MHz)
C1 (pF)
C2 (pF)
Rd (
)
MIN. (V)
MAX. (V) (MAX.) T
OST
(ms)
TDK
CCR4.0MC3
4.0
On-chip
On-chip
--
4.5
5.5
0.28
CCR5.0MC3
5.0
On-chip
On-chip
--
4.5
5.5
0.20
Murata Mfg.
CSA4.00MG040
4.0
100
100
--
4.5
5.5
0.20
Co., Ltd.
CST4.00MGW040
4.0
On-chip
On-chip
--
4.5
5.5
0.20
CSTS0400MG06
4.0
On-chip
On-chip
--
4.5
5.5
0.16
CSA6.60MTZ040
6.6
100
100
--
4.5
5.5
0.20
CST6.60MTW040
6.6
On-chip
On-chip
--
4.5
5.5
0.20
CSTS0660MG06
6.6
On-chip
On-chip
--
4.5
5.5
0.09
Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible.
2. Do not cross the wiring with the other signal lines in the area enclosed by the broken lines.
3. Sufficiently evaluate the matching between
PD703025A and the resonator.
(2) External clock input
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pin as possible.
2. Sufficiently evaluate the matching between the
PD703003A, 703004A, or 703025A
and the high-speed CMOS inverter.
X1
High-speed CMOS inverter
External clock
X2
Open
17
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
DC Characteristics (T
A
= 40 to +85
C, V
DD
= 5.0 V
10%, V
SS
= 0 V)
(1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, high
V
IH
Except for X1 and pins listed in Note
2.2
V
DD
+ 0.3
V
Note
0.8V
DD
V
DD
+ 0.3
V
Input voltage, low
V
IL
Except for X1 and pins listed in Note
0.5
+0.8
V
Note
0.5
0.2V
DD
V
Clock input voltage, high
V
XH
X1
0.8V
DD
V
DD
+ 0.5
V
Clock input voltage, low
V
XL
X1
0.5
+0.6
V
Schmitt-triggered input
V
T
+
Note, rising edge
3.0
V
Threshold voltage
V
T
Note, falling edge
2.0
V
Schmitt-triggered input hysteresis width V
T
+
V
T
Note
0.5
V
Output voltage, high
V
OH
I
OH
= 2.5 mA
0.7V
DD
V
I
OH
= 100
A
V
DD
0.4
V
Output voltage, low
V
OL
I
OL
= 2.5 mA
0.45
V
Input leakage current, high
I
LIH
V
I
= V
DD
10
A
Input leakage current, low
I
LIL
V
I
= 0 V
10
A
Output leakage current, high
I
LOH
V
O
= V
DD
10
A
Output leakage current, low
I
LOL
V
O
= 0 V
10
A
Software pull-up resistor
R
P35/INTP131/SO3,
15
40
90
k
P36/INTP132/SI3,
P37/INTP133/SCK3
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,
P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Remarks 1. TYP. values are reference values for when T
A
= 25
C and V
DD
= 5.0 V.
2.
= Internal system clock frequency
PD703003A, 703004A, 703025A
18
Data Sheet U13188EJ4V0DS00
DC Characteristics (T
A
= 40 to +85
C, V
DD
= 5.0 V
10%, V
SS
= 0 V)
(2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Power
PD703003A, When
I
DD1
Direct mode
Note
1.9
+ 5 2.1
+ 17
mA
supply 703004A
operating
PLL mode
Note
2.0
+ 7 2.2
+ 20
mA
current
In
I
DD2
Direct mode
Note
1.2
+ 5 1.3
+ 13
mA
HALT mode
PLL mode
Note
1.3
+ 7 1.4
+ 15
mA
In
I
DD3
Direct mode
Note
8
+ 300 10
+ 500
A
IDLE mode
PLL mode
Note
0.1
+ 2 0.2
+ 3
mA
In
I
DD4
2
50
A
STOP mode
PD703025A
When
I
DD1
Direct mode
Note
2.5
+ 2 2.8
+ 16.5
mA
operating
PLL mode
Note
2.6
+ 4 2.9
+19.5
mA
In
I
DD2
Direct mode
Note
1.3
+ 5 1.4
+ 13
mA
HALT mode
PLL mode
Note
1.3
+ 10 1.4
+ 18
mA
In
I
DD3
Direct mode
Note
8
+ 300 10
+ 500
A
IDLE mode
PLL mode
Note
0.1
+ 2 0.2
+ 3
mA
In
I
DD4
2
50
A
STOP mode
Note When using A/D converter:
= 5 to 33 MHz
When not using A/D converter:
= 2 to 33 MHz
Remarks 1. TYP. values are reference values for when T
A
= 25
C and V
DD
= 5.0 V. The power supply current
does not include AV
REF1
to AV
REF3
or the current that flows across a software pull-up resistor.
2.
= Internal system clock frequency
19
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
Data Retention Characteristics (T
A
= 40 to +85
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention voltage
V
DDDR
STOP mode
1.5
5.5
V
Data retention current
I
DDDR
V
DD
= V
DDDR
40
C
T
A
+50
C
0.2V
DDDR
50
A
50
C < T
A
85
C
0.2V
DDDR
200
A
Power supply voltage rise time
t
RVD
200
s
Power supply voltage fall time
t
FVD
200
s
Power supply voltage hold time
t
HVD
0
ms
(vs. STOP mode setting)
STOP mode release signal input time t
DREL
Note
0
ns
Data retention high-level input voltage
V
IHDR
Note
0.9V
DDDR
V
DDDR
V
Data retention low-level input voltage
V
ILDR
0
0.1V
DDDR
V
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,
P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
Remark
TYP. values are reference values for when T
A
= 25
C and V
DD
= 5.0 V.
t
HVD
V
DD
V
DD
t
FVD
t
RVD
t
DREL
V
DD
V
DDDR
RESET (input)
V
IHDR
NMI (input)
(Released at falling edge)
V
IHDR
V
ILDR
NMI (input)
(Released at rising edge)
STOP mode setting (fifth clock after PSC register is set)
PD703003A, 703004A, 703025A
20
Data Sheet U13188EJ4V0DS00
AC Characteristics (T
A
= 40 to +85
C, V
DD
= 5.0 V
10%, V
SS
= 0 V)
AC test input waveform
(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/
TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14,
P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
(b) Pins other than those listed in (a) above
AC test output measurement points
Load condition
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the device's load capacitance to below 50 pF.
C
L
= 50 pF
DUT
(Device under testing)
2.2 V
0.8 V
2.2 V
0.8 V
2.4 V
0.4 V
Point of
mesurement
Point of
mesurement
0.8V
DD
0.2V
DD
0.8V
DD
0.2V
DD
V
DD
0 V
2.2 V
0.8 V
2.2 V
0.8 V
Point of
mesurement
21
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(1) Clock timing
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
X1 input cycle
<1>
t
CYX
Direct mode
20
Note 1
15
Note 1
ns
PLL mode (PLL locked)
200
Note 1
151
Note 1
ns
X1 input high-level width
<2>
t
WXH
Direct mode
7
6
ns
X1 input fall time
<5>
t
XF
Direct mode
7
7
ns
PLL mode
15
10
ns
CPU operating frequency
Note 2
25
Note 2
33
MHz
Notes 1. When using A/D converter: 100 ns
When not using A/D converter: 250 ns
2. When using A/D converter: 5 MHz
When not using A/D converter: 2 MHz
3. When using A/D converter: 200 ns
When not using A/D converter: 500 ns
Remark
T = t
CYK
PLL mode
80
60
ns
X1 input low-level width
<3>
t
WXL
Direct mode
7
6
ns
PLL mode
80
60
ns
X1 input rise time
<4>
t
XR
Direct mode
7
7
ns
CLKOUT output cycle
<6>
t
CYK
40
Note 3
30
Note 3
ns
CLKOUT input high-level width
<7>
t
WKH
0.5T 5
0.5T 5
ns
CLKOUT input low-level width
<8>
t
WKL
0.5T 5
0.5T 5
ns
CLKOUT input rise time
<9>
t
KR
5
5
ns
CLKOUT input fall time
<10> t
KF
5
5
ns
Delay time from X1
to CLKOUT <11> t
DXK
Direct mode
3
17
3
17
ns
PLL mode
15
10
ns
X1 (input)
CLKOUT (output)
<1>
<2>
<4>
<5>
<6>
<7>
<11>
<11>
<8>
<9>
<10>
<3>
PD703003A, 703004A, 703025A
22
Data Sheet U13188EJ4V0DS00
(2) Input waveform
(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/
SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
Input rise time
<12> t
IR2
20
20
ns
Input fall time
<13> t
IF2
20
20
ns
(b) Pins other than those listed in (a) above
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
Input rise time
<14> t
IR1
10
10
ns
Input fall time
<15> t
IF1
10
10
ns
(3) Output waveform (other than CLKOUT)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
Output rise time
<16> t
OR
10
10
ns
Output fall time
<17> t
OF
10
10
ns
0.8V
DD
0.2V
DD
0.8V
DD
0.2V
DD
V
DD
0 V
<13>
<12>
Input signal
2.2 V
<15>
<14>
0.8 V
2.2 V
0.8 V
2.4 V
0.4 V
Input signal
0.8 V
<16>
<17>
2.2 V
2.2 V
0.8 V
Output signal
23
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(4) Reset timing
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
RESET high-level width
<18> t
WRSH
500
500
ns
RESET low-level width
<19> t
WRSL
When power supply is ON
500 + T
OST
500 + T
OST
ns
and STOP mode has been
released
Other than when power
500
500
ns
supply is ON and STOP
mode has been released
Remark
T
OST
: Oscillation stabilization time
RESET (input)
<18>
<19>
PD703003A, 703004A, 703025A
24
Data Sheet U13188EJ4V0DS00
(5) Read timing (1/2)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
Delay time from CLKOUT
to address <20> t
DKA
3
20
3
20
ns
Delay time from CLKOUT
to R/W, UBEN, LBEN <78> t
DKA2
2
+13
2
+13
ns
Delay time from CLKOUT
to address float <21> t
FKA
3
15
3
15
ns
Delay time from CLKOUT
to ASTB <22> t
DKST
3
15
3
15
ns
Delay time from CLKOUT
to DSTB <23> t
DKD
3
15
3
15
ns
Data input setup time (to CLKOUT
) <24> t
SIDK
5
5
ns
Data input hold time (from CLKOUT
) <25> t
HKID
5
5
ns
WAIT setup time (to CLKOUT
) <26> t
SWTK
5
5
ns
WAIT hold time (from CLKOUT
) <27> t
HKWT
5
5
ns
Address hold time (from CLKOUT
) <28> t
HKA
0
0
ns
Address setup time (to ASTB
)
<29> t
SAST
40
C
T
A
+70
C
0.5T 10
0.5T 10
ns
70
C < T
A
85
C
0.5T 12
0.5T 12
ns
Address hold time (from ASTB
) <30> t
HSTA
0.5T 10
0.5T 10
ns
Delay time from DSTB
to address float <31> t
FDA
0
0
ns
Data input setup time (to address) <32> t
SAID
40
C
T
A
+70
C
(2 + n)T 22
(2 + n)T 22
ns
70
C < T
A
85
C
(2 + n)T 25
(2 + n)T 25
ns
Data input setup time (to DSTB
) <33> t
SDID
40
C
T
A
+70
C
(1 + n)T 20
(1 + n)T 20
ns
70
C < T
A
85
C
(1 + n)T 24
(1 + n)T 24
ns
Delay time from ASTB
to DSTB
<34> t
DSTD
0.5T 10
0.5T 10
ns
Data input hold time (from DSTB
) <35> t
HDID
0
0
ns
Delay time from DSTB
to address output <36> t
DDA
(1 + i)T
(1 + i)T
ns
Delay time from DSTB
to ASTB
<37> t
DDSTH
0.5T 10
0.5T 10
ns
Delay time from DSTB
to ASTB
<38> t
DDSTL
(1.5 + i)T 10
(1.5 + i)T 10
ns
DSTB low-level width
<39> t
WDL
40
C
T
A
+70
C
(1 + n)T 10
(1 + n)T 10
ns
70
C < T
A
85
C
(1 + n)T 13
(1 + n)T 13
ns
ASTB high-level width
<40> t
WSTH
T 10
T 10
ns
WAIT setup time (to address)
<41> t
SAWT1
n
1, 40
C
T
A
+70
C
1.5T 20
1.5T 20
ns
n
1, 70
C < T
A
85
C
1.5T 24
1.5T 24
ns
<42> t
SAWT2
n
1, 40
C
T
A
+70
C
(1.5 + n)T 20
(1.5 + n)T 20
ns
n
1, 70
C < T
A
85
C
(1.5 + n)T 24
(1.5 + n)T 24
ns
WAIT hold time (from address)
<43> t
HAWT1
n
1
(0.5 + n)T
(0.5 + n)T
ns
<44> t
HAWT2
n
1
(1.5 + n)T
(1.5 + n)T
ns
WAIT setup time (to ASTB
)
<45> t
SSTWT1
n
1, 40
C
T
A
+70
C
T 18
T 18
ns
n
1, 70
C < T
A
85
C
T 20
T 20
ns
<46> t
SSTWT2
n
1
(1 + n)T 15
(1 + n)T 15
ns
WAIT hold time (from ASTB
)
<47> t
HSTWT1
n
1
nT
nT
ns
<48> t
HSTWT2
n
1
(1 + n)T
(1 + n)T
ns
Remarks 1. T = t
CYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4. Maintain at least one of the two data input hold times, either t
HKID
(<25>) or t
HDID
(<35>).
25
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(5) Read timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
A16 to A19 (output)
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output)
WAIT (input)
<32>
<20>
R/W (output)
UBEN (output)
LBEN (output)
<78>
<28>
<25>
<24>
<21>
A0 to A15 (output)
D0 to D15 (input)
<22>
<29>
<30>
<22>
<35>
<37>
<36>
<23>
<31>
<34>
<40>
<33>
<23>
<39>
<38>
<26>
<27>
<26>
<47>
<46>
<48>
<27>
<45>
<41>
<44>
<43>
<42>
Remark Broken lines indicate high impedance.
PD703003A, 703004A, 703025A
26
Data Sheet U13188EJ4V0DS00
(6) Write timing (1/2)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
Delay time from CLKOUT
to address <20> t
DKA
3
20
3
20
ns
Delay time from CLKOUT
to R/W, UBEN, LBEN <78> t
DKA2
2
+13
2
+13
ns
Delay time from CLKOUT
to ASTB <22> t
DKST
3
15
3
15
ns
Delay time from CLKOUT
to DSTB <23> t
DKD
3
15
3
15
ns
WAIT setup time (to CLKOUT
) <26> t
SWTK
5
5
ns
WAIT hold time (from CLKOUT
) <27> t
HKWT
5
5
ns
Address hold time (from CLKOUT
) <28> t
HKA
0
0
ns
Address setup time (to ASTB
)
<29> t
SAST
40
C
T
A
+70
C
0.5T 10
0.5T 10
ns
70
C < T
A
85
C
0.5T 12
0.5T 12
ns
Address hold time (from ASTB
) <30> t
HSTA
0.5T 10
0.5T 10
ns
Delay time from ASTB
to DSTB
<34> t
DSTD
0.5T 10
0.5T 10
ns
Delay time from DSTB
to ASTB
<37> t
DDSTH
0.5T 10
0.5T 10
ns
DSTB low-level width
<39> t
WDL
40
C
T
A
+70
C
(1 + n)T 10
(1 + n)T 10
ns
70
C < T
A
85
C
(1 + n)T 13
(1 + n)T 13
ns
ASTB high-level width
<40> t
WSTH
T 10
T 10
ns
WAIT setup time (to address)
<41> t
SAWT1
n
1, 40
C
T
A
+70
C
1.5T 20
1.5T 20
ns
n
1, 70
C < T
A
85
C
1.5T 24
1.5T 24
ns
<42> t
SAWT2
n
1, 40
C
T
A
+70
C
(1.5 + n)T 20
(1.5 + n)T 20
ns
n
1, 70
C < T
A
85
C
(1.5 + n)T 24
(1.5 + n)T 24
ns
WAIT hold time (from address)
<43> t
HAWT1
n
1
(0.5 + n)T
(0.5 + n)T
ns
<44> t
HAWT2
n
1
(1.5 + n)T
(1.5 + n)T
ns
WAIT setup time (to ASTB
)
<45> t
SSTWT1
n
1, 40
C
T
A
+70
C
T 18
T 18
ns
n
1, 70
C < T
A
85
C
T 20
T 20
ns
<46> t
SSTWT2
n
1
(1 + n)T 15
(1 + n)T 15
ns
WAIT hold time (from ASTB
)
<47> t
HSTWT1
n
1
nT
nT
ns
<48> t
HSTWT2
n
1
(1 + n)T
(1 + n)T
ns
Delay time from
<49> t
DKOD
40
C
T
A
+70
C
20
20
ns
CLKOUT
to data output
70
C < T
A
85
C
23
23
ns
Delay time from DSTB
to data output <50> t
DDOD
10
10
ns
Data output hold time (from CLKOUT
) <51> t
HKOD
0
0
ns
Data output setup time (to DSTB
) <52> t
SODD
(1 + n)T 15
(1 + n)T 15
ns
Data output hold time (from DSTB
) <53> t
HDOD
T 10
T 10
ns
Remarks 1. T = t
CYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
27
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(6) Write timing (2/2): 1 wait
Remark Broken lines indicate high impedance.
T1
T2
TW
T3
CLKOUT (output)
A16 to A19 (output)
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output)
WAIT (input)
<20>
<78>
<28>
<49>
A0 to A15 (output)
D0 to D15 (output)
<22>
<29>
<30>
<22>
<37>
<53>
<23>
<50>
<23>
<40>
<52>
<34>
<39>
<26>
<27>
<26>
<47>
<46>
<48>
<27>
<45>
<41>
<44>
<43>
<42>
<51>
R/W (output)
UBEN (output)
LBEN (output)
PD703003A, 703004A, 703025A
28
Data Sheet U13188EJ4V0DS00
(7) Bus hold timing (1/2)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Units
MIN.
MAX.
MIN.
MAX.
HLDRQ setup time (to CLKOUT
) <54> t
SHQK
5
5
ns
HLDRQ hold time (from CLKOUT
) <55> t
HKHQ
5
5
ns
HLDAK delay time from CLKOUT
<56> t
DKHA
20
20
ns
HLDRQ high-level width
<57> t
WHQH
T + 10
T + 10
ns
HLDAK low-level width
<58> t
WHAL
40
C
T
A
+70
C
T 10
T 10
ns
70
C < T
A
85
C
T 12
T 12
ns
Delay time from CLKOUT
to bus float <59> t
DKF
20
20
ns
Delay time from HLDAK
to bus output <60> t
DHAC
3
3
ns
Delay time from HLDRQ
to HLDAK
<61> t
DHQHA1
(2n + 7.5)T + 20
(2n + 7.5)T + 20
ns
Delay time from HLDRQ
to HLDAK
<62> t
DHQHA2
0.5T
1.5T + 20
0.5T
1.5T + 20
ns
Remarks 1. T = t
CYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
29
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(7) Bus hold timing (2/2)
Note UBEN (output), LBEN (output)
Remark
Broken lines indicate high impedance.
TH
TH
TH
TI
TH
CLKOUT (output)
A16 to A19 (output),
Note
HLDAK (output)
DSTB (output)
R/W (output)
HLDRQ (input)
ASTB (output)
AD0 to AD15 (I/O)
D0 to D15
(input or output)
<55>
<61>
<62>
<57>
<54>
<54>
<56>
<58>
<56>
<60>
<59>
PD703003A, 703004A, 703025A
30
Data Sheet U13188EJ4V0DS00
(8) Interrupt timing
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
NMI high-level width
<63> t
WNIH
500
500
ns
NMI low-level width
<64> t
WNIL
500
500
ns
INTPn high-level width
<65> t
WITH
n = 110 to 113, 120 to 123,
3T + 10
3T + 10
ns
130 to 133, 140 to 143
INTPn low-level width
<66> t
WITL
n = 110 to 113, 120 to 123,
3T + 10
3T + 10
ns
130 to 133, 140 to 143
Remark
T = t
CYK
Remark
n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
NMI (input)
<63>
<64>
INTPn (input)
<65>
<66>
31
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(9) CSI timing (1/2)
(a) Master mode
(i)
Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
SCKn cycle
<67> t
CYSK1
Output
160
120
ns
SCKn high-level width
<68> t
WSKH1
Output
0.5t
CYSK1
20
0.5t
CYSK1
20
ns
SCKn low-level width
<69> t
WSKL1
Output
0.5t
CYSK1
20
0.5t
CYSK1
20
ns
SIn setup time (to SCKn
)
<70> t
SSISK1
30
30
ns
SIn hold time (from SCKn
)
<71> t
HSKSI1
0
0
ns
SOn output delay time (from SCKn
) <72> t
DSKSO1
18
18
ns
SOn output hold time (from SCKn
) <73> t
HSKSO1
0.5t
CYSK1
5
0.5t
CYSK1
5
ns
Remark
n = 0 to 2
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
SCK3 cycle
<67> t
CYSK3
Output
R
L
= 1.5 k
500
500
ns
SCK3 high-level width
<68> t
WSKH3
Output
C
L
= 50 pF
0.5t
CYSK3
70
0.5t
CYSK3
70
ns
SCK3 low-level width
<69> t
WSKL3
Output
0.5t
CYSK3
70
0.5t
CYSK3
70
ns
SI3 setup time (to SCK3
)
<70> t
SSISK3
100
100
ns
SI3 hold time (from SCK3
)
<71> t
HSKSI3
50
50
ns
SO3 output delay time (from SCK3
) <72> t
DSKSO3
R
L
= 1.5 k
150
150
ns
SO3 output hold time (from SCK3
) <73> t
HSKSO3
C
L
= 50 pF
0.5t
CYSK3
5
0.5t
CYSK3
5
ns
Remark
R
L
and C
L
are the load resistance and load capacitance of the SCK3 and SO3 output lines.
(b) Slave mode
(i)
Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
SCKn cycle
<67> t
CYSK2
Input
160
120
ns
SCKn high-level width
<68> t
WSKH2
Input
50
30
ns
SCKn low-level width
<69> t
WSKL2
Input
50
30
ns
SIn setup time (to SCKn
)
<70> t
SSISK2
10
10
ns
SIn hold time (from SCKn
)
<71> t
HSKSI2
10
10
ns
SOn output delay time (from SCKn
) <72> t
DSKSO2
30
30
ns
SOn output hold time (from SCKn
) <73> t
HSKSO2
t
WSKH2
t
WSKH2
ns
Remark
n = 0 to 2
PD703003A, 703004A, 703025A
32
Data Sheet U13188EJ4V0DS00
(9) CSI timing (2/2)
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
SCK3 cycle
<67> t
CYSK4
Input
500
500
ns
SCK3 high-level width
<68> t
WSKH4
Input
180
180
ns
SCK3 low-level width
<69> t
WSKL4
Input
180
180
ns
SI3 setup time (to SCK3
)
<70> t
SSISK4
100
100
ns
SI3 hold time (from SCK3
)
<71> t
HSKSI4
50
50
ns
SO3 output delay time (from SCK3
) <72> t
DSKSO4
R
L
= 1.5 k
150
150
ns
SO3 output hold time (from SCK3
) <73> t
HSKSO4
C
L
= 50 pF
t
WSKH4
t
WSKH4
ns
Remark
R
L
and C
L
are the load resistance and load capacitance of the SCK3 and SO3 output lines.
SCKn (I/O)
SIn (Input)
SOn (output)
<67>
<69>
<68>
<70>
<71>
<72>
<73>
Input data
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 3
33
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
(10) RPU timing
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
TI1n high-level width
<74> t
WTIH
3T + 10
3T + 10
ns
TI1n low-level width
<75> t
WTIL
3T + 10
3T + 10
ns
TCLR1n high-level width
<76> t
WTCH
3T + 10
3T + 10
ns
TCLR1n low-level width
<77> t
WTCL
3T + 10
3T + 10
ns
Remark
T = t
CYK
TI1n (input)
<74>
<75>
TCLR1n (input)
<76>
<77>
Remark n = 1 to 4
PD703003A, 703004A, 703025A
34
Data Sheet U13188EJ4V0DS00
A/D Converter Characteristics (T
A
= 40 to +85
C, V
DD
= AV
DD
= 5 V
10%, V
SS
= AV
SS
= 0 V)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Resolution
--
10
10
10
10
10
10
bit
Overall error
Note 1
--
4.5 V
AV
REF1
AV
DD
0.4
0.4
%FSR
--
3.5 V
AV
REF1
AV
DD
0.7
0.7
%FSR
Quantization error
--
1/2
1/2
LSB
Conversion time
t
CONV
4.5 V
AV
REF1
AV
DD
48
60
t
CYK
3.5 V
AV
REF1
AV
DD
48
60
t
CYK
Sampling time
t
SAMP
4.5 V
AV
REF1
AV
DD
8
10
t
CYK
3.5 V
AV
REF1
AV
DD
8
10
t
CYK
Zero-scale error
Note 1
--
4.5 V
AV
REF1
AV
DD
1.5
3.5
1.5
3.5
LSB
--
3.5 V
AV
REF1
AV
DD
1.5
4.5
1.5
4.5
LSB
Full-scale error
Note 1
--
4.5 V
AV
REF1
AV
DD
1.5
2.5
1.5
2.5
LSB
--
3.5 V
AV
REF1
AV
DD
1.5
4.5
1.5
4.5
LSB
Non-linearity error
Note 1
--
4.5 V
AV
REF1
AV
DD
1.5
2.5
1.5
2.5
LSB
--
3.5 V
AV
REF1
AV
DD
1.5
4.5
1.5
4.5
LSB
Analog input
V
IAN
0.3
AV
DD
0.3
AV
DD
V
voltage
Note 2
+ 0.3
+ 0.3
Reference voltage
AV
REF1
3.5
AV
DD
3.5
AV
DD
V
AV
REF1
current
AI
REF1
1.2
3.0
1.2
3.0
mA
AV
DD
power supply
AI
DD
2.3
6.0
2.3
6.0
mA
current
Notes 1. Excludes quantization error.
2. When V
IAN
= 0, the conversion result becomes 000H.
When 0 < V
IAN
< AV
REF1
, conversion has 10-bit resolution.
When AV
REF1
V
IAN
AV
DD
, the conversion result becomes 3FFH.
35
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
D/A Converter Characteristics (T
A
= 40 to +85
C, V
DD
= AV
DD
= 5 V
10%, V
SS
= AV
SS
= 0 V)
Parameter
Symbol
Conditions
25 MHz Version
33 MHz Version
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Resolution
--
8
8
8
8
8
8
bit
Overall error
--
Load condition: 2 M
, 30 pF
0.8
0.8
%
AV
REF2
= V
DD
AV
REF3
= 0
--
Load condition: 2 M
, 30 pF
1.0
1.0
%
AV
REF2
= 0.75V
DD
AV
REF3
= 0.25V
DD
--
Load condition: 4 M
, 30 pF
0.6
0.6
%
AV
REF2
= V
DD
AV
REF3
= 0
--
Load condition: 4 M
, 30 pF
0.8
0.8
%
AV
REF2
= 0.75V
DD
AV
REF3
= 0.25V
DD
Settling time
--
Load condition: 2 M
, 30 pF
10
10
s
Output resistance
RO
8
8
k
AV
REF2
input voltage
AV
REF2
0.75V
DD
V
DD
0.75V
DD
V
DD
V
AV
REF3
input voltage
AV
REF3
0
0.25V
DD
0
0.25V
DD
V
Resistance between
R
AIREF
DACS0, DACS1 = 55H
2
4
2
4
k
AV
REF2
and AV
REF3
PD703003A, 703004A, 703025A
36
Data Sheet U13188EJ4V0DS00
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
16.00
0.20
14.00
0.20
0.50 (T.P.)
1.00
J
16.00
0.20
K
C
14.00
0.20
I
0.08
1.00
0.20
L
0.50
0.20
F
1.00
N
P
Q
0.08
1.40
0.05
0.10
0.05
S100GC-50-8EU, 8EA-2
S
1.60 MAX.
H
0.22
+
0.05
-
0.04
M
0.17
+
0.03
-
0.07
R
3
+
7
-
3
1
25
26
50
100
76
75
51
S
S
N
J
detail of lead end
C
D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
4. PACKAGE DRAWING
37
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
Package peak temperature: 235
C, Time: 30 seconds max. (at 210
C or
higher), Count: Two times or less, Exposure limit: 7 days
Note
(after that,
prebake at 125
C for 10 hours)
Package peak temperature: 215
C, Time: 40 seconds max. (at 200
C or
higher), Count: Two times or less, Exposure limit: 7 days
Note
(after that,
prebake at 125
C for 10 hours)
Pin temperature: 300
C max., Time 3 seconds max. (per pin row)
5. RECOMMENDED SOLDERING CONDITIONS
The
PD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended
conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales represen-
tatives.
Table 5-1. Soldering Conditions
PD703003AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14
14 mm)
PD703003AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14
14 mm)
PD703004AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14
14 mm)
PD703004AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14
14 mm)
PD703025AGC-25-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14
14 mm)
PD703025AGC-33-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14
14 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
IR35-107-2
VPS
VP15-107-2
Partial heating
--
Note After opening a dry pack, store it at 25
C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
PD703003A, 703004A, 703025A
38
Data Sheet U13188EJ4V0DS00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
RELATED DOCUMENTS
PD703003 Data Sheet (U12261E)
PD70F3003 Data Sheet (U12036E)
PD70F3003A, 70F3025A Data Sheet (U13189E)
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
V850 Family and V853 are trademarks of NEC Corporation.
39
PD703003A, 703004A, 703025A
Data Sheet U13188EJ4V0DS00
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
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Tel: 02-66 75 41
Fax: 02-66 75 42 99
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Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
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Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
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Electron Devices Division
Rodovia Presidente Dutra, Km 214
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Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
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Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
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Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J99.1
PD703003A, 703004A, 703025A
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
M8E 00. 4
The information in this document is current as of March, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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