Document Outline

COVER
FEATURES
APPLICATIONS
ORDERING INFORMATION
PIN CONFIGURATION (Top view)
PIN NAMES
INTERNAL BLOCK DIAGRAM
1. DIFFERENCES AMONG PRODUCTS
2. PIN FUNCTIONS
- 2.1 Port Pins
- 2.2 Non-port Pins
- 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
3. FUNCTION BLOCKS
- 3.1 Internal Units
  - 3.1.1 CPU
  - 3.1.2 Bus control unit (BCU)
  - 3.1.3 ROM
  - 3.1.4 RAM
  - 3.1.5 Ports
  - 3.1.6 Interrupt controller (INTC)
  - 3.1.7 Clock generator (CG)
  - 3.1.8 Real-time pulse unit (RPU)
  - 3.1.9 Serial interface (SIO)
  - 3.1.10 A/D converter (ADC)
4. CPU FUNCTIONS
5. BUS CONTROL FUNCTIONS
6. MEMORY ACCESS CONTROL FUNCTIONS
- 6.1 SRAM Connection
- 6.2 Page ROM Controller (ROMC)
  - 6.2.1 Features
  - 6.2.2 Page ROM connection
- 6.3 DRAM Controller
  - 6.3.1 Features
  - 6.3.2 DRAM Connections
7. DMA FUNCTIONS (DMA CONTROLLER)
8. INTERRUPT/EXCEPTION PROCESSING FUNCTIONS
- 8.1 Features
9. CLOCK GENERATION FUNCTIONS
10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
11. SERIAL INTERFACE FUNCTION
- 11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
- 11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
- 11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
12. A/D CONVERTER
13. PORT FUNCTIONS
14. RESET FUNCTION
15. INSTRUCTION SET
16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)
17. PACKAGE DRAWING
18. RECOMMENDED SOLDERING CONDITIONS

The information in this document is subject to change without notice.

MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

V850E/MS1

32/16-BIT SINGLE-CHIP MICROCONTROLLERS

Document No. U13995EJ1V0DS00 (1st edition)
Date Published April 1999 N CP(K)
Printed in Japan

PRELIMINARY DATA SHEET

1999

The

PD703101-33 and

PD703102-33 are members of the V850 Family

of 32-bit single-chip microcontrollers

designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU

core, ROM, RAM, interrupt controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.

The

PD703100-33 and

PD703100-40 are ROM-less versions of the

PD703101-33 and

PD703102-33

products.

The

PD703100-A33,

PD703100-A40,

PD703101-A33, and

PD703102-A33 are also available as products

having a 3.3-V power supply for external pins.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

V850E/MS1 User's Manual Hardware:

U12688E

V850E/MS1 User's Manual Architecture: U12197E

FEATURES

Number of instructions: 81

Minimum instruction execution time

25 ns (@ 40-MHz operation) ·····

PD703100-40

30 ns (@ 33-MHz operation) ·····

PD703100-33, 703101-33, 703102-33

General registers 32 bits

Instruction set optimized for control applications

Internal memory ROM : None (

PD703100-33, 703100-40),

96 Kbytes (

PD703101-33),

128 Kbytes (

PD703102-33)

RAM : 4 Kbytes

Advanced on-chip interrupt controller

Real-time pulse unit suitable for control operations

Powerful serial interface (on-chip dedicated baud rate generator)

On-chip clock generator

10-bit resolution A/D converter: 8 channels

DMA controller: 4 channels

Power saving functions

APPLICATIONS

Office automation equipment: printers, facsimile machines, PPCs, etc.

Multimedia equipment: digital still cameras, video printers, etc.

Consumer equipment: single-lens reflex cameras, etc.

Industrial equipment: motor controllers, NC machine tools, etc.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

ORDERING INFORMATION

Part Number

Package

Maximum Operating

Frequency (MHz)

Internal ROM

(bytes)

PD703100GJ-33-8EU

144-pin plastic LQFP (fine pitch) (20

20 mm)

33 MHz

None

PD703100GJ-40-8EU

144-pin plastic LQFP (fine pitch) (20

20 mm)

40 MHz

None

PD703101GJ-33-xxx-8EU

144-pin plastic LQFP (fine pitch) (20

20 mm)

33 MHz

96 Kbytes

PD703102GJ-33-xxx-8EU

144-pin plastic LQFP (fine pitch) (20

20 mm)

33 MHz

128 Kbytes

Remark xxx indicates ROM code suffix.

PIN CONFIGURATION (Top view)

144-pin plastic LQFP (fine pitch) (20

×
×
×
×

20 mm)

PD703100GJ-33-8EU

PD703101GJ-33-xxx-8EU

PD703100GJ-40-8EU

PD703102GJ-33-xxx-8EU

INTP103/DMARQ3/P07
INTP102/DMARQ2/P06
INTP101/DMARQ1/P05
INTP100/DMARQ0/P04

TI10/P03

TCLR10/P02

TO101/P01
TO100/P00

INTP113/DMAAK3/P17
INTP112/DMAAK2/P16
INTP111/DMAAK1/P15
INTP110/DMAAK0/P14

TI11/P13

TCLR11/P12

TO111/P11
TO110/P10

INTP123/TC3/P107
INTP122/TC2/P106
INTP121/TC1/P105
INTP120/TC0/P104

TI12/P103

TCLR12/P102

TO121/P101
TO120/P100

ANI7/P77
ANI6/P76
ANI5/P75
ANI4/P74
ANI3/P73
ANI2/P72
ANI1/P71
ANI0/P70

REF

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
HV

CS0/RAS0/P80
CS1/RAS1/P81
CS2/RAS2/P82
CS3/RAS3/P83
CS4/RAS4/IOWR/P84
CS5/RAS5/IORD/P85
CS6/RAS6/P86
CS7/RAS7/P87
LCAS/LWR/P90
UCAS/UWR/P91
RD/P92
WE/P93
BCYST/P94
OE/P95
HLDAK/P96
HLDRQ/P97
V

REFRO/PX5
WAIT/PX6
CLKOUT/PX7
TO150/P120
TO151/P121
TCLR15/P122
TI15/P123
INTP150/P124
INTP151/P125
INTP152/P126

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73

NMI/P20

P21

TXD0/SO0/P22

RXD0/SI0/P23

SCK0/P24

TXD1/SO1/P25

RXD1/SI1/P26

SCK1/P27

INTP133/SCK2/P37

INTP132/SI2/P36

INTP131/SO2/P35

INTP130/P34

TI13/P33

TCLR13/P32

TO131/P31

TO130/P30

INTP143/SCK3/P117

INTP142/SI3/P116

INTP141/SO3/P115

INTP140/P114

TI14/P113

TCLR14/P112

TO141/P111

TO140/P110

CKSEL

MODE0

MODE1

MODE2

MODE3

RESET

INTP153/ADTRG/P127

D0/P40

D1/P41

D2/P42

D3/P43

D4/P44

D5/P45

D6/P46

D7/P47

D8/P50

D9/P51

D10/P52

D11/P53

D12/P54

D13/P55

D14/P56

D15/P57

A0/PA0

A1/PA1

A2/PA2

A3/PA3

A4/PA4

A5/PA5

A6/PA6

A7/PA7

A8/PB0

A9/PB1

A10/PB2

A11/PB3

A12/PB4

A13/PB5

A14/PB6

A15/PB7

144

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

PIN NAMES

A0 to A23

: Address Bus

P50 to P57

: Port 5

ADTRG

: AD Trigger Input

P60 to P67

: Port 6

ANI0 to ANI7

: Analog Input

P70 to P77

: Port 7

: Analog Power Supply

P80 to P87

: Port 8

REF

: Analog Reference Voltage

P90 to P97

: Port 9

: Analog Ground

P100 to P107

: Port 10

BCYST

: Bus Cycle Start Timing

P110 to P117

: Port 11

CKSEL

: Clock Generator Operating Mode Select

P120 to P127

: Port 12

CLKOUT

: Clock Output

PA0 to PA7

: Port A

CS0 to CS7

: Chip Select

PB0 to PB7

: Port B

: Clock Generator Power Supply

PX5 to PX7

: Port X

: Clock Generator Ground

RAS0 to RAS7

: Row Address Strobe

D0 to D15

: Data Bus

: Read

DMAAK0 to DMAAK3 : DMA Acknowledge

REFRQ

: Refresh Request

DMARQ0 to DMARQ3 : DMA Request

RESET

: Reset

HLDAK

: Hold Acknowledge

RXD0, RXD1

: Receive Data

HLDRQ

: Hold Request

SCK0 to SCK3

: Serial Clock

: Power Supply for External Pins

SI0 to SI3

: Serial Input

INTP100 to INTP103, : Interrupt Request from Peripherals

SO0 to SO3

: Serial Output

INTP110 to INTP113,

TC0 to TC3

: Terminal Count Signal

INTP120 to INTP123,

TCLR10 to TCLR15 : Timer Clear

INTP130 to INTP133,

TI10 to TI15

: Timer Input

INTP140 to INTP143,

TO100, TO101,

: Timer Output

INTP150 to INTP153

TO110, TO111,

IORD

: I/O Read Strobe

TO120, TO121,

IOWR

: I/O Write Strobe

TO130, TO131,

LCAS

: Lower Column Address Strobe

TO140, TO141,

LWR

: Lower Write Strobe

TO150, TO151

MODE0 to MODE3

: Mode

TXD0, TXD1

: Transmit Data

NMI

: Non-Maskable Interrupt Request

UCAS

: Upper Column Address Strobe

: Output Enable

UWR

: Upper Write Strobe

P00 to P07

: Port 0

: Power Supply for Internal Unit

P10 to P17

: Port 1

: Ground

P20 to P27

: Port 2

WAIT

: Wait

P30 to P37

: Port 3

: Write Enable

P40 to P47

: Port 4

X1, X2

: Crystal

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

INTERNAL BLOCK DIAGRAM

TCLR10 to TCLR15

TI10 to TI15

TO100, TO101,
TO110, TO111,
TO120, TO121,
TO130, TO131,
TO140, TO141,
TO150, TO151

INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133,
INTP140 to INTP143,
INTP150 to INTP153

NMI

INTC

RPU

UART0/CSI0

SIO

SCK0

SI0/RXD0

SO0/TXD0

BRG0

UART1/CSI1

SCK1

SI1/RXD1

SO1/TXD1

BRG1

CSI2

SCK2

SI2

SO2

BRG2

CSI3

SCK3

SI3

SO3

REF

ADC

ADTRG

ANI0 to ANI7

Port

PX5 to PX7

PB0 to PB7

PA0 to PA7

P120 to P127

P110 to P117

P100 to P107

P90 to P97

P80 to P87

P70 to P77

P60 to P67

P50 to P57

P40 to P47

P30 to P37

P21 to P27

P20

P10 to P17

P00 to P07

Note

ROM

4 Kbytes

RAM

Instruction queue

System registers

General registers

(32 bits

32)

Multiplier

(32

64)

Barrel

shifter

ALU

DRAMC

Page ROM

controller

DMAC

BCU

CPU

TC0 to TC3

LWR/LCAS

DMAAK0 to DMARQ3

DMARQ0 to DMARQ3

D0 to D15

A0 to A23

WAIT

CS0 to CS7/RAS0 to RAS7

UWR/UCAS

BCYST

REFRQ

IORD

IOWR

HLDAK

HLDRQ

CKSEL

CLKOUT

System

controller

RESET

MODE0 to MODE3

Note

PD703100-33, 703100-40: None

PD703101-33: 96 Kbytes (mask ROM)

PD703102-33: 128 Kbytes (mask ROM)

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

CONTENTS

DIFFERENCES AMONG PRODUCTS...........................................................................................

PIN FUNCTIONS .............................................................................................................................

2.1

Port Pins .................................................................................................................................

2.2

Non-port Pins .........................................................................................................................

2.3

Pin I/O Circuits and Recommended Connection of Unused Pins.....................................

FUNCTION BLOCKS ......................................................................................................................

3.1

Internal Units ..........................................................................................................................

3.1.1

CPU ...........................................................................................................................................

3.1.2

Bus control unit (BCU) ...............................................................................................................

3.1.3

ROM ..........................................................................................................................................

3.1.4

RAM...........................................................................................................................................

3.1.5

Ports ..........................................................................................................................................

3.1.6

Interrupt controller (INTC) ..........................................................................................................

3.1.7

Clock generator (CG).................................................................................................................

3.1.8

Real-time pulse unit (RPU) ........................................................................................................

3.1.9

Serial interface (SIO) .................................................................................................................

3.1.10 A/D converter (ADC) ..................................................................................................................

CPU FUNCTIONS............................................................................................................................

BUS CONTROL FUNCTIONS........................................................................................................

MEMORY ACCESS CONTROL FUNCTIONS ..............................................................................

6.1

SRAM Connection..................................................................................................................

6.2

Page ROM Controller (ROMC) ..............................................................................................

6.2.1

Features.....................................................................................................................................

6.2.2

Page ROM connection...............................................................................................................

6.3

DRAM Controller ....................................................................................................................

6.3.1

Features.....................................................................................................................................

6.3.2

DRAM Connections ...................................................................................................................

DMA FUNCTIONS (DMA CONTROLLER) ...................................................................................

INTERRUPT/EXCEPTION PROCESSING FUNCTIONS...............................................................

8.1

Features ..................................................................................................................................

CLOCK GENERATION FUNCTIONS ............................................................................................

10. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT).....................................................

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

11. SERIAL INTERFACE FUNCTION ..................................................................................................

11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1).......................................................

11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) ...................................................................

11.3 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)..................................................

12. A/D CONVERTER............................................................................................................................

13. PORT FUNCTIONS .........................................................................................................................

14. RESET FUNCTION ..........................................................................................................................

15. INSTRUCTION SET .........................................................................................................................

16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)......................................................

17. PACKAGE DRAWING ..................................................................................................................... 120

18. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 121

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

1. DIFFERENCES AMONG PRODUCTS

Product Name

PD703100

PD703101

PD703102

PD70F3102

Item

A33

A40

A33

Internal ROM

None

96 Kbytes

(mask ROM)

128 Kbytes

(mask ROM)

128 Kbytes

(flash memory)

Maximum operating

frequency

33 MHz

40 MHz

33 MHz

40 MHz

33 MHz

4.5 to 5.5 V

3.0 to 3.6 V

4.5 to

5.5 V

3.0 to

3.6 V

4.5 to

5.5 V

3.0 to

3.6 V

4.5 to

5.5 V

3.0 to

3.6 V

Operation mode

Single-chip

mode 0, 1

None

Provided

Flash memory

programming

mode

None

Provided

Flash memory

programming pin

None

Provided (V

)

Electrical

specifications

Power consumptions differ (refer to the data sheet of each product).

Package

144LQFP

157FBGA

144LQFP

157FBGA

144LQFP

157FBGA

144LQFP

157FBGA

Others

Noise tolerance and noise radiation will differ due to the differences in circuit scale and mask layout.

Remark 144LQFP: 144-pin plastic LQFP (fine pitch) (20

20 mm)

157FBGA: 157-pin plastic FBGA (14

14 mm)

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

2. PIN FUNCTIONS

2.1 Port Pins

(1/3)

Pin Name

I/O

Function

Alternate Function

P00

TO100

P01

TO101

P02

TCLR10

P03

TI10

P04

INTP100/DMARQ0

P05

INTP101/DMARQ1

P06

INTP102/DMARQ2

P07

I/O

Port 0

8-bit I/O port

Input/output mode can be specified in 1-bit units

INTP103/DMARQ3

P10

TO110

P11

TO111

P12

TCLR11

P13

TI11

P14

INTP110/DMAAK0

P15

INTP111/DMAAK1

P16

INTP112/DMAAK2

P17

I/O

Port 1

8-bit I/O port

Input/output mode can be specified in 1-bit units

INTP113/DMAAK3

P20

NMI

P21

P22

TXD0/SO0

P23

RXD0/SO0

P24

SCK0

P25

TXD1/SO1

P26

RXD1/SI1

P27

I/O

Port 2

P20 is an input only port.

When a valid edge is input, this pin operates as NMI input. Also, bit 0

of the P2 register indicates the NMI input status.

P21 to P27 are 7-bit I/O port.

Input/output mode can be specified in 1-bit units

SCK1

P30

TO130

P31

TO131

P32

TCLR13

P33

TI13

P34

INTP130

P35

INTP131/SO2

P36

INTP132/SI2

P37

I/O

Port 3

8-bit I/O port.

Input/output mode can be specified in 1-bit units

INTP133/SCK2

P40 to P47

I/O

Port 4

8-bit I/O port

Input/output mode can be specified in 1-bit units

D0 to D7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(2/3)

Pin Name

I/O

Function

Alternate Function

P50 to P57

I/O

Port 5

8-bit I/O port

Input/output mode can be specified in 1-bit units

D8 to D15

P60 to P67

I/O

Port 6

8-bit I/O port

Input/output mode can be specified in 1-bit units

A16 to A23

P70 to P77

Port 7

8-bit input only port

ANI0 to ANI7

P80

CS0/RAS0

P81

CS1/RAS1

P82

CS2/RAS2

P83

CS3/RAS3

P84

CS4/RAS4/IOWR

P85

CS5/RAS5/IORD

P86

CS6/RAS6

P87

I/O

Port 8

8-bit I/O port

Input/output mode can be specified in 1-bit units

CS7/RAS7

P90

LCAS/LWR

P91

UCAS/UWR

P92

P93

P94

BCYST

P95

P96

HLDAK

P97

I/O

Port 9

8-bit I/O port

Input/output mode can be specified in 1-bit units

HLDRQ

P100

TO120

P101

TO121

P102

TCLR12

P103

TI12

P104

INTP120/TC0

P105

INTP121/TC1

P106

INTP122/TC2

P107

I/O

Port 10

8-bit I/O port

Input/output mode can be specified in 1-bit units

INTP123/TC3

P110

TO140

P111

TO141

P112

TCLR14

P113

TI14

P114

INTP140

P115

INTP141/SO3

P116

INTP142/SI3

P117

I/O

Port 11

8-bit I/O port

Input/output mode can be specified in 1-bit units

INTP143/SCK3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

2.2 Non-port Pins

(1/4)

Pin Name

I/O

Function

Alternate Function

TO100

P00

TO101

P01

TO110

P10

TO111

P11

TO120

P100

TO121

P101

TO130

P30

TO131

P31

TO140

P110

TO141

P111

TO150

P120

TO151

Pulse signal output for timers 10 to 15

P121

TCLR10

P02

TCLR11

P12

TCLR12

P102

TCLR13

P32

TCLR14

P112

TCLR15

External clear signal input for timers 10 to 15

P122

TI10

P03

TI11

P13

TI12

P103

TI13

P33

TI14

P113

TI15

External count clock input for timers 10 to 15

P123

INTP100

P04/DMARQ0

INTP101

P05/DMARQ1

INTP102

P06/DMARQ2

INTP103

External maskable interrupt request input, shared as external capture

trigger input for timer 10

P07/DMARQ3

INTP110

P14/DMAAK0

INTP111

P15/DMAAK1

INTP112

P16/DMAAK2

INTP113

External maskable interrupt request input, shared as external capture

trigger input for timer 11

P17/DMAAK3

INTP120

P104/TC0

INTP121

P105/TC1

INTP122

P106/TC2

INTP123

External maskable interrupt request input, shared as external capture

trigger input for timer 12

P107/TC3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(2/4)

Pin Name

I/O

Function

Alternate Function

INTP130

P34

INTP131

P35/SO2

INTP132

P36/SI2

INTP133

External maskable interrupt request input, shared as external capture

trigger input for timer 13

P37/SCK2

INTP140

P114

INTP141

P115/SO3

INTP142

P116/SI3

INTP143

External maskable interrupt request input, shared as external capture

trigger input for timer 14

P117/SCK3

INTP150

P124

INTP151

P125

INTP152

P126

INTP153

External maskable interrupt request input, shared as external capture

trigger input for timer 15

P127/ADTRG

SO0

P22/TXD0

SO1

P25/TXD1

SO2

P35/INTP131

SO3

Serial transmit data output (3-wire) for CSI0 to CSI3

P115/INTP141

SI0

P23/RXD0

SI1

P26/RXD1

SI2

P36/INTP132

SI3

Serial receive data input (3-wire) for CSI0 to CSI3

P116/INTP142

SCK0

P24

SCK1

P27

SCK2

P37/INTP133

SCK3

I/O

Serial clock I/O (3-wire) for CSI0 to CSI3

P117/INTP143

TXD0

P22/SO0

TXD1

Serial transmit data output for UART0 and UART1

P25/SO1

RXD0

P23/SI0

RXD1

Serial receive data input for UART0 and UART1

P26/SI1

D0 to D7

P40 to P47

D8 to D15

I/O

16-bit data bus for external memory

P50 to P57

A0 to A7

PA0 to PA7

A8 to A15

PB0 to PB7

A16 to A23

24-bit address bus for external memory

P60 to P67

LWR

Lower byte write-enable signal output for external data bus

P90/LCAS

UWR

Higher byte write-enable signal output for external data bus

P91/UCAS

Read strobe signal output for external data bus

P92

Write enable signal output for DRAM

P93

Output enable signal output for DRAM

P95

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(3/4)

Pin Name

I/O

Function

Alternate Function

LCAS

Column address strobe signal output for DRAM's lower data

P90/LWR

UCAS

Column address strobe signal output for DRAM's higher data

P91/UWR

RAS0 to RAS3

P80/CS0 to P83/CS3

RAS4

P84/CS4/IOWR

RAS5

P85/CS5/IORD

RAS6

P86/CS6

RAS7

Low address strobe signal output for DRAM

P87/CS7

BCYST

Strobe signal output indicating start of bus cycle

P94

CS0 to CS3

P80/RAS0 to

P83/RAS3

CS4

P84/RAS4/IOWR

CS5

P85/RAS5/IORD

CS6

P86/RAS6

CS7

Chip select signal output

P87/RAS7

WAIT

Control signal input for inserting waits in bus cycle

PX6

REFRQ

Refresh request signal output for DRAM

PX5

IOWR

DMA write strobe signal output

P84/RAS4/CS4

IORD

DMA read strobe signal output

P85/RAS5/CS5

DMARQ0 to

DMARQ3

DMA request signal input

P04/INTP100 to

P07/INTP103

DMAAK0 to

DMAAK3

DMA acknowledge signal output

P14/INTP110 to

P17/INTP113

TC0 to TC3

DMA end (terminal count) signal output

P104/INTP120 to

P107/INTP123

HLDAK

Bus hold acknowledge output

P96

HLDRQ

Bus hold request input

P97

ANI0 to ANI7

Analog input to A/D converter

P70 to P77

NMI

Non-maskable interrupt request input

P20

CLKOUT

System clock output

PX7

CKSEL

Input for specifying clock generator's operation mode

MODE0 to

MODE3

Specify operation modes

RESET

System reset input

Oscillator connection for system clock. Input is via X1 when using an

external clock.

ADTRG

A/D converter external trigger input

P127/INTP153

REF

Reference voltage input for A/D converter

Positive power supply for A/D converter

Ground potential for A/D converter

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows

the various circuit types using partially abridged diagrams.

When connecting to V

or V

via a resistor, a resistance value in the range of 1 to 10 k

is recommended.

Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)

I/O Circuit Type

Recommended Connection of Unused Pins

P00/TO100, P01/TO101

P02/TCLR10, P03/TI10

P04/INTP100/DMARQ0 to

P07/INTP103/DMARQ3

5-K

P10/TO110, P11/TO111

P12/TCLR11, P13/TI11

P14/INTP110/DMAAK0 to

P17/INTP113/DMAAK3

5-K

Input : Independently connect to HV

or V

via a resistor

Output: Leave open

P20/NMI

Connect directly to V

P21

P22/TXD0/SO0

P23/RXD0/SI0

P24/SCK0

5-K

P25/TXD1/SO1

P26/RXD1/SI1

P27/SCK1

5-K

P30/TO130, P31/TO131

P32/TCLR13,P33/TI13

P34/INTP130

P35/INTP131/SO2

P36/INTP132/SI2

P37/INTP133/SCK2

5-K

P40/D0 to P47/D7

P50/D8 to P57/D15

P60/A16 to P67/A23

Input : Independently connect to HV

or V

via a resistor

Output: Leave open

P70/ANI0 to P77/ANI7

Connect directly to V

P80/CS0/RAS0 to P83/CS3/RAS3

P84/CS4/RAS4/IOWR,

P85/CS5/RAS5/IORD

P86/CS6/RAS6, P87/CS7/RAS7

P90/LCAS/LWR

P91/UCAS/UWR

Input : Independently connect to HV

or V

via a resistor

Output: Leave open

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)

I/O Circuit Type

Recommended Connection of Unused Pins

P92/RD

P93/WE

P94/BCYST

P95/OE

P96/HLDAK

P97/HLDRQ

P100/TO120, P101/TO121

P102/TCLR12, P103/TI12

P104/INTP120/TC0 to

P107/INTP123/TC3

5-K

P110/TO140, P111/TOI41

P112/TCLR14, P113/TI14

P114/INTP140

P115/INTP141/SO3

P116/INTP142/SI3

P117/INTP143/SCK3

5-K

P120/TO150, P121/TO151

P122/TCLR15, P123/TI15

P124/INTP150 to P126/INTP152

P127/INTP153/ADTRG

5-K

PA0/A0-PA7/A7

PB0/A8-PB7/A15

PX5/REFRQ

PX6/WAIT

PX7/CLKOUT

Input : Independently connect to HV

or V

via a resistor

Output: Leave open

CKSEL

Connect directly to HV

RESET

MODE0 to MODE2

MODE3

Connect to V

via a resistor (R

VPP

)

REF

, AV

Connect directly to V

Connect directly to HV

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

3. FUNCTION BLOCKS

3.1 Internal Units

3.1.1 CPU

The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic

operations, data transfers, and almost all other instruction processing.

Other dedicated on-chip hardware, such as the multiplier (16 bits

16 bits

32 bits, or 32 bits

32 bits

bits) and the barrel shifter (32 bits) help accelerate processing of complex instructions.

3.1.2 Bus control unit (BCU)

The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an

instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU

generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an

internal instruction queue of the CPU.

The BCU contains DRAM controller (DRAMC), page ROM controller, and DMA controller (DMAC).

(a) DRAM controller (DRAMC)

The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to the

DRAM.

It supports high-speed page DRAM and EDO DRAM, and has two types of cycles for accessing DRAM.

These types of cycles are referred to as normal access (off-page) and page access (on-page).

The DRAM controller also has a refresh function that is associated with the CBR refresh cycle.

(b) Page ROM controller

The page ROM controller supports access to ROM that has the page access function.

It compares the address with that of the preceding bus cycle and controls the waits for normal access (off-

page) and page access (on-page). The page ROM controller can support page sizes of 8 to 64 bytes.

(c) DMA controller (DMAC)

The DMA controller transfers data between memory and an I/O device in place of the CPU.

The two address modes are flyby (one-cycle) transfer and two-cycle transfer. The three bus modes are single

transfer, single-step transfer, and block transfer.

3.1.3 ROM

The

PD703101-33 contains 96-Kbytes mask ROM, and the

PD703102-33 contains 128-Kbytes mask ROM.

The CPU can access ROM in one clock cycle when an instruction is fetched.

When single-chip mode 0 is set, ROM is mapped to the address space starting at 00000000H. When single-chip

mode 1 is set, ROM is mapped to the address space starting at 00100000H. When ROM-less mode 0 or 1 is set,

ROM cannot be accessed.

The

PD703100-33 and

PD703100-40 have no internal ROM.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

3.1.4 RAM

RAM is mapped to the 4-Kbyte address space starting at FFFFE000H. The CPU can access RAM in one clock

cycle when an instruction is fetched or data is accessed.

3.1.5 Ports

In addition to the 123 pins (ports 0 to 12, A, B, and X) comprising I/O ports (of which nine pins comprise an input-

only port), various port pin and control pin functions can be selected for these pins.

3.1.6 Interrupt controller (INTC)

This controller handles hardware interrupt requests (NMI, INTP100 to INTP103, INTP110 to INTP113, INTP120 to

INTP123, INTP130 to INTP133, INTP140 to INTP143, and INTP150 to INTP153) from on-chip peripheral I/O and

external hardware. Eight interrupt priority levels can be specified for these interrupt requests, and multiplexed

servicing control can be performed for interrupt sources.

3.1.7 Clock generator (CG)

A frequency of five times (using an on-chip PLL) or one-half times (not using an on-chip PLL) that of the input

clock (f

) is supplied as the internal system clock (

). Either an external oscillator is connected to pins X1 and X2

(only when the on-chip PLL synthesizer is used) or an external clock is input from the X1 pin as the input clock.

3.1.8 Real-time pulse unit (RPU)

The RPU includes a six-channel 16-bit timer/event counter and a two-channel 16-bit interval timer, which enables

measurement of pulse intervals and frequency as well as programmable pulse output.

3.1.9 Serial interface (SIO)

Four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (UART) and a

clocked serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other

two channels are fixed as CSI.

For UART, data is transferred via the TXD and RXD pins. For CSI, data is transferred via the SO, SI, and SCK

pins.

The serial clock source can be selected from dedicated baud rate generator output or the internal system clock.

3.1.10 A/D converter (ADC)

This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using

the successive approximation method.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

4. CPU FUNCTIONS

{

RISC-based architecture

{

Uses five-stage pipeline control to enable single-clock execution of almost all instructions

{

Minimum instruction execution time

25 ns (@ 40-MHz operation) ...

PD703100-40

30 ns (@ 33-MHz operation) ...

PD703100-33, 703101-33, 703102-33

{

Memory space

Program space : 64-Mbyte linear

Data space

: 4-Gbyte linear

{

General registers 32 bits

{

Internal 32-bit architecture

{

5-stage pipeline control

{

Multiply/divide instructions

{

Saturated operation instructions

{

32-bit shift instruction: 1 clock

{

Long/short format

{

Four types of bit manipulation instructions

Set

Clear

Not

Test

5. BUS CONTROL FUNCTIONS

{

16-bit/8-bit data bus sizing function

{

8-space chip select output function

{

Wait functions

Programmable wait function for up to seven states for each memory block

External wait function using WAIT pin

{

Idle state insertion function

{

Bus mastering arbitration function

{

Bus hold function

{

Alternate function for port pins are connectable to external bus

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

6.2 Page ROM Controller (ROMC)

The page ROM controller (ROMC) supports access to ROM (page ROM) that has the page access function.

It compares the address with that of the preceding bus cycle and performs wait control for normal access (off-

page) and page access (on-page). The page ROM controller can support page widths of 8 to 64 bytes.

6.2.1 Features

{

Can be connected directly to 8-bit or 16-bit page ROM

{

For 16-bit bus width, it supports 4-, 8-, 16-, or 32-word page access

For 8-bit bus width, it supports 8-, 16-, 32-, or 64-word page access

{

Enables waits to be set (0 to 7 waits) independently for off-page and on-page access

6.2.2 Page ROM connection

The following figure shows page ROM connection examples.

Figure 6-2. Page ROM Connection Examples (1/2)

(a) 16-Mbit (1 M

×
×
×
×

16) page ROM

A1 to A20

D0 to D15

CSn

V850E/MS1

16-Mbit (1 M

16) page ROM

A0 to A19

O1 to O16

WORD/BYTE

Remark n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

6.3 DRAM Controller

6.3.1 Features

{

Generates the RAS, UCAS, and LCAS signals

{

Can be connected directly to high-speed page DRAM and EDO DRAM

{

Supports RAS hold mode

{

Can assign 4 types of DRAM to 8 memory block spaces

{

Supports 2CAS type DRAM

{

Can be switched between row and column address multiplex widths

{

Can insert waits (0 to 3 waits) at each of the following timings

Row address pre-charge wait

Row address hold wait

Data access wait

Column address pre-charge wait

{

Supports CBR refresh and CBR self refresh

6.3.2 DRAM Connections

The following figure shows DRAM connection examples.

Figure 6-3. DRAM Connection Examples (1/2)

(a) 16-Mbit (1 M

×
×
×
×

16) DRAM

16-Mbit (1 M

16) DRAM

RASn

LCAS

UCAS

A0 to A9

I/O1 to I/O16

A1 to A10

D0 to D15

RASn

LCAS

V850E/MS1

UCAS

Remark n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Figure 8-1. Interrupt Control Function Block Diagram

Internal bus

xxMKn (interrupt mask flag)

xxICn register

ISPR register

Handler
address

generator

CPU

PSW

Interrupt request

Interrupt request
acknowledge

HALT mode
release signal

RPU

DMAC

A/D converter

SIO

CSI0

UART0

CSI1

UART1

CSI2

CSI3

INTM1

(edge detection)

INTM2

(edge detection)

Note

INTM3

(edge detection)

INTM4

(edge detection)

INTM5

(edge detection)

INTM6

(edge detection)

INTP100
INTP101

INTP102
INTP103

INTP110
INTP111

INTP112
INTP113

INTP120
INTP121

INTP122
INTP123

INTP130
INTP131

INTP132
INTP133

INTP140
INTP141

INTP142
INTP143

INTP150
INTP151

INTP152
INTP153

3210

Selector

3210

Selector

3210

Selector

3210

Selector

3210

Selector

3210

Selector

xxPRn0 to xxPRn3 (interrupt priority order specification bit)

INTOV10
INTOV11
INTOV12
INTOV13
INTOV14
INTOV15

INTCM40
INTCM41

INTDMA0
INTDMA1
INTDMA2
INTDMA3

INTCSI0

INTSER0

INTSR0

INTST0

INTCSI1

INTSER1

INTSR1

INTST1

INTCSI2
INTCSI3

INTAD

INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
INTP120/INTCC120
INTP121/INTCC121
INTP122/INTCC122
INTP123/INTCC123
INTP130/INTCC130
INTP131/INTCC131
INTP132/INTCC132
INTP133/INTCC133
INTP140/INTCC140
INTP141/INTCC141
INTP142/INTCC142
INTP143/INTCC143

INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP153/INTCC153

OVIF10
OVIF11
OVIF12
OVIF13

OVIF14
OVIF15
P10IF0
P10IF1
P10IF2
P10IF3
P11IF0
P11IF1

P11IF2
P11IF3
P12IF0
P12IF1
P12IF2
P12IF3
P13IF0
P13IF1

P13IF2
P13IF3
P14IF0
P14IF1
P14IF2
P14IF3
P15IF0
P15IF1

P15IF2
P15IF3
CMIF40
CMIF41
DMAIF0
DMAIF1
DMAIF2

DMAIF3
CSIF0
SEIF0
SRIF0
STIF0
CSIF1
SEIF1
SRIF1

STIF1
CSIF2
CSIF3
ADIF

NMI

Note Noise elimination

Remark xx: OV, CM, P10 to P15, DMA, CS, SE, SR, ST, AD

n: None, or 10 to 15, 40, 41, 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Table 8-1. List of Interrupts (1/3)

Interrupt/Exception Source

Type

Category

Name

Control

Generation Source

Generat-

ing Unit

Default

Priority

Excep-

tion

Code

Handler

Address

Restore

Interrupt

INTSR0

SRIC0

UART0 receive

completion

SIO

0320H

00000320H

nextPC

Interrupt

INTST0

STIC0

UART0 send

completion

SIO

0330H

00000330H

nextPC

Interrupt

INTCSI1

CSIC1

CSI1 send/receive

completion

SIO

0340H

00000340H

nextPC

Interrupt

INTSER1

SEIC1

UART1 receive error

SIO

0350H

00000350H

nextPC

Interrupt

INTSR1

SRIC1

UART1 receive

completion

SIO

0360H

00000360H

nextPC

Interrupt

INTST1

STIC1

UART1 send

completion

SIO

0370H

00000370H

nextPC

Interrupt

INTCSI2

CSIC2

CSI2 send/receive

completion

SIO

0380H

00000380H

nextPC

Interrupt

INTCSI3

CSIC3

CSI3 send/receive

completion

SIO

03C0H

000003C0H

nextPC

Maskable

Interrupt

INTAD

ADIC

A/D conversion

completion

ADC

0400H

00000400H

nextPC

Remarks 1. Default priority: Priority that takes precedence when two or more maskable interrupt requests having

the same priority level are generated at the same time. The highest priority is 0.

Restore PC: The PC value that is saved in EIPC or FEPC when the interrupt or exception

processing is started. However, the restore PC value that is saved when an interrupt is

acknowledged during the execution of a division instruction (DIV, DIVH, DIVU, or

DIVHU), is the PC value of the current instruction (DIV, DIVH, DIVU, or DIVHU).

2. The execution address of the illegal instruction when an illegal opcode exception occurs is obtained

according to the calculation "restore PC - 4."

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Figure 10-1. Block Diagram of Timer 1 (16-bit Timer/Event Counter)

INTOV11
TO110
TO111
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113

TO101

TO100

INTOV10

Internal system

clock ( )

INTP100/INTCC100
INTP101/INTCC101
INTP102/INTCC102
INTP103/INTCC103

INTOV15
TO150
TO151
INTP150/INTCC150
INTP151/INTCC151
INTP152/INTCC152
INTP153/INTCC153

TCLR10

TI10

INTP100

INTP101

INTP102

INTP103

TCLR11

TI11

INTP110
INTP111
INTP112
INTP113

TM11

Selector

Q
Q

Note 3

IMS100 IMS101 IMS102 IMS103

TM15

···

TCLR15

TI15

INTP150
INTP151
INTP152
INTP153

Selector

CC100

TM10 (16 bits)

TM10

ETI10

1/4

1/2

1/8

1/16

Note 2

Note 1

PRS100,
PRS101

PRM

101

Edge detection

Clear and

count control

CC101

CC102

CC103

ALV101

OVF10

Clear and
start

ALV100

Note 3

1/4

Noise

elimination

Edge

detection

(INTM1)

Notes 1. Internal count clock

2. External count clock

3. Reset priority

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

11. SERIAL INTERFACE FUNCTION

The serial interface function provides two 6-channel serial interfaces.

Up to four channels can be used at the same time.

(1) Asynchronous serial interface (UART0 and UART1): 2 channels

(2) Clocked serial interface (CSI0 to CSI3): 4 channels

Caution UART0 and CSI0 share a pin, as do UART1 and CSI1. One or the other of each pair can be

selected via a register (ASIM00, ASIM10).

11.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)

{

Transfer rate

150 bps to 76800 bps (using the dedicated baud rate generator when the internal system clock is

33 MHz)

Maximum 4.125 Mbps (using the

/2 clock when the internal system clock is 33 MHz)

{

Full duplex communications

On-chip receive buffer (RXBn)

{

2-pin configuration

TXDn : Transmit data output pin

RXDn: Receive data input pin

{

Receive error detection functions

Parity error

Framing error

Overrun error

{

Interrupt sources: 3 types

Receive error interrupt (INTSERn)

Receive completion interrupt (INTSRn)

Transmission completion interrupt (INTSTn)

{

The character length of transmission/reception data is specified by the ASIMn0 and ASIMn1 registers.

{

Character length

7, 8 bits

9 bits (when adding an expansion bit)

{

Parity function: odd, even, 0, none

{

Transmission stop bit: 1, 2 bits

{

On-chip dedicated baud rate generator

{

Serial clock (SCKn) output function

Remark n = 0, 1

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Figure 11-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)

UART1

UART0

RXD1

RXD0

RXE0

TXD1

TXD0

SCK1

SCK0

1/16

TXS0/TXS0L

RXB0/RXB0L

Transmit shift

Receive shift

Receive buffer

Receive

control

parity check

Transmit

control

parity addition

1/16

BRG0

BRG1

1/2

SCLS01, SCLS00

INTST0

INTSER0

INTSR0

INTST1

INTSER1

INTSR1

Selector

Internal system

clock ( )

11.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)

{

High-speed transfer

Maximum 10 Mbps (when the internal system clock is operating at 40 MHz) ...

PD703100-40

Maximum 8.25 Mbps (when the internal system clock is operating at 33 MHz) ...

PD703100-33,

PD703101-33,

PD703102-33

{

Half-duplex communications

{

Character length: 8 bits

{

Can switch between MSB first or LSB first for data

{

Either external serial clock input or internal serial clock output can be selected

{

3-wire type

SOn:

Serial data output

SIn:

Serial data input

SCKn: Serial clock input/output

{

Interrupt source: 1 type

Transmission/reception completion interrupt (INTCSIn)

Remark n = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

13. PORT FUNCTIONS

{

Number of ports

Dedicated input ports: 9

Input/output ports

: 114

{

Shares pins with other peripheral function I/O

{

Input and output can be specified in 1-bit units

The block diagrams of the various ports are divided into 16 block types identified by A to P as shown in Table 13-

1. Figures 13-1 to 13-16 show the block diagrams of each type.

Table 13-1. List of Port Block Types

Port Name

Pin Name

Port Function

Function in Control Mode

Block Type

Port 0

P00 to P07

8-bit input/output

Input/output of real-time pulse unit (RPU), external

interrupt input, DMA controller (DMAC) input

A, B, M

Port 1

P10 to P17

8-bit input/output

Input/output of real-time pulse unit (RPU), external

interrupt input, DMA controller (DMAC) output

A, B, K

Port 2

P20 to P27

1-bit input,

7-bit input/output

NMI input, serial interface (UART0/CSI0, UART1/CSI1)

input/output

A, C, D, I, J

Port 3

P30 to P37

8-bit input/output

Input/output of real-time pulse unit (RPU), external

interrupt input, serial interface (CSI2) input/output

A, B, K, M,

Port 4

P40 to P47

8-bit input/output

External data bus (D0 to D7)

Port 5

P50 to P57

8-bit input/output

External data bus (D8 to D15)

Port 6

P60 to P67

8-bit input/output

External address bus (A16 to A23)

Port 7

P70 to P77

8-bit input/output

A/D converter (ADC) analog input

Port 8

P80 to P87

8-bit input/output

External bus interface control signal output

O, P

Port 9

P90 to P97

8-bit input/output

External bus interface control signal input/output

H, O

Port 10

P100 to

P107

8-bit input/output

Input/output of real-time pulse unit (RPU), external

interrupt input, DMA controller (DMAC) output

A, B, K

Port 11

P110 to

P117

8-bit input/output

Input/output of real-time pulse unit (RPU), external

interrupt input, serial interface (CSI3) input/output

A, B, K, M,

Port 12

P120 to

P127

8-bit input/output

Input/output of real-time pulse unit (RPU), external

interrupt input, A/D converter (ADC) external trigger input

A, B

Port A

PA0 to PA7

8-bit input/output

External address bus (A0 to A7)

Port B

PB0 to PB7

8-bit input/output

External address bus (A8 to A15)

Port X

PX5 to PX7

3-bit input/output

Refresh request signal output, wait insertion signal input,

internal system clock output

A, L

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

15. INSTRUCTION SET

Table 15-1. Symbols Used to Describe Operands

Symbol

Description

reg1

General registers (r0 to r31): used as source registers

reg2

General registers (r0 to r31): used mainly as destination registers

reg3

General registers (r0 to r31): used mainly to store the remainders of division results and the higher 3 bits

of multiplication results

imm

-bit immediate

disp

-bit displacement

regID

System register number

bit#3

3-bit data for specifying the bit number

Element pointer (r30)

cccc

4-bit data indicating the condition code

vector

5-bit data used for specifying the trap vector (00H to 1FH)

list

List of

registers

Table 15-2. Symbols Used to Describe Opcodes

Symbol

Description

1-bit data of code specifying reg1 or regID

1-bit data of code specifying reg2

1-bit data of code specifying reg3

1-bit displacement data

1-bit immediate data

cccc

4-bit data indicating condition code

bbb

3-bit data for specifying bit number

1-bit data specifying register list

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Table 15-3. Symbols Used in Operation

Symbol

Description

Input for

GR [ ]

General register

SR [ ]

System register

zero-extend (n)

Extend n with zeros until word length

sign-extend (n)

Extend n with signs until word length

load-memory (a, b)

Read data of size b from address a

store-memory (a, b, c)

Write data b of address a by size c

load-memory-bit (a, b)

Read bit b of address a

store-memory-bit (a, b, c)

Write c to bit b of address a

saturated (n)

Execute saturation processing of n (n is a two's complement)

If, as a result of the calculation,

7FFFFFFFH, let it be 7FFFFFFFH.

80000000H, let it be 80000000H

result

Reflect the result in a flag

Byte

Byte (8 bits)

Half-word

Half word (16 bits)

Word

Word (32 bits)

Add

Subtract

Bit concatenation

Multiply

Divide

Remainder of division result

AND

Logical AND

Logical OR

XOR

Exclusive OR

NOT

Logical NOT

logically shift left by

Logical shift left

logically shift right by

Logical shift right

arithmetically shift right by

Arithmetic shift right

Table 15-4. Symbols Used for Execution Clock

Symbol

Description

i : issue

When executing another instruction immediately after executing an instruction

r : repeat

When repeating the same instruction immediately after executing the instruction

l : latency

When referring to instruction execution results in the next instruction

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Table 15-5. Symbols Used in Flag Operations

Identifier

Description

(Blank)

No change

Clear to 0

Set or cleared according to the results

Previously saved values are restored

Table 15-6. Condition Codes

Condition

Name (cond)

Condition Code

(cccc)

Condition Formula

Description

0000

OV = 1

Overflow

1000

OV = 0

No overflow

C/L

0001

CY = 1

Carry

Lower (Less than)

NC/NL

1001

CY = 0

No carry

Not lower (Greater than or equal)

Z/E

0010

Z = 1

Zero

Equal

NZ/NE

1010

Z = 0

Not zero

Not equal

0011

(CY or Z) = 1

Not higher (Less than or equal)

1011

(CY or Z) = 0

Higher (Greater than)

0100

S = 1

Negative

1100

S = 0

Positive

0101

Always (unconditional)

1101

SAT = 1

Saturated

0110

(S xor OV) = 1

Less than signed

1110

(S xor OV) = 0

Greater than or equal signed

0111

((S xor OV) or Z) = 1

Less than or equal signed

1111

((S xor OV) or Z) = 0

Greater than signed

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Instruction Set

(1/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

reg1,reg2

r r r r r 0 0 1 1 1 0 R R R R R

GR[reg2]

GR[reg2]+GR[reg1]

ADD

imm5,reg2

r r r r r 0 1 0 0 1 0 i i i i i

GR[reg2]

GR[reg2]+sign-extend(imm5)

r r r r r 1 1 0 0 0 0 r r r r r

ADDI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1]+sign-extend(imm16)

AND

reg1,reg2

r r r r r 0 0 1 0 1 0 R R R R R

GR[reg2]

GR[reg2]AND GR[reg1]

r r r r r 1 1 0 1 1 0 R R R R R

ANDI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1]AND zero-

extend(imm16)

d d d d d 1 0 1 1 d d d c c c c

When

conditions are

satisfied

Note 2

Bcond

disp9

Note 1

if conditions are satisfied

then PC

PC+sign-

extend(disp9)

When

conditions are

not satisfied

r r r r r 1 1 1 1 1 1 0 0 0 0 0

BSH

reg2,reg3

w w w w w 0 1 1 0 1 0 0 0 0 1 0

GR[reg3]

GR[reg2] (23 : 16) II GR[reg2]

(31 : 24) II GR[reg2] (7 : 0) II GR[reg2] (15 : 8)

r r r r r 1 1 1 1 1 1 0 0 0 0 0

BSW

reg2,reg3

w w w w w 0 1 1 0 1 0 0 0 0 0 0

GR[reg3]

GR[reg2] (7 : 0) II GR[reg2] (15 : 8) II

GR[reg2] (23 : 16) II GR[reg2] (31 : 24)

CALLT

imm6

0 0 0 0 0 0 1 0 0 0 i i i i i i

CTPC

PC+2(return PC)

CTPSW

PSW

adr

CTBP+zero-extend(imm6 logically

shift left by 1)

CTBP+zero-extend(Load-

memory(adr, Half-word))

1 0 b b b 1 1 1 1 1 0 R R R R R

bit#3,

disp 16[reg1]

d d d d d d d d d d d d d d d d

adr

GR[reg1]+sign-extend(disp16)

Z flags

Not(Load-memory-bit(adr,bit#3))

Store-memory-bit (adr,bit#3,0)

Note 3

r r r r r 1 1 1 1 1 1 R R R R R

CLR1

reg2,[reg1]

0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0

adr

GR[reg1]

Z flags

Not(Load-memory-bit(adr,reg2))

Store-memory-bit (adr,reg2,0)

Note 3

r r r r r 1 1 1 1 1 1 i i i i i

cccc,imm5,reg2,

reg3

w w w w w 0 1 1 0 0 0 c c c c 0

if condition are satisfied then

GR[reg3]

sign-extended(imm5)

else GR[reg3]

GR[reg2]

r r r r r 1 1 1 1 1 1 R R R R R

CMOV

cccc,reg1,reg2,

reg3

w w w w w 0 1 1 0 0 1 c c c c 0

if conditions are satisfied

then GR[reg3]

GR[reg1]

else GR[reg3]

GR[reg2]

reg1,reg2

r r r r r 0 0 1 1 1 1 R R R R R

result

GR[reg2]

GR[reg1]

CMP

imm5,reg2

r r r r r 0 1 0 0 1 1 i i i i i

result

GR[reg2]

sign-extend(imm5)

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0

CTRET

0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0

CTPC

PSW

CTPSW

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0

PSW.ID

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(2/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

0 0 0 0 0 1 1 0 0 1 i i i i i L

imm5,list12

L L L L L L L L L L L 0 0 0 0 0

sp+zero-extend(imm5 logically shift left

by 2)

GR[reg in list12]

Load-memory(sp,Word)

sp+4

repeat 2 steps above untill all regs in list12

is loaded

N+1

Note 4

N+1

Note 4

N+1

Note 4

0 0 0 0 0 1 1 0 0 1 i i i i i L

L L L L L L L L L L L R R R R R

Note 5

DISPOSE

imm5,list12,[reg1]

sp+zero-extend(imm5 logically shif left

by 2)

GR[reg in list12]

Load-memory(sp,Word)

sp+4

repeat 2 steps above until all regs in list 12

is loaded

GR[reg1]

N+3

Note 4

N+3

Note 4

N+3

Note 4

r r r r r 1 1 1 1 1 1 R R R R R

DIV

reg1,reg2,reg3

w w w w w 0 1 0 1 1 0 0 0 0 0 0

GR[reg2]

GR[reg1]

GR[reg3]

GR[reg2]%GR[reg1]

reg1,reg2

r r r r r 0 0 0 0 1 0 R R R R R

GR[reg2]

GR[reg1]

Note 6

r r r r r 1 1 1 1 1 1 R R R R R

DIVH

reg1,reg2,reg3

w w w w w 0 1 0 1 0 0 0 0 0 0 0

GR[reg2]

GR[reg1]

Note 6

GR[reg3]

GR[reg2]%GR[reg1]

r r r r r 1 1 1 1 1 1 R R R R R

DIVHU

reg1,reg2,reg3

w w w w w 0 1 0 1 0 0 0 0 0 1 0

GR[reg2]

GR[reg1]

Note 6

GR[reg3]

GR[reg2]%GR[reg1]

r r r r r 1 1 1 1 1 1 R R R R R

DIVU

reg1,reg2,reg3

w w w w w 0 1 0 1 1 0 0 0 0 1 0

GR[reg2]

GR[reg1]

GR[reg3]

GR[reg2]%GR[reg1]

1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0

PSW.ID

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0

HALT

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0

Stop

r r r r r 1 1 1 1 1 1 0 0 0 0 0

HSW

reg2,reg3

w w w w w 0 1 1 0 1 0 0 0 1 0 0

GR[reg3]

GR[reg2] (15 : 0) II GR[reg2]

(31: 6)

r r r r r 1 1 1 1 0 d d d d d d

d d d d d d d d d d d d d d d 0

JARL

disp22,reg2

Note 7

GR[reg2]

PC+4

PC+signextend(disp22)

JMP

[reg1]

0 0 0 0 0 0 0 0 0 1 1 R R R R R

GR[reg1]

0 0 0 0 0 1 1 1 1 0 d d d d d d

d d d d d d d d d d d d d d d 0

disp22

Note 7

PC+sign-extend(disp22)

r r r r r 1 1 1 0 0 0 R R R R R

LD.B

disp16[reg1],reg2

d d d d d d d d d d d d d d d d

adr

GR[reg1]+signe-extend(disp16)

GR[reg2]

sign-extend(Load-memory

(adr,Byte))

Note 9

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(3/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

r r r r r 1 1 1 1 0 b R R R R R

d d d d d d d d d d d d d d d 1

LD.BU

disp16[reg1],reg2

Notes 8, 10

adr

GR[reg1]+sign-extend(disp16)

GR[reg2]

zero-extend(Load-memory

(adr,Byte))

Note 11

r r r r r 1 1 1 0 0 1 R R R R R

d d d d d d d d d d d d d d d 0

LD.H

disp16[reg1],reg2

Note 8

adr

GR[reg1]+sign-extend(disp16)

GR[reg2]

sign-extend(Load-memory

(adr,Half-word))

Note 9

r r r r r 1 1 1 1 1 1 R R R R R

d d d d d d d d d d d d d d d 1

LD.HU

disp16[reg1],reg2

Note 8

adr

GR[reg1]+sign-extend(disp16)

GR[reg2]

zero-extend(Load-memory

(adr,Half-word))

Note 11

r r r r r 1 1 1 0 0 1 R R R R R

LD.W

disp16[reg1],reg2

d d d d d d d d d d d d d d d 1

adr

GR[reg1]+signe-extend(disp16)

GR[reg2]

Load-memory(adr,Word)

Note 9

r r r r r 1 1 1 1 1 1 R R R R R

0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Other than

regID=PSW

LDSR

reg2,regID

Note 12

SR[regID]

GR[reg2]

regID=PSW

reg1,reg2

r r r r r 0 0 0 0 0 0 R R R R R

GR[reg2]

GR[reg1]

imm5,reg2

r r r r r 0 1 0 0 0 0 i i i i i

GR[reg2]

sign-extend(imm5)

0 0 0 0 0 1 1 0 0 0 1 R R R R R

i i i i i i i i i i i i i i i i

MOV

imm32,reg1

i i i i i i i i i i i i i i i i

GR[reg1]

imm32

r r r r r 1 1 0 0 0 1 R R R R R

MOVEA

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1]+ sign-extend(imm16)

r r r r r 1 1 0 0 1 0 R R R R R

MOVHI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1]+(imm16 II 0

)

r r r r r 1 1 1 1 1 1 R R R R R

reg1,reg2,reg3

w w w w w 0 1 0 0 0 1 0 0 0 0 0

GR[reg3] II GR[reg2]

GR[reg2]

GR[reg1]

Note 14

r r r r r 1 1 1 1 1 1 i i i i i

MUL

imm9,reg2,reg3

w w w w w 0 1 0 0 1 1 1 1 1 0 0

GR[reg3] II GR[reg2]

GR[reg2]

sign-

extend(imm9)

Note 13

Note 14

reg1,reg2

r r r r r 0 0 0 1 1 1 R R R R R

GR[reg2]

Note 6

GR[reg1]

Note 6

MULH

imm5,reg2

r r r r r 0 1 0 1 1 1 i i i i i

GR[reg2]

Note 6

sign-extend (imm5)

r r r r r 1 1 0 1 1 R R R R R R

MULHI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1]

Note 6

imm16

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(4/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

r r r r r 1 1 1 1 1 1 R R R R R

reg1,reg2,reg3

w w w w w 0 1 0 0 0 1 0 0 0 1 0

GR[reg3] II GR[reg2]

GR[reg2]

GR[reg1]

Note 14

r r r r r 1 1 1 1 1 1 i i i i i

MULU

imm9,reg2,reg3

w w w w w 0 1 0 0 1 1 1 1 1 1 0

GR[reg3] II GR[reg2]

GR[reg2]

zero-

extend(imm9)

Note 14

NOP

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Pass at least one clock cycle doing nothing

NOT

reg1,reg2

r r r r r 0 0 0 0 0 1 R R R R R

GR[reg2]

NOT(GR[reg1])

0 1 b b b 1 1 1 1 1 0 R R R R R

bit#3,disp16[reg1]

d d d d d d d d d d d d d d d d

adr

GR[reg1]+sign-extend(disp16)

Z flag

Not(Load-memory-bit(adr,bit#3))

Store-memory-bit(adr,bit#3,Z flag)

Note 3

r r r r r 1 1 1 1 1 1 R R R R R

NOT1

reg2,[reg1]

0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0

adr

GR[reg1]

Z flag

Not(Load-memory-bit(adr,reg2))

Store-memory-bit(adr,reg2,Z flag)

Note 3

reg1,reg2

r r r r r 0 0 1 0 0 0 R R R R R

GR[reg2]

GR[reg2] OR GR[reg1]

r r r r r 1 1 0 1 0 0 R R R R R

ORI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1] OR zero-

extend(imm16)

0 0 0 0 0 1 1 1 1 0 i i i i i L

list12,imm5

L L L L L L L L L L L 0 0 0 0 1

Store-memory(sp-4,GR[reg in list12],Word)

sp-4

repeat 1 step above until all regs in list12 is

stored sp

sp-zero-extend(imm5)

N+1

Note 4

N+1

Note 4

N+1

Note 4

0 0 0 0 0 1 1 1 1 0 i i i i i L

L L L L L L L L L L L f f 0 1 1

PREPARE

list12,imm5,

sp/imm

Note 15

imm16/imm32

Note 16

Store-memory(sp-4,GR[reg in list12],Word)

sp-4

repeat 1 step above until all regs in list12 is

stored sp

sp-zero-extend(imm5)

N+2

Note 4

Note 17

N+2

Note 4

Note 17

N+2

Note 4

Note 17

0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0

RETI

0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0

if PSW.EP=1

then PC

EIPC

PSW

EIPSW

else if PSW.NP = 1

then PC

FEPC

PSW

FEPSW

else

EIPC

PSW

EIPSW

r r r r r 1 1 1 1 1 1 R R R R R

reg1,reg2

0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0

GR[reg2]

GR[reg2]arithmetically shift right

by GR[reg1]

SAR

imm5,reg2

r r r r r 0 1 0 1 0 1 i i i i i

GR[reg2]

GR[reg2]arithmetically shift right

by zero-extend(imm5)

r r r r r 1 1 1 1 1 0 c c c c c

SASF

cccc,reg2

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0

if conditions are satisfied

then GR[reg2]

(GR[reg2] Logically shift

left by 1)

OR 00000001H

else GR[reg2]

(GR[reg2] Logically shift

left by 1)

OR 00000000H

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(5/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

SATADD

reg1,reg2

r r r r r 0 0 0 1 1 0 R R R R R

GR[reg2]

saturated(GR[reg2]+GR[reg1])

imm5,reg2

r r r r r 0 1 0 0 0 1 i i i i i

GR[reg2]

saturated(GR[reg2]+sign-

extend(imm5)

SATSUB

reg1,reg2

r r r r r 0 0 0 1 0 1 R R R R R

GR[reg2]

saturated(GR[reg2]

GR[reg1])

r r r r r 1 1 0 0 1 1 R R R R R

SATSUBI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

saturated(GR[reg1]

sign-

extend(imm16)

SATSUBR

reg1,reg2

r r r r r 0 0 0 1 0 0 R R R R R

GR[reg2]

saturated(GR[reg1]

GR[reg2])

r r r r r 1 1 1 1 1 1 0 c c c c

SETF

cccc,reg2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

If conditions are satisfied

then GR[reg2]

00000001H

else GR[reg2]

00000000H

0 0 b b b 1 1 1 1 1 0 R R R R R

bit#3,disp16[reg1]

d d d d d d d d d d d d d d d d

adr

GR[reg1]+sign-extend(disp16)

Z flag

Not(Load-memory-bit(adr,bit#3))

Store-memory-bit(adr,bit#3,1)

Note 3

r r r r r 1 1 1 1 1 1 R R R R R

SET1

reg2,[reg1]

0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0

adr

GR[reg1]

Z flag

Not(Load-memory-bit(adr,reg2))

Store-memory-bit(adr,reg2,1)

Note 3

r r r r r 1 1 1 1 1 1 R R R R R

SHL

reg1,reg2

0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0

GR[reg2]

GR[reg2] logically shift left by

GR[reg1]

imm5,reg2

r r r r r 0 1 0 1 1 0 i i i i i

GR[reg2]

GR[reg2] logically shift left by

zero-extend(imm5)

r r r r r 1 1 1 1 1 1 R R R R R

SHR

reg1,reg2

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

GR[reg2]

GR[reg2] logically shift right by

GR[reg1]

imm5,reg2

r r r r r 0 1 0 1 0 0 i i i i i

GR[reg2]

GR[reg2] logically shift right by

zero-extend(imm5)

SLD.B

disp7[ep],reg2

r r r r r 0 1 1 0 d d d d d d d

adr

ep+zero-extend(disp7)

GR[reg2]

sign-extend(Load-

memory(adr,Byte))

Note 9

SLD.BU

disp4[ep],reg2

Note 18

r r r r r 0 0 0 0 1 1 0 d d d d

adr

ep+zero-extend(disp4)

GR[reg2]

zero-extend(Load-

memory(adr,Byte))

Note 9

r r r r r 1 0 0 0 d d d d d d d

SLD.H

disp8[ep],reg2

Note 19

adr

ep+zero-extend(disp8)

GR[reg2]

sign-extend(Load-

memory(adr,Half-word))

Note 9

SLD.HU

disp5[ep],reg2

Notes 18, 20

r r r r r 0 0 0 0 1 1 1 d d d d

adr

ep+zero-extend(disp5)

GR[reg2]

zero-extend(Load-

memory(adr,Half-word))

Note 9

r r r r r 1 0 1 0 d d d d d d 0

SLD.W

disp8[ep],reg2

Note 21

adr

ep+zero-extend(disp8)

GR[reg2]

Load-memory(adr,Word))

Note 9

SST.B

reg2,disp7[ep]

r r r r r 0 1 1 1 d d d d d d d

adr

ep+zero-extend(disp7)

Store-memory(adr,GR[reg2],Byte)

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(6/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

r r r r r 1 0 0 1 d d d d d d d

SST.H

reg2,disp8[ep]

Note 19

adr

ep+zero-extend(disp8)

Store-memory(adr,GR[reg2],Half-word)

r r r r r 1 0 1 0 d d d d d d 1

SST.W

reg2,disp8[ep]

Note 21

adr

ep+zero-extend(disp8)

Store-memory(adr,GR[reg2],Word)

r r r r r 1 1 1 0 1 0 R R R R R

ST.B

reg2,disp16[reg1]

d d d d d d d d d d d d d d d d

adr

GR[reg1]+sign-extend(disp16)

Store-memory(adr,GR[reg2],Byte)

r r r r r 1 1 1 0 1 1 R R R R R

d d d d d d d d d d d d d d d 0

ST.H

reg2,disp16[reg1]

Note 8

adr

GR[reg1]+sign-extend(disp16)

Store-memory(adr,GR[reg2],Half-word)

r r r r r 1 1 1 0 1 1 R R R R R

d d d d d d d d d d d d d d d 1

ST.W

reg2,disp16[reg1]

Note 8

adr

GR[reg1]+sign-extend(disp16)

Store-memory(adr,GR[reg2],Word)

r r r r r 1 1 1 1 1 1 R R R R R

STSR

regID,reg2

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

GR[reg2]

SR[regID]

SUB

reg1,reg2

r r r r r 0 0 1 1 0 1 R R R R R

GR[reg2]

GR[reg1]

SUBR

reg1,reg2

r r r r r 0 0 1 1 0 0 R R R R R

GR[reg2]

GR[reg1]

GR[reg2]

SWITCH

reg1

0 0 0 0 0 0 0 0 0 1 0 R R R R R

adr

(PC+2)+(GR[reg1] logically shift left

by 1)

(PC+2)+sign-extend((Load-

memory(adr,Hafl-word))

logically shift left by 1)

SXB

reg1

0 0 0 0 0 0 0 0 1 0 1 R R R R R

GR[reg1]

sign-extend

(GR[reg1] (7 : 0)

SXH

reg1

0 0 0 0 0 0 0 0 1 1 1 R R R R R

GR[reg1]

sign-extend

(GR[reg1] (15 : 0))

0 0 0 0 0 1 1 1 1 1 1 i i i i i

TRAP

vector

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

EIPC

PC+4 (restore PC)

EIPSW

PSW

ECR.EICC

Interrupt code

PSW.EP

PSW.ID

00000040H (when vector

is 00H to 0FH)

00000050H (when vector

is 10H to 1FH)

TST

reg1,reg2

r r r r r 0 0 1 0 1 1 R R R R R

result

GR[reg2] AND GR[reg1]

1 1 b b b 1 1 1 1 1 0 R R R R R

bit#3,disp16[reg1]

d d d d d d d d d d d d d d d d

adr

GR[reg1]+sign-extend(disp16)

Z flag

Not(Load-memory-bit(adr,bit#3))

Note 3

r r r r r 1 1 1 1 1 1 R R R R R

TST1

reg2,[reg1]

0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0

adr

GR[reg1]

Z flag

Not(Load-memory-bit(adr,reg2))

Note 3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(7/7)

Execution

Clock

Flags

Mnemonic

Operand

Opcode

Operation

SAT

XOR

reg1,reg2

r r r r r 0 0 1 0 0 1 R R R R R

GR[reg2]

GR[reg2] XOR GR[reg1]

r r r r r 1 1 0 1 0 1 R R R R R

XORI

imm16,reg1,reg2

i i i i i i i i i i i i i i i i

GR[reg2]

GR[reg1] XOR zero-extend

(imm16)

ZXB

reg1

0 0 0 0 0 0 0 0 1 0 0 R R R R R

GR[reg1]

zero-extend(GR[reg1] (7 : 0))

ZXH

reg1

0 0 0 0 0 0 0 0 1 1 0 R R R R R

GR[reg1]

zero-extend(GR[reg1] (15 : 0))

Notes 1. dddddddd: Higher 8 bits of disp9.

2. 3 clocks if the final instruction includes PSW write access.

3. If there is no wait state (3 + the number of read access wait states).

4. N is the total number of list 12 read registers. (according to the number of wait states. Also, if there are

no wait states, N is the number of list 12 registers.)

5. RRRRR other than 00000.

6. Only the lower half word data are valid.

7. ddddddddddddddddddddd: Higher 21 bits of disp22.

8. ddddddddddddddd: Higher 15 bits of disp16.

9. According to the number of wait states (1 if there are no wait states).

10. b: bit 0 of disp16.

11. According to the number of wait states (2 if there are no wait states).

12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the

reg1 field is used in the op code. Therefore, the meaning of the register specification in the mnemonic

description and in the opcode differs from other instructions.

rrrrr

: regID specification

RRRRR: reg2 specification

13. 11111: Lower 5 bits of imm9.

1111 : Lower 4 bits of imm9.

14. 1 when r = w (the lower 32 bits of the results are not written in the register) or w = r0 (the higher 32 bits

of the results are not written in the register).

15. sp/imm: specified by bits 19 and 20 of the sub opcode.

16. ff = 00: load sp in ep.

01: load sign expanded 16-bit immediate data (bits 47 to 32) in ep.

10: load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.

11: load 32-bit immediate data (bits 63 to 32) in ep.

17. If imm=imm32, N + 3 clocks.

18. rrrrr other than 00000.

19. ddddddd: Higher 7 bits of disp8.

20. dddd: Higher 4 bits of disp5.

21. dddddd: Higher 6 bits of disp8.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

16. ELECTRICAL SPECIFICATIONS (PRELIMINARY VALUES)

Absolute Maximum Ratings (T

= 25

°
°
°
°

Parameter

Symbol

Condition

Rating

Unit

0.5 to +4.6

pin, HV

0.5 to +7.0

0.5 to +4.6

0.5 to +0.5

0.5 to HV

+ 0.5

Power supply voltage

0.5 to +0.5

X1 pin, except MODE3 pin

0.5 to HV

+ 0.5

Input voltage

MODE3 pin

0.5 to V

+ 0.5

Clock input voltage

X1, V

= 3.0 to 3.6 V

0.5 to V

+ 1.0

1 pin

4.0

Low-level output current

Total of all pins

100

1 pin

4.0

High-level output current

Total of all pins

100

Output voltage

= 5.0 V

10 %

0.5 to HV

+ 0.5

> HV

0.5 to HV

+ 0.5

Analog input voltage

IAN

P70/ANI0 to

P77/ANI7 pins

0.5 to AV

+ 0.5

> HV

0.5 to HV

+ 0.5

A/D converter reference input

voltage

REF

0.5 to AV

+ 0.5

Operating ambient temperature

PD703100-40

40 to +70

PD703100-33, 703101-33, 703102-33

40 to +85

Storage temperature

stg

60 to +150

Caution

1. Do not make direct connections of the output (or input/output) pins of the IC product with

each other, and also avoid direct connections to V

, V

, or GND. However, the open drain

pins or the open collector pins can be directly connected with each other. A direct

connection can also be made for an external circuit designed with timing specifications that

prevent conflicting output from pins subject to high-impedance state.

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily

for any parameter. That is, the absolute maximum ratings are rated values at which the

product is on the verge of suffering physical damage, and therefore the product must be

used under conditions that ensure that the absolute maximum ratings are not exceeded.

The ratings and conditions shown below for DC characteristics and AC characteristics are

within the range for normal operation and quality assurance.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Capacitance (T

= 25

°
°
°
°

C, V

= HV

= CV

= V

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input capacitance

Input/output capacitance

Output capacitance

fc = 1 MHz

Unmeasured pins returned to 0 V.

Operating Conditions

Operation

Mode

Internal Operating Clock Frequency (

)

Operating Ambient

Temperature (T

)

Power Supply Voltage

, HV

)

PD703100-40

2 to 40 MHz

40 to +70

Direct mode

PD703100-33, 703101-33, 703102-33

2 to 33 MHz

40 to +85

PD703100-40

20 to 40 MHz

40 to +70

PLL mode

PD703100-33, 703101-33, 703102-33

20 to 33 MHz

40 to +85

= 3.0 to 3.6 V,

= 5.0 V

10%

Recommended Oscillation Circuits

(a) Ceramic resonator or crystal resonator connection (T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40,

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-33,

µ
µ
µ
µ

PD703102-33)

Cautions

1. Connect the oscillation circuit as closely to the X1 and X2 pins as possible.

2. Do not wire any other signal lines in the area indicated by the broken line.

3. Throughly evaluate the matching between the

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703100-40,

µ
µ
µ
µ

PD703101-33,

and

µ
µ
µ
µ

PD703102-33 and the oscillators.

(b) External clock input (T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40, T

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-

33,

µ
µ
µ
µ

PD703102-33)

Open

External clock

Caution Input CMOS-level voltage to the X1 pin.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

DC Characteristics (T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40,T

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-33,

µ
µ
µ
µ

PD703102-33, V

= CV

= 3.0 to 3.6 V, HV

= 5.0

±
±
±
±

10%, V

=0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Except Note 1

2.2

+ 0.3

High-level input voltage

Note 1

0.8HV

+ 0.3

Except Note 1 and Note 2

0.5

+0.8

Low-level input voltage

Note 1

0.5

0.2HV

X1 pin

Direct mode

0.8V

+ 0.3

High-level clock input voltage

PLL mode

0.8V

+ 0.3

X1 pin

Direct mode

0.3

0.15V

Low-level clock input voltage

PLL mode

0.3

0.15V

Note 1, rising edge

3.0

Schmitt-triggered input

threshold voltage

Note 1, falling edge

2.0

Schmitt-triggered input

hysteresis width

Note 1

0.5

2.5 mA

0.7HV

High-level output voltage

100

0.4

Low-level output voltage

= 2.5 mA

0.45

High-level input leakage

current

LIH

Except V

= H

VDD

or Note 2

Low-level input leakage

current

LIL

Except V

= 0 V or Note 2

High-level output leakage

current

LOH

= H

VDD

Low-level output leakage

current

LOL

= 0 V

Analog pin input leakage

current

LIAN

Note 2

T.B.D.

otes

1. P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,

P34/INTP130, P35/INTP131/SO2, P36/INTP132/S12, P37/INTP133/SCK2, P104/INTP120/TC0 to

P107/INTP123/TC3, Pl14/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3,

P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,

P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14,

P123/TI15, P20/NMI, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2,

RESET

2. When the P70/ANI0 to P77/ANI7 pins are used as analog input.

Remark TYP. values are reference values for when T

= 25

C, V

= CV

= 3.3 V, and HV

= 5.0 V.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

DC Characteristics (T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40,T

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-33,

µ
µ
µ
µ

PD703102-33, V

= CV

= 3.0 to 3.6 V, HV

= 5.0

±
±
±
±

10%, V

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

+ CV

2.0

3.6

Direct mode

1.8

3.0

+ CV

2.7

17.0

3.6

During

normal

operation

DD1

PLL mode

1.3

3.6

3.0

+ CV

1.4

2.5

Direct mode

0.8

1.6

+ CV

1.8

10.0

2.5

HALT mode

DD2

PLL mode

0.8

1.0

1.6

+ CV

1.5

3.0

Direct mode

PLL mode

+ CV

1.8

3.0

IDLE mode

DD3

+ CV

100

Power supply

current

STOP

mode

DD4

Remarks 1. TYP. values are reference values for when T

= 25°C, V

= CV

= 3.3 V, and HV

= 5.0 V.

2. Direct mode:

= 2 to 40 MHz (

PD703100-40)

= 2 to 33 MHz (

PD703100-33,

PD703101-33,

PD703102-33)

PLL mode:

= 20 to 40 MHz (

PD703100-40)

= 20 to 33 MHz (

PD703100-33,

PD703101-33,

PD703102-33)

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Data Hold Characteristics(T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40, T

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-

33,

µ
µ
µ
µ

PD703102-33)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

DDDR

STOP mode, V

= V

DDDR

1.5

3.6

Data hold voltage

DDDR

STOP mode,

= HV

DDDR

5.5

Data hold current

DDDR

= V

DDDR

T.B.D.

Power supply voltage rise

time

RVD

200

Power supply voltage fall time

FVD

200

Power supply voltage hold

time (to STOP mode setting)

HVD

STOP mode release signal

input time

DREL

Data hold high-level input

voltage

IHDR

Note

0.8 HV

DDDR

Data hold low-level input

voltage

ILDR

Note

0.2 HV

DDDR

Note P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3,

P34/INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to

P107/INTP123/TC3, P114/INTP140, P115/INTP141/SO3, Pl16/INTP142/SI3, P117/INTP143/SCK3,

P124/INTP150 to P126/INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13,

P102/TCLR12, P112/TCLR14, P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12,P113/TI14,

P123/TI15, P20/NMI, P23/RXD0/SI0 ,P24/SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET

Remark TYP. values are reference values for when T

= 25

RESET (input)

IHDR

ILDR

HVD

FVD

DDDR

RVD

DREL

STOP mode setting

NMI (input)
(Released by falling edge)

NMI (input)
(Released by rising edge)

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

AC Characteristics (T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40, T

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-33,

µ
µ
µ
µ

PD703102-33, V

= CV

= 3.0 to 3.6 V, HV

= 5.0

±
±
±
±

10%, V

= 0 V, output pin load

capacitance: C

= 50 pF)

AC Test Input Waveform

(a) P04/INTP100/DMARQ0 to P07/INTP103/DMARQ3, P14/INTP110/DMAAK0 to P17/INTP113/DMAAK3, P34/

INTP130, P35/INTP131/SO2, P36/INTP132/SI2, P37/INTP133/SCK2, P104/INTP120/TC0 to P107/INTP123/

TC3, P114/INTP140, P115/INTP141/SO3, P116/INTP142/SI3, P117/INTP143/SCK3, P124/INTP150 to P126/

INTP152, P127/INTP153/ADTRG, P02/TCLR10, P12/TCLR11, P32/TCLR13, P102/TCLR12, P112/TCLR14,

P122/TCLR15, P03/TI10, P13/TI11, P33/TI13, P103/TI12, P113/TI14, P123/TI15, P20/NMI, P23/RXD0/SI0, P24/

SCK0, P26/RXD1/SI1, P27/SCK1, MODE0 to MODE2, RESET

0 V

0.8HV

0.2HV

0.8HV

0.2HV

Test

points

Input signal

(b) Pins other than those listed in (a) above

2.4 V

0.4 V

2.2 V

0.8 V

2.2 V

0.8 V

Test

points

Input signal

AC Test Output Test Points

2.4 V

0.8 V

2.4 V

0.8 V

Test

points

Output Signal

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Load Condition

= 50 pF

DUT

(Measured Device)

Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert

a buffer or other element to reduce the devide's load capacitance 50 pF.

(1) Clock timing

Parameter

Symbol

Condition

MIN.

MAX.

Unit

PD703100-40

12.5

250

Direct

mode

PD703100-33,

703101-33,

703102-33

250

PD703100-40

125

250

X1 input cycle

<1>

CYX

PLL mode

PD703100-33,

703101-33,

703102-33

150

250

Direct mode

X1 input high-level width

<2>

WXH

PLL mode

Direct mode

X1 input low-level width

<3>

WXL

PLL mode

Direct mode

X1 input rise time

<4>

PLL mode

X1 input fall time

<5>

Direct mode

PLL mode

PD703100-40

MHz

CPU operating frequency

PD703100-33, 703101-33,

703102-33

MHz

CLKOUT output cycle

<6>

CYK

500

CLKOUT input high-level width

<7>

WKH

0.5T 7

CLKOUT input low-level width

<8>

WKL

0.5T 4

CLKOUT input rise time

<9>

CLKOUT input fall time

<10>

CLKOUT output delay time from X1

<11>

DXK

Direct mode

T.B.D.

Remark T = t

CYK

Parameter

Symbol

Condition

TYP.

Unit

Free-running oscillation frequency

PLL mode

T.B.D.

MHz

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(4) SRAM, external ROM, or external I/O access timing

(a) Access timing (SRAM, external ROM, or external I/O) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Address, CSn output delay time (from

CLKOUT

)

<16>

DKA

Address, CSn output hold time (from

CLKOUT

)

<17>

HKA

RD, IORD

delay time

(from CLKOUT

)

<18>

DKRDL

RD, IORD

delay time

(from CLKOUT

)

<19>

HKRDH

UWR, LWR, IOWR

delay time (from

CLKOUT

)

<20>

DKWRL

UWR, LWR, IOWR

delay time (from

CLKOUT

)

<21>

HKWRH

BCYST

delay time (from CLKOUT

)

<22>

DKBSL

BCYST

delay time (from CLKOUT

)

<23>

HKBSH

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

Data input setup time

(to CLKOUT

)

<26>

SKID

Data input hold time

(from CLKOUT

)

<27>

HKID

Data output delay time

(from CLKOUT

)

<28>

DKOD

Data output hold time

(from CLKOUT

)

<29>

HKOD

Remarks 1. Maintain at least one of the data input hold times t

HKID

and t

HRDID

2. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(b) Read timing (SRAM, external ROM, or external I/O) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Data input setup time (to address)

<30>

SAID

(1.5 + w

+ w) T 28

Data input setup time (to RD)

<31>

SRDID

(1 + w

+ w) T 32

RD, IORD low-level width

<32>

WRDL

(1 + w

+ w) T 10

RD, IORD high-level width

<33>

WRDH

T 10

RD, IORD

delay time from address,

CSn

<34>

DARD

0.5T 10

Address delay time from RD, IORD

<35>

DRDA

(0.5 + i) T 10

Data input hold time (from RD, IORD

)

<36>

HRDID

Data output delay time from RD, IORD

<37>

DRDOD

(0.5 + i) T 10

WAIT setup time (to address)

<38>

SAW

Note

T 25

WAIT setup time (to BCYST

)

<39>

SBSW

Note

T 25

WAIT hold time (to BCYST

)

<40>

HBSW

Note

Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the DWC1 and DWC2 registers.

4. i: the number of idle states that are inserted when a write cycle follows a read cycle.

5. Maintain at least one of the data input hold times t

HKID

and t

HRDID

6. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(c) Write timing (SRAM, external ROM, or external I/O) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to address)

<38>

SAW

Note

T 25

WAIT setup time (to BCYST

)

<39>

SBSW

Note

T 25

WAIT hold time (from BCYST

)

<40>

HBSW

Note

UWR, LWR, IOWR

delay time from

address, CSn

<41>

DAWR

0.5T 10

Address setup time (to UWR, LWR,

IOWR

)

<42>

SAWR

(1.5 + w

+ w) T 10

Address delay time from UWR, LWR,

IOWR

<43>

DWRA

0.5T 10

UWR, LWR, IOWR high-level width

<44>

WWRH

T 10

UWR, LWR, IOWR low-level width

<45>

WWRL

(1 + w

+ w) T 10

Data output setup time

(to UWR, LWR, IOWR

)

<46>

SODWR

(1.5 + w

+ w) T 10

Data output hold time

(from UWR, LWR, IOWR

)

<47>

HWROD

0.5T 10

Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the DWC1 and DWC2 registers.

4. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(d) DMA flyby transfer timing (SRAM

external I/O transfer) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

RD low-level width

<32>

WRDL

(1 + w

+ w

+ w)

T 10

RD high-level width

<33>

WRDH

T 10

delay time from address, CSn

<34>

DARD

0.5T 10

Address delay time from RD

<35>

DRDA

(0.5 + i) T 10

Data output delay time from RD

<37>

DRDOD

(0.5 + i) T 10

WAIT setup time (to address)

<38>

SAW

Note

T 25

WAIT setup time (to BCYST

)

<39>

SBSW

Note

T 25

WAIT hold time (from BCYST

)

<40>

HBSW

Note

IOWR

delay time from address

<41>

DAWR

0.5T 10

Address setup time (to IOWR

)

<42>

SAWR

(1.5 + w

+ w) T 10

Address delay time from UWR, LWR,

IOWR

<43>

DWRA

0.5T 10

IOWR high-level width

<44>

WWRH

T 10

IOWR low-level width

<45>

WWRL

(1 + w

+ w) T 10

= 0

delay time from IOWR

<48>

DWRRD

= 1

T 10

IOWR

delay time from DMAAKm

<49>

DDAWR

0.5T 10

DMAAKm

delay time from IOWR

<50>

DWRDA

(0.5 + w

) T 10

Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the DWC1 and DWC2 registers.

4. w

: the number of waits that are inserted for a source-side access during a DMA flyby transfer.

5. i: the number of idle states that are inserted when a write cycle follows a read cycle.

6. n = 0 to 7, m = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(e) DMA flyby transfer timing (external I/O

SRAM transfer) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

IORD low-level width

<32>

WRDL

(1 + w

+ w

+ w)

T 10

IORD high-level width

<33>

WRDH

T 10

IORD

delay time from address, CSn

<34>

DARD

0.5T 10

Address delay time from IORD

<35>

DRDA

(0.5 + i) T 10

Data output delay time from IORD

<37>

DRDOD

(0.5 + i) T 10

WAIT setup time (to address)

<38>

SAW

Note

T 25

WAIT setup time (to BCYST

)

<39>

SBSW

Note

T 25

WAIT hold time (from BCYST

)

<40>

HBSW

Note

UWR, LWR

delay time from address

<41>

DAWR

0.5T 10

Address setup time (to UWR, LWR

)

<42>

SAWR

(1.5 + w

+ w) T 10

Address delay time from UWR, LWR,

IOWR

<43>

DWRA

0.5T 10

UWR, LWR high-level width

<44>

WWRH

T 10

UWR, LWR low-level width

<45>

WWRL

(1 + w

+ w) T 10

= 0

IORD

delay time from UWR, LWR

<48>

DWRRD

= 1

T 10

IORD

delay time from DMAAKm

<51>

DDARD

0.5T 10

DMAAKm

delay time from IORD

<52>

DRDDA

0.5T 10

Note For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the DWC1 and DWC2 registers.

4. w

: the number of waits that are inserted for a source-side access during a DMA flyby transfer.

5. i: the number of idle states that are inserted when a write cycle follows a read cycle.

6. n = 0 to 7, m = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(5) Page ROM access timing (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

Data input setup time

(to CLKOUT

)

<26>

SKID

Data input hold time

(from CLKOUT

)

<27>

HKID

Off-page data input setup time (to

address)

<30>

SAID

(1.5 + w

+ w) T 28

Off-page data input setup time (to RD)

<31>

SRDID

(1 + w

+ w) T 32

Off-page RD low-level width

<32>

WRDL

(1 + w

+ w) T 10

RD high-level width

<33>

WRDH

0.5T 10

Data input hold time (from RD)

<36>

HRDID

Data output delay time from RD

<37>

DRDOD

(0.5 + i) T 10

On-page RD low-level width

<53>

WORDL

(1.5 + w

+ w)

T 10

On-page data input setup time

(to address)

<54>

SOAID

(1.5 + w

+ w) T 28

On-page data input setup time (to RD)

<55>

SORDID

(1.5 + w

+ w) T 32

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the DWC1 and DWC2 registers.

4. w

: the number of waits due to the PRC register.

5. i: the number of idle states that are inserted when a write cycle follows a read cycle.

6. Maintain at least one of the data input hold times t

HKID

and t

HRDID

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(5) Page ROM access timing (2/2)

CLKOUT (Output)

On-page address

Note

TDW

TO1

TPRW

TO2

<24>

<25>

<24>

<25>

<24>

<25>

<24>

<25>

<26>

<27>

<36>

<32>

<31>

<53>

<55>

<27>

<26>

<36>

<37>

<33>

<30>

<54>

Off-page address

Note

CSn (Output)

UWR, LWR (Output)

RD (Output)

D0 to 15 (I/O)

WAIT (Input)

BCYST (Output)

Note On-page and off-page addresses are as follows.

PRC register

MA5

MA4

MA3

On-page Addresses

Off-page Addresses

A0, A1

A2 to A23

A0 to A2

A3 to A23

A0 to A3

A4 to A23

A0 to A4

A5 to A23

Remarks 1. This is the timing for the following case.

Number of waits due to the DWC1 and DWC2 registers (TDW) : 1

Number of waits due to the PRC register (TPRW)

: 1

2. The broken lines indicate high impedance.

3. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(6) DRAM access timing

(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

Data input setup time (to CLKOUT

)

<26>

SKID

Data input hold time (from CLKOUT

)

<27>

HKID

Data output delay time from OE

<37>

DRDOD

(0.5 + i) T 10

Row address setup time

<56>

ASR

(0.5 + w

) T 10

Row address hold time

<57>

RAH

(0.5 + w

) T 10

Column address setup time

<58>

ASC

0.5T 10

Column address hold time

<59>

CAH

(1.5 + w

+ w) T 10

Read/write cycle time

<60>

(3 + w

+ w

+ w)

T 10

RAS precharge time

<61>

(0.5 + w

) T 10

RAS pulse time

<62>

RAS

(2.5 + w

+ w

+ w)

T 10

RAS hold time

<63>

RSH

(1.5 + w

+ w) T 10

Column address read time for RAS

<64>

RAL

(2 + w

+ w) T 10

CAS pulse width

<65>

CAS

(1 + w

+ w) T 10

CAS-RAS precharge time

<66>

CRP

(1 + w

) T 10

CAS hold time

<67>

CSH

(2 + w

+ w

+ w)

T 10

WE setup time

<68>

RCS

(2 + w

+ w

) T 10

WE hold time (from RAS

)

<69>

RRH

0.5T 10

WE hold time (from CAS

)

<70>

RCH

T 10

CAS precharge time

<71>

CPN

(2 + w

+ w

) T 10

Output enable access time

<72>

OEA

(2 + w

+ w

+ w)

T 28

RAS access time

<73>

RAC

(2 + w

+ w

+ w)

T 28

Access time from column address

<74>

(1.5 + w

+ w) T 28

CAS access time

<75>

CAC

(1 + w

+ w) T 28

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

4. w

: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

5. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

6. i: the number of idle states that are inserted when a write cycle follows a read cycle.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(b) Read timing (high-speed page DRAM access: on-page) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Data input setup time (to CLKOUT

)

<26>

SKID

Data input hold time (from CLKOUT

)

<27>

HKID

Data output delay time from OE

<37>

DRDOD

(0.5 + i) T 10

Column address setup time

<58>

ASC

(0.5 + w

) T 10

Column address hold time

<59>

CAH

(1.5 + w

) T 10

RAS hold time

<63>

RSH

(1.5 + w

) T 10

Column address read time for RAS

<64>

RAL

(2 + w

+ w

) T 10

CAS pulse width

<65>

CAS

(1 + w

) T 10

WE setup time (to CAS

)

<68>

RCS

(1 + w

) T 10

WE hold time (from RAS

)

<69>

RRH

0.5T 10

WE hold time (from CAS

)

<70>

RCH

T 10

Output enable access time

<72>

OEA

(1 + w

+ w

) T 28

Access time from column address

<74>

(1.5 + w

+ w

) T 28

CAS access time

<75>

CAC

(1 + w

) T 28

Output buffer turn-off delay time (from

)

<78>

OEZ

Output buffer turn-off delay time (from

CAS

)

<79>

OFF

Access time from CAS precharge

<80>

ACP

(2 + w

+ w

) T 28

CAS precharge time

<81>

(1 + w

) T 10

High-speed page mode cycle time

<82>

(2 + w

+ w

) T 10

RAS hold time for CAS precharge

<83>

RHCP

(2.5 + w

+ w

) T 10

Remarks 1. T = t

CYK

2. w

: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

3. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

4. i: the number of idle states that are inserted when a write cycle follows a read cycle.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

Row address setup time

<56>

ASR

(0.5 + w

) T 10

Row address hold time

<57>

RAH

(0.5 + w

) T 10

Column address setup time

<58>

ASC

0.5T 10

Column address hold time

<59>

CAH

(1.5 + w

+ w) T 10

Read/write cycle time

<60>

(3 + w

+ w

+ w)

T 10

RAS precharge time

<61>

(0.5 + w

) T 10

RAS pulse time

<62>

RAS

(2.5 + w

+ w

+ w)

T 10

RAS hold time

<63>

RSH

(1.5 + w

+ w) T 10

Column address read time (from RAS

)

<64>

RAL

(2 + w

+ w) T 10

CAS pulse width

<65>

CAS

(1 + w

+ w) T 10

CAS-RAS precharge time

<66>

CRP

(1 + w

) T 10

CAS hold time

<67>

CSH

(2 + w

+ w

+ w)

T 10

CAS precharge time

<71>

CPN

(2 + w

+ w

) T 10

RAS column address delay time

<76>

RAD

(0.5 + w

) T 10

RAS-CAS delay time

<77>

RCD

(1 + w

) T 10

WE setup time (to CAS

)

<84>

WCS

(1 + w

+ w

)

T 10

WE hold time (from CAS

)

<85>

WCH

(1 + w

+ w) T 10

Data setup time (to CAS

)

<86>

(1.5 + w

+ w

) T 10

Data hold time (from CAS

)

<87>

(1.5 + w

+ w) T 10

Remarks 1. T = t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

4. w

: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

5. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(d) Write timing (high-speed page DRAM access: on-page) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Column address setup time

<58>

ASC

(0.5 + w

) T 10

Column address hold time

<59>

CAH

(1.5 + w

) T 10

RAS hold time

<63>

RSH

(1.5 + w

) T 10

Column address read time (from RAS

)

<64>

RAL

(2 + w

+ w

) T 10

CAS pulse width

<65>

CAS

(1 + w

) T 10

CAS precharge time

<81>

(1 + w

) T 10

RAS hold time for CAS precharge

<83>

RHCP

(2.5 + w

+ w

)

T 10

WE setup time (to CAS

)

<84>

WCS

T 10

WE hold time (from CAS

)

<85>

WCH

(1 + w

) T 10

Data setup time (to CAS

)

<86>

(0.5 + w

) T 10

Data hold time (from CAS

)

<87>

(1.5 + w

) T 10

WE read time (from RAS

)

<88>

RWL

= 0

(1.5 + w

) T 10

WE read time (from CAS

)

<89>

CWL

= 0

(1 + w

) T 10

Data setup time (to WE

)

<90>

DSWE

= 0

0.5T 10

Data hold time (from WE

)

<91>

DHWE

= 0

(1.5 + w

) T 10

WE pulse width

<92>

= 0

(1 + w

) T 10

Remarks 1. T = t

CYK

2. w

: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

3. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(e) Read timing (EDO DRAM) (1/3)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Data input setup time (to CLKOUT

)

<26>

SKID

Data input hold time (from CLKOUT

)

<27>

HKID

Data output delay time from OE

<37>

DRDOD

(0.5 + i) T 10

Row address setup time

<56>

ASR

(0.5 + w

) T 10

Row address hold time

<57>

RAH

(0.5 + w

) T 10

Column address setup time

<58>

ASC

0.5T 10

Column address hold time

<59>

CAH

(0.5 + w

) T 10

RAS precharge time

<61>

(0.5 + w

) T 10

Column address read time (from RAS

)

<64>

RAL

(2 + w

+ w

) T 10

CAS-RAS precharge time

<66>

CRP

(1 + w

) T 10

CAS hold time

<67>

CSH

(1.5 + w

+ w

) T 10

WE setup time (to CAS

)

<68>

RCS

(2 + w

+ w

) T 10

WE hold time (from RAS

)

<69>

RRH

0.5T 10

WE hold time (from CAS

)

<70>

RCH

1.5T 10

RAS access time

<73>

RAC

(2 + w

+ w

) T 28

Access time from column address

<74>

(1.5 + w

) T 28

CAS access time

<75>

CAC

(1 + w

) T 28

Column address delay time from RAS

<76>

RAD

(0.5 + w

) T 10

RAS-CAS delay time

<77>

RCD

(1 + w

) T 10

Output buffer turn-off delay time (from

OE)

<78>

OEZ

Access time from CAS precharge

<80>

ACP

(1.5 + w

+ w

) T 28

CAS precharge time

<81>

(0.5 + w

) T 10

RAS hold time for CAS precharge

<83>

RHCP

(2 + w

+ w

) T 10

Read cycle time

<93>

HPC

(1 + w

+ w

) T 10

RAS pulse width

<94>

RASP

(2.5 + w

+ w

) T 10

CAS pulse width

<95>

HCAS

(0.5 + w

) T 10

Off-page

<96>

OCH1

(2 + w

+ w

) T 10

CAS hold time from OE

On-page

<97>

OCH2

(0.5 + w

) T 10

Data input hold time (from CAS

)

<98>

DHC

Remarks 1. T = t

CYK

2. w

: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

3. w

: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

4. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

5. w

: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

6. i: the number of idle states that are inserted when a write cycle follows a read cycle.

Preliminary Data Sheet U13995EJ1V0DS00

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(e) Read timing (EDO DRAM) (3/3)

TRPW

TRHW

TDAW TCPW

TDAW

<56>

<57>

<59>

<58>

<76>

<64>

<94>

<61>

<67>

<83>

<77>

<95>

<81>

<75>

<66>

<93>

<95>

<80>

<97>

<74>

<27>

<78>

Data

<74>

Data

<70>

<69>

<68>

<96>

<100>

<26>

<37>

<27>

<98>

<26>

<75>

<73>

<99>

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

UCAS (Output)

LCAS (Output)

WE (Output)

OE (Output)

D0 to D15 (I/O)

BCYST (Output)

WAIT (Input)

Row address

Column address

Note For on-page access from another cycle during the RASn low level signal.

Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).

Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1

Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1

Number of waits due to the DACxx bit of the DRCn register (TDAW): 1

Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1

2. The broken lines indicate high impedance.

3. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

100

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(f) Write timing (EDO DRAM) (1/2)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Row address setup time

<56>

ASR

(0.5 + w

) T 10

Row address hold time

<57>

RAH

(0.5 + w

) T 10

Column address setup time

<58>

ASC

0.5T 10

Column address hold time

<59>

CAH

(0.5 + w

) T 10

RAS precharge time

<61>

(0.5 + w

) T 10

RAS hold time

<63>

RSH

(1.5 + w

) T 10

Column address read time

(from RAS

)

<64>

RAL

(2 + w

+ w

) T 10

CAS-RAS precharge time

<66>

CRP

(1 + w

) T 10

CAS hold time

<67>

CSH

(1.5 + w

+ w

) T 10

Column address delay time from RAS

<76>

RAD

(0.5 + w

) T 10

RAS-CAS delay time

<77>

RCD

(1 + w

) T 10

CAS precharge time

<81>

(0.5 + w

) T 10

RAS hold time for CAS precharge

<83>

RHCP

(2 + w

+ w

) T 10

WE hold time (from CAS

)

<85>

WCH

(1 + w

) T 10

Data hold time (from CAS

)

<87>

(0.5 + w

) T 10

WE read time

(from RAS

)

On-page

<88>

RWL

= 0

(1.5 + w

) T 10

WE read time

(from CAS

)

On-page

<89>

CWL

= 0

(0.5 + w

) T 10

WE pulse width

On-page

<92>

= 0

(1 + w

) T 10

Write cycle time

<93>

HPC

(1 + w

+ w

) T 10

RAS pulse width

<94>

RASP

(2.5 + w

+ w

) T 10

CAS pulse width

<95>

HCAS

(0.5 + w

) T 10

Off-page

<101>

WCS1

(1 + w

+ w

) T 10

WE setup time

(to CAS

)

On-page

<102>

WCS2

T 10

Off-page

<103>

DS1

(1.5 + w

+ w

) T 10

Data setup time

(to CAS

)

On-page

<104>

DS2

(0.5 + w

) T 10

Remarks 1. T = t

CYK

2. w

: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

3. w

: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

4. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

5. w

: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

Preliminary Data Sheet U13995EJ1V0DS00

101

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(f) Write timing (EDO DRAM) (2/2)

TRPW

TRHW

TDAW

TCPW

TDAW

<56>

<57>

<59>

<58>

<59>

<76>

<64>

<94>

<61>

<67>

<83>

<77>

<95>

<81>

<63>

<66>

<93>

<95>

<89>

<88>

<102>

<101>

<92>

<85>

<103>

<87>

<104>

<87>

Data

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

UCAS (Output)

LCAS (Output)

RD (Output)

OE (Output)

WE (Output)

D0 to D15 (I/O)

BCYST (Output)

WAIT (Input)

Row address

Column address

Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).

Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1

Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1

Number of waits due to the DACxx bit of the DRCn register (TDAW): 1

Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1

2. The broken lines indicate high impedance.

3. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

102

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(g) DMA flyby transfer timing (DRAM (EDO, high-speed page)

external I/O transfer) (1/3)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

Data output delay time from OE

<37>

DRDOD

(0.5 + i) T 10

IOWR

delay time from address

<41>

DAWR

(0.5 + w

) T 10

Address setup time

(to UWR, LWR IOWR

)

<42>

SAWR

(2 + w

+ w

)

T 10

Address delay time from IOWR

<43>

DWRA

0.5T 10

= 0

delay time from IOWR

<48>

DWRRD

= 1

T 10

IOWR low-level width

<50>

WWRL

(2 + w

+ w

+ w)

T 10

Row address setup time

<56>

ASR

(0.5 + w

) T 10

Row address hold time

<57>

RAH

(0.5 + w

) T 10

Column address setup time

<58>

ASC

0.5T 10

Column address hold time

<59>

CAH

(1.5 + w

+ w

+ w)

T 10

Read/write cycle time

<60>

(3 + w

+ w

+w) T 10

RAS precharge time

<61>

(0.5 + w

) T 10

RAS hold time

<63>

RSH

(1.5 + w

+ w

+ w)

T 10

Column address read time for RAS

<64>

RAL

(2 + w

+ w

+ w)

T 10

CAS pulse width

<65>

CAS

(1 + w

+ w

+ w)

T 10

CAS-RAS precharge time

<66>

CRP

(1 + w

) T 10

CAS hold time

<67>

CSH

(2 + w

+ w

+w)

T 10

WE setup time (to CAS

)

<68>

RCS

(2 + w

+ w

) T 10

WE hold time (from RAS

)

<69>

RRH

0.5T 10

WE hold time (from CAS

)

<70>

RCH

1.5T 10

CAS precharge time

<71>

CPN

(2 + w

+ w

) T 10

RAS column address delay time

<76>

RAD

(0.5 + w

) T 10

RAS-CAS delay time

<77>

RCD

(1 + w

) T 10

Preliminary Data Sheet U13995EJ1V0DS00

104

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) R external I/O transfer) (2/3)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

Output buffer turn-off delay time (from

)

<78>

OEZ

Output buffer turn-off delay time (from

CAS

)

<79>

OFF

CAS precharge time

<81>

(0.5 + w

) T 10

High-speed page mode cycle time

<82>

(2 + w

+ w

+ w)

T 10

RAS hold time for CAS precharge

<83>

RHCP

(2.5 + w

+ w

+ w)

T 10

RAS pulse width

<94>

RASP

(2.5 + w

+ w

+ w)

T 10

Off-page

<96>

OCH1

(2.5 + w

+ w

+ w) T 10

CAS hold time

(from CAS

)

On-page

<97>

OCH2

(1.5 + w

+ w

+ w)

T 10

CAS

delay time from DMAAKm

<105>

DDACS

(1.5 + w

) T 10

CAS

delay time from IOWR

<106>

DRDCS

(1 + w

) T 10

Remarks 1. T=t

CYK

2. w: the number of waits due to WAIT.

3. w

: the number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

4. w

: the number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

5. w

: the number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

6. w

: the number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to

13).

7. w

: the number of waits that are inserted for a source-side access during a DMA flyby transfer.

8. m = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

105

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(g) DMA flyby transfer timing (DRAM (EDO, high-speed page)

external I/O transfer) (3/3)

TRPW

TRHW

TDAW

TCPW

TO1

TO2

TDAW

<56>

<57>

<58>

<59>

<76>

<61>

<60>

<94>

<64>

<77>

<65>

<83>

<63>

<81>

<67>

<66>

<71>

<82>

<96>

<105>

<68>

<69>

<70>

<79>

<48>

<97>

<106>

<42>

<41>

<50>

<43>

<78>

<37>

<24>

<25>

<24>

<25>

<24>

Data

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

UCAS (Output)

LCAS (Output)

RD (Output)
OE (Output)

DMAAKm (Output)

WE (Output)

IORD (Output)

IOWR (Output)

D0 to D15 (I/O)

WAIT (Input)

BCYST (Output)

Row address

Column address

Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).

Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1

Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1

Number of waits due to the DACxx bit of the DRCn register (TDAW): 1

Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1

Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0

2. The broken lines indicate high impedance.

3. n = 0 to 7, m = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

106

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(h) DMA flyby transfer timing (external I/O

DRAM (EDO, high-speed page) transfer) (1/3)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

WAIT setup time (to CLKOUT

)

<24>

SWK

WAIT hold time (from CLKOUT

)

<25>

HKW

IORD low-level width

<32>

WRDL

(2 + w

+ w

+ w) T 10

IORD high-level width

<33>

WRDH

T 10

IORD

delay time from address, CSn

<34>

DARD

0.5T 10

Address delay time from IORD

<35>

DRDA

(0.5 + i) T 10

Row address setup time

<56>

ASR

(0.5 + w

) T 10

Row address hold time

<57>

RAH

(0.5 + w

) T 10

Column address setup time

<58>

ASC

0.5T 10

Column address hold time

<59>

CAH

(1.5 + w

+ w

) T 10

Read/write cycle time

<60>

(3 + w

+ w

+ w)

T 10

RAS precharge time

<61>

(0.5 + w

) T 10

RAS hold time

<63>

RSH

(1.5 + w

+ w

) T 10

Column address read time for RAS

<64>

RAL

(2 + w

+ w

+ w) T 10

CAS pulse width

<65>

CAS

(1 + w

+ w

) T 10

CAS-RAS precharge time

<66>

CRP

(1 + w

) T 10

CAS hold time

<67>

CSH

(2 + w

+ w

+ w) T 10

CAS precharge time

<71>

CPN

(2 + w

+ w

+ w) T 10

RAS column address delay time

<76>

RAD

(0.5 + w

) T 10

RAS-CAS delay time

<77>

RCD

(1 + w

+ w) T 10

CAS precharge time

<81>

(0.5 + w

+ w) T 10

High-speed page mode cycle time

<82>

(2 + w

+ w

+ w) T 10

RAS hold time for CAS precharge

<83>

RHCP

(2.5 + w

+ w

+ w) T 10

WE hold time (from CAS

)

<85>

WCH

(1 + w

) T 10

WE read time (from RAS

)

<88>

RWL

= 0

(1.5 + w

+ w) T 10

WE read time (from CAS

)

<89>

CWL

= 0

(1 + w

+ w) T 10

WE pulse width

<92>

= 0

(1 + w

+ w) T 10

RAS pulse width

<94>

RASP

(2.5 + w

+ w

+ w) T 10

Off-page

<101>

WCS1

= 0

(1 + w

+ w

+ w) T 10

WE setup time

(to CAS

)

On-page

<102>

WCS2

T 10

Preliminary Data Sheet U13995EJ1V0DS00

109

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(h) DMA flyby transfer timing (external I/O

DRAM (EDO, high-speed page) transfer) (3/3)

TRPW

TRHW

TDAW

TCPW

TO2

TDAW

TO1

<56>

<57>

<58>

<76>

<61>

<60>

<94>

<64>

<77>

<65>

<63>

<81>

<67>

<66>

<71>

<82>

<101>

<105>

<83>

<85>

<89>

<106>

<34>

<107>

<33>

<24>

<25>

<24>

<25>

<24>

Data

<59>

<88>

<102>

<92>

<35>

<32>

<25>

CLKOUT (Output)

A0 to A23 (Output)

RASn (Output)

UCAS (Output)

LCAS (Output)

RD (Output)
OE (Output)

DMAAKm (Output)

WE (Output)

IOWR (Output)

IORD (Output)

D0 to D15 (I/O)

WAIT (Input)

BCYST (Output)

Row address

Column address

Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).

Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1

Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1

Number of waits due to the DACxx bit of the DRCn register (TDAW): 1

Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1

Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0

2. The broken lines indicate high impedance.

3. n = 0 to 7, m = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

110

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(i) CBR refresh timing

Parameter

Symbol

Condition

MIN.

MAX.

Unit

RAS precharge time

<61>

(1.5 + w

RRW

) T 10

RAS pulse width

<62>

RAS

(1.5 + w

RCW

Note

) T 10

CAS hold time

<108>

CHR

(1.5 + w

RCW

Note

) T 10

REFRQ pulse width

<109>

WRFL

(3 + w

RRW

+ w

RCW

Note

) T 10

RAS precharge CAS hold time

<110>

RPC

(0.5 + w

RRW

) T 10

REFRQ active delay time

(from CLKOUT

)

<111>

DKRF

REFRQ inactive delay time

(from CLKOUT

)

<112>

HKRF

CAS setup time

<113>

CSR

T 10

Note At least one clock cycle is inserted by default for w

RCW

regardless of the settings of the RCW0 to RCW2 bits

of the RWC register.

Remarks 1. T = t

CYK

2. w

RRW

: the number of waits due to the RRW0 and RRW1 bits of the RWC register.

3. w

RCW

: the number of waits due to the RCW0 to RCW2 bits of the RWC register.

REFRQ (Output)

TRCW

Note

TRRW

<109>

<111>

<112>

RASn (Output)

<62>

UCAS (Output)

<108>

<110>

<61>

<113>

<110>

LCAS (Output)

CLKOUT (Output)

Note This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.

Remarks 1. This is the timing for the following case.

Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1

Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2

2. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

111

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(j) CBR self-refresh timing

Parameter

Symbol

Condition

MIN.

MAX.

Unit

REFRQ active delay time

(from CLKOUT

)

<111>

DKRF

REFRQ inactive delay time

(from CLKOUT

)

<112>

HKRF

CAS hold time

<114>

CHS

RAS precharge time

<115>

RPS

(1 + 2w

SRW

) T 10

Remarks 1. T = t

CYK

2. w

SRW

: the number of waits due to the SRW0 to SRW2 bits of the RWC register.

<111>

TRRW

TSRW

TRCW

TSRW

Output signals

other than above

<115>

<112>

<114>

CLKOUT (Output)

REFRQ (Output)

RASn (Output)

UCAS (Output)

LCAS (Output)

Remarks 1. This is the timing for the following case.

Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1

Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1

Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2

2. The broken lines indicate high impedance.

3. n = 0 to 7

Preliminary Data Sheet U13995EJ1V0DS00

116

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(9) Interrupt timing

Parameter

Symbol

Condition

MIN.

MAX.

Unit

NMI high-level width

<132>

WNIH

500

NMI low-level width

<133>

WNIL

500

INTPn high-level width

<134>

WITH

4T + 10

INTPn low-level width

<135>

WITL

4T + 10

Remarks 1. n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153

2. T = t

CYK

NMI (Input)

<132>

<133>

INTPn (Input)

<134>

<135>

Remark n = 100 to 103, 110 to 113, 120 to 123, 130 to 133, 140 to 143, or 150 to 153

(10) RPU timing

Parameter

Symbol

Condition

MIN.

MAX.

Unit

TI1n high-level width

<136>

WTIH

3T + 18

TI1n low-level width

<137>

WTIL

3T + 18

TCLR1n high-level width

<138>

WTCH

3T + 18

TCLR1n low-level width

<139>

WTCL

3T + 18

Remarks 1. n = 0 to 5

2. T = t

CYK

TI1n (Input)

<136>

<137>

TCLR1n (Input)

<138>

<139>

Remark n = 0 to 5

Preliminary Data Sheet U13995EJ1V0DS00

118

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

(12) CSI0 to CSI3 timing

(a) Master mode

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCKn cycle

<147>

CYSK1

Output

100

SCKn high-level width

<148>

WSK1H

Output

0.5t

CYSK1

SCKn low-level width

<149>

WSK1L

Output

0.5t

CYSK1

SIn setup time (to SCKn

)

<150>

SSISK

SIn hold time (from SCKn

)

<151>

HSKSI

SOn output delay time (from SCKn

)

<152>

DSKSO

SOn output hold time (from SCKn

)

<153>

HSKSO

0.5t

CYSK1

Remark n = 0 to 3

(b) Slave mode

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCKn cycle

<147>

CYSK1

Input

100

SCKn high-level width

<148>

WSK1H

Input

SCKn low-level width

<149>

WSK1L

Input

SIn setup time (to SCKn

)

<150>

SSISK

SIn hold time (from SCKn

)

<151>

HSKSI

SOn output delay time (from SCKn

)

<152>

DSKSO

SOn output hold time (from SCKn

)

<153>

HSKSO

WSK1H

Remark n = 0 to 3

SCKn (I/O)

<149>

<147>

<148>

Sln (Input)

<150>

<151>

Input data

SOn (Output)

<152>

Output data

<153>

Remarks 1. The broken lines indicate high impedance.

2. n = 0 to 3

Preliminary Data Sheet U13995EJ1V0DS00

119

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

A/D Converter Characteristics (T

= 40 to +70

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-40, T

= 40 to +85

°
°
°
°

C ...

µ
µ
µ
µ

PD703100-33,

µ
µ
µ
µ

PD703101-33,

µ
µ
µ
µ

PD703102-33, V

= CV

= 3.0 to 3.6 V, HV

= 5.0 V

±
±
±
±

10%,

= 0 V, HV

 0.5 V < AV

< HV

, output pin load capacitance: C

= 50

pF)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Resolution

bit

Total error

LSB

Quantization error

1/2

LSB

Conversion time

CONV

Sampling time

SAMP

833

Zero scale error

LSB

Full scale error

LSB

Nonlinearity error

LSB

Analog input voltage

IAN

0.3

REF

+ 0.3

Analog input resistance

REF

input voltage

REF

= AV

4.5

5.5

REF

input current

REF

1.6

current

Preliminary Data Sheet U13995EJ1V0DS00

120

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

17. PACKAGE DRAWING

144 PIN PLASTIC LQFP (FINE PITCH) (20 20)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.

22.0

0.2

0.866

0.008

20.0

0.2

0.787+0.009

0.008

20.0

0.2

0.787+0.009

0.008

1.25

22.0

0.2

0.866

0.008

0.049

S144GJ-50-8EU-2

1.7 MAX.

0.067 MAX.

1.0

0.2

0.039+0.009

0.008

0.5

0.2

0.020+0.008

0.009

1.25

0.049

0.22

0.009

0.002

0.10

0.004

0.5 (T.P.)

0.020 (T.P.)

0.145

0.006

0.002

0.10

0.004

1.4

0.1

0.055

0.004

0.125

0.075

0.005

0.003

+0.05

0.04

+0.055

0.045

108

109

144

detail of lead end

Preliminary Data Sheet U13995EJ1V0DS00

121

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

18. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 18-1. Surface Mounting Type Soldering Conditions

µ
µ
µ
µ

PD703100GJ-40-8EU

: 144-pin plastic LQFP (fine pitch) (20

×
×
×
×

20 mm)

µ
µ
µ
µ

PD703100GJ-33-8EU

: 144-pin plastic LQFP (fine pitch) (20

×
×
×
×

20 mm)

µ
µ
µ
µ

PD703101GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20

×
×
×
×

20 mm)

µ
µ
µ
µ

PD703102GJ-33-xxx-8EU : 144-pin plastic LQFP (fine pitch) (20

×
×
×
×

20 mm)

Soldering Method

Soldering Conditions

Recommended

Condition

Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 sec. Max. (at 210

C or higher), Count:

two times or less, Exposure limit: 3 days

Note

(after that, prebake at 125

C for 10 hours)

IR35-103-2

Partial heating

Pin temperature: 300

C Max., Time: 3 sec. Max. (per pin row)

Note After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Preliminary Data Sheet U13995EJ1V0DS00

123

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Related Documents

PD70F3102-33 Data Sheet (U13844E)

PD703100-A33,

PD703100-A40,

PD703101-A33,

PD703102-A33 Data Sheet (To be

prepared)

PD70F3102-A33 Data Sheet (U13845E)

V850 Family Application Note Flash Memory Self-Programming Library (U13261E)

Reference Materials: Electrical Characteristics for Microcomputer (IEI-601

Note

)

Note This document number is that of Japanese version.

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

V850E/MS1 Family and V850 are trademarks of NEC Corporation.

Preliminary Data Sheet U13995EJ1V0DS00

125

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33, 703102-33

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

J99.1

µ
µ
µ
µ

PD703100-33, 703100-40, 703101-33,

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

Lisence not needed

PD703100-33, 703100-40

The customer must judge the need for lisence :

PD703101-33, 703102-33

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5

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