Document Outline
- COVER
- PREFACE
- CHAPTER 1 INTRODUCTION
- 1.1 Outline
- 1.2 Features
- 1.3 Applications
- 1.4 Ordering Information
- 1.5 Pin Configuration (Top View)
- 1.6 Configuration of Function Block
- 1.6.1 Internal block diagram
- 1.6.2 Internal units
- CHAPTER 2 PIN FUNCTIONS
- 2.1 List of Pin Functions
- 2.2 Pin Status
- 2.3 Description of Pin Functions
- 2.4 Types of Pin I/O Circuits and Connection of Unused Pins
- 2.5 Pin I/O Circuits
- CHAPTER 3 CPU FUNCTION
- 3.1 Features
- 3.2 CPU Register Set
- 3.2.1 Program register set
- 3.2.2 System register set
- 3.3 Operation Modes
- 3.3.1 Operation modes
- 3.3.2 Operation mode specification
- 3.4 Address Space
- 3.4.1 CPU address space
- 3.4.2 Image
- 3.4.3 Wrap-around of CPU address space
- 3.4.4 Memory map
- 3.4.5 Area
- 3.4.6 External memory expansion
- 3.4.7 Recommended use of address space
- 3.4.8 On-chip peripheral I/O registers
- 3.4.9 Specific registers
- 3.4.10 System wait control register (VSWC)
- 3.4.11 Cautions
- CHAPTER 4 BUS CONTROL FUNCTION
- 4.1 Features
- 4.2 Bus Control Pins
- 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access
- 4.3 Memory Block Function
- 4.3.1 Chip select control function
- 4.4 Bus Cycle Type Control Function
- 4.5 Bus Access
- 4.5.1 Number of access clocks
- 4.5.2 Bus sizing function
- 4.5.3 Bus width
- 4.6 Wait Function
- 4.6.1 Programmable wait function
- 4.6.2 External wait function
- 4.6.3 Relationship between programmable wait and external wait
- 4.7 Idle State Insertion Function
- 4.8 Bus Priority Order
- 4.9 Boundary Operation Conditions
- 4.9.1 Program space
- 4.9.2 Data space
- CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
- 5.1 SRAM, External ROM, External I/O Interface
- 5.1.1 Features
- 5.1.2 SRAM, external ROM, external I/O access
- CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
- 6.1 Features
- 6.2 Configuration
- 6.3 Control Registers
- 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
- 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)
- 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3)
- 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
- 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
- 6.3.6 DMA disable status register (DDIS)
- 6.3.7 DMA restart register (DRST)
- 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
- 6.4 Transfer Modes
- 6.4.1 Single transfer mode
- 6.4.2 Single-step transfer mode
- 6.4.3 Block transfer mode
- 6.5 Transfer Types
- 6.6 Transfer Target
- 6.6.1 Transfer type and transfer target
- 6.6.2 External bus cycles during DMA transfer (two-cycle transfer)
- 6.7 DMA Channel Priorities
- 6.8 Next Address Setting Function
- 6.9 DMA Transfer Start Factors
- 6.10 Forcible Suspension
- 6.11 DMA Transfer End
- 6.12 Forcible Termination
- 6.12.1 Restrictions on forcible termination of DMA transfer
- 6.13 Time Required for DMA Transfer
- 6.14 Cautions
- CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
- 7.1 Features
- 7.2 Non-Maskable Interrupt
- 7.2.1 Operation
- 7.2.2 Restore
- 7.2.3 Non-maskable interrupt status flag (NP)
- 7.2.4 Edge detection function
- 7.3 Maskable Interrupts
- 7.3.1 Operation
- 7.3.2 Restore
- 7.3.3 Priorities of maskable interrupts
- 7.3.4 Interrupt control register (xxICn)
- 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)
- 7.3.6 In-service priority register (ISPR)
- 7.3.7 Maskable interrupt status flag (ID)
- 7.3.8 Interrupt trigger mode selection
- 7.4 Software Exception
- 7.4.1 Operation
- 7.4.2 Restore
- 7.4.3 Exception status flag (EP)
- 7.5 Exception Trap
- 7.5.1 Illegal opcode definition
- 7.5.2 Debug trap
- 7.6 Multiple Interrupt Servicing Control
- 7.7 Interrupt Response Time
- 7.8 Periods in Which CPU Does Not Acknowledge Interrupts
- CHAPTER 8 CLOCK GENERATION FUNCTION
- 8.1 Features
- 8.2 Configuration
- 8.3 Input Clock Selection
- 8.3.1 Direct mode
- 8.3.2 PLL mode
- 8.3.3 Peripheral command register (PHCMD)
- 8.3.4 Clock control register (CKC)
- 8.3.5 Peripheral status register (PHS)
- 8.4 PLL Lockup
- 8.5 Power Save Control
- 8.5.1 Overview
- 8.5.2 Control registers
- 8.5.3 HALT mode
- 8.5.4 IDLE mode
- 8.5.5 Software STOP mode
- 8.6 Securing Oscillation Stabilization Time
- 8.6.1 Oscillation stabilization time security specification
- 8.6.2 Time base counter (TBC)
- CHAPTER 9 TIMER/COUNTER FUNCTION
- 9.1 Timer 0
- 9.1.1 Features (timer 0)
- 9.1.2 Function overview (timer 0)
- 9.1.3 Functions added to V850E/IA2
- 9.1.4 Basic configuration
- 9.1.5 Control registers
- 9.1.6 Operation
- 9.1.7 Operation timing
- 9.2 Timer 1
- 9.2.1 Features (timer 1)
- 9.2.2 Function overview (timer 1)
- 9.2.3 Basic configuration
- 9.2.4 Control registers
- 9.2.5 Operation
- 9.2.6 Supplementary description of internal operation
- 9.3 Timer 2
- 9.3.1 Features (timer 2)
- 9.3.2 Function overview (timer 2)
- 9.3.3 Basic configuration
- 9.3.4 Control registers
- 9.3.5 Operation
- 9.3.6 PWM output operation in timer 2 compare mode
- 9.4 Timer 3
- 9.4.1 Features (timer 3)
- 9.4.2 Function overview (timer 3)
- 9.4.3 Function added to V850E/IA2
- 9.4.4 Basic configuration
- 9.4.5 Control registers
- 9.4.6 Operation
- 9.4.7 Application examples
- 9.4.8 Cautions
- 9.5 Timer 4
- 9.5.1 Features (timer 4)
- 9.5.2 Function overview (timer 4)
- 9.5.3 Basic configuration
- 9.5.4 Control register
- 9.5.5 Operation
- 9.5.6 Application example
- 9.5.7 Cautions
- 9.6 Timer Connection Function
- 9.6.1 Overview
- 9.6.2 Control register
- CHAPTER 10 SERIAL INTERFACE FUNCTION
- 10.1 Features
- 10.1.1 Selecting UART1 or CSI1 mode
- 10.2 Asynchronous Serial Interface 0 (UART0)
- 10.2.1 Features
- 10.2.2 Configuration
- 10.2.3 Control registers
- 10.2.4 Interrupt requests
- 10.2.5 Operation
- 10.2.6 Dedicated baud rate generator 0 (BRG0)
- 10.2.7 Cautions
- 10.3 Asynchronous Serial Interface 1 (UART1)
- 10.3.1 Features
- 10.3.2 Configuration
- 10.3.3 Control registers
- 10.3.4 Interrupt requests
- 10.3.5 Operation
- 10.3.6 Synchronous mode
- 10.3.7 Dedicated baud rate generator 1 (BRG1)
- 10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1)
- 10.4.1 Features
- 10.4.2 Configuration
- 10.4.3 Control registers
- 10.4.4 Operation
- 10.4.5 Output pins
- 10.4.6 Dedicated baud rate generator 3 (BRG3)
- CHAPTER 11 A/D CONVERTER
- 11.1 Features
- 11.2 Configuration
- 11.3 Functions Added to V850E/IA2
- 11.4 Control Registers
- 11.5 Interrupt Requests
- 11.6 A/D Converter Operation
- 11.6.1 A/D converter basic operation
- 11.6.2 Operation modes and trigger modes
- 11.7 Operation in A/D Trigger Mode
- 11.7.1 Operation in select mode
- 11.7.2 Operation in scan mode
- 11.8 Operation in A/D Trigger Polling Mode
- 11.8.1 Operation in select mode
- 11.8.2 Operation in scan mode
- 11.9 Operation in Timer Trigger Mode
- 11.9.1 Operation in select mode
- 11.9.2 Operation in scan mode
- 11.10 Operation in External Trigger Mode
- 11.10.1 Operation in select mode
- 11.10.2 Operation in scan mode
- 11.11 Operation Cautions
- 11.11.1 Stopping A/D conversion operation
- 11.11.2 Trigger input during A/D conversion operation
- 11.11.3 External or timer trigger interval
- 11.11.4 Operation in standby modes
- 11.11.5 Compare match interrupt in timer trigger mode
- 11.11.6 Timing that makes the A/D conversion result undefined
- 11.12 How to Read A/D Converter Characteristics Table
- CHAPTER 12 PORT FUNCTIONS
- 12.1 Features
- 12.2 Basic Configuration of Ports
- 12.3 Pin Functions of Each Port
- 12.3.1 Port 0
- 12.3.2 Port 1
- 12.3.3 Port 2
- 12.3.4 Port 3
- 12.3.5 Port 4
- 12.3.6 Port DH
- 12.3.7 Port DL
- 12.3.8 Port CT
- 12.3.9 Port CM
- 12.4 Operation of Port Function
- 12.4.1 Writing to I/O port
- 12.4.2 Reading from I/O port
- 12.4.3 Output status of alternate function in control mode
- 12.5 Noise Eliminator
- 12.5.1 Interrupt pins
- 12.5.2 Timer 10, timer 3 input pins
- 12.5.3 Timer 2 input pins
- 12.6 Cautions
- 12.6.1 Hysteresis characteristics
- CHAPTER 13 RESET FUNCTION
- 13.1 Features
- 13.2 Pin Functions
- 13.3 Initialization
- CHAPTER 14 REGULATOR
- 14.1 Features
- 14.2 Functional Outline
- 14.3 Connection Example
- 14.4 Control Register
- CHAPTER 15 FLASH MEMORY (uPD70F3114)
- 15.1 Features
- 15.2 Writing Using Flash Programmer
- 15.3 Programming Environment
- 15.4 Communication Mode
- 15.5 Pin Connection
- 15.5.1 MODE1/VPP pin
- 15.5.2 Serial interface pin
- 15.5.3 RESET# pin
- 15.5.4 NMI pin
- 15.5.5 MODE0, MODE1 pins
- 15.5.6 Port pins
- 15.5.7 Other signal pins
- 15.5.8 Power supply
- 15.6 Programming Method
- 15.6.1 Flash memory control
- 15.6.2 Flash memory programming mode
- 15.6.3 Selection of communication mode
- 15.6.4 Communication commands
- 15.7 Flash Memory Programming by Self-Programming
- 15.7.1 Outline of self-programming
- 15.7.2 Self-programming function
- 15.7.3 Outline of self-programming interface
- 15.7.4 Hardware environment
- 15.7.5 Software environment
- 15.7.6 Self-programming function number
- 15.7.7 Calling parameters
- 15.7.8 Contents of RAM parameters
- 15.7.9 Errors during self-programming
- 15.7.10 Flash information
- 15.7.11 Area number
- 15.7.12 Flash programming mode control register (FLPMC)
- 15.7.13 Calling device internal processing
- 15.7.14 Erasing flash memory flow
- 15.7.15 Continuous writing flow
- 15.7.16 Internal verify flow
- 15.7.17 Acquiring flash information flow
- 15.7.18 Self-programming library
- 15.8 How to Distinguish Flash Memory and Mask ROM Versions
- CHAPTER 16 ELECTRICAL SPECIFICATIONS
- 16.1 Normal Operation Mode
- 16.2 Flash Memory Programming Mode
- CHAPTER 17 PACKAGE DRAWINGS
- CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A NOTES ON TARGET SYSTEM DESIGN
- APPENDIX B REGISTER INDEX
- APPENDIX C INSTRUCTION SET LIST
- C.1 Conventions
- C.2 Instruction Set (Alphabetical Order)
- APPENDIX D REVISION HISTORY
- D.1 Major Revisions in This Edition
- D.2 Revision History up to Previous Edition
Printed in Japan
Document No. U15195EJ5V0UD00 (5th edition)
Date Published August 2005 N CP(K)
V850E/IA2
32-Bit Single-Chip Microcontrollers
Hardware
User's Manual
PD703114
PD703114(A)
PD70F3114
PD70F3114(A)
2001
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User's Manual U15195EJ5V0UD
[MEMO]
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User's Manual U15195EJ5V0UD
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2
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4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
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6
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User's Manual U15195EJ5V0UD
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User's Manual U15195EJ5V0UD
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