Document Outline

COVER
Major Revisions in This Edition
PREFACE
CHAPTER 1 INTRODUCTION
- 1.1 V850ES/KF1, V850ES/KG1, and V850ES/KJ1 Product Lineup
- 1.2 V850ES/KF1
  - 1.2.1 Features (V850ES/KF1)
  - 1.2.2 Applications (V850ES/KF1)
  - 1.2.3 Ordering information (V850ES/KF1)
  - 1.2.4 Pin configuration (top view) (V850ES/KF1)
  - 1.2.5 Function block configuration (V850ES/KF1)
- 1.3 V850ES/KG1
  - 1.3.1 Features (V850ES/KG1)
  - 1.3.2 Applications (V850ES/KG1)
  - 1.3.3 Ordering information (V850ES/KG1)
  - 1.3.4 Pin configuration (top view) (V850ES/KG1)
  - 1.3.5 Function block configuration (V850ES/KG1)
- 1.4 V850ES/KJ1
  - 1.4.1 Features (V850ES/KJ1)
  - 1.4.2 Applications (V850ES/KJ1)
  - 1.4.3 Ordering information (V850ES/KJ1)
  - 1.4.4 Pin configuration (top view) (V850ES/KJ1)
  - 1.4.5 Function block configuration (V850ES/KJ1)
CHAPTER 2 PIN FUNCTIONS
- 2.1 List of Pin Functions
- 2.2 Pin Status
- 2.3 Description of Pin Functions
  - 2.3.1 V850ES/KF1
  - 2.3.2 V850ES/KG1
  - 2.3.3 V850ES/KJ1
- 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins
- 2.5 Pin I/O Circuits
CHAPTER 3 CPU FUNCTIONS
- 3.1 Features
- 3.2 CPU Register Set
  - 3.2.1 Program register set
  - 3.2.2 System register set
- 3.3 Operation Modes
- 3.4 Address Space
  - 3.4.1 CPU address space
  - 3.4.2 Image
  - 3.4.3 Wrap-around of CPU address space
  - 3.4.4 Memory map
  - 3.4.5 Areas
  - 3.4.6 Peripheral I/O registers
  - 3.4.7 Special registers
  - 3.4.8 Cautions
CHAPTER 4 PORT FUNCTIONS
- 4.1 Features
  - 4.1.1 V850ES/KF1
  - 4.1.2 V850ES/KG1
  - 4.1.3 V850ES/KJ1
- 4.2 Basic Port Configuration
  - 4.2.1 V850ES/KF1
  - 4.2.2 V850ES/KG1
  - 4.2.3 V850ES/KJ1
- 4.3 Port Configuration
  - 4.3.1 Port 0
  - 4.3.2 Port 1
  - 4.3.3 Port 3
  - 4.3.4 Port 4
  - 4.3.5 Port 5
  - 4.3.6 Port 6
  - 4.3.7 Port 7
  - 4.3.8 Port 8
  - 4.3.9 Port 9
  - 4.3.10 Port CD
  - 4.3.11 Port CM
  - 4.3.12 Port CS
  - 4.3.13 Port CT
  - 4.3.14 Port DH
  - 4.3.15 Port DL
- 4.4 Port Function Operation
  - 4.4.1 Write operation to I/O port
  - 4.4.2 Read operation from I/O port
  - 4.4.3 Arithmetic operation with I/O ports
CHAPTER 5 BUS CONTROL FUNCTION
- 5.1 Features
- 5.2 Bus Control Pins
  - 5.2.1 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
  - 5.2.2 Pin status in each operation mode
- 5.3 Memory Block Function
  - 5.3.1 Chip select control function
- 5.4 External Bus Interface Mode Control Function
- 5.5 Bus Access
  - 5.5.1 Number of clocks for access
  - 5.5.2 Bus size setting function
  - 5.5.3 Access by bus size
- 5.6 Wait Function
  - 5.6.1 Programmable wait function
  - 5.6.2 External wait function
  - 5.6.3 Relationship between programmable wait and external wait
  - 5.6.4 Programmable address wait function
- 5.7 Idle State Insertion Function
- 5.8 Bus Hold Function
  - 5.8.1 Functional outline
  - 5.8.2 Bus hold procedure
  - 5.8.3 Operation in power save mode
- 5.9 Bus Priority
- 5.10 Boundary Operation Conditions
  - 5.10.1 Program space
  - 5.10.2 Data space
- 5.11 Bus Timing
- 5.12 Cautions
CHAPTER 6 CLOCK GENERATION FUNCTION
- 6.1 Overview
- 6.2 Configuration
- 6.3 Control Registers
- 6.4 Operation
  - 6.4.1 Operation of each clock
  - 6.4.2 Clock output function
  - 6.4.3 External clock input function
- 6.5 PLL Function
  - 6.5.1 Overview
  - 6.5.2 Control register
  - 6.5.3 Usage
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 TO 05
- 7.1 Functions
- 7.2 Configuration
- 7.3 Control Registers
- 7.4 Operation
  - 7.4.1 Operation as interval timer (16 bits)
  - 7.4.2 PPG output operation
  - 7.4.3 Pulse width measurement
  - 7.4.4 Operation as external event counter
  - 7.4.5 Square-wave output operation
  - 7.4.6 One-shot pulse output operation
  - 7.4.7 Cautions
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
- 8.1 Functions
- 8.2 Configuration
- 8.3 Control Registers
- 8.4 Operation
  - 8.4.1 Operation as interval timer (8 bits)
  - 8.4.2 Operation as external event counter (8 bits)
  - 8.4.3 Square-wave output operation (8-bit resolution)
  - 8.4.4 8-bit PWM output operation
  - 8.4.5 Operation as interval timer (16 bits)
  - 8.4.6 Operation as external event counter (16 bits)
  - 8.4.7 Square-wave output operation (16-bit resolution)
  - 8.4.8 Cautions
CHAPTER 9 8-BIT TIMERS H0 AND H1
- 9.1 Functions
- 9.2 Configuration
- 9.3 Control Registers
- 9.4 Operation
  - 9.4.1 Operation as interval timer
  - 9.4.2 PWM pulse generator mode operation
  - 9.4.3 Carrier generator mode operation
CHAPTER 10 REAL-TIME OUTPUT FUNCTION (RTO)
- 10.1 Function
- 10.2 Configuration
- 10.3 RTO Control Registers
- 10.4 Operation
- 10.5 Usage
- 10.6 Cautions
- 10.7 Security Function
CHAPTER 11 WATCH TIMER FUNCTIONS
- 11.1 Functions
- 11.2 Configuration
- 11.3 Watch Timer Control Registers
- 11.4 Operation
  - 11.4.1 Operation as watch timer
  - 11.4.2 Operation as interval timer
  - 11.4.3 Cautions
- 11.5 Prescaler 3
  - 11.5.1 Control registers
  - 11.5.2 Generation of count clock
CHAPTER 12 WATCHDOG TIMER FUNCTIONS
- 12.1 Watchdog Timer 1
  - 12.1.1 Functions
  - 12.1.2 Configuration
  - 12.1.3 Watchdog timer 1 control register
  - 12.1.4 Operation
- 12.2 Watchdog Timer 2
  - 12.2.1 Functions
  - 12.2.2 Configuration
  - 12.2.3 Watchdog timer 2 control register
  - 12.2.4 Operation
CHAPTER 13 A/D CONVERTER
- 13.1 Function
- 13.2 Configuration
- 13.3 Control Registers
- 13.4 Relationship Between Analog Input Voltage and A/D Conversion Result
- 13.5 Operation
  - 13.5.1 Basic operation
  - 13.5.2 Conversion operation (software trigger mode)
  - 13.5.3 Power fail monitoring function
- 13.6 Cautions
- 13.7 How to Read A/D Converter Characteristics Table
CHAPTER 14 D/A CONVERTER
- 14.1 Functions
- 14.2 Configuration
- 14.3 D/A Converter Control Register
- 14.4 Operation
  - 14.4.1 Operation in normal mode
  - 14.4.2 Operation in real-time output mode
  - 14.4.3 Cautions
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE (UART)
- 15.1 Selecting UART2 or I2C1 Mode
- 15.2 Features
- 15.3 Configuration
- 15.4 Control Registers
- 15.5 Interrupt Requests
- 15.6 Operation
  - 15.6.1 Data format
  - 15.6.2 Transmit operation
  - 15.6.3 Continuous transmission operation
  - 15.6.4 Receive operation
  - 15.6.5 Reception error
  - 15.6.6 Parity types and corresponding operation
  - 15.6.7 Receive data noise filter
- 15.7 Dedicated Baud Rate Generator n (BRGn)
  - 15.7.1 Baud rate generator n (BRGn) configuration
  - 15.7.2 Serial clock generation
  - 15.7.3 Baud rate setting example
  - 15.7.4 Allowable baud rate range during reception
  - 15.7.5 Transfer rate during continuous transmission
- 15.8 Cautions
CHAPTER 16 CLOCKED SERIAL INTERFACE 0 (CSI0)
- 16.1 Features
- 16.2 Configuration
- 16.3 Control Registers
- 16.4 Operation
  - 16.4.1 Single transfer mode
  - 16.4.2 Repeat transfer mode
- 16.5 Output Pins
CHAPTER 17 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
- 17.1 Functions
- 17.2 Configuration
- 17.3 Control Registers
- 17.4 Operation
  - 17.4.1 Operation stop mode
  - 17.4.2 3-wire serial I/O mode
  - 17.4.3 3-wire serial I/O mode with automatic transmit/receive function
CHAPTER 18 I2C BUS
- 18.1 Selecting UART2 or I2C1 Mode
- 18.2 Features
- 18.3 Configuration
- 18.4 Control Registers
- 18.5 Functions
  - 18.5.1 Pin configuration
- 18.6 I2C Bus Definitions and Control Methods
  - 18.6.1 Start condition
  - 18.6.2 Addresses
  - 18.6.3 Transfer direction specification
  - 18.6.4 Acknowledge signal (ACK#)
  - 18.6.5 Stop condition
  - 18.6.6 Wait signal (WAIT#)
- 18.7 I2C Interrupt Requests (INTIICn)
  - 18.7.1 Master device operation
  - 18.7.2 Slave device operation (when receiving slave address data (match with SVAn))
  - 18.7.3 Slave device operation (when receiving extension code)
  - 18.7.4 Operation without communication
  - 18.7.5 Arbitration loss operation (operation as slave after arbitration loss)
  - 18.7.6 Operation when arbitration loss occurs (no communication after arbitration loss)
- 18.8 Interrupt Request (INTIICn) Generation Timing and Wait Control
- 18.9 Address Match Detection Method
- 18.10 Error Detection
- 18.11 Extension Code
- 18.12 Arbitration
- 18.13 Wakeup Function
- 18.14 Communication Reservation
- 18.15 Cautions
- 18.16 Communication Operations
  - 18.16.1 Master Operations
  - 18.16.2 Slave operation
- 18.17 Timing of Data Communication
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION
- 19.1 Outline
  - 19.1.1 Features
- 19.2 Non-Maskable Interrupts
  - 19.2.1 Operation
  - 19.2.2 Restore
  - 19.2.3 NP flag
  - 19.2.4 Noise elimination for NMI pin
  - 19.2.5 Edge detection function for NMI pin
- 19.3 Maskable Interrupts
  - 19.3.1 Operation
  - 19.3.2 Restore
  - 19.3.3 Priorities of maskable interrupts
  - 19.3.4 Interrupt control register (xxlCn)
  - 19.3.5 Interrupt mask registers 0 to 2 (IMR0 to IMR2)
  - 19.3.6 In-service priority register (ISPR)
  - 19.3.7 Maskable interrupt status flag
  - 19.3.8 Watchdog timer mode register 1 (WDTM1)
  - 19.3.9 Elimination of noise from INTP0 to INTP6
  - 19.3.10 INTP0 to INTP6 edge detection function
- 19.4 Software Exceptions
  - 19.4.1 Operation
  - 19.4.2 Restore
  - 19.4.3 Exception status flag (EP)
- 19.5 Exception Trap
  - 19.5.1 Illegal op code
  - 19.5.2 Debug trap
- 19.6 Multiple Interrupt Servicing Control
- 19.7 Interrupt Response Time
- 19.8 Periods in Which Interrupts Are Not Acknowledged by CPU
CHAPTER 20 KEY INTERRUPT FUNCTION
- 20.1 Function
- 20.2 Key Interrupt Control Register
CHAPTER 21 STANDBY FUNCTION
- 21.1 Overview
- 21.2 HALT Mode
  - 21.2.1 Setting and operation status
  - 21.2.2 Releasing HALT mode
- 21.3 IDLE Mode
  - 21.3.1 Setting and operation status
  - 21.3.2 Releasing IDLE mode
- 21.4 STOP Mode
  - 21.4.1 Setting and operation status
  - 21.4.2 Releasing STOP mode
- 21.5 Securing Oscillation Stabilization Time
- 21.6 Subclock Operation Mode
  - 21.6.1 Setting and operation status
  - 21.6.2 Releasing subclock operation mode
- 21.7 Sub-IDLE Mode
  - 21.7.1 Setting and operation status
  - 21.7.2 Releasing sub-IDLE mode
- 21.8 Control Registers
CHAPTER 22 RESET FUNCTION
- 22.1 Overview
- 22.2 Configuration
- 22.3 Operation
CHAPTER 23 REGULATOR
- 23.1 Outline
- 23.2 Operation
CHAPTER 24 ROM CORRECTION FUNCTION
- 24.1 Overview
- 24.2 Control Registers
  - 24.2.1 Correction address registers 0 to 3 (CORAD0 to CORAD3)
  - 24.2.2 Correction control register (CORCN)
- 24.3 ROM Correction Operation and Program Flow
CHAPTER 25 FLASH MEMORY
- 25.1 Features
- 25.2 Writing with Flash Programmer
- 25.3 Programming Environment
- 25.4 Communication Mode
- 25.5 Pin Processing
  - 25.5.1 VPP pin
  - 25.5.2 Serial interface pins
  - 25.5.3 RESET# pin
  - 25.5.4 Port pins
  - 25.5.5 Other signal pins
  - 25.5.6 Power supply
- 25.6 Programming Method
  - 25.6.1 Controlling flash memory
  - 25.6.2 Flash memory programming mode
  - 25.6.3 Selecting communication mode
  - 25.6.4 Communication commands
  - 25.6.5 Resources used
CHAPTER 26 ELECTRICAL SPECIFICATIONS
CHAPTER 27 PACKAGE DRAWINGS
CHAPTER 28 RECOMMENDED SOLDERING CONDITIONS
APPENDIX A REGISTER INDEX
APPENDIX B REVISION HISTORY

User's Manual U15862EJ3V0UD

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Purchase of NEC Electronics I

C components conveys a license under the Philips I

C Patent Rights to

use these components in an I

C system, provided that the system conforms to the I

C Standard

Specification as defined by Philips.

V850 Series, V850ES/KF1, V850ES/KG1, and V850ES/KJ1 are trademarks of NEC Electronics
Corporation.

User's Manual U15862EJ3V0UD

These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.

The information in this document is current as of November, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
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written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
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determine NEC Electronics' willingness to support a given application.

(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics

(as defined above).

M8E 02. 11-1

User's Manual U15862EJ3V0UD

Regional Information

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics America, Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
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Hong Kong
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Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

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Tel: 021-6841-1138
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Tel: 02-2719-2377
Fax: 02-2719-5951

NEC Electronics Singapore Pte. Ltd.

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Tel: 6253-8311
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J02.11

NEC Electronics (Europe) GmbH

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Tel: 0211-65 03 01
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· Sucursal en España

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· Succursale Française

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Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:

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Document Outline

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