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1996

DATA SHEET

The

PD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA

controller, interrupt controller, etc. are all integrated. The

PD70325 is software compatible with the 16/8-bit single-

chip microcontroller

PD70320 (V25

). The V25+ greatly improves the DMA responsivity and transfer rate compared

to the V25.

FEATURES

Software compatible with V25

Software compatible with

PD70108/70116 (in native mode) (some instructions added)

Internal 16-bit architecture and external 8-bit data bus

3-stage pipeline method

Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)

: 200 ns/10 MHz (external 20 MHz)

Memory space 1 Mbyte

On-chip RAM : 256 words

8 bits

Input port (port T) with comparator : 8 bits

I/O lines (input port : 4 bits, input/output ports : 20 bits)

Serial interface : 2 channels

· Internal dedicated baud rate generator

· Asynchronous mode and I/O interface mode

Interrupt controller

· Programmable priority (8 levels)

· 3 types of interrupt response method

Vectored interrupt function, register bank switching function, macro service function

DRAM and pseudo SRAM refreshing function

DMA controller : 2 channels

· 4 types of DMA transfer mode

· Transfer rate

Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release

mode)

Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release

mode, or burst mode)

· Address pointer (linear) : 20 bits

· Terminal counter : 16 bits

16-bit timer : 2 channels

Time base counter (20 bits) : 1 channel

On-chip clock generator

Programmable wait function

Standby function (STOP, HALT)

MOS INTEGRATED CIRCUIT

V25+

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The information in this document is subject to change without notice.

The mark shows major revised points.

PD70325

1995

Document No. U12850EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan

PD70325

Comparison between V25 and V25+

V25

V35

V25+

V35+

PD70320

PD70330

PD70325

PD70335

Transfer processing method

Depends on microprogram

Depends on dedicated hardware

Maximum transfer rate (8-MHz

0.6 Mbytes/second 0.8 Mbytes/second

4 Mbytes/second

5.3 Mbytes/second

operation)

Sampling timing of DMA request

Between instruction execution cycles

Between bus cycles

DMA service channel

In on-chip RAM area

In special function register

Specification method of transfer address Segment method

Linear method

Execution format in single-step mode 1 DMA transfer/1 instruction execution

1 DMA transfer/1 bus cycle

Interrupt request during DMA transfer Accepts only NMI

Not accepted

(demand release mode)

Number of necessary waits when

Not necessary

2 waits

stop is controlled by DMARQ

(demand release mode)

Transfer processing units

Byte/word

Byte

Byte/word

TC (terminal counter) setting value

Number of times of DMA transfer

(Number of times of DMA transfer) 1

Generation timing of terminal counter TC = 0

TC = FFFFH

TC output low-level width

Fixed

Expanded by wait insertion

Transmit clock output in

Not available

Available (SCK0 pin)

asynchronous mode (channel 0)

Serial error register

Yes

Serial status register

Receive buffer full flag

In serial status register

Transmit buffer empty flag

In serial status register

All sent flag

In serial status register

Interrupt source register

Yes

External data bus

8 bits

16 bits

8 bits

16 bits

Maximum operating frequency

8 MHz

10 MHz

DMA

function

Serial

interface

Interrupt
function

PD70325

PIN CONFIGURATION (Top View)

94-Pin Plastic QFP

PD70325GJ-8-5BG

PD70325GJ-10-5BG

Remarks 1. NC : Non-Connection

2. IC : Internally Connected

Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally.

2. Fix EA pin to low level.

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75

A11

A10

P07/CLKOUT

P06

74 73 72

P23/DMARQ1

P24/DMAAK1

P25/

TC1

P26/HLDAK

P27/HLDRQ

NMI (P10)

P11/INTP0

P12/INTP1

P13/INTP2/INTAK

P14/INT/POLL

P15/

TOUT

P16/SCK0

P17/READY

PT0

PT1

PT2

PT3

PT4

PT5

PT6

PT7

A12

A13

A14

A15

A16

A17

A18

A19

RxD0

GND

CTS0

TxD0

RxD1

CTS1

TxD1

P20/DMARQ0

P21/DMAAK0

P22/TC0

P05

P04

P03

P02

P01

P00

MREQ

IOSTB

MSTB

R/W

REFRQ

RESET

GND

PD70325

84-Pin Plastic QFJ

PD70325L-8

PD70325L-10

Remark

IC: Internally Connected

Cautions 1. Fix IC pin individually to high level via a pull-up resistor externally.

Fix EA pin to low level.

P07/CLKOUT

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

RxD0

GND

CTS0

TxD0

RxD1

CTS1

TxD1

P20/DMARQ0

P21/DMAAK0

P22/

TC0

PT7

PT6

PT5

PT4

PT3

PT2

PT1

PT0

P17/READY

P16/SCK0

P15/TOUT

P14/INT/POLL

P13/INTP2/INTAK

P12/INTP1

P11/INTP0

NMI (P10)

P27/HLDRQ

P26/HLDAK

P25/TC1

P24/DMAAK1

P23/DMARQ1

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

11 10 9

1 84 83 82 81 80 79 78 77 76 75

P06

P05

P04

P03

P02

P01

P00

MREQ

IOSTB

MSTB

R/W

REFRQ

RESET

GND

PD70325

Note The internal ROM of 8 Kbytes is reserved for specific use such as testing and not user-accessible.

INTERNAL BLOCK DIAGRAM

P20/DMARQ0

P21/DMAAK0

P22/TC0

P23/DMARQ1

P24/DMAAK1

P25/TC1

TxD0

RxD0

P16/SCK0

CTS0

TxD1

RxD1

CTS1

NMI (P10)

P11/INTP0
P12/INTP1

P13/INTP2/INTAK

P14/INT/POLL

A0 to A19

RESET

HLDAK/P26

HLDRQ/P27

READY/P17

MREQ

MSTB

R/W

IOSTB

POLL/INT/P14

D0 to D7

GND

BUS CONTROL LOGIC

STAGING LATCH

PROGRAMMABLE
DMA
CONTROLLER

SERIAL
INTERFACE

BAUD RATE
GENERATOR

PROGRAMMABLE
INTERRUPT
CONTROLLER

INSTRUCTION DECODER
MICRO SEQUENSER
MICRO ROM

ALU

LC
etc.

PSW

TA
TB
TC

INTERNAL RAM
256 byte
· GR
· MACRO SERVICE
CHANNEL

QUEUE

(6 byte)

16-BIT TIMER

TIME BASE

COUNTER

PORT

PORT with

COMPARATOR

TOUT/P15

CLKOUT/P07

PT0 to 7

REFRQ

ADM

INTERNAL ROM

Note

8 Kbyte

(reserved)

PFP

INC

PD70325

CONTENTS

PIN FUNCTIONS .................................................................................................................................. 8

1.1

Port Pins ....................................................................................................................................................... 8

1.2

Non-port Pins ............................................................................................................................................... 9

INSTRUCTION SETS ......................................................................................................................... 10

2.1

Comparison between

PD70108 and 70116 ........................................................................................... 10

2.2

Instruction Set Operation ......................................................................................................................... 12

2.3

Instruction Set Table ................................................................................................................................. 16

2.4

Number of Clocks Table ........................................................................................................................... 38

ELECTRICAL SPECIFICATIONS ...................................................................................................... 49

PACKAGE DRAWINGS ..................................................................................................................... 74

RECOMMENDED SOLDERING CONDITIONS ................................................................................ 76

PD70325

1. PIN FUNCTIONS

1.1 Port Pins

Pin Name

Input/Output

Port Function

Control Function

P00 to P06

Input & output

8-bit input/output ports, each to

P07/CLKOUT

Input & output/output

be specified bit-by-bit

System clock output

NMI (P10)

Input

Used as non-maskable interrupt

request input (input port)

P11/INTP0

Used as both external interrupt

P12/INTP1

request input and input port

P13/INTP2/INTAK

Input/input/output

INT acknowledge signal output

P14/POLL/INT

Input & output/input/input

Used as both specifiable input/

External interrupt request input

output port and POLL input

P15/ TOUT

Input & output/output

Input/output port specifiable

Timer output

P16/SCK0

bit-by-bit

Serial clock output

P17/READY

Input & output/input

READY input

P20/DMARQ0

Input & output/input

8-bit input/output port specifiable DMA request input (CH0)

P21/DMAAK0

Input & output/input

bit-by-bit

DMA acknowledge output (CH0)

P22/TC0

DMA end output (CH0)

P23/DMARQ1

Input & output/input

DMA request input (CH1)

P24/DMAAK1

Input & output/output

DMA acknowledge output (CH1)

P25/TC1

DMA end output (CH1)

P26/HLDAK

Input & output/output

HOLD acknowledge output

P27/HLDRQ

Input & output/input

HOLD input

PT0 to PT7

Input

8-bit input port with comparator

Remark

All port pins become input ports after reset is released.

When using P13/INTP2/INTAK as a INTAK pin, be sure to pull up the pin to avoid a malfunction of external

interrupt controller after reset is released.

PD70325

1.2 Non-port Pins

Pin Name

Input/Output

Function

TxD0

Output

Serial data output

TxD1

RxD0

Input

Serial data input

RxD1

CTS0

Input & output

CTS input in asynchronous mode, receive clock input/output in I/O interface mode

CTS1

Input

CTS input

REFRQ

Output

DRAM refresh pulse output

Input

Comparator reference voltage input

RESET

Reset signal input

Fix to low level

Used to connect crystal resonator for oscillating system clock.

External clock is entered by entering reverse phase clock to both X1 and X2 pins.

D0 to D7

Input & output

8-bit data bus

A0 to A19

Output

20-bit address output

MREQ

Output used to indicate that memory bus cycle has been started

MSTB

Memory read/memory write strobe output

R/ W

Read cycle/write cycle ID signal output

IOSTB

I/O read / I/O write strobe output

Positive power supply pins (all pins should be connected)

GND

GND pins (all pins should be connected)

Internally connected (fix to high level via a pull-up resistor externally)

PD70325

2. INSTRUCTION SETS

The

PD70325 instruction sets are compatible with those of

PD70320.

2.1 Comparison between

PD70108 and 70116

The

PD70325 instruction sets are upward-compatible with those of

PD70108/70116 in native mode.

The following instructions are newly added to the

PD70108/ 70116.

(1) Conditional branch instruction

BTCLR ······· Bit test instruction used for special function registers

If, when this BTCLR is executed, the target special function register bit status is "1", the bit is

reset (0) and the program is branched to short-label described in the operand. If the target bit

status is "0", the program is moved to the next instruction. PSW is not changed in this instruction.

(Descriptive format)

Operand

Mnemonic

Special Function

Branch Address

BTCLR

sfr

imm3

short-label

(2) Interrupt instructions

RETRBI ······ Return instruction used for register banks

This instruction is used to return the program from the interrupt service routine in which the

servicing.

(Descriptive format)

Mnemonic

Operand

RETRBI

None

FINT ··········· This instruction is used to report the interrupt controller that interrupt servicing has ended.

If an interrupt other than NMI, INT, and software interrupt is used, this instruction must be

executed prior to the instruction for returning from interrupt servicing. It should not be used for

NMI, INT and software interrupts.

(Descriptive format)

(3) CPU instruction

STOP ········· Instruction for transition to STOP state

(Descriptive format)

Mnemonic

Operand

FINT

None

Mnemonic

Operand

STOP

None

PD70325

(4) Register bank switch instructions

BRKCS ······ Used to switch register banks

A register bank is switched to the register bank indicated by the lower 3 bits in the 16-bit register

described in the operand. The program is also branched with this instruction to the address

obtained from the PS stored in advance in the new register bank and the vector PC.

The RETRBI instruction is used to return the program from the new register bank.

(Descriptive format)

TSKSW ······ Used to switch register banks

Just like the BRKCS instruction, this instruction is also executed to select a register bank. The

program is branched to the address obtained from the PS stored in advance in the new register

bank and the address obtained from the PC save area.

(Descriptive format)

(5) Data transfer instructions

MOVSPA ··· Used to transfer SS and SP values

This instruction is executed to transfer both SS and SP values before the register bank is switched

to SS and SP of the current (post-switching) register bank.

(Descriptive format)

MOVSPB ··· Used to transfer SS and SP values

This instruction is executed to transfer the SS and SP values of the current (pre-switching)

bit register described in the operand.

(Descriptive format)

Some

PD70108/ 70116 instructions should be much cared as shown below when used for the

PD70325.

· I/O instruction, primitive I/O instruction

If PSW IBRK flag is reset (0), an interrupt is generated without executing this instruction. Be sure to set (1)

the IBRK flag when using the I/O instruction.

· FPO instruction

An interrupt is generated without executing this instruction.

Mnemonic

Operand

BRKCS

reg16

Mnemonic

Operand

TSKSW

reg16

Mnemonic

Operand

MOVSPA

None

Mnemonic

Operand

MOVSPB

reg16

PD70325

2.2 Instruction Set Operation

Table 2-1. Operand Identifier

Identifier

Description

reg, reg'

8-/16-bit general register

reg8, reg8'

8-bit general register

reg16, reg16'

16-bit general register

dmem

8-/16-bit memory location

mem

8-/16-bit memory location

mem8

8-bit memory location

mem16

16-bit memory location

mem32

32-bit memory location

sfr

8-bit special function register location

imm

Constant within 0 to FFFFH

imm3

Constant within 0 to 7

imm4

Constant within 0 to FH

imm8

Constant within 0 to FFH

imm16

Constant within 0 to FFFFH

acc

sreg

Segment register

src-table

256-byte conversion table name

src-block

dst-block

near-proc

Procedure in the current program segment

far-proc

Procedure in another program segment

near-label

Label in the current program segment

short-label

Label within end of instruction to 128 to +127 bytes

far-label

Label in another program segment

memptr16

Word including location offset in the current program segment to which control is to be passed

memptr32

Double-word including location offset in another program segment to which control is to be passed

and segment base address

regptr16

16-bit general register including location offset in another program segment to which control is to be

passed

pop-value

Number of bytes to be abandoned from stack (0 to 64K, normally even number)

fp-op

Immediate value to judge instruction code of external floating point operation chip

PD70325

Identifier

Description

Byte/word specification bit (0: byte, 1: word). However, when s = 1, the sign extended byte data

should be 16-bit operand even when W is 1.

reg, reg'

mem

Memory field (000 to 111)

mod

Mode field (00 to 10)

Sign extension specification bit (0: Sign is not extended, 1: Sign is extended)

X, XXX, YYY, ZZZ

Data used to judge instruction code of external floating-point operation chip

Table 2-2. Operation Code Identifier

Table 2-3. Operation Identifier (1/2)

Identifier

Description

Accumulator (16 bits)

Accumulator (upper byte)

Accumulator (lower byte)

Stack pointer (16 bits)

Program counter (16 bits)

PSW

Program status word (16 bits)

Index register (source) (16 bits)

Index register (destination) (16 bits)

Program segment register (16 bits)

DS1

Data segment 1 register (16 bits)

DS0

Data segment 0 register (16 bits)

Stack segment register (16 bits)

Auxiliary carry flag

Carry flag

Parity flag

Sign flag

Zero flag

DIR

Direction flag

Interrupt enable flag

Overflow flag

BRK

Break flag

(···)

Contents in memory shown in ( )

disp

Displacement (8/16 bits)

ext-disp8

16 bits obtained by extending sign of 8-bit displacement

PD70325

Table 2-3. Operation Identifier (2/2)

Identifier

Description

temp

Temporary register (8/16/32 bits)

tmpcy

Temporary carry flag (1 bit)

seg

Immediate segment data (16 bits)

offset

Immediate offset data (16 bits)

Transfer direction

Addition

Subtraction

Multiplication

Division

Modulo

AND

Exclusive OR

××

2-digit hexadecimal number

××××

4-digit hexadecimal number

Identifier

Description

(Blank)

No change

Cleared to 0

Set to 1

Set or cleared according to the result

Not defined

The previously saved value is restored.

Table 2-4. Flag Operation Identifier

Table 2-5. Memory Addressing

0 0

0 1

1 0

0 0 0

BW + IX

BW + IX + disp 8

BW + IX + disp 16

0 0 1

BW + IY

BW + IY + disp 8

BW + IY + disp 16

0 1 0

BP + IX

BP + IX + disp 8

BP + IX + disp 16

0 1 1

BP + IY

BP + IY + disp 8

BP + IY + disp 16

1 0 0

+ disp 8

+ disp 16

1 0 1

+ disp 8

+ disp 16

1 1 0 DIRECT ADDRESS

BP + disp 8

BP + disp 16

1 1 1

BW + disp 8

BW + disp 16

mod

mem

PD70325

2.3

Instruction Set Table

Data
transfer

MOV

LDEA

TRANS

XCH

MOVSPA

Note

MOVSPB

Note

reg,reg'

mem,reg

reg,mem

mem,imm

reg,imm

acc,dmem

dmem,acc

sreg,reg16

sreg,mem16

reg16,sreg

mem16,sreg

DS0,reg16,
mem32
DS1,reg16,
mem32

AH,PSW

PSW,AH

reg16,mem16

src-table

reg,reg'

mem,reg
reg,mem
AW,reg16
reg16,AW

reg16

Operation Code

1 0 0 0 1 0 1 W

1 0 0 0 1 0 0 W

1 0 0 0 1 0 1 W

1 1 0 0 0 1 1 W

1 0 1 1 W reg

1 0 1 0 0 0 0 W

1 0 1 0 0 0 1 W

1 0 0 0 1 1 1 0

1 0 0 0 1 1 0 0

1 1 0 0 0 1 0 1

1 1 0 0 0 1 0 0

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 0 1

1 1 0 1 0 1 1 1

1 0 0 0 0 1 1 W

1 0 0 1 0 reg

0 0 0 0 1 1 1 1

1 1 1 1 1 reg

7 6 5 4 3 2 1 0

1 1 reg reg'

mod reg mem

mod 0 0 0 mem

1 1 0 sreg reg

mod 0 sreg mem

1 1 0 sreg reg

mod 0 sreg mem

mod reg mem

1 1 reg reg'

mod reg mem

0 0 1 0 0 1 0 1

1 0 0 1 0 1 0 1

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 6

2 to 3

2 to 4

Bytes

Flags

AC CY V

reg

reg'

(mem)

reg

(mem)

imm

reg

imm

When W = 0, AL

(dmem)

When W = 1, AH

(dmem + 1), AL

(dmem)

When W = 0, (dmem)

When W = 1, (dmem + 1)

AH, (dmem)

sreg

reg16

sreg

(mem16)

reg16

sreg

(mem16)

sreg

reg16

(mem32)

DS0

(mem32 + 2)

reg16

(mem32)

DS1

(mem32 + 2)

S, Z, F1, AC, F0, P, IBRK, CY

reg16

mem16

(BW + AL)

reg

reg'

(mem)

reg

reg16

New register bank SS and SP

old register bank SS and SP

SS and SP of reg16-indicated new register bank

old register bank

SS and SP

Operation

sreg : SS, DS0, DS1

Note These instructions are newly added to the PD70108/70116.

PD70325

REPC

REPNC

REP

REPE

REPZ

REPNE

REPNZ

MOVBK

CMPBK

CMPM

LDM

STM

dst-block,

src-block

src-block,

dst-block

src-block

dst-block

Operation Code

0 1 1 0 0 1 0 1

0 1 1 0 0 1 0 0

1 1 1 1 0 0 1 1

1 1 1 1 0 0 1 0

1 0 1 0 0 1 0 W

1 0 1 0 0 1 1 W

1 0 1 0 1 1 1 W

1 0 1 0 1 1 0 W

1 0 1 0 1 0 1 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

Bytes

Flags

AC CY V

Executes the primitive block transfer instruction in the continued
byte while CW

0, and decrements CW by one. If any interruption

is held at this time, it is processed. The program exits the loop
when CY

Same as above.
The program exits the loop when CY

Executes the primitive block transfer instruction in the continued
byte while CW

0, and decrements CW by one. If any interruption

is held at this time, it is processed. The program exits the loop
when the primitive block transfer instruction is CMPBK or CMPM,
and when Z

Same as above.
The program exits the loop when Z

When W = 0, (IY)

(IX)

DIR = 0: IX

IX + 1, IY

IY + 1

DIR = 1: IX

IX 1, IY

IY 1

When W = 1, (IY + 1, IY)

(IX + 1, IX)

DIR = 0: IX

IX + 2, IY

IY + 2

DIR = 1: IX

IX 2, IY

IY 2

When W = 0, (IX) (IY)
DIR = 0: IX

IX + 1, IY

IY + 1

DIR = 1: IX

IX 1, IY

IY 1

When W = 1, (IX + 1, IX) (IY + 1, IY)
DIR = 0: IX

IX + 2, IY

IY + 2

DIR = 1: IX

IX 2, IY

IY 2

When W = 0, AL (IY)
DIR = 0: IY

IY + 1; DIR = 1: IY

IY 1

When W = 1, AW (IY + 1, IY)
DIR = 0: IY

IY + 2; DIR = 1: IY

IY 2

When W = 0, AL

(IX)

DIR = 0: IX

IX + 1; DIR = 1: IX

IX 1

When W = 1, AW

(IX + 1, IX)

DIR = 0: IX + 2; DIR = 1: IX

IX 2

When W = 0, (IY)

DIR = 0: IY

IY + 1; DIR = 1: IY

IY 1

When W = 1, (IY + 1, IY)

DIR = 0: IY

IY + 2; DIR = 1: IY

IY 2

Operation

Repeat
prefix

Primitive
block
transfer

PD70325

INS

EXT

OUT

INM

OUTM

reg8,reg8'

reg8,imm4

reg8,reg8'

reg8,imm4

acc,imm8

acc,DW

imm8,acc

DW,acc

dst-block,DW

DW,src-block

Operation Code

0 0 0 0 1 1 1 1

1 1 reg' reg

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

1 1 reg' reg

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

1 1 1 0 0 1 0 W

1 1 1 0 1 1 0 W

1 1 1 0 0 1 1 W

1 1 1 0 1 1 1 W

0 1 1 0 1 1 0 W

0 1 1 0 1 1 1 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

Bytes

Flags

AC CY V

16-bit field

When W = 0, AL

(imm8)

When W = 1, AH

(imm8 + 1), AL

(imm8)

When W = 0, AL

(DW)

When W = 1, AH

(DW + 1), AL

(DW)

When W = 0, (imm8)

When W = 1, (imm8 + 1)

AH, (imm8)

When W = 0, (DW)

When W = 1, (DW + 1)

AH, (DW)

When W = 0, (IY)

(DW)

DIR = 0: IY

IY + 1; DIR = 1: IY

IY 1

When W = 1, (IY + 1, IY)

(DW + 1, DW)

DIR = 0: IY

IY + 2; DIR = 1: IY

IY 2

When W = 0, (DW)

(IX)

DIR = 0: IX

IX + 1; DIR = 1: IX

IX 1

When W = 1, (DW + 1, DW)

(IX + 1, IX)

DIR = 0: IX

IX + 2; DIR = 1: IX

IX 2

Operation

Bit field
opera-
tion

I/O

0 0 1 1 0 0 0 1

0 0 1 1 1 0 0 1

0 0 1 1 0 0 1 1

0 0 1 1 1 0 1 1

Note

Primitive
I/O

Note When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed.

PD70325

ADD

ADDC

SUB

SUBC

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

Operation Code

0 0 0 0 0 0 1 W

0 0 0 0 0 0 0 W

0 0 0 0 0 0 1 W

1 0 0 0 0 0 s W

0 0 0 0 0 1 0 W

0 0 0 1 0 0 1 W

0 0 0 1 0 0 0 W

0 0 0 1 0 0 1 W

1 0 0 0 0 0 s W

0 0 0 1 0 1 0 W

0 0 1 0 1 0 1 W

0 0 1 0 1 0 0 W

0 0 1 0 1 0 1 W

1 0 0 0 0 0 s W

0 0 1 0 1 1 0 W

0 0 0 1 1 0 1 W

0 0 0 1 1 0 0 W

0 0 0 1 1 0 1 W

1 0 0 0 0 0 s W

0 0 0 1 1 1 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

3 to 4

3 to 6

2 to 3

Bytes

Flags

AC CY V

reg

reg + reg'

(mem)

(mem) + reg

reg

reg + (mem)

reg

reg + imm

(mem)

(mem) + imm

When W = 0, AL

AL + imm

When W = 1, AW

AW + imm

reg

reg + reg' + CY

(mem)

(mem) + reg + CY

reg

reg + (mem) + CY

reg

reg + imm + CY

(mem)

(mem) + imm + CY

When W = 0, AL

AL + imm + CY

When W = 1, AW

AW + imm + CY

reg

reg reg'

(mem)

(mem) reg

reg

reg (mem)

reg

reg imm

(mem)

(mem) imm

When W = 0, AL

AL imm

When W = 1, AW

AW imm

reg

reg reg' CY

(mem)

(mem) reg CY

reg

reg (mem) CY

reg

reg imm CY

(mem)

(mem) imm CY

When W = 0, AL

AL imm CY

When W = 1, AW

AW imm CY

Operation

Addi-
tion/
subtrac-
tion

1 1 reg reg'

mod reg mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 reg reg'

mod reg mem

1 1 0 1 0 reg

mod 0 1 0 mem

1 1 reg reg'

mod reg mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 reg reg'

mod reg mem

1 1 0 1 1 reg

mod 0 1 1 mem

PD70325

ADD4S

SUB4S

CMP4S

ROL4

ROR4

INC

DEC

reg8

mem8

reg8

mem8

reg8

mem

reg16

reg8

mem

reg16

Operation Code

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

mod 0 0 0 mem

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

mod 0 0 0 mem

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 W

0 1 0 0 0 reg

1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 W

0 1 0 0 1 reg

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

3 to 5

2 to 4

Bytes

Flags

AC CY V

dst BCD string

dst BCD string + src BCD string

dst BCD string

dst BCD string src BCD string

reg8

reg8 + 1

(mem)

(mem) + 1

reg16

reg16 + 1

reg8

reg8 1

(mem)

(mem) 1

reg16

reg16 1

Operation

BCD
opera-
tion

0 0 1 0 0 0 0 0

0 0 1 0 0 0 1 0

0 0 1 0 0 1 1 0

0 0 1 0 1 0 0 0

0 0 1 0 1 0 1 0

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 1 reg

mod 0 0 1 mem

Note

Incre-
ment/
decre-
ment

Upper
Byte

Lower
Byte

reg

Upper
Byte

Lower
Byte

mem

Upper
Byte

Lower
Byte

reg

Upper
Byte

Lower
Byte

mem

Note The number of BCD digits is given in the CL register. The value can be set within 1 to 254.

PD70325

MULU

MUL

reg8

mem8

reg16

mem16

reg8

mem8

reg16

mem16

reg16,
(reg16',)

Note

imm8

reg16,
mem16,
imm8

reg16,
(reg16',)

Note

imm16

reg16,
mem16,
imm16

Operation Code

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

0 1 1 0 1 0 1 1

0 1 1 0 1 0 0 1

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 5

4 to 6

Bytes

Flags

AC CY V

reg8

AH = 0: CY

0, V

0: CY

1, V

(mem8)

AH = 0: CY

0, V

0: CY

1, V

DW, AW

reg16

DW = 0: CY

0, V

DW = 1: CY

1, V

DW, AW

(mem16)

DW = 0: CY

0, V

DW = 1: CY

1, V

reg8

Extension of AH = AL sign: CY

0, V

Extension of AH

AL sign: CY

1, V

(mem8)

Extension of AH = AL sign: CY

0, V

Extension of AH

AL sign: CY

1, V

DW, AW

reg16

Extension of DW = AW sign: CY

0, V

Extension of DW

AW sign: CY

1, V

DW, AW

(mem16)

Extension of DW = AW sign: CY

0, V

Extension of DW

AW sign: CY

1, V

reg16

reg16'

imm8

Product

16 bits: CY

0, V

Product > 16 bits: CY

1, V

reg16

(mem16)

imm8

Product

16 bits: CY

0, V

Product > 16 bits: CY

1, V

reg16

reg16'

imm16

Product

16 bits: CY

0, V

Product > 16 bits: CY

1, V

reg16

(mem16)

imm16

Product

16 bits: CY

0, V

Product > 16 bits: CY

1, V

Operation

Multipli-
cation

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 reg reg'

mod reg mem

1 1 reg reg'

mod reg mem

Note The 2nd operand is omissible. If omitted, the 1st operand is assumed.

PD70325

DIVU

reg8

mem8

reg16

mem16

Operation Code

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

Bytes

Flags

AC CY V

temp

When temp

reg8

FFH

temp%reg8, AL

temp

reg8

When temp

reg8 > FFH

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

temp

When temp

(mem8)

FFH

temp%(mem8), AL

temp

(mem8)

When temp

(mem8) > FFH

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

temp

DW, AW

When temp

reg16

FFFFH

temp%reg16, AW

temp

reg16

When temp

reg16 > FFFFH

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

temp

DW, AW

When temp

(mem16)

FFFFH

temp%(mem16), AW

temp

(mem16)

When temp

(mem16) > FFFFH

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

Operation

Unsign-
ed
division

1 1 1 1 0 reg

mod 1 1 0 mem

1 1 1 1 0 reg

mod 1 1 0 mem

PD70325

DIV

reg8

mem8

reg16

mem16

Operation Code

1 1 1 1 0 1 1 0

1 1 1 1 0 1 1 1

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

Bytes

Flags

AC CY V

Operation

Signed
division

1 1 1 1 1 reg

mod 1 1 1 mem

1 1 1 1 1 reg

mod 1 1 1 mem

temp

When temp

reg8 > 0 and temp

reg8

7FH or

temp

reg8 < 0 and temp

reg8 > 0 7FH 1

temp%reg8, AL

temp

reg8

When temp

reg8 > 0 and temp

reg8 > 7FH or

temp

reg8 > 0 and temp

reg8 < 0 7FH 1

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

temp

When temp

(mem8) > 0 and temp

(mem8)

7FH or

temp

(mem8) < 0 and temp

(mem8) > 0 7FH 1

temp%(mem8), AL

temp

(mem8)

When temp

(mem8) > 0 and temp

(mem8) > 7FH or

temp

(mem8) > 0 and temp

(mem8) < 0 7FH 1

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

temp

DW, AW

When temp

reg16 > 0 and temp

reg16

7FFFH or

temp

reg16 < 0 and temp

reg16 > 0 7FFFH 1

temp%reg16, AW

temp

reg16

When temp

reg16 > 0 and temp

reg16 > 7FFFH or

temp

reg16 > 0 and temp

reg16 < 0 7FFFH 1

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

temp

DW, AW

When temp

(mem16) > 0 and temp

(mem16)

7FFFH or

temp

(mem16) < 0 and temp

(mem16) > 0 7FFFH 1

temp%(mem16), AW

temp

(mem16)

When temp

(mem16) > 0 and temp

(mem16) > 7FFFH or

temp

(mem16) > 0 and temp

(mem16) < 0 7FFFH 1

(SP 1, SP 2)

PSW, (SP 3, SP 4)

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

0, PS

(3, 2), PC

(1, 0)

PD70325

ADJBA

ADJ4A

ADJBS

ADJ4S

CVTBD

CVTDB

CVTBW

CVTWL

CMP

NOT

NEG

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg

mem

reg

mem

Operation Code

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 0 1 0 1 0 0

1 1 0 1 0 1 0 1

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

0 0 1 1 1 0 1 W

0 0 1 1 1 0 0 W

0 0 1 1 1 0 1 W

1 0 0 0 0 0 s W

0 0 1 1 1 1 0 W

1 1 1 1 0 1 1 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

Bytes

Flags

AC CY V

When AL

0FH > 9 or AC = 1, AL

AL + 6

AH + 1, AC

1, CY

AC, AL

0FH

When AL

0FH > 9 or AC = 1,

AL + 6, AC

When AL > 9FH or CY = 1,
AL

AL + 60H, CY

When AL

0FH > 9 or AC = 1,

AL 6, AH

AH 1, AC

AC, AL

0FH

When AL

0FH > 9 or AC = 1,

AL 6, AC

When AL > 9FH or CY = 1,
AL

AL 60H, CY

AL ÷ 0AH, AL

AL%0AH

0AH + AL, AH

When AL < 80H, AH

0. In other cases, AH

FFH.

When AW < 8000H, DW

0. In other cases, DW

FFFFH.

reg reg'

(mem) reg

reg (mem)

reg imm

(mem) imm

When W = 0, AL imm
When W = 1, AW imm

reg

(mem)

reg

reg + 1

(mem)

(mem) + 1

Operation

BCD
adjust-
ment

0 0 0 0 1 0 1 0

1 1 reg reg'

mod reg mem

1 1 1 1 1 reg

mod 1 1 1 mem

1 1 0 1 0 reg

mod 0 1 0 mem

1 1 0 1 1 reg

mod 0 1 1 mem

Data
conver-
sion

Compare

Comple-
ment
opera-
tion

PD70325

TEST

AND

XOR

reg,reg'

mem,reg
reg,mem

reg,imm

mem,imm

acc,imm

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

reg,reg'

mem,reg

reg,mem

reg,imm

mem,imm

acc,imm

Operation Code

1 0 0 0 0 1 0 W

1 1 1 1 0 1 1 W

1 0 1 0 1 0 0 W

0 0 1 0 0 0 1 W

0 0 1 0 0 0 0 W

0 0 1 0 0 0 1 W

1 0 0 0 0 0 0 W

0 0 1 0 0 1 0 W

0 0 0 0 1 0 1 W

0 0 0 0 1 0 0 W

0 0 0 0 1 0 1 W

1 0 0 0 0 0 0 W

0 0 0 0 1 1 0 W

0 0 1 1 0 0 1 W

0 0 1 1 0 0 0 W

0 0 1 1 0 0 1 W

1 0 0 0 0 0 0 W

0 0 1 1 0 1 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

3 to 4

3 to 6

2 to 3

2 to 4

3 to 4

3 to 6

2 to 3

Bytes

Flags

AC CY V

reg

reg'

(mem)

reg

imm

(mem)

imm

When W = 0, AL

imm8

When W = 1, AW

imm16

reg

reg'

(mem)

reg

(mem)

reg

imm

(mem)

imm

When W = 0, AL

imm8

When W = 1, AW

imm16

reg

reg'

(mem)

reg

(mem)

reg

imm

(mem)

imm

When W = 0, AL

imm8

When W = 1, AW

imm16

reg

reg'

(mem)

reg

(mem)

reg

imm

(mem)

imm

When W = 0, AL

imm8

When W = 1, AW

imm16

Operation

Logical
opera-
tion

1 1 reg' reg

mod reg mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 reg reg'

mod reg mem

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 reg reg'

mod reg mem

1 1 0 0 1 reg

mod 0 0 1 mem

1 1 reg reg'

mod reg mem

1 1 1 1 0 reg

mod 1 1 0 mem

PD70325

TEST1

NOT1

reg8,CL

mem8,CL

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

reg8,CL

mem8,CL

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

Operation Code

0 0 0 1 0 0 0 0

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

3 to 5

4 to 6

3 to 5

4 to 6

Bytes

Flags

AC CY V

reg8 bit No. CL = 0: Z

reg8 bit No. CL = 1: Z

(mem8) bit No. CL = 0: Z

(mem8) bit No. CL = 1: Z

reg16 bit No. CL = 0: Z

reg16 bit No. CL = 1: Z

(mem16) bit No. CL = 0: Z

(mem16) bit No. CL = 1: Z

reg8 bit No. imm3 = 0: Z

reg8 bit No. imm3 = 1: Z

(mem8) bit No. imm3 = 0: Z

(mem8) bit No. imm3 = 1: Z

reg16 bit No. imm4 = 0: Z

reg16 bit No. imm4 = 1: Z

(mem16) bit No. imm4 = 0: Z

(mem16) bit No. imm4 = 1: Z

reg8 bit No. CL

(mem8) bit No. CL

reg16 bit No. CL

(mem16) bit No. CL

reg8 bit No. imm3

(mem8) bit No. imm3

reg16 bit No. imm4

(mem16) bit No. imm4

Operation

Bit
manipu-
lation

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

0 0 0 0

0 0 0 1

1 0 0 0

1 0 0 1

0 1 1 0

0 1 1 1

1 1 1 0

1 1 1 1

2nd byte

Note

3rd byte

Note

1st byte = 0FH

1 1 1 1 0 1 0 1

NOT1

Note

PD70325

CLR1

SET1

reg8,CL

mem8,CL

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

reg8,CL

mem8,CL

reg16,CL

mem16,CL

reg8,imm3

mem8,imm3

reg16,imm4

mem16,imm4

Operation Code

0 0 0 1 0 0 1 0

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

3 to 5

4 to 6

3 to 5

4 to 6

Bytes

Flags

AC CY V

reg8 bit No. CL

(mem8) bit No. CL

reg16 bit No. CL

(mem16) bit No. CL

reg8 bit No. imm3

(mem8) bit No. imm3

reg16 bit No. imm4

(mem16) bit No. imm4

reg8 bit No. CL

(mem8) bit No. CL

reg16 bit No. CL

(mem16) bit No. CL

reg8 bit No. imm3

(mem8) bit No. imm3

reg16 bit No. imm4

(mem16) bit No. imm4

Operation

Bit
manipu-
lation

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

0 0 1 0

0 0 1 1

1 0 1 0

1 0 1 1

0 1 0 0

0 1 0 1

1 1 0 0

1 1 0 1

2nd byte

Note

3rd byte

Note

Note 1st byte = 0FH

DIR

1 1 1 1 1 0 0 0

1 1 1 1 1 1 0 0

1 1 1 1 1 0 0 1

1 1 1 1 1 1 0 1

DIR

CLR1

SET1

PD70325

SHL

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

Operation Code

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 5

Bytes

Flags

AC CY V

reg MSB, reg

reg

When reg MSB

CY, V

When reg MSB = CY, V

(mem) MSB, (mem)

(mem)

When (mem) MSB

CY, V

When (mem) MSB = CY, V

The following operations are repeated while temp

and temp

reg MSB, reg

reg

temp

temp 1

The following operations are repeated while temp

and temp

(mem) MSB, (mem)

(mem)

temp

temp 1

The following operations are repeated while temp

imm8

and temp

reg MSB, reg

reg

temp

temp 1

The following operations are repeated while temp

imm8

and temp

(mem) MSB, (mem)

(mem)

temp

temp 1

Operation

Shift

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 1 0 0 reg

mod 1 0 0 mem

1 1 1 0 0 reg

mod 1 0 0 mem

PD70325

SHR

SHRA

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

Operation Code

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 5

2 to 4

3 to 5

Bytes

Flags

AC CY V

reg LSB, reg

reg

reg MSB

bit following reg MSB: V

reg MSB = bit following reg MSB: V

(mem) LSB, (mem)

(mem)

(mem) MSB

bit following (mem) MSB: V

(mem) MSB = bit following (mem) MSB: V

The following operations are repeated while temp

and temp

reg LSB, reg

reg

temp

temp 1

The following operations are repeated while temp

and temp

(mem) LSB, (mem)

(mem)

temp

temp 1

The following operations are repeated while temp

imm8

and temp

reg LSB, reg

reg

temp

temp 1

The following operations are repeated while temp

imm8

and temp

(mem) LSB, (mem)

(mem)

temp

temp 1

reg LSB, reg

reg

2, V

The operand MSB remains the same status.
CY

(mem) LSB, (mem)

(mem)

2, V

The operand MSB remains the same status.
The following operations are repeated while temp

and temp

0. CY

reg LSB, reg

reg

temp

temp 1

The operand MSB remains the same status.
The following operations are repeated while temp

and temp

0. CY

(mem) LSB, (mem)

(mem)

The operand MSB remains the same status.
The following operations are repeated while temp

imm8

and temp

0. CY

reg LSB, reg

reg

temp

temp 1

The operand MSB remains the same status.
The following operations are repeated while temp

imm8

and temp

0. CY

(mem) LSB, (mem)

(mem)

temp

temp 1

The operand MSB remains the same status.

Operation

Shift

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 1 0 1 reg

mod 1 0 1 mem

1 1 1 1 1 reg

mod 1 1 1 mem

1 1 1 1 1 reg

mod 1 1 1 mem

1 1 1 1 1 reg

mod 1 1 1 mem

temp

temp 1

PD70325

ROL

ROR

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

Operation Code

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 5

2 to 4

3 to 5

Bytes

Flags

AC CY V

reg MSB, reg

reg

2 + CY

reg MSB

CY: V

reg MSB = CY: V

(mem) MSB, (mem)

(mem)

2 + CY

(mem) MSB

CY: V

(mem) MSB = CY: V

The following operations are repeated while temp

and temp

reg MSB, reg

reg

2 + CY

temp

temp 1

The following operations are repeated while temp

and temp

(mem) MSB, (mem)

(mem)

2 + CY

temp

temp 1

The following operations are repeated while temp

imm8

and temp

reg MSB, reg

reg

2 + CY

temp

temp 1

The following operations are repeated while temp

imm8

and temp

(mem) MSB, (mem)

(mem)

2 + CY

temp

temp 1

reg LSB, reg

reg ÷ 2

reg MSB

bit following reg MSB: V

reg MSB = bit following reg MSB: V

(mem) LSB, (mem)

(mem) ÷ 2

(mem) MSB

bit following (mem) MSB: V

(mem) MSB = bit following (mem) MSB: V

The following operations are repeated while temp

CL and temp

reg LSB, reg

reg ÷ 2

reg MSB

temp

temp 1

The following operations are repeated while temp

CL and temp

(mem) LSB, (mem)

(mem) ÷ 2

(mem) MSB

temp

temp 1

The following operations are repeated while temp

imm8 and temp

reg LSB, reg

reg ÷ 2

reg MSB

temp

temp 1

The following operations are repeated while temp

imm8 and temp

(mem) LSB, (mem)

(mem) ÷ 2

(mem) MSB

temp

temp 1

Operation

Rotate

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 0 reg

mod 0 0 0 mem

1 1 0 0 1 reg

mod 0 0 1 mem

1 1 0 0 1 reg

mod 0 0 1 mem

1 1 0 0 1 reg

mod 0 0 1 mem

PD70325

ROLC

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

Operation Code

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 5

Bytes

Flags

AC CY V

tmpcy

CY, CY

reg MSB

reg

2 + tmpcy

reg MSB

CY: V

reg MSB = CY: V

tmpcy

CY, CY

(mem) MSB

(mem)

2 + tmpcy

(mem) MSB

CY: V

(mem) MSB = CY: V

The following operations are repeated while temp

CL and temp

tmpcy

CY, CY

reg MSB

reg

2 + tmpcy

temp

temp 1

The following operations are repeated while temp

CL and temp

tmpcy

CY, CY

(mem) MSB

(mem)

2 + tmpcy

temp

temp 1

The following operations are repeated while temp

imm8

and temp

tmpcy

CY, CY

reg MSB

reg

2 + tmpcy

temp

temp 1

The following operations are repeated while temp

imm8

and temp

tmpcy

CY, CY

(mem) MSB

(mem)

2 + tmpcy

temp

temp 1

Operation

Rotate

1 1 0 1 0 reg

mod 0 1 0 mem

1 1 0 1 0 reg

mod 0 1 0 mem

1 1 0 1 0 reg

mod 0 1 0 mem

PD70325

RORC

reg,1

mem,1

reg,CL

mem,CL

reg,imm8

mem,imm8

Operation Code

1 1 0 1 0 0 0 W

1 1 0 1 0 0 1 W

1 1 0 0 0 0 0 W

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

3 to 5

Bytes

Flags

AC CY V

tmpcy

CY, CY

reg LSB

reg

reg MSB

tmpcy

reg MSB

bit following reg MSB: V

reg MSB = bit following reg MSB: V

tmpcy

CY, CY

(mem) LSB

(mem)

(mem) MSB

tmpcy

(mem) MSB

bit following (mem) MSB: V

(mem) MSB = bit following (mem) MSB: V

The following operations are repeated while temp

CL and temp

tmpcy

CY, CY

reg LSB

reg

reg MSB

tmpcy

temp

temp 1

The following operations are repeated while temp

CL and temp

tmpcy

CY, CY

(mem) LSB

(mem)

(mem) MSB

tmpcy

temp

temp 1

The following operations are repeated while temp

imm8

and temp

tmpcy

CY, CY

reg LSB

reg

reg MSB

tmpcy

temp

temp 1

The following operations are repeated while temp

imm8

and temp

tmpcy

CY, CY

(mem) LSB

(mem)

(mem) MSB

tmpcy

temp

temp 1

Operation

Rotate

1 1 0 1 1 reg

mod 0 1 1 mem

1 1 0 1 1 reg

mod 0 1 1 mem

1 1 0 1 1 reg

mod 0 1 1 mem

PD70325

CALL

RET

near-proc

regptr16

memptr16

far-proc

memptr32

pop-value

Operation Code

1 1 1 0 1 0 0 0

1 1 1 1 1 1 1 1

1 0 0 1 1 0 1 0

1 1 1 1 1 1 1 1

1 1 0 0 0 0 1 1

1 1 0 0 0 0 1 0

1 1 0 0 1 0 1 1

1 1 0 0 1 0 1 0

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

Bytes

Flags

AC CY V

(SP 1, SP 2)

PC, SP

SP 2

PC + disp

(SP 1, SP 2)

PC, PC

regptr16

SP 2

(SP 1, SP 2)

PC, SP

SP 2

(memptr16)

(SP 1, SP 2)

PS, (SP 3, SP 4)

SP 4

seg, PC

offset

(SP 1, SP 2)

PS, (SP 3, SP 4)

SP 4

(memptr32 + 2), PC

(memptr32)

(SP + 1, SP)

SP + 2

(SP + 1, SP)

SP + 2, SP

SP + pop-value

(SP + 1, SP)

(SP + 3, SP + 2)

SP + 4

(SP + 1, SP)

(SP + 3, SP + 2)

SP + 4, SP

SP + pop-value

Operation

Sub-
routine
control

1 1 0 1 0 reg

mod 0 1 0 mem

mod 0 1 1 mem

PD70325

PUSH

POP

PREPARE

DISPOSE

mem16

reg16

sreg

PSW

imm8

imm16

mem16

reg16

sreg

PSW

imm16,imm8

near-label

short-label

regptr16

memptr16

far-label

memptr32

Operation Code

1 1 1 1 1 1 1 1

0 1 0 1 0 reg

0 0 0 sreg 1 1 0

1 0 0 1 1 1 0 0

0 1 1 0 0 0 0 0

0 1 1 0 1 0 1 0

0 1 1 0 1 0 0 0

1 0 0 0 1 1 1 1

0 1 0 1 1 reg

0 0 0 sreg 1 1 1

1 0 0 1 1 1 0 1

0 1 1 0 0 0 0 1

1 1 0 0 1 0 0 0

1 1 0 0 1 0 0 1

1 1 1 0 1 0 0 1

1 1 1 0 1 0 1 1

1 1 1 1 1 1 1 1

1 1 1 0 1 0 1 0

1 1 1 1 1 1 1 1

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

Bytes

Flags

AC CY V

(SP 1, SP 2)

(mem16)

SP 2

(SP 1, SP 2)

reg16

SP 2

(SP 1, SP 2)

sreg

SP 2

(SP 1, SP 2)

PSW

SP 2

Push registers on the stack

(SP 1, SP 2)

imm8 sign extension

SP 2

(SP 1, SP 2)

imm16

SP 2

(mem16)

(SP + 1, SP)

SP + 2

reg16

(SP + 1, SP)

SP + 2

sreg

(SP + 1, SP)

sreg: SS, DS0, DS1

SP + 2

PSW

(SP + 1, SP)

SP + 2

Pop registers from the stack

Prepare New Stack Frame

Dispose of Stack Frame

PC + disp

PC + ext-disp8

regptr16

(memptr16)

seg

offset

(memptr32 + 2)

(memptr32)

Operation

Stack
manipu-
lation

mod 1 1 0 mem

mod 0 0 0 mem

1 1 1 0 0 reg

mod 1 0 0 mem

mod 1 0 1 mem

Branch

PD70325

BNV

BC
BL
BNC
BNL
BE
BZ
BNE
BNZ

BNH

BPE

BPO

BLT

BGE

BLE

BGT

DBNZNE

DBNZE

DBNZ

BCWZ

BTCLR

Note

short-label

sfr,
imm3,
short-label

Operation Code

0 1 1 1 0 0 0 0

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

Bytes

Flags

AC CY V

if V = 1

if V = 0

if CY = 1

if CY = 0

if Z = 1

if Z = 0

if CY

Z = 1

if CY

Z = 0

if S = 1

if S = 0

if P = 1

if P = 0

if S

V = 1

if S

V = 0

if (S

Z = 1

if (S

Z = 0

CW = CW 1
if Z = 0 and CW

CW = CW 1
if Z = 1 and CW

CW = CW 1
if CW

if CW = 0

When (sfr) bit No. imm3 = 1, PC

PC + ext-disp8 and (sfr)

bit No. imm3

Operation

Condi-
tional
branch

1 0 0 1 1 1 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

1 1 1 0 0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 0 0 0 1 1 1 1

PC + ext-disp8

Note This instruction is newly added to the PD70108/70116.

PD70325

BRK

BRKV

RETI

RETRBI

Note

FINT

Note

CHKIND

BRKCS

Note

TSKSW

Note

imm8
(

reg16,mem32

reg16

Operation Code

1 1 0 0 1 1 0 0

1 1 0 0 1 1 0 1

1 1 0 0 1 1 1 0

1 1 0 0 1 1 1 1

0 0 0 0 1 1 1 1

0 1 1 0 0 0 1 0

0 0 0 0 1 1 1 1

1 1 0 0 0 reg

0 0 0 0 1 1 1 1

1 1 1 1 1 reg

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

Bytes

Flags

AC CY V

(SP 1, SP 2)

PSW, (SP 3, SP 4)

PS,

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

(15, 14), PC

(13, 12)

(SP 1, SP 2)

PSW, (SP 3, SP 4)

PS,

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

4 + 3, n

4 + 2), PC

4 + 1, n

4) n = imm8

When V = 1,
(SP 1, SP 2)

PSW, (SP 3, SP 4)

PS,

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

(19, 18), PC

(17, 16)

(SP + 1, SP), PS

(SP + 3, SP + 2),

PSW

(SP + 5, SP + 4), SP

SP + 6

Save PC, PSW

Save PSW

Reports the CPU internal interrupt controller that interrupt service
routine operation has ended.

When (mem32) > reg16 or (mem32 + 2) < reg16,
(SP 1, SP 2)

PSW, (SP 3, SP 4)

PS,

(SP 5, SP 6)

PC, SP

SP 6

0, BRK

(23, 22), PC

(21, 20)

RB2 0

lower 3 bits of reg16, IE

0, BRK

Save PSW

PSW, Save PC

PC, PC

Vector PC

RB2

lower 3 bits of reg16,

Old register bank Save PSW and Save PC

PSW and PC,

PSW and PC

New register bank Save PSW and Save PC

Operation

Interrupt

1 0 0 1 0 0 0 1

1 0 0 1 0 0 1 0

mod reg mem

0 0 1 0 1 1 0 1

1 0 0 1 0 1 0 0

Note These instructions are newly added to the PD70108/70116.

PD70325

HALT

STOP

Note 2

POLL

BUSLOCK

FPO1

Note 3

FPO2

Note 3

NOP

Note 1

fp-op

fp-op,mem

fp-op

fp-op,mem

Operation Code

1 1 1 1 0 1 0 0

0 0 0 0 1 1 1 1

1 0 0 1 1 0 1 1

1 1 1 1 1 0 1 0

1 1 1 1 1 0 1 1

1 1 1 1 0 0 0 0

1 1 0 1 1 X X X

0 1 1 0 0 1 1 X

1 0 0 1 0 0 0 0

0 0 1 sreg 1 1 0

7 6 5 4 3 2 1 0

Group

Mnemonic

Operand

2 to 4

Bytes

Flags

AC CY V

CPU Halt

CPU Stop

Poll and wait

Bus Lock Prefix

No Operation

data bus

(mem)

No Operation

data bus

(mem)

No Operation

Segment override prefix

Operation

CPU
control

1 0 0 1 1 1 1 0

1 1 Y Y Y Z Z Z

mod Y Y Y mem

1 1 Y Y Y Z Z Z

mod Y Y Y mem

Notes 1. DS0:, DS1:, PS: and SS:

2. This instruction is newly added to the PD70108/70116.
3. In the PD70320, an interrupt is generated without executing these instructions.

PD70325

mod

mem

Clocks

000

BW + IX

BW + IX + disp8

BW + IX + disp16

001

BW + IY

BW + IY + disp8

BW + IY + disp16

010

BP + IX

BP + IX + disp8

BP + IX + disp16

011

BP + IY

BP + IY + disp8

BP + IY + disp16

100

IX + disp8

IX + disp16

101

IY + disp8

IY + disp16

110

Direct address

BP + disp8

BP + disp16

111

BW + disp8

BW + disp16

2.4 Number of Clocks Table

(1) Legend

The number of clocks, for memory operand, differs among addressing modes. So, use the following values for

"EA" items shown in Table 2-9 Number of Clocks.

Table 2-8. Number of Clocks for Each Memory Addressing

"T" indicates the number of wait states. Use any number of waits starting at "0" (no wait).

PD70325

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Data

MOV

reg, reg'

transfer

mem, reg

EA + 4 + T

EA + 2

EA + 6 + 2·T

EA + 2

reg, mem

EA + 6 + T

EA + 8 + 2·T

mem, imm

EA + 5 + T

EA + 5 + 2·T

EA + 5 + T

reg, imm

acc, dmem

9 + T

11 + 2·T

dmem, acc

7 + T

9 + 2·T

sreg, reg16

sreg, mem16

EA + 10 + 2·T

reg16, sreg

mem16, sreg

EA + 7 + 2·T

EA + 3

DS0, reg16,

EA + 19 + 4·T

mem32

DS1, reg16,

EA + 19 + 4·T

mem32

AH, PSW

PSW, AH

LDEA

reg16, mem16

EA + 2

TRANS

src-table

10 + T

XCH

reg, reg'

mem, reg/

EA + 10 + 2·T

EA + 8 + 2·T

EA + 14 + 2·T

EA + 10 + 2·T

reg, mem

AW, reg16/

reg16, AW

MOVSPA

MOVSPB

reg16

Repeat

REPC

prefix

REPNC

REP/REPE/

REPZ

REPNE/

REPNZ

Primitive

MOVKB

Note 1

dst-block,

20 + 2·T

16 + T

24 + 4·T

20 + 2·T

block

Note 2

src-block

16 + (16 + 2·T)·n

16 + (12 + T)·n

16 + (20 + 4·T)·n

16 + (12 + 2·T)·n

transfer

CMPKB

Note 1

dst-block,

23 + 2·T

19 + T

27 + 4·T

21 + 4·T

Note 2

src-block

16 + (21 + 2·T)·n

16 + (25 + 4·T)·n

16 + (25 + 2·T)·n

Notes 1. Not repeated

2. Repeated, n: number of transfer times (n

(2) Number of clocks

Table 2-9. Number of Clocks (1/10)

PD70325

Table 2-9. Number of Clocks (2/10)

Notes 1. Not repeated

2. Repeated, n: number of transfer times (n

3. When IBRK = 1

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Primitive

CMPM

Note 1

dst-block

17 + T

19 + 2·T

block

Note 2

src-block

16 + (15 + T)·n

16 + (17 + 2·T)·n

transfer

LDM

Note 1

src-block

12 + T

14 + 2·T

Note 2

16 + (10 + T)·n

16 + (12 + 2·T)·n

STM

Note 1

dst-block

12 + T

14 + 2·T

Note 2

16 + (8 + T)·n

16 + (6 + T)·n

16 + (10 + 2·T)·n

16 + (6 + 2·T)·n

Bit field

INS

reg8, reg8'

63 to 155 (The processing differs among bit lengths.)

manipula-

reg8, imm4

64 to 156 (The processing differs among bit lengths.)

tion

EXT

reg8, reg8'

41 to 121 (The processing differs among bit lengths.)

reg8, imm4

42 to 122 (The processing differs among bit lengths.)

I/O

acc, imm8

14 + T

16 + 2·T

Note 3

acc, DW

13 + T

15 + 2·T

OUT

imm8, acc

10 + T

10 + 2·T

Note 3

DW, acc

9 + T

9 + 2·T

Primitive

INM

dst-block, DW

19 + 2·T

17 + 2·T

21 + 4·T

17 + 4·T

I/O

Note 3

18 + (13 + 2·T)·n

18 + (11 + 2·T)·n

18 + (15 + 4·T)·n

18 + (11 + 4·T)·n

OUTM

DW, src-block

19 + 2·T

17 + 2·T

21 + 4·T

17 + 4·T

Note 3

18 + (13 + 2·T)·n

18 + (11 + 2·T)·n

18 + (15 + 4·T)·n

18 + (11 + 4·T)·n

Addition/

ADD

reg, reg'

subtraction

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

ADDC

reg, reg'

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

PD70325

Table 2-9. Number of Clocks (3/10)

Note n: 1/2 of the number of BCD digits

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Addition/

SUB

reg, reg'

subtraction

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

SUBC

reg, reg'

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + 2·T

EA + 7 + 2·T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

BCD

ADD4S

Note

22 + (27 + 3·T)·n

22 + (25 + 3·T)·n

operation

SUB4S

Note

22 + (27 + 3·T)·n

22 + (25 + 3·T)·n

CMP4S

Note

22 + (23 + 3·T)·n

ROL4

reg8

mem8

EA + 18 + 2·T

EA + 16 + 2·T

ROR4

reg8

mem8

EA + 24 + 2·T

EA + 22 + 2·T

Increment / INC

reg8

decrement

mem8

EA + 11 + 2·T

EA + 9 + 2·T

EA + 15 + 4·T

EA + 11 + 4·T

reg16

DEC

reg8

mem8

EA + 11 + 2·T

EA + 9 + 2·T

EA + 15 + 4·T

EA + 11 + 4·T

reg16

Multiplica-

MULU

reg8

tion

mem8

EA + 26 + T

reg16

mem16

EA + 34 + 2·T

PD70325

Table 2-9. Number of Clocks (4/10)

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Multiplica-

MUL

reg8

31 to 40

tion

mem8

EA + 33 + T to

EA + 42 + T

reg16

39 to 48

mem16

EA + 43 + 2·T to

EA + 52 + 2·T

reg16, (reg16',)

39 to 49

imm8

reg16, mem16,

EA + 43 + 2·T to

imm8

EA + 53 + 2·T

reg16, (reg16',)

40 to 50

imm16

reg16, mem16,

EA + 44 + 2·T to

imm16

EA + 54 + 2·T

Unsigned

DIVU

reg8

division

mem8

EA + 33 + T

reg16

mem16

EA + 43 + 2·T

Signed

DIV

reg8

46 to 56

division

mem8

EA + 48 + T to

EA + 58 + T

reg16

54 to 64

mem16

EA + 58 + 2·T to

EA + 68 + 2·T

BCD

ADJBA

adjustment ADJ4A

ADJBS

ADJ4S

Data

CVTBD

conversion CVTDB

CVTBW

CVTWL

Compare

CMP

reg, reg'

mem, reg

EA + 6 + T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 7 + T

EA + 10 + 2·T

acc, imm

PD70325

Table 2-9. Number of Clocks (5/10)

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Comple

NOT

reg

ment

mem

EA + 11 + 2·T

EA + 9 + T

EA + 15 + 4·T

EA + 11 + 2·T

operation

NEG

reg

mem

EA + 11 + 2·T

EA + 9 + T

EA + 15 + 4·T

EA + 11 + 2·T

Logical

TEST

reg, reg'

operation

mem, reg/

EA + 8 + T

EA + 10 + 2·T

reg, mem

reg, imm

mem, imm

EA + 11 + T

EA + 11 + 2·T

acc, imm

AND

reg, reg'

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + T

EA + 7 + T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

reg, reg'

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + T

EA + 7 + T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

XOR

reg, reg'

mem, reg

EA + 8 + 2·T

EA + 6 + T

EA + 12 + 4·T

EA + 8 + 2·T

reg, mem

EA + 6 + T

EA + 8 + 2·T

reg, imm

mem, imm

EA + 9 + T

EA + 7 + T

EA + 14 + 4·T

EA + 10 + 4·T

acc, imm

Bit

TEST1

reg8, CL

manipula-

mem8, CL

EA + 11 + T

tion

reg16, CL

mem16, CL

EA + 13 + 2·T

reg8, imm3

mem8, imm3

EA + 8 + T

reg16, imm4

mem16, imm4

EA + 10 + 2·T

NOT1

reg8, CL

mem8, CL

EA + 13 + 2·T

EA + 11 + T

reg16, CL

PD70325

Table 2-9. Number of Clocks (6/10)

Note n: Shift count

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Bit

NOT1

mem16, CL

EA + 17 + 4·T

EA + 13 + 2·T

manipula-

reg8, imm3

tion

mem8, imm3

EA + 10 + 2·T

EA + 8 + T

reg16, imm4

mem16, imm4

EA + 14 + 4·T

EA + 10 + 2·T

NOT1

Bit

CLR1

reg8, CL

manipula-

mem8, CL

EA + 14 + 2·T

EA + 12 + T

tion

reg16, CL

mem16, CL

EA + 18 + 4·T

EA + 14 + 2·T

reg8, imm3

mem8, imm3

EA + 11 + 2·T

EA + 9 + T

reg16, imm4

mem16, imm4

EA + 15 + 4·T

EA + 10 + 2·T

SET1

reg8, CL

mem8, CL

EA + 13 + 2·T

EA + 11 + T

reg16, CL

mem16, CL

EA + 17 + 4·T

EA + 13 + 2·T

reg8, imm3

mem8, imm3

EA + 10 + 2·T

EA + 8 + T

reg16, imm4

mem16, imm4

EA + 14 + 4·T

EA + 10 + 2·T

CLR1

DIR

SET1

DIR

Shift

SHL

reg,1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

SHR

reg, 1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

Note

PD70325

Table 2-9. Number of Clocks (7/10)

Note n: Shift count

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Shift

SHR

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

SHRA

reg,1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

Rotate

ROL

reg,1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

ROR

reg,1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

ROLC

reg,1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

RORC

reg,1

mem, 1

EA + 14 + 2·T

EA + 12 + T

EA + 18 + 4·T

EA + 14 + 2·T

Note

PD70325

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Rotate

RORC

reg, CL

11 + 2·n

mem, CL

EA + 17 + 2·T + 2·n EA + 15 + T + 2·n EA + 21 + 4·T + 2·n EA + 17 + 2·T + 2·n

reg, imm8

9 + 2·n

mem, imm8

EA + 13 + 2·T + 2·n EA + 11 + T + 2·n EA + 17 + 4·T + 2·n EA + 13 + 2·T + 2·n

Subroutine CALL

near-proc

22 + 2·T

18 + 2·T

control

regptr16

22 + 2·T

18 + 2·T

memptr16

EA + 26 + 4·T

EA + 24 + 4·T

far-proc

38 + 4·T

34 + 4·T

memptr32

EA + 36 + 8·T

EA + 24 + 8·T

RET

20 + 2·T

pop-value

20 + 2·T

29 + 4·T

pop-value

30 + 4·T

Stack

PUSH

mem16

EA + 18 + 4·T

EA + 14 + 4·T

manipula-

reg16

10 + 2·T

tion

sreg

11 + 2·T

PSW

10 + 2·T

82 + 16·T

imm8

13 + 2·T

imm16

14 + 2·T

POP

mem16

EA + 16 + 4·T

EA + 12 + 2·T

reg16

12 + 2·T

sreg

13 + 2·T

PSW

14 + 2·T

82 + 16·T

PREPARE

imm16, imm8

When imm8 = 0, 27 + 2·T

When imm8 = 1, 39 + 4·T

When imm8 = n, n > 1, 46 + 19(n 1) + 4·T

DISPOSE

12 + 2·T

Table 2-9. Number of Clocks (8/10)

Notes 1. n: Shift count

2. Depth of procedure block (lexical level)

Note 1

Note 2

PD70325

Table 2-9. Number of Clocks (9/10)

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

Branch

near-label

short-label

regptr16

memptr16

EA + 17 + 2·T

far-label

memptr32

EA + 25 + 4·T

Conditional BV

short-label

15/8

branch

Note

BNV

short-label

15/8

BC/BL

short-label

15/8

BNC/BNL

short-label

15/8

BE/BZ

short-label

15/8

BNE/BNZ

short-label

15/8

BNH

short-label

15/8

short-label

15/8

short-label

15/8

short-label

15/8

BPE

short-label

15/8

BPO

short-label

15/8

BLT

short-label

15/8

BGE

short-label

15/8

BLE

short-label

15/8

BGT

short-label

15/8

DBNZNE

short-label

17/8

DBNZE

short-label

17/8

DBNZ

short-label

17/8

BCWZ

short-label

15/8

BTCLR

sfr, imm3,

29/21

short-label

Interrupt

BRK

55 + 10·T

43 + 10·T

imm8 (

56 + 10·T

44 + 10·T

BRKV

55 + 10·T

43 + 10·T

RETI

45 + 6·T

37 + 2·T

RETRBI

FINT

CHKIND

reg16, mem32

EA + 26 + 4·T

Note In the number of clocks, the value on the left side of / indicates the number of clocks when the condition is

true, and the value on the right side indicates the number of clocks when the condition is false.

PD70325

Table 2-9. Number of Clocks (10/10)

Number of Clocks

Byte Processing

Word Processing

Group

Mnemonic

Operands

On-chip RAM

Access Enable

Access Disable

Access Enable

Access Disable

BRKCS

reg16

bank switch TSKSW

reg16

CPU

HALT

control

STOP

POLL

BUSLOCK

FPO1

fp-op

60 + 10·T

48 + 10·T

fp-op, mem

60 + 10·T

48 + 10·T

FPO2

fp-op

60 + 10·T

48 + 10·T

fp-op, mem

60 + 10·T

48 + 10·T

NOP

Segment override prefix

(DS0:, DS1:, PS: and SS:)

PD70325

3. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Test Conditions

Rating

Unit

Supply Voltage

0.5 to +7.0

0.5 to V

+ 0.5

Input Voltage

0.5 to V

+ 0.5

Output Voltage

0.5 to V

+ 0.5

Output Current Low

Each output pin

4.0

Total

Output Current High

Each output pin

2.0

Total

Operating Ambient Temperature

10 to +70

Storage Temperature

stg

65 to +150

Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with each

other, and also avoid direct connections to V

, V

or GND. However, the open drain pins or

the open collector pins can be directly connected with each other. For the external circuit

designed with the timing specifications so that any collision of the outputs from the pins subject

to high-impedance state may be prevented, direct connection can be also made.

2. Product quality may suffer if the absolute maximum ratings are exceeded for even a single

parameter, or even momentarily. In other words, the absolute maximum ratings are rated values

at which the product is on the verge of suffering physical damage, and therefore the product

must be used under conditions which ensure that the absolute maximum ratings are not

exceeded. The normal operation and reliability of the product can be only assured with the

specifications and the conditions indicated as the DC and AC characteristics.

PD70325

OSCILLATOR CHARACTERISTICS

PD70325-8 (T

= 10 to +70

C, V

= +5.0 V

10%, V

= 0 V, 0 V

+ 0.1 V)

PD70325-10 (T

= 10 to +70

C, V

= +5.0 V

5%, V

= 0 V, 0 V

+ 0.1 V)

Resonator

Recommended Circuit

Parameter

PD70325-8

PD70325-10

Unit

MIN.

MAX.

MIN.

MAX.

Ceramic or Crystal

Oscillation

MHz

Resonator

frequency (f

)

External Clock

X1 input

MHz

frequency (f

)

X1 input rise/

fall time (t

, t

)

X1 input high-/

low-level width

WXH

, t

WXL

)

Cautions 1. Mount the oscillation circuit as close to pins X1 and X2 as possible.

2. Do not route other signal lines through the area within the dotted line.

RECOMMENDED OSCILLATOR CONSTANT

(1) The following ceramic resonator and external capacity are recommended.

(2) The following crystal resonator and external capacity are recommended.

Remark

For more details on the characteristics of the resonators, please contact the manufacturer.

HCMOS
Inverter

Open

Manufacturer

Part Number

Recommended Constants

C1 [pF]

C2 [pF]

Murata Mfg. Co., Ltd.

CSA16.00MX040

CSA20.00MX040

TDK

FCR16.0M2G

Manufacturer

Part Number

Recommended Constants

C1 [pF]

C2 [pF]

Kinseki Co., Ltd.

HC-49/U(KR-100)

HC-49/U(KR-160)

HC-49/U(KR-200)

PD70325

CAPACITANCE (T

= 25

C, V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input Capacitance

= 1 MHz

Output Capacitance

Unmeasured pins returned to 0 V.

Input/output Capacitance

DC CHARACTERISTICS

PD70325-8 (T

= 10 to +70

C, V

= +5.0 V

10%)

PD70325-10 (T

= 10 to +70

C, V

= +5.0 V

5%)

AC CHARACTERISTICS

(1)

PD70325-8 (T

= 10 to +70

C, V

= +5.0 V

10%)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input Voltage Low

0.8

Input Voltage High

IH1

Except RESET, P10/NMI, X1, X2

2.2

IH2

RESET, P10/NMI, X1, X2

0.8V

Output Voltage Low

= 1.6 mA

0.45

Output Voltage High

= 0.4 mA

1.0

Input Current

EA, P10/NMI; 0

Input Leakage Current

Except EA, P10/NMI; 0

Output Leakage Current

Current

0 V

0.5

1.0

Supply Current

DD1

Operating mode

PD70325-8

120

PD70325-10

130

DD2

HALT mode

PD70325-8

PD70325-10

DD3

STOP mode

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

X1 Input Cycle Time

CYX

250

X1 Input High-/Low-Level Width

WXH

, t

WXL

X1 Input Rise/Fall Time

, t

CLKOUT Output Cycle Time

CYK

/2, T = t

CYK

125

2000

CLKOUT Output High-/Low-Level Width

WKH

, t

WKL

0.5T 15

CLKOUT Output Rise/Fall Time

, t

Input Rise/Fall Time

, t

Except RESET, NMI,

X1 and X2

IRS

, t

IFS

RESET, NMI

Output Rise/Fall Time

, t

Except CLKOUT

PD70325

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

Address Delay Time from CLKOUT

DKA

Data Input Delay Time from Address

DADR

(n + 1.5)T 70

Data Delay Time from MREQ

DMRD

(n + 1)T 60

Data Delay Time from MSTB

DMSD

(n + 0.5)T 60

MSTB

Delay Time from MREQ

DMRMS

0.5T 35

0.5T + 35

MREQ Low-Level Width

WMRL

(n + 1)T 30

(n + 1)T + 30

Address Hold Time (from MREQ

)

HMA

0.5T 30

Data Input Hold Time (from MREQ

)

HMDR

Control Signal Recovery Time

RVC

T 25

Data Output Delay Time from Address

DADW

0.5T 35

0.5T + 50

Address Setup Time (to MREQ

)

DAMR

0.5T 30

Address Setup Time (to MSTB

)

DAMS

T 30

MSTB Low-Level Width

WMSL

(n + 0.5)T 30

(n + 0.5)T + 30

Data Output Setup Time (to MSTB

)

SDM

(n + 1)T 50

Data Output Hold Time (from MSTB

)

HMDW

0.5T 30

Address Setup Time (to IOSTB

)

DAIS

0.5T 30

Data Delay Time from IOSTB

DISD

(n + 1)T 60

IOSTB Low-Level Width

WISL

(n + 1)T 30

Address Hold Time (from IOSTB

)

HISA

0.5T 30

Data Input Hold Time (from IOREQ

)

HISDR

Data Output Setup Time (to IOSTB

)

SDIS

(n + 1)T 50

Data Output Hold Time (from IOSTB

)

HISDW

0.5T 30

DMARQ Setup Time (to MREQ

)

SDADQ

Demand release mode, n

(n 1)T 50

DMARQ Hold Time (from DMAAK

)

HDADQ

Demand release mode

DMAAK Output Low-Level Width

WDMRL

Read operation

(n + 1.5)T 30

Delay Time from DMAAK

DDATC

0.5T + 50

TC Low-Level Width

WTCL

(n + 2)T 30

DMAAK Output Low-Level Width

WDMWL

Write operation

(n + 1)T 30

Address Setup Time (to REFRQ

)

DARF

0.5T 30

REFRQ Low-Level Width

WRFL

(n + 1)T 30

Address Hold Time (from REFRQ

)

HRFA

0.5T 30

RESET Low-Level Width

WRSL1

STOP mode release/

power-ON reset

WRSL2

System reset

READY Setup Time

SCRY0

T 100

(to MREQ

, IOSTB

)

SCRY

(n 1)T 100

Remark

n indicates the number of wait states. No wait is "n = 0".

PD70325

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

READY Hold Time

HCRY0

n = 2

(from MREQ

, IOSTB

)

HCRY

(n 1)T

HCRY1

(n 2)T

HLDRQ Setup Time (to CLKOUT

)

SHQK

HLDAK

Delay Time from CLKOUT

DKHA

HLDAK

Delay Time from Bus Float

CFHA

T 50

Bus Output Delay Time from HLDAK

DHAC

T 50

HLDAK

Delay Time from HLDRQ

DHQHA

3T + 160

Bus Output Delay Time from HLDRQ

DHQC

3T + 30

HLDRQ Low-Level Width

WHQL

1.5T

HLDAK Low-Level Width

WHAL

INT, DMARQ Setup Time (to CLKOUT

) t

SIQK

INT, DMARQ High-/Low-Level Width

WIQH

, t

WIQL

POLL Setup Time (to CLKOUT

)

SPLK

NMI High-/Low-Level Width

WNIH

, t

WNIL

CTS Low-Level Width

WCTL

INT Setup Time (to CLKOUT

)

SIRK

INTAK

Delay Time from CLKOUT

DKIA

INT Hold Time (from INTAK

)

HIAIQ

INTAK Low-Level Width

WIAL

2T 30

INTAK High-Level Width

WIAH

T 30

Data Delay Time from INTAK

DIAD

2T 130

Data Hold Time (from INTAK

)

HIAD

0.5T

SCK0 Cycle Time

CYTK

1000

SCK0 High-/Low-Level Width

WSTH

, t

WSTL

450

TxD Delay Time from SCK0

DTKD

210

TxD Hold Time (from SCK0

)

HTKD

CTS0 Cycle Time

CYRK

1000

CTS0 High-/Low-Level Width

WSRH

, t

WSRL

420

RxD Setup/Hold Time (to/from CTS0

)

SRDK

, t

HKRD

Remark

n indicates the number of wait states. No wait is "n = 0".

PD70325

(2)

PD70325-10 (T

= 10 to +70

C, V

= +5.0 V

5%)

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

X1 Input Cycle Time

CYX

250

X1 Input High-/Low-Level Width

WXH

, t

WXL

X1 Input Rise/Fall Time

, t

CLKOUT Output Cycle Time

CYK

/2, T = t

CYK

100

2000

CLKOUT Output High-/Low-Level Width t

WKH

, t

WKL

0.5T 12

CLKOUT Output Rise/Fall Time

, t

Input Rise/Fall Time

, t

Except RESET, NMI,

X1 and X2

IRS

, t

IFS

RESET, NMI

Output Rise/Fall Time

, t

Except CLKOUT

Address Delay Time from CLKOUT

DKA

Data Input Delay Time from Address

DADR

(n + 1.5)T 60

Data Delay Time from MREQ

DMRD

(n + 1)T 50

Data Delay Time from MSTB

DMSD

(n + 0.5)T 50

MSTB

Delay Time from MREQ

DMRMS

0.5T 20

0.5T + 30

MREQ Low-Level Width

WMRL

(n + 1)T 25

(n + 1)T + 25

Address Hold Time (from MREQ

)

HMA

0.5T 30

Data Input Hold Time (from MREQ

)

HMDR

Control Signal Recovery Time

RVC

T 25

Data Output Delay Time from Address

DADW

0.5T 30

0.5T + 50

Address Setup Time (to MREQ

)

DAMR

0.5T 30

Address Setup Time (to MSTB

)

DAMS

T 30

MSTB Low-Level Width

WMSL

(n + 0.5)T 25

(n + 0.5)T + 25

Data Output Setup Time (to MSTB

)

SDM

(n + 1)T 50

Data Output Hold Time (from MSTB

)

HMDW

0.5T 30

Address Setup Time (to IOSTB

)

DAIS

0.5T 30

Data Delay Time from IOSTB

DISD

(n + 1)T 50

IOSTB Low-Level Width

WISL

(n + 1)T 25

Address Hold Time (from IOSTB

)

HISA

0.5T 30

Data Input Hold Time (from IOREQ

)

HISDR

Data Output Setup Time (to IOSTB

)

SDIS

(n + 1)T 50

Data Output Hold Time (from IOSTB

)

HISDW

0.5T 30

DMARQ Setup Time (to MREQ

)

SDADQ

Demand release mode, n

(n 1)T 50

DMARQ Hold Time (from DMAAK

)

HDADQ

Demand release mode

DMAAK Output Low-Level Width

WDMRL

Read operation

(n + 1.5)T 25

Delay Time from DMAAK

DDATC

0.5T + 35

TC Low-Level Width

WTCL

(n + 2)T 25

DMAAK Output Low-Level Width

WDMWL

Write operation

(n + 1)T 25

Address Setup Time (to REFRQ

)

DARF

0.5T 30

REFRQ Low-Level Width

WRFL

(n + 1)T 25

Address Hold Time (from REFRQ

)

HRFA

0.5T 30

Remark

n indicates the number of wait states. No wait is "n = 0".

PD70325

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

RESET Low-Level Width

WRSL1

STOP mode release/

power-ON reset

WRSL2

System reset

READY Setup Time

SCRY0

T 80

(to MREQ

, IOSTB

)

SCRY

(n 1)T 80

READY Hold Time

HCRY0

n = 2

(from MREQ

, IOSTB

)

HCRY

(n 1)T

HCRY1

(n 2)T

HLDRQ Setup Time (to CLKOUT

)

SHQK

HLDAK

Delay Time from CLKOUT

DKHA

HLDAK

Delay Time from Bus Float

CFHA

T 35

Bus Output Delay Time from HLDAK

DHAC

T 35

HLDAK

Delay Time from HLDRQ

DHQHA

3T + 160

Bus Output Delay Time from HLDRQ

DHQC

3T + 30

HLDRQ Low-Level Width

WHQL

1.5T

HLDAK Low-Level Width

WHAL

INT, DMARQ Setup Time (to CLKOUT

) t

SIQK

INT, DMARQ High-/Low-Level Width

WIQH

, t

WIQL

POLL Setup Time (to CLKOUT

)

SPLK

NMI High-/Low-Level Width

WNIH

, t

WNIL

CTS Low-Level Width

WCTL

INT Setup Time (to CLKOUT

)

SIRK

INTAK

Delay Time from CLKOUT

DKIA

INT Hold Time (from INTAK

)

HIAIQ

INTAK Low-Level Width

WIAL

2T 25

INTAK High-Level Width

WIAH

T 25

Data Delay Time from INTAK

DIAD

2T 100

Data Hold Time (from INTAK

)

HIAD

0.5T

SCK0 Cycle Time

CYTK

1000

SCK0 High-/Low-Level Width

WSTH

, t

WSTL

450

TxD Delay Time from SCK0

DTKD

210

TxD Hold Time (from SCK0

)

HTKD

CTS0 Cycle Time

CYRK

1000

CTS0 High-/Low-Level Width

WSRH

, t

WSRL

420

RxD Setup/Hold Time (to/from CTS0

)

SRDK

, t

HKRD

Remark

n indicates the number of wait states. No wait is "n = 0".

PD70325

COMPARATOR CHARACTERISTICS

PD70325-8 (T

= 10 to +70

C, V

= +5.0 V

10%)

PD70325-10 (T

= 10 to +70

C, V

= +5.0 V

5%)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Comparator Accuracy

ACOMP

100

Threshold Voltage

+ 0.1

Compare Time

COMP

CYK

PT Input Voltage

IPT

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS

= 10 to +70

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

Data Hold Supply Voltage

DDDR

2.5

5.5

Rise/Fall Time

RVD

, t

FVD

200

PD70325

DATA HOLDING TIMING

AC TEST INPUT WAVEFORM (Except RESET, NMI, X1 and X2)

AC TEST INPUT WAVEFORM (RESET, NMI, X1 and X2)

AC TEST OUTPUT TEST POINTS

Output load condition: 100 pF

LOAD CONDITION

Caution When the load capacity exceeds 100 pF depending on the circuit configuration, make the load

capacity of this device less than 100 pF by inserting a buffer, etc.

90%

10%

DDDR

FVD

RVD

2.2 V

0.8 V

Test Points

2.2 V

0.8 V

IFS

Test Points

0.8 V

IRS

2.2 V

0.8 V

Test Points

2.2 V

0.8 V

DUT

= 100 pF

PD70325

READY TIMING

When 2 wait states are inserted:

When (n 2) extra wait states are inserted [n

3]:

Notes 1. In case of memory cycle

2. In case of I/O cycle

Caution The wait state insertion by the external READY signal is necessary to make the value of wait control

register (WTC) "11" (2 waits + insertion state by READY pin).

HCRY0

SCRY0

TAW

MREQ

Note 1

IOSTB

Note 2

READY

TAW

HCRY1

SCRY

HCRY

(n 2)

READY

SCRY0

MREQ

Note 1

IOSTB

Note 2

PD70325

CLOCK SYNCHRONIZATION TIMING

The V25 Family is designed to create access signals to memory and I/O, based on the MREQ signal and IOSTB

signal. When V25 Family products are connected with memory and I/O, design is possible even if there are no AC

characteristics based on the clock. The clock synchronization timing shown below is for executing accurate READY

input control using the system clock.

(1)

PD70325-8 (T

= 10 to +70

C, V

= +5.0 V

10%)

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

Data Delay Time from CLKOUT

DKD

115

Data Input Setup Time

SDK

Data Input Hold Time

HKD

MREQ Delay Time

DKMR

IOSTB Delay Time

DKIS

READY Setup Time

SRYK

READY Hold Time

HKRY

(2)

PD70325-10 (T

= 10 to +70

C, V

= +5.0 V

5%)

Parameter

Symbol

Test Conditions

MIN.

MAX.

Unit

Data Delay Time from CLKOUT

DKD

110

Data Input Setup Time

SDK

Data Input Hold Time

HKD

MREQ Delay Time

DKMR

IOSTB Delay Time

DKIS

READY Setup Time

SRYK

READY Hold Time

HKRY

PD70325

4. PACKAGE DRAWINGS

94 PIN PLASTIC QFP ( 20)

ITEM

MILLIMETERS

INCHES

1.6

0.8

0.15

0.063

0.031

0.006

S94GJ-80-5BG-3

NOTE

Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.

20.0

0.2

0.787

0.15

0.006

0.1

0.004

+0.004

0.003

+0.009

0.008

23.2

0.4

0.913

0.35

0.10

0.014+0.004

0.005

0.8

0.2

0.031+0.009

0.008

0.10

0.004

3.7

0.146

4.0 MAX.

0.158 MAX.

+0.10

0.05

20.0

0.2

0.787+0.009

0.008

+0.017

0.016

0.8 (T.P.)

0.031 (T.P.)

°±

23.2

0.4

0.913+0.017

0.016

1.6

0.8

0.063

0.031

1.6

0.2

0.063

0.008

detail of lead end

PD70325

84 PIN PLASTIC QFJ ( 1150 mil)

P84L-50A3-2

ITEM

MILLIMETERS

INCHES

30.2

0.2

29.28

0.6

4.4

0.2

2.8

0.2

29.28

1.189

0.008

0.076

0.024

0.110

0.035 MIN.

1.153

NOTE

0.12

0.40

0.10

3.4

0.9 MIN.

0.005

0.016

+0.004

0.005

Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

0.134

0.173

1.153

1.27 (T.P.)

0.050 (T.P.)

28.20

0.20

1.110

1.189

0.008

30.2

0.2

1.94

0.15

0.006

R 0.8

R 0.031

+0.009

0.008

0.20

0.008

+0.10

0.05

+0.004

0.002

+0.009

0.008

+0.007

0.006

+0.009

0.008

PD70325

5. RECOMMENDED SOLDERING CONDITIONS

The following conditions must be met when soldering this product.

For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"

(C10535E)

Please consult with our sales office when using other soldering process or under different soldering conditions.

Table 5-1. Surface Mount Type Soldering Conditions

(1)

PD70325GJ-8-5BG

: 94-pin plastic QFP (20

20 mm)

PD70325GJ-10-5BG : 94-pin plastic QFP (20

20 mm)

Soldering Process

Soldering Conditions

Symbol

Infrared ray reflow

Package peak temperature: 235

C, Reflow time: 30 seconds or less (at 210

IR35-367-3

or higher), Number of reflow processes: 3 or less

Exposure limit

Note

: 7 days (36 hours pre-baking is required at 125

C afterwards)

VPS

Package peak temperature: 215

C, Reflow time: 40 seconds or less (at 200

VP15-367-3

or higher), Number of reflow processes: 3 or less

Exposure limit

Note

: 7 days (36 hours pre-baking is required at 125

C afterwards)

Wave soldering

Solder temperature: 260

C or below, Flow time: 10 seconds or less,

WS60-367-1

Number of flow processes: 1

Exposure limit

Note

: 7 days (36 hours pre-baking is required at 125

C afterwards)

Pre-heating temperature: 120

C max. (package surface temperature)

Partial heating

Pin temperature: 300

C or below,

method

Flow time: 3 seconds or less (per side of device)

(2)

PD70325L-8 : 84-pin plastic QFJ (1150

1150 mil)

PD70325L-10 : 84-pin plastic QFJ (1150

1150 mil)

Soldering Process

Soldering Conditions

Symbol

VPS

Package peak temperature: 215

C, Reflow time: 40 seconds or less (at 200

VP15-162-1

or higher), Number of reflow processes: 1

Exposure limit

Note

: 2 days (16 hours pre-baking is required at 125

C afterwards)

Partial heating

Pin temperature: 300

C or below,

method

Flow time: 3 seconds or less (per side of device)

Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25

C and relative

humidity at 65% or less.

Caution

Use of more than one soldering process should be avoided (except for partial heating method).

PD70325

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

PD70325

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J97. 8

PD70325

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

Related documents V25+, V35+ User's Manual -- Hardware IEU-706 (Japanese version)

V25, V35 Family User's Manual -- Instructions U12120J (Japanese version)

Reference document Electrical Characteristics for Microcomputer IEI-601 (Japanese version)

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