1998

DATA SHEET

The mark

shows major revised points.

MOS INTEGRATED CIRCUIT

PD70F3003A, 70F3025A

V853

32-/16-BIT SINGLE-CHIP MICROCONTROLLER

Document No. U13189EJ3V0DS00 (3rd edition)
Date Published May 2000 N CP(K)
Printed in Japan

DESCRIPTION

The

PD70F3003A and

PD70F3025A have a flash memory instead of the internal mask ROM of the

PD703003A/

703004A and

PD703025A, respectively. This model is useful for small-scale production of a variety of application

sets or early start of production since the program can be written and erased by the user even with the

PD70F3003

mounted on the board.

Functions in detail are described in the following user's manuals. Be sure to read these manuals when

you design your systems.

V853 User's Manual-Hardware

: U10913E

V850 Family

User's Manual-Architecture : U10243E

FEATURES

· Compatible with

PD703003A, 703004A and 703025A

· Can be replaced with mask ROM model for mass production of application set

PD70F3003A

PD703003A, 703004A

PD70F3025A

PD703025A

· Internal memory

Flash memory: 128K bytes (

PD70F3003A)

256K bytes (

PD70F3025A)

Remark For differences among the products, refer to 1. DIFFERENCES AMONG PRODUCT.

ORDERING INFORMATION

Part Number

Package

Maximum Operating Frequency (MHz)

PD70F3003AGC-25-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

PD70F3003AGC-33-8EU

100-pin plastic LQFP (fine pitch) (14

14 mm)

PD70F3025AGC-25-8EU

Note

100-pin plastic LQFP (fine pitch) (14

14 mm)

PD70F3025AGC-33-8EU

Note

100-pin plastic LQFP (fine pitch) (14

14 mm)

Note Under development

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

PIN CONFIGURATION (Top View)

· 100-Pin Plastic LQFP (fine pitch) (14

14 mm)

PD70F3003AGC-25-8EU

PD70F3025AGC-25-8EU

PD70F3003AGC-33-8EU

PD70F3025AGC-33-8EU

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

100

P31/TO131

P32/TCLR13

P33/TI13

P34/INTP130

P35/INTP131/SO3

P36/INTP132/SI3

P37/INTP133/SCK3

P63/A19
P62/A18
P61/A17
P60/A16

P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10

P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4

P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
ANO1
AV

REF2

REF3

P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141

P30/TO130

P27/SCK1

P26/RXD1/SI1

P25/TXD1/SO1

P24/SCK0

P23/RXD0/SI0

P22/TXD0/SO0

P21/PWM1

P20/PWM0

NMI

P17/INTP123/SCK2

P16/INTP122/SI2

P15/INTP121/SO2

P14/INTP120

P13/TI12

P12/TCLR12

P11/TO121

P10/TO120

REF1

P77/ANI7

P76/ANI6

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P90/LBEN

P91/UBEN

P92/R/W

P93/DSTB

P94/ASTB

P95/HLDAK

P96/HLDRO

WAIT

MODE

RESET

/CKSEL

CLKOUT

P110/TO140

Caution Connect V

pin to V

pin except the case that

PD70F3003A or 70F3025A is used in flash

memory programming mode.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

P40-P47

: Port4

P50-P57

: Port5

P60-P63

: Port6

P70-P77

: Port7

P90-P96

: Port9

P110-P117

: Port11

PWM0, PWM1

: Pulse Width Modulation

RESET

: Reset

R/W

: Read/Write Status

RXD0, PXD1

: Receive Data

SCK0-SCK3

: Serial Clock

SI0-SI3

: Serial Input

SO0-SO3

: Serial Output

TO110, TO111,

: Timer Output

TO120, TO121,

TO130, TO131,

TO140, TO141

TCLR11-TCLR14

: Timer Clear

TI11-TI14

: Timer Input

TXD0, TXD1

: Transmit Data

UBEN

: Upper Byte Enable

WAIT

: Wait

X1, X2

: Crystal

: Power Supply

: Programming Power Supply

: Ground

PIN NAMES

A16-A19

: Address Bus

AD0-AD15

: Address/Data Bus

ADTRG

: AD Trigger Input

ANI0-ANI7

: Analog Input

ANO0, ANO1

: Analog Output

ASTB

: Address Strobe

: Analog V

REF1

-AV

REF3

: Analog Reference Voltage

: Analog V

: Power Supply for Clock Generator

: Ground for Clock Generator

CKSEL

: Clock Select

CLKOUT

: Clock Output

DSTB

: Data Strobe

HLDAK

: Hold Acknowledge

HLDRQ

: Hold Request

INTP110-INTP113,

: Interrupt Request from Peripherals

INTP120-INTP123,

INTP130-INTP133,

INTP140-INTP143

LBEN

: Lower Byte Enable

MODE

: Mode

NMI

: Non-maskable Interrupt Request

P00-P07

: Port0

P10-P17

: Port1

P20-P27

: Port2

P30-P37

: Port3

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

INTERNAL BLOCK DIAGRAM

INTP110-INTP113
INTP120-INTP123
INTP130-INTP133
INTP140-INTP143

NMI

TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141

TCLR11-TCLR14

TI11-TI14

SO0/TXD0

INTC

RPU

CSI2

SIO

BRG2

CSI3

Flash memory

Note 1

RAM

Note 2

CPU

32-bit
barrel shifter

System
register

General-
purpose
register
32 bits

ALU

Multiplier

Ports

P110-P117

P90-P96

P70-P77

P60-P63

P50-P57

P40-P47

P30-P37

P20-P27

P10-P17

P00-P07

BCU

Instruction
queue

ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16-A19
AD0-AD15

HLDRQ
HLDAK

CKSEL
CLKOUT
X1
X2

MODE

RESET

UART0/CSI0

BRG0

UART1/CSI1

BRG1

D/A
Converter

A/D
Converter

ANI0-ANI7

REF1

ADTRG

ANO0, ANO1

REF2

, AV

REF3

SI0/RXD0

SCK0

SO1/TXD1

SI1/RXD1

SCK1

SO2

SI2

SCK2

SO3

SI3

SCK3

PWM

PWM0, PWM1

Notes 1.

PD70F3003A : 128K bytes

PD70F3025A: 256K bytes

PD70F3003A: 4K bytes

PD70F3025A: 8K bytes

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

CONTENTS

DIFFERENCES AMONG PRODUCTS ······························································································

PIN FUNCTIONS ································································································································

2.1

Port Pins ·····················································································································································

2.2

Pins Other Than Port Pins ························································································································

2.3

I/O Circuits of Pins and Recommended Connections of Unused Pins ················································ 11

3. ELECTRICAL SPECIFICATIONS ······································································································· 14

3.1

Normal Operation Mode ···························································································································· 14

3.2

Flash Memory Programming Mode ·········································································································· 35

PACKAGE DRAWING ······················································································································· 37

RECOMMENDED SOLDERING CONDITIONS ················································································· 38

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

1. DIFFERENCES AMONG PRODUCTS

Parameter

PD703003

PD703003A

PD703004A

PD703025A

PD70F3003

PD70F3003A

PD70F3025A

Internal ROM

Mask ROM

Flash memory

128K bytes

96K bytes 256K bytes 128K bytes

256K bytes

Internal RAM

4K bytes

8K bytes

4K bytes

8K bytes

Operation Normal

Single chip

Provided

mode

operation

mode

ROM-less mode

Provided

None

Provided

None

Flash memory programming mode

None

Provided

None

Provided

CKC register value at reset

00H

MODE = 0: 03H

00H

MODE = 0: 03H

MODE = 1: 00H

Electrical specifications

Current consumption, etc. differs. (Refer to each product data sheets.)

Others

Noise immunity and noise radiation differ because circuit scale and mask

layout differ.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

2. PIN FUNCTIONS

2.1 Port Pins

(1/2)

Pin Name

I/O

Function

Shared with:

P00

I/O

Port 0

TO110

P01

8-bit I/O port.

TO111

P02

Can be set in input or output mode in 1-bit units.

TCLR11

P03

TI11

P04

INTP110

P05

INTP111

P06

INTP112

P07

INTP113/ADTRG

P10

I/O

Port 1

TO120

P11

8-bit I/O port.

TO121

P12

Can be set in input or output mode in 1-bit units.

TCLR12

P13

TI12

P14

INTP120

P15

INTP121/SO2

P16

INTP122/SI2

P17

INTP123/SCK2

P20

I/O

Port 2

PWM0

P21

8-bit I/O port.

PWM1

P22

Can be set in input or output mode in 1-bit units.

TXD0/SO0

P23

RXD0/SI0

P24

SCK0

P25

TXD1/SO1

P26

RXD1/SI1

P27

SCK1

P30

I/O

Port 3

TO130

P31

8-bit I/O port.

TO131

P32

Can be set in input or output mode in 1-bit units.

TCLR13

P33

TI13

P34

INTP130

P35

INTP131/SO3

P36

INTP132/SI3

P37

INTP133/SCK3

P40-P47

I/O

Port 4

AD0-AD7

8-bit I/O port.

Can be set in input or output mode in 1-bit units.

P50-P57

I/O

Port 5

AD8-AD15

8-bit I/O port.

Can be set in input or output mode in 1-bit units.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

2.2 Pins Other Than Port Pins

(1/2)

Pin Name

I/O

Function

Shared with:

TO110

Output

Pulse signal output of timer 11-14

P00

TO111

P01

TO120

P10

TO121

P11

TO130

P30

TO131

P31

TO140

P110

TO141

P111

TCLR11

Input

External clear signal of timer 11-14

P02

TCLR12

P12

TCLR13

P32

TCLR14

P112

TI11

Input

External count clock of timer 11-14

P03

TI12

P13

TI13

P33

TI14

P113

INTP110

Input

External maskable interrupt reuest input and external capture

P04

INTP111

trigger input of timer 11

P05

INTP112

P06

INTP113

P07/ADTRG

INTP120

Input

External maskable interrupt reuest input and external capture

P14

INTP121

trigger input of timer 12

P15/SO2

INTP122

P16/S12

INTP123

P17/SCK2

INTP130

Input

External maskable interrupt reuest input and external capture

P34

INTP131

trigger input of timer 13

P35/SO3

INTP132

P36/SI3

INTP133

P37/SCK3

INTP140

Input

External maskable interrupt reuest input and external capture

P114

INTP141

trigger input of timer 14

P115

INTP142

P116

INTP143

P117

SO0

Output

Serial transmit data output of CSI0-CSI3 (3 wire)

P22/TXD0

SO1

P25/TXD1

SO2

P15/INTP121

SO3

P35/INTP131

SI0

Input

Serial receive data output of CSI0-CSI3 (3 wire)

P23/RXD0

SI1

P26/RXD1

SI2

P16/INTP122

SI3

P36/INTP132

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(2/2)

Pin Name

I/O

Function

Shared with:

SCK0

I/O

Serial clock I/O of CSI0-CSI3 (3 wire)

P24

SCK1

P27

SCK2

P17/INTP123

SCK3

P37/INTP133

TXD0

Output

Serial transmit data output of UART0-UART1

P22/SO0

TXD1

P25/SO1

RXD0

Input

Serial receive data input of UART0-UART1

P23/SI0

RXD1

P26/SI1

PWM0

Output

Pulse signal output of PWM

P20

PWM1

P21

AD0-AD7

I/O

16-bit multiplexed address/data bus when external memory is connected

P40-P47

AD8-AD15

P50-P57

A16-A19

Output

High-order address bus when external memory is connected

P60-P63

LBEN

Output

Low-order byte enable signal output of external data bus

P90

UBEN

High-order byte enable signal output of external data bus

P91

R/W

Output

External read/write status output

P92

DSTB

External data strobe signal output

P93

ASTB

External address strobe signal output

P94

HLDAK

Output

Bus hold acknowledge output

P95

HLDRQ

Input

Bus hold request input

P96

ANI0-ANI7

Input

Analog input to A/D converter

P70-P77

ANO0, ANO1

Output

Analog output of D/A converter

NMI

Input

Non-maskable interrupt request input

CLKOUT

Output

System clock output

CKSEL

Input

Input specifying operation mode of clock generator

WAIT

Input

Control signal input inserting wait state in bus cycle

MODE

Input

Operation mode specification

RESET

Input

System reset input

Input

System clock resonator connection. Input external clock to X1 to

supply external clock.

ADTRG

Input

A/D converter external trigger input

P07/INTP113

REF1

Input

Reference voltage input for A/D converter

REF2

Input

Reference voltage input for D/A converter

REF3

Positive power supply for A/D converter

Ground potential for A/D converter

Positive power supply for internal clock generator

CKSEL

Ground potential for internal clock generator

Positive power supply

Ground potential

High voltage application pin when program is written/verified

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

2.3 I/O Circuits of Pins and Recommended Connections of Unused Pins

Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure

2-1 shows a partially simplified diagram of each circuit.

When connecting a pin to V

or V

via resistor, use of a resistor of 1 to 10 k

is recommended.

Table 2-1. I/O Circuit Types of Each Pin and Recommended Connections of Unused Pins (1/2)

I/O Circuit Type

Recommended Connections

P00/TO110, P01/TO111

Input

: Individually connect to V

or V

via resistor.

P02/TCLR11, P03/TI11,

Output : Leave unconnected.

P04/INTP110-P07/INTP113/ADTRG

P10-TO120, P11/TO121

P12/TCLR12, P13/TI12

P14/INTP120

P15/INTP121/SO2

P16/INTP122/SI2

P17/INTP123/SCK2

P20/PWM0, P21/PWM1

P22/TXD0/SO0

P23/RXD0/SI0, P24/SCK0

P25/TXD1/SO1

P26/RXD1/SI1, P27/SCK1

P30/TO130, P31/TO131

P32/TCLR13, P33/TI13

P34/INTP130

P35/INTP131/SO3

10-A

P36/INTP132/SI3

P37/INTP133/SCK3

P40/AD0-P47/AD7

P50/AD8-P57/AD15

P60/A16-P63/A19

P70/ANI0-P77/ANI7

Directly connect to V

P90/LBEN

Input: Individually connect to V

or V

via resistor.

P91/UBEN

Output: Leave unconnected.

P92/R/W

P93/DSTB

P94/ASTB

P95/HLDAK

P96/HLDRQ

P110/TO140, P111/TO141

P112/TCLR14, P113/TI14

P114/INTP140-P117/INTP143

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

3. ELECTRICAL SPECIFICATIONS

3.1 Normal Operation Mode

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Condition

Ratings

Unit

Supply voltage

0.5 to +7.0

0.5 to V

+ 0.3

0.5 to +0.5

0.5 to V

+ 0.3

0.5 to +0.5

Input voltage

Note, V

= 5.0 V

10%

0.5 to V

+ 0.3

pin in flash memory programming mode,

0.5 to +11.0

= 5.0 V

10%

Clock input voltage

X1 pin, V

= 5.0 V

10%

0.5 to V

+ 1.0

Output current, low

1 pin

4.0

Total of all pins

100

Output current, high

1 pin

4.0

Total of all pins

100

Output voltage

= 5.0 V

10%

0.5 to V

+ 0.3

Analog input voltage

IAN

P70/ANI0-P77/ANI7

> V

0.5 to V

+ 0.3

0.5 to AV

+ 0.3

Analog reference input voltage

REF

REF1

-AV

REF3

> V

0.5 to V

+ 0.3

0.5 to AV

+ 0.3

Operating ambient temperature

40 to +85

Storage temperature

stg

65 to +125

Note

Except X1, P70/AN0-P77/AN7, AV

REF1

-AV

REF3

Cautions 1. Do not directly connect the output (or I/O) pins of two or more IC products, and do not directly

connect them to V

, V

, or GND pin. Open-drain pins and open-collector pins may be directly

connected to one another however. Moreover, an external circuit that is designed to prevent

contention of output can be connected to pins that go into a high-impedance state.

2. Should the absolute maximum rating of even one of the above parameters be exceeded even

momentarily, the quality of the program may be degraded. The absolute maximum ratings

are, therefore, the values exceeding which the product may be physically damaged. Use the

product so that these values are never exceeded.

The normal operating ranges of ratings and conditions in which the quality of the product

is guaranteed are specified in the following DC Characteristics and AC Characteristics.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input capacitance

fc = 1 MHz

I/O capacitance

Pins other than tested pin: 0 V

Output capacitance

Operating Conditions

Operation Mode

Internal Operating Clock Frequency (

)

Operating Temperature (T

)

Supply Voltage (V

)

Direct mode,

2 to 33 MHz

Note 1

40 to +85

5.0 V

10%

PLL mode

5 to 33 MHz

Note 2

40 to +85

5.0 V

10%

Notes 1. When A/D converter not used.

2. When A/D converter used.

DC Characteristics (T

= 40 to +85

C, V

= 5.0 V

10%, V

= 0 V)

(1/2)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input voltage, high

Except X1 and Note 1

2.2

+ 0.3

Note 1

0.8 V

+ 0.3

Input voltage, low

Except X1 and Note 1

0.5

+0.8

Note 1

0.5

0.2 V

Clock input voltage, high

0.8 V

+ 0.5

Clock input voltage, low

0.5

0.6

Schmitt trigger input threshold voltage

Note 1, rising

3.0

Note 1, falling

2.0

Schmitt trigger input hysteresis width

Note 1

0.5

Output voltage, high

= 2.5 mA

0.7 V

= 100

0.4

Output voltage, low

= 2.5 mA

0.45

Input leakage current, high

LIH

= V

Input leakage current, low

LIL

= 0 V

Output leakage current, high

LOH

= V

Output leakage current, low

LOL

= 0 V

Software pull-up resistor

P35/INTP131/SO3,

P36/INTP132/SI3,

P37/INTP133/SCK3

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(2/2)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Supply

PD70F3003A Operating

DD1

Direct mode

Note 2

2.2

+ 7.5

2.5

+ 22

current

PLL mode

Note 2

2.3

+ 9.5

2.6

+ 25

In HALT mode

DD2

Direct mode

Note 2

1.2

+ 7.5

1.3

+ 15

PLL mode

Note 2

1.3

+ 9.5

1.4

+ 17

In IDLE mode

DD3

Direct mode

Note 2

+ 300

+ 500

PLL mode

Note 2

0.1

+ 2

0.2

+ 3

In STOP mode

DD4

CESEL = 0, Note 3

CESEL = 0, Note 4

200

CESEL = 1, Note 3

200

CESEL = 1, Note 4

500

PD70F3025A Operating

DD1

Direct mode

Note 2

2.5

+ 8

2.8

+ 22.5

PLL mode

Note 2

2.6

+ 10 2.9

+ 25.5

In HALT mode

DD2

Direct mode

Note 2

1.3

+ 7.5

1.4

+ 15

PLL mode

Note 2

1.3

+ 12.5 1.4

+ 20

In IDLE mode

DD3

Direct mode

Note 2

+ 300

+ 500

PLL mode

Note 2

0.1

+ 2

0.2

+ 3

In STOP mode

DD4

CESEL = 0, Note 3

CESEL = 0, Note 4

200

CESEL = 1, Note 3

300

CESEL = 1, Note 4

500

Notes 1. P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,

P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/

SCK3, P112/TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE

2. When A/D converter used

= 5 to 33 MHz

When A/D converter not used :

= 2 to 33 MHz

3. 40

+50

4. 50

C < T

Remarks 1. TYP. value is a value for your reference at T

= 25

C and V

= 5.0 V. The supply current does

not include AV

REF1

-AV

REF3

and the current running through the software pull-up resistor.

: Internal system clock frequency

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

Data Retention Characteristics (T

= 40 to +85

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Data hold voltage

DDDR

STOP mode

1.5

5.5

Data hold current

DDDR

= V

DDDR

+50

0.2 V

DDDR

C < T

0.2 V

DDDR

200

Supply voltage rise time

RVD

200

Supply voltage fall time

FVD

200

Supply voltage hold time

HVD

(vs. STOP mode setting)

STOP mode release signal input time

DREL

Data hold input voltage, high

IHDR

Note

0.9 V

DDDR

Data hold input voltage, low

ILDR

Note

0.1 V

DDDR

Note

P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/

SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/

TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/

TCLR14, P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1

Remark

TYP. value is a value for your reference at T

= 25

C and V

= 5.0 V.

HVD

FVD

RVD

DREL

DDDR

RESET (input)

IHDR

NMI (input)

(Release by falling edge)

IHDR

ILDR

NMI (input)

(Release by rising edge)

STOP mode is set (at fifth clock after PSC register has been set).

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

AC Characteristics (T

= 40 to +85

C, V

= 5.0 V

10%, V

= 0 V)

AC test input wave

(a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/

SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/

TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112,TCLR14,

P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE, X1

(b) Other than (a)

AC test output test point

Load condition

Test point

0.8 V

0.2 V

0.8 V

0.2 V

0 V

Test point

2.2 V

0.8 V

2.2 V

0.8 V

2.4 V

0.4 V

Test point

2.2 V

0.8 V

2.2 V

0.8 V

= 50 pF

DUT

(tested device)

Caution If the load capacitance exceeds 50 pF due to the circuit configuration,

decrease the load capacitance of this device to less then 50 pF by using a buffer.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(1) Clock timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

X1 input cycle

<1>

CYX

Direct mode

Note 1

PLL mode

200

Note 1

151

Note 1

(PLL lock status)

X1 input width, high

<2>

WXH

Direct mode

PLL mode

X1 input width, low

<3>

WXL

Direct mode

PLL mode

X1 input rise time

<4>

Direct mode

PLL mode

X1 input fall time

<5>

Direct mode

PLL mode

CPU operating frequency

Note 2

MHz

CLKOUT output cycle

<6>

CYK

Note 3

CLKOUT width, high

<7>

WKH

0.5 T 5

CLKOUT width, low

<8>

WKL

0.5 T 5

CLKOUT rise time

<9>

CLKOUT fall time

<10>

CLKOUT delay time

<11>

DXK

Direct mode

Notes 1. When A/D converter used: 100 ns

When A/D converter not used: 250 ns

2. When A/D converter used: 5 MHz

When A/D converter not used: 2 MHz

3. When A/D converter used: 200 ns

When A/D converter not used: 500 ns

Remark

T = t

CYK

<1>

<2>

<4>

<11>

<5>

<6>

<7>

<9>

<10>

<8>

<3>

X1 (input)

CLKOUT (output)

<11>

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(2) Input wave

(a) P02/TCLR11, P03/TI11, P04/INTP110-P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/

SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/

TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14,

P113/TI14, P114/INTP140-P117/INTP143, RESET, NMI, MODE

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

Input rise time

<12>

IR2

Input fall time

<13>

IF2

(b) Other than (a)

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

Input rise time

<14>

IR1

Input fall time

<15>

IF1

0.8 V

0.2 V

0.8 V

0.2 V

0 V

Input signal

< 13 >

< 12 >

2.2 V

0.8 V

2.2 V

0.8 V

2.4 V

0.4 V

Input signal

< 15 >

< 14 >

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(3) Output wave (other than CLKOUT)

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

Output rise time

<16>

Output fall time

<17>

(4) Reset timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

RESET width, high

<18>

WRSH

500

RESET width, low

<19>

WRSL

On power appli-

500 + T

OST

500 + T

OST

cation, or on

releasing STOP

mode

Except on power

500

application, or

except on releas-

ing STOP mode

Remark

OST

: oscillation stabilization time

0.8 V

2.2 V

Output signal

< 16 >

< 17 >

2.2 V

0.8 V

RESET (input)

< 18 >

< 19 >

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(5) Read timing (1/2)

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

CLKOUT

address delay time

<20>

DKA

CLKOUT

R/W, UBEN, LBEN delay time <78>

DKA2

+13

CLKOUT

address float delay time

<21>

FKA

CLKOUT

ASTB delay time

<22>

DKST

CLKOUT

DSTB delay time

<23>

DKD

Data input setup time (vs. CLKOUT

)

<24>

SIDK

Data input hold time (vs. CLKOUT

)

<25>

HKID

WAIT setup time (vs. CLKOUT

)

<26>

SWTK

WAIT hold time (vs. CLKOUT

)

<27>

HKWT

Address hold time (vs. CLKOUT

) <28>

HKA

Address setup time (vs. ASTB

)

<29>

SAST

+70

C 0.5 T 10

0.5 T 10

0.5 T 12

Address hold time (vs. ASTB

)

<30>

HSTA

0.5 T 10

DSTB

address float delay time <31>

FDA

Data input setup time (vs. address)

<32>

SAID

+70

(2 + n) T 22

(2 + n) T 25

Data input setup time (vs. DSTB

)

<33>

SDID

+70

(1 + n) T 20

(1 + n) T 24

ASTB

DSTB

delay time

<34>

DSTD

0.5 T 10

Data input hold time (vs. DSTB

)

<35>

HDID

DSTB

address output delay time

<36>

DDA

(1 + i) T

DSTB

ASTB

delay time

<37>

DDSTH

0.5 T 10

DSTB

ASTB

delay time

<38>

DDSTL

(1.5 + i) T 10

DSTB width, low

<39>

WDL

+70

C (1 + n) T 10

(1 + n) T 10

(1 + n) T 13

ASTB width, high

<40>

WSTH

T 10

WAIT setup time (vs. address)

<41>

SAWT1

1, 40

+70

1.5 T 20

1, 70

1.5 T 24

<42>

SAWT2

1, 40

+70

(1.5 + n) T 20

1, 70

(1.5 + n) T 24

WAIT hold time (vs. address)

<43>

HAWT1

(0.5 + n) T

<44>

HAWT2

(1.5 + n) T

WAIT setup time (vs. ASTB

)

<45>

SSTWT1

1, 40

+70

T 18

1, 70

T 20

<46>

SSTWT2

(1 + n) T 15

WAIT hold time (vs. ASTB

)

<47>

HSTWT1

<48>

HSTWT2

(1 + n) T

Remarks 1. T = t

CYK

2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when

the programmable wait state is inserted.

3. i indicates the number of idle states (0 or 1) t be inserted in the read cycle.

4. Be sure to observe at least one of data input hold times t

HKID

(<25>) and t

HDID

(<35>).

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(6) Write timing (1/2)

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

CLKOUT

address delay time

<20>

DKA

CLKOUT

R/W, UBEN, LBEN delay time <78>

DKA2

+13

CLKOUT

ASTB delay time

<22>

DKST

CLKOUT

DSTB delay time

<23>

DKD

WAIT setup time (vs. CLKOUT

)

<26>

SWTK

WAIT hold time (vs. CLKOUT

)

<27>

HKWT

Address hold time (vs. CLKOUT

) <28>

HKA

Address setup time (vs. ASTB

)

<29>

SAST

+70

C 0.5 T 10

0.5 T 10

0.5 T 12

Address hold time (vs. ASTB

)

<30>

HSTA

0.5 T 10

ASTB

DSTB

delay time

<34>

DSTD

0.5 T 10

DSTB

ASTB

delay time

<37>

DDSTH

0.5 T 10

DSTB width, low

<39>

WDL

+70

C (1 + n) T 10

(1 + n) T 10

(1 + n) T 13

ASTB width, high

<40>

WSTH

T 10

WAIT setup time (vs. address)

<41>

SAWT1

1, 40

+70

1.5 T 20

1, 70

1.5 T 24

<42>

SAWT2

1, 40

+70

(1.5 + n) T 20

1, 70

(1.5 + n) T 24

WAIT hold time (vs. address)

<43>

HAWT1

(0.5 + n) T

<44>

HAWT2

(1.5 + n) T

WAIT setup time (vs. ASTB

)

<45>

SSTWT1

1, 40

+70

T 18

1, 70

T 20

<46>

SSTWT2

(1 + n) T 15

WAIT hold time (vs. ASTB

)

<47>

HSTWT1

<48>

HSTWT2

(1 + n) T

CLKOUT

data output delay time

<49>

DKOD

+70

DSTB

data output delay time

<50>

DDOD

Data output hold time (vs. CLKOUT

)

<51>

HKOD

Data output setup time (vs. DSTB

)

<52>

SODD

(1 + n) T 15

Data output hold time (vs. DSTB

) <53>

HDOD

T 10

Remarks 1. T = t

CYK

2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when

the programmable wait state is inserted.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(7) Bus hold timing (1/2)

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

HLDRQ setup time (vs. CLKOUT

)

<54>

SHOK

HLDRQ hold time (vs. CLKOUT

)

<55>

HKHQ

CLKOUT

HLDAK delay time

<56>

DKHA

HLDRQ width, high

<57>

WHQH

T + 10

HLDAK width, low

<58>

WHAL

+70

T 10

T 12

CLKOUT

Bus float delay time

<59>

DKF

HLDAK

bus output delay time

<60>

DHAC

HLDRQ

HLDAK

delay time

<61>

DHQHA1

(2 n + 7.5) T + 20

HLDRQ

HLDAK

delay time

<62>

DHQHA2

0.5 T

1.5 T + 20

0.5 T

1.5 T + 20

Remarks 1. T = t

CYK

2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when

the programmable wait state is inserted.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(9) CSI timing (1/2)

(a) Master mode

(i)

CSI0-CSI2 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67>

CYSK1

Output

160

120

SCKn width, high

<68>

WSKH1

Output

0.5 t

CYSK1

0.5 t

CYSK1

SCKn width, low

<69>

WSKL1

Output

0.5 t

CYSK1

0.5 t

CYSK1

SIn setup time (vs. SCKn

)

<70>

SSISK1

SIn hold time (vs. SCKn

)

<71>

HSKSI1

SOn output delay time (vs. SCKn

)

<72>

DSKSO1

SOn output hold time (vs. SCKn

) <73>

HSKSO1

0.5 t

CYSK1

0.5 t

CYSK1

Remark n = 0-2

(ii) CSI3 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCK3 cycle

<67>

CYSK3

Output

500

SCK3 width, high

<68>

WSKH3

Output

0.5 t

CYSK3

0.5 t

CYSK3

SCK3 width, low

<69>

WSKL3

Output

0.5 t

CYSK3

0.5 t

CYSK3

SI3 setup time (vs. SCK3

)

<70>

SSISK3

100

SI3 hold time (vs. SCK3

)

<71>

HSKSI3

SO3 output delay time (vs. SCK3

)

<72>

DSKSO3

= 1.5 K

150

= 50 pF

SO3 output hold time (vs. SCK3

) <73>

HSKSO3

0.5 t

CYSK3

0.5 t

CYSK3

Remark R

and C

are the load resistance and load capacitance respectively of the SCK3 and SO3 output

lines.

(b) Slave mode

(i)

CSI0-CSI2 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCKn cycle

<67>

CYSK2

Input

160

120

SCKn width, high

<68>

WSKH2

Input

SCKn width, low

<69>

WSKL2

Input

SIn setup time (vs. SCKn

)

<70>

SSISK2

SIn hold time (vs. SCKn

)

<71>

HSKSI2

SOn output delay time (vs. SCKn

)

<72>

DSKSO2

SOn output hold time (vs. SCKn

) <73>

HSKSO2

WSKH2

Remark n = 0-2

= 1.5

= 50

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(9) CSI timing (2/2)

(ii) CSI3 timing

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

SCK3 cycle

<67>

CYSK4

Input

500

SCK3 width, high

<68>

WSKH4

Input

180

SCK3 width, low

<69>

WSKL4

Input

180

SI3 setup time (vs. SCK3

)

<70>

SSISK4

100

SI3 hold time (vs. SCK3

)

<71>

HSKSI4

SO3 output delay time (vs. SCK3

)

<72>

DSKSO4

= 1.5 k

150

SO3 output hold time (vs. SCK3

) <73>

HSKSO4

= 50 pF

WSKH4

Remark R

and C

are the load resistance and load capacitance respectively of the SCK3 and SO3 output

lines.

SCKn (I/O)

SIn (input)

SOn (output)

< 67 >

< 69 >

< 68 >

< 70 >

< 71 >

< 72 >

< 73 >

Input data

Output data

Remark 1. The broken line indicates the high-impedance state.
2. n = 0-3

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

A/D Converter Characteristics (T

= 40 to +85

C, V

= AV

= 5 V

10%, V

= V

= 0 V)

Parameter

Symbol

Conditions

25 MHz Model

33 MHz Model

Unit

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

Resolution

bit

Overall error

Note 1

4.5 V

REF1

0.4

%FSR

3.5 V

REF1

0.7

%FSR

Quantize error

1/2

LSB

Conversion time

CONV

4.5 V

REF1

CYK

3.5 V

REF1

CYK

Sampling time

SAMP

4.5 V

REF1

CYK

3.5 V

REF1

CYK

Zero-scale error

Note 1

4.5 V

REF1

1.5

3.5

1.5

3.5

LSB

3.5 V

REF1

1.5

4.5

1.5

4.5

LSB

Full-scale error

Note 1

4.5 V

REF1

1.5

2.5

1.5

2.5

LSB

3.5 V

REF1

1.5

4.5

1.5

4.5

LSB

Non-linear error

Note 1

4.5 V

REF1

1.5

2.5

1.5

2.5

LSB

3.5 V

REF1

1.5

4.5

1.5

4.5

LSB

Analog input

IAN

0.3

voltage

Note 2

+0.3

Reference voltage

REF1

3.5

REF1

current

REF1

1.2

3.0

1.2

3.0

supply current

2.3

6.0

2.3

6.0

Notes 1. Except quantize error

2. The conversion result is 000H when V

IAN

= 0.

Converted with 10-bit resolution when 0 < V

IAN

< AV

REF1

The conversion result is 3FFH when AV

REF1

IAN

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

D/A Converter Characteristics (T

= 40 to +85

C, V

= AV

= 5 V

10%, V

= AV

= 0 V)

Parameter

Symbol

Conditions

25 MHz Model

33 MHz Model

Unit

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

Resolution

bit

Overall error

Load conditions: 2 M

, 30 pF

0.8

REF2

= V

REF3

= 0

Load conditions: 2 M

, 30 pF

1.0

REF2

= 0.75 V

REF3

= 0.25 V

Load conditions: 4 M

, 30 pF

0.6

REF2

= V

REF3

= 0

Load conditions: 4 M

, 30 pF

0.8

REF2

= 0.75 V

REF3

= 0.25 V

Settling time

Load conditions: 2 M

, 30 pF

Output resistance

REF2

input voltage

REF2

0.75 V

REF3

input voltage

REF3

0.25 V

REF2

-AV

REF3

AIREF

DACS0, DACS1 = 55H

resistance value

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

3.2 Flash Memory Programming Mode

Basic Characteristics (T

= 10 to 40

C (when rewrifing), T

= 40 to +85

C (when not rewriting))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Operating frequency

MHz

Supply voltage

4.5

5.5

PPL

low level detection

0.5

0.2 V

PPM

, V

level detection

0.8 V

1.2 V

PPH

high voltage detection

9.7

10.3

10.6

supply current

3.0

+ 25

supply current

= 10.3 V

200

Number of rewrite

Note

WRT

times

Note

Operation is not guaranteed when rewrite is performed more than 20 times.

Cautions 1. V

pull-down resistance value (R

VPP

) is recommended to be in the range 5 k

to 15 k

2. Set the transfer rate between programmer and device as follows.

CSI0

: 0.2 to 1 MHz

UART0: 4800 to 76800 bps

Remark

: Internal system clock frequency

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

4. PACKAGE DRAWING

100-PIN PLASTIC LQFP (FINE PITCH) (14x14)

NOTE

Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

16.00

0.20

14.00

0.20

0.50 (T.P.)

1.00

16.00

0.20

14.00

0.20

0.08

1.00

0.20

0.50

0.20

1.00

0.08

1.40

0.05

0.10

0.05

S100GC-50-8EU, 8EA-2

1.60 MAX.

0.22

0.05

0.04

0.17

0.03

0.07

°+

100

detail of lead end

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

5. RECOMMENDED SOLDERING CONDITIONS

Solder this product under the following recommended conditions.

For details of the recommended soldering conditions, refer to information document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended, consult NEC.

Table 5-1. Soldering Conditions

PD70F3003AGC-25-8EU : 100-pin plastic LQFP (fine pitch) (14

14 mm)

PD70F3003AGC-33-8EU : 100-pin plastic LQFP (fine pitch) (14

14 mm)

PD70F3025AGC-25-8EU : 100-pin plastic LQFP (fine pitch) (14

14 mm)

PD70F3025AGC-33-8EU : 100-pin plastic LQFP (fine pitch) (14

14 mm)

Soldering Method

Soldering Condition

Symbol of Recommended

Soldering Condition

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max.

IR35-103-3

(210

C min.), Number of times: 3 max., Number of days:

Note

(after that, prebaking is necessary at 125

for 10 hours.)

VPS

Package peak temperature: 215

C, Time: 40 seconds max.

VP15-103-3

(200

C min.), Number of times: 3 max., Number of days:

Note

(after that, prebaking is necessary at 125

for 10 hours.)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per

side of device)

Note

The number of days for storage at 25

C, 65% RH MAX after the dry pack has been opened.

Caution

Do not use two or more soldering methods in combination (except partial heating method).

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input

levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered to have a

possibility of being an output pin. All handling related to the unused pins must be judged device

by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until

the reset signal is received. Reset operation must be executed immediately after power-on for

devices having reset function.

Related document

PD703003 Data Sheet (U12261E)

PD703003A, 703004A, 703025A Data Sheet (U13188E)

PD70F3003 Data Sheet (U12036E)

Reference document: Concept of Electrical Characteristics - Microcomputers (IEI-601) (Japanese version)

The related documents referred to in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

V850 Family and V853 are trademarks of NEC Corporation.

PD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J99.1

PD70F3003A, 70F3025A

[MEMO]

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98.8

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