Document Outline
- COVER
- DESCRIPTION
- FEATURES
- APPLICATIONS
- ORDERING INFORMATION
- PIN CONFIGURATION
- PIN IDENTIFICATION
- INTERNAL BLOCK DIAGRAM
- 1. PIN FUNCTIONS
- 1.1 Port Pins
- 1.2 Non-Port Pins
- 1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
- 2. ELECTRICAL SPECIFICATIONS
- 3. PACKAGE DRAWINGS
- 4. RECOMMENDED SOLDERING CONDITIONS
MOS INTEGRATED CIRCUIT
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
V850/SA1
TM
32-BIT SINGLE-CHIP MICROCONTROLLER
Document No. U14527EJ3V0DS00 (3rd edition)
Date Published July 2001 N CP(K)
Printed in Japan
DATA SHEET
2000
The mark
shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
DESCRIPTION
The
PD70F3015B, 70F3015BY, 70F3017A, and 70F3017AY are products with on-chip flash memory. Because
the devices can be programmed by the user on-board, they are ideal for the evaluation stages of system
development, small-scale production of a variety of products, and rapid development of new products.
The V850/SA1 provides a high-level cost performance ideal for applications ranging from low-power camcorders
and other AV equipment to portable telephone equipment such as cellular phones and personal handyphone
systems (PHS).
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
V850/SA1 User's Manual Hardware:
U12768E
V850 Family
TM
User's Manual Architecture:
U10243E
FEATURES
Number of instructions: 74
Minimum instruction execution time:
58.8 ns (@ 17 MHz operation with main system
clock (f
XX
))
50 ns (@ 20 MHz operation with main system
clock (f
XX
))
30.5
s (@ 32.768 kHz operation with subsystem
clock (f
XT
))
General-purpose registers: 32 bits
32 registers
Instruction set:
Signed multiplication, saturation operations, 32-bit
shift instructions, bit manipulation instructions,
load/store instructions
Memory space:
16 MB linear address space
Memory block division function: 2 MB per block
Internal memory
Flash memory
128 KB (
PD70F3015B, 70F3015BY)
256 KB (
PD70F3017A, 70F3017AY)
RAM
4 KB (
PD70F3015B, 70F3015BY)
8 KB (
PD70F3017A, 70F3017AY)
External bus interface: 16-bit data bus
Address bus: Separate output enabled
Interrupts and exceptions
External: 8, internal: 23, exceptions: 1
I/O lines Total: 85
Timer/counters
16-bit timer:
2 channels
8-bit timer:
4 channels
Watch timer: 1 channel
Watchdog timer: 1 channel
Serial interface (SIO)
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
I
2
C bus interface (
PD70F3015BY, 70F3017AY)
A/D converter: 12 channels
DMA controller: 3 channels
RTP: 8 bits
1 channel or 4 bits 2 channels
Power-saving functions: HALT/IDLE/STOP modes
Packages: 100-pin plastic LQFP (14
14 mm)
121-pin plastic FBGA (12
12 mm)
Data Sheet U14527EJ3V0DS
2
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
APPLICATIONS
Low-power portable devices
Cellular phones, PHSs, and camcorders
ORDERING INFORMATION
Part Number
Package
Internal ROM
PD70F3015BGC-8EU
PD70F3015BYGC-8EU
PD70F3017AGC-8EU
PD70F3017AF1-EA6
PD70F3017AYGC-8EU
PD70F3017AYF1-EA6
100-pin plastic LQFP (fine pitch) (14 x 14 mm)
100-pin plastic LQFP (fine pitch) (14 x 14 mm)
100-pin plastic LQFP (fine-pitch) (14
14 mm)
121-pin plastic FBGA (12
12 mm)
100-pin plastic LQFP (fine-pitch) (14
14 mm)
121-pin plastic FBGA (12
12 mm)
128 KB (flash memory)
128 KB (flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
256 KB (Flash memory)
Data Sheet U14527EJ3V0DS
3
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
PIN CONFIGURATION
100-pin plastic LQFP (fine-pitch) (14
14 mm)
PD70F3015BGC-8EU
PD70F3015BYGC-8EU
PD70F3017AGC-8EU
PD70F3017AYGC-8EU
Notes 1. Connect the V
PP
pin to V
SS
in the normal operating mode.
2. Applies to the
PD70F3015BY and PD70F3017AY only.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P20/SI2
P15/SCK1/ASCK0
P14/SO1/TXD0
P13/SI1/RXD0
P12/SCK0/SCL
Note 2
P11/SO0
P10/SI0/SDA
Note 2
P07/INTP6
P06/INTP5/RTPTRG
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P107/RTP7/A12
P110/A1
P111/A2
P112/A3
P113/A4
RESET
P114/XT1
XT2
V
DD
X2
X1
V
SS
CLKOUT
P120/WAIT
P90/LBEN/WRL
P91/UBEN
P92/R/W/WRH
P93/DSTB/RD
P94/ASTB
P95/HLDAK
P96/HLDRQ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P21/SO2
P22/SCK2
P23/RXD1
P24/TXD1
P25/ASCK1
V
DD
V
SS
P26/TI2/TO2
P27/TI3/TO3
P30/TI00
P31/TI01
P32/TI10
P33/TI11
P34/TO0/A13
P35/TO1/A14
P36/TI4/TO4/A15
P37/TI5/TO5
V
PP
Note 1
P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9
P105/RTP5/A10
P106/RTP6/A11
P71/ANI1
P70/ANI0
AV
REF
AV
SS
AV
DD
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
Data Sheet U14527EJ3V0DS
4
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
121-pin plastic FBGA (12
12 mm)
PD70F3017AF1-EA6
PD70F3017AYF1-EA6
Top View
Bottom View
N M L K J H G F E D C B A
A B C D E F G H J K L M N
13
12
11
10
9
8
7
6
5
4
3
2
1
Pin
Number
Pin Name
Pin
Number
Pin Name
Pin
Number
Pin Name
Pin
Number
Pin Name
Pin
Number
Pin Name
Pin
Number
Pin Name
A1
P20
B8
P83
D2
V
DD
G11
P60
K13
BV
DD
M7
V
SS
A2
P15
B9
P80
D3
V
SS
G12
P56
L1
P104
M8
V
SS
A3
V
SS
B10
P75
D11
AV
DD
G13
P57
L2
P105
M9
P92
A4
P13
B11
AV
SS
D12
AV
DD
H1
P34
L3
RESET
M10
P95
A5
P11
B12
AV
SS
D13
AV
DD
H2
P37
L4
V
DD
M11
P41
A6
P06
B13
P71
E1
P25
H3
P35
L5
V
SS
M12
P45
A7
P03
C1
P22
E2
V
DD
H11
P55
L6
X2
M13
P44
A8
P00
C2
P23
E3
P30
H12
P53
L7
P90
N1
P107
A9
P81
C3
V
SS
E11
AV
DD
H13
P54
L8
P120
N2
P110
A10
P76
C4
P24
E12
P64
J1
V
PP
Note
L9
P93
N3
P112
A11
P73
C5
P07
E13
P65
J2
V
PP
Note
L10
P96
N4
V
DD
A12
P72
C6
P04
F1
P26
J3
P100
L11
BV
SS
N5
XT1
A13
AV
SS
C7
P01
F2
P27
J11
P52
L12
BV
SS
N6
V
SS
B1
P21
C8
P82
F3
P33
J12
P50
L13
BV
SS
N7
V
SS
B2
P14
C9
P77
F11
P63
J13
P51
M1
P106
N8
CLKOUT
B3
V
SS
C10
P74
F12
P61
K1
P101
M2
P111
N9
P91
B4
P12
C11
AV
SS
F13
P62
K2
P102
M3
P113
N10
P94
B5
P10
C12
P70
G1
P31
K3
P103
M4
V
DD
N11
P40
B6
P05
C13
AV
REF
G2
P32
K11
P46
M5
XT2
N12
P42
B7
P02
D1
V
DD
G3
P36
K12
P47
M6
X1
N13
P43
Note
Connect the V
PP
pin to V
SS
in the normal operating mode.
Remarks 1. Alternate function names are omitted. The alternate functions are identical to the 100-pin plastic
LQFP. However, the SCL and SDA pins are provided only in the
PD70F3017AY.
2. Connect the D4 pin directly to V
SS
.
Data Sheet U14527EJ3V0DS
5
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
PIN IDENTIFICATION
A1 to A21:
Address Bus
P100 to P107:
Port 10
AD0 to AD15:
Address/Data Bus
P110 to P114:
Port 11
ADTRG:
AD Trigger Input
P120:
Port 12
ANI0 to ANI11:
Analog Input
RD:
Read
ASCK0, ASCK1:
Asynchronous Serial Clock
RESET:
Reset
ASTB:
Address Strobe
RTP0 to RTP7:
Real-Time Port
AV
DD
:
Analog V
DD
RTPTRG:
RTP Trigger
AV
REF
:
Analog Reference Voltage
R/W:
Read/Write Status
AV
SS
:
Analog V
SS
RXD0, RXD1:
Receive Data
BV
DD
:
Power Supply for Bus Interface
SCK0 to SCK2:
Serial Clock
BV
SS
:
Ground for Bus Interface
SCL
Note
:
Serial Clock
CLKOUT:
Clock Output
SDA
Note
:
Serial Data
DSTB:
Data Strobe
SI0 to SI2:
Serial Input
HLDAK:
Hold Acknowledge
SO0 to SO2:
Serial Output
HLDRQ:
Hold Request
TI00, TI01, TI10, :
Timer Input
INTP0 to INTP6:
Interrupt Request From Peripherals
TI11, TI2 to TI5
LBEN:
Lower Byte Enable
TO0 to TO5:
Timer Output
NMI:
Non-maskable Interrupt Request
TXD0,TXD1:
Transmit Data
P00 to P07:
Port 0
UBEN:
Upper Byte Enable
P10 to P15:
Port 1
V
DD
:
Power Supply
P20 to P27:
Port 2
V
PP
:
Programming Power Supply
P30 to P37:
Port 3
V
SS
:
Ground
P40 to P47:
Port 4
WAIT:
Wait
P50 to P57:
Port 5
WRH:
Write Strobe High Level Data
P60 to P65:
Port 6
WRL:
Write Strobe Low Level Data
P70 to P77:
Port 7
X1, X2:
Crystal for Main System Clock
P80 to P83:
Port 8
XT1, XT2:
Crystal for Subsystem Clock
P90 to P96:
Port 9
Note Applies to the
PD70F3015BY and PD70F3017AY only.
Data Sheet U14527EJ3V0DS
6
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
INTERNAL BLOCK DIAGRAM
Notes 1.
PD70F3015B, 70F3015BY: 128 KB
PD70F3017A, 70F3017AY: 256 KB
2.
PD70F3015B, 70F3015BY: 4 KB
PD70F3017A, 70F3017AY: 8 KB
3. Applies to the
PD70F3015BY and PD70F3017AY only.
NMI
TI00, TI01,
TI10, TI11
TO0, TO1
SIO
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA
Note 3
SCK0/SCL
Note 3
INTP0 to INTP6
INTC
CSI0/I
2
C
Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
CSI1/UART0
SO2
SI2
SCK2
CSI2
TXD1
RXD1
ASCK1
Note 1
PC
ALU
CPU
Flash
memory
Note 2
RAM
HLDRQ (P96)
HLDAK (P95)
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT
A1 to A12
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
CG
(P40 to P47, P50 to P57)
(P100 to P107, P110 to P113)
P120
P114
P110 to P113
P100 to P107
P90 to P96
P80 to P83
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
RTP0 to RTP7
RTPTRG
AV
DD
AV
REF
AV
SS
ANI0 to ANI11
ADTRG
CLKOUT
X1
X2
XT1 (P114)
XT2
RESET
V
DD
V
SS
BV
DD
BV
SS
V
PP
BCU
Timer/counters
16-bit timer:
TM0, TM1
8-bit timer:
TM2 to TM5
DMAC: 3 ch
Watch timer
Watchdog
timer
RTP
A/D
converter
UART1
32-bit
barrel shifter
System
registers
Multiplier
16 x 16 32
General-purpose
registers
32 bits x 32
Instruction
queue
Port
Data Sheet U14527EJ3V0DS
7
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
CONTENTS
1.
PIN FUNCTIONS ..................................................................................................................................8
1.1
Port Pins ..................................................................................................................................................... 8
1.2
Non-Port Pins........................................................................................................................................... 11
1.3
Pin I/O Circuits and Recommended Connection of Unused Pins ....................................................... 14
2.
ELECTRICAL SPECIFICATIONS ......................................................................................................18
3.
PACKAGE DRAWINGS .....................................................................................................................43
4.
RECOMMENDED SOLDERING CONDITIONS ................................................................................45
Data Sheet U14527EJ3V0DS
8
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
1. PIN FUNCTIONS
1.1 Port Pins
(1/3)
Pin Name
I/O
PULL
Function
Alternate Function
P00
NMI
P01
INTP0
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG
P07
I/O
Yes
Port 0
8-bit I/O port
Input/output can be specified in 1-bit units.
INTP6
P10
SI0/SDA
Note
P11
SO0
P12
SCK0/SCL
Note
P13
SI1/RXD0
P14
SO1/TXD0
P15
I/O
Yes
Port 1
6-bit I/O port
Input/output can be specified in 1-bit units.
SCK1/ASCK0
P20
SI2
P21
SO2
P22
SCK2
P23
RXD1
P24
TXD1
P25
ASCK1
P26
TI2/TO2
P27
I/O
Yes
Port 2
8-bit I/O port
Input/output can be specified in 1-bit units.
TI3/TO3
P30
TI00
P31
TI01
P32
TI10
P33
TI11
P34
TO0/A13
P35
TO1/A14
P36
TI4/TO4/A15
P37
I/O
Yes
Port 3
8-bit I/O port
Input/output can be specified in 1-bit units.
TI5/TO5
Note Applies to the
PD70F3015BY and PD70F3017AY only.
Remark
PULL: On-chip pull-up resistor
Data Sheet U14527EJ3V0DS
9
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(2/3)
Pin Name
I/O
PULL
Function
Alternate Function
P40
AD0
P41
AD1
P42
AD2
P43
AD3
P44
AD4
P45
AD5
P46
AD6
P47
I/O
No
Port 4
8-bit I/O port
Input/output can be specified in 1-bit units.
AD7
P50
AD8
P51
AD9
P52
AD10
P53
AD11
P54
AD12
P55
AD13
P56
AD14
P57
I/O
No
Port 5
8-bit I/O port
Input/output can be specified in 1-bit units.
AD15
P60
A16
P61
A17
P62
A18
P63
A19
P64
A20
P65
I/O
No
Port 6
6-bit I/O port
Input/output can be specified in 1-bit units.
A21
P70
ANI0
P71
ANI1
P72
ANI2
P73
ANI3
P74
ANI4
P75
ANI5
P76
ANI6
P77
Input
No
Port 7
8-bit input port
ANI7
P80
ANI8
P81
ANI9
P82
ANI10
P83
Input
No
Port 8
4-bit input port
ANI11
Remark
PULL: On-chip pull-up resistor
Data Sheet U14527EJ3V0DS
10
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(3/3)
Pin Name
I/O
PULL
Function
Alternate Function
P90
LBEN/WRL
P91
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
I/O
No
Port 9
7-bit I/O port
Input/output can be specified in 1-bit units.
HLDRQ
P100
RTP0/A5
P101
RTP1/A6
P102
RTP2/A7
P103
RTP3/A8
P104
RTP4/A9
P105
RTP5/A10
P106
RTP6/A11
P107
I/O
Yes
Port 10
8-bit I/O port
Input/output can be specified in 1-bit units.
RTP7/A12
P110
A1
P111
A2
P112
A3
P113
I/O
Yes
A4
P114
Input
No
Port 11
5-bit I/O port
Input/output can be specified in 1-bit units.
P114 is fixed as input only.
XT1
P120
I/O
No
Port 12
1-bit I/O port
WAIT
Remark
PULL: On-chip pull-up resistor
Data Sheet U14527EJ3V0DS
11
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
1.2 Non-Port Pins
(1/3)
Pin Name
I/O
PULL
Function
Alternate Function
A1 to A4
P110 to P113
A5 to A12
P100/RTP0 to
P107/RTP7
A13
P34/TO0
A14
P35/TI1
A15
Output
Yes
Low-order address bus used for external memory expansion
P36/TI4/TO4
A16 to A21
Output
No
High-order address bus used for external memory expansion
P60 to P65
AD0 to AD7
P40 to P47
AD8 to AD15
I/O
No
16-bit multiplexed address/data bus used for external memory
expansion
P50 to P57
ADTRG
Input
Yes
A/D converter external trigger input
P05/INTP4
ANI0 to ANI7
Input
No
P70 to P77
ANI8 to ANI11
Input
No
Analog input to A/D converter
P80 to P83
ASCK0
P15/SCK1
ASCK1
Input
Yes
Serial clock input for UART0 and UART1
P25
ASTB
Output
No
External address strobe signal output
P94
AV
DD
-
-
Positive power supply for A/D converter
-
AV
REF
Input
-
Reference voltage input for A/D converter
-
AV
SS
-
-
Ground potential for A/D converter
-
BV
DD
-
-
Positive power supply for bus interface
-
BV
SS
-
-
Ground potential for bus interface
-
CLKOUT
Output
-
Internal system clock output
-
DSTB
Output
No
External data strobe signal output
P93/RD
HLDAK
Output
No
Bus hold acknowledge output
P95
HLDRQ
Input
No
Bus hold request input
P96
INTP0 to INTP3
External interrupt request input (analog noise elimination)
P01 to P04
INTP4
P05/ADTRG
INTP5
P06/RTPTRG
INTP6
Input
Yes
External interrupt request input (digital noise elimination)
P07
LBEN
Output
No
External data bus's low-order byte enable signal output
P90/WRL
NMI
Input
Yes
Non-maskable interrupt request input
P00
RD
Output
No
Read strobe signal output
P93/DSTB
RESET
Input
-
System reset input
-
RTP0 to RTP7
Output
Yes
Real-time output port
P100/A5 to P107/A12
Remark
PULL: On-chip pull-up resistor
Data Sheet U14527EJ3V0DS
12
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(2/3)
Pin Name
I/O
PULL
Function
Alternate Function
RTPTRG
Input
Yes
RTP external trigger input
P06/INTP5
R/W
Output
No
External read/write status output
P92/WRH
RXD0
P13/SI1
RXD1
Input
Yes
Serial receive data input for UART0 and UART1
P23
SCK0
P12
SCK1
P15/ASCK0
SCK2
Serial clock I/O (3-wire type) for CSI0 to CSI2
P22
SCL
I
2
C serial clock I/O
Note
P12/SCK0
SDA
I/O
Yes
I
2
C serial transmit/receive data I/O
Note
P10/SI0
SI0
P10
SI1
P13/RXD0
SI2
Input
Yes
Serial receive data input (3-wire type) for CSI0 to CSI2
P20
SO0
P11
SO1
P14/TXD0
SO2
Output
Yes
Serial transmit data output (3-wire type) for CSI0 to CSI2
P21
TI00
External capture trigger input and external count clock input
for TM0
P30
TI01
External capture trigger input for TM0
P31
TI10
External capture trigger input and external count clock input
for TM1
P32
TI11
External capture trigger input for TM1
P33
TI2
External count clock input for TM2
P26/TO2
TI3
External count clock input for TM3
P27/TO3
TI4
External count clock input for TM4
P36/TO4/A15
TI5
Input
Yes
External count clock input for TM5
P37/TO5
TO0, TO1
Pulse signal output for TM0, TM1
P34/A13, P35/A14
TO2
Pulse signal output for TM2
P26/TI2
TO3
Pulse signal output for TM3
P27/TI3
TO4
Pulse signal output for TM4
P36/TI4/A15
TO5
Output
Yes
Pulse signal output for TM5
P37/TI5
TXD0
P14/SO1
TXD1
Output
Yes
Serial transmit data output for UART0 and UART1
P24
UBEN
Output
No
High-order byte enable signal output for external data bus
P91
V
DD
-
-
Positive power supply pin
-
V
SS
-
-
GND potential
-
Note Applies to the
PD70F3015BY and PD70F3017AY only.
Remark
PULL: On-chip pull-up resistor
Data Sheet U14527EJ3V0DS
13
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(3/3)
Pin Name
I/O
PULL
Function
Alternate Function
WAIT
Input
No
Control signal input for inserting wait in bus cycle
P120
WRH
High-order byte write strobe signal output for external data
bus
P92/R/W
WRL
Output
No
Low-order byte write strobe signal output for external data bus
P90/LBEN
X1
Input
-
X2
-
-
Resonator connection for main system clock
-
XT1
Input
No
P114
XT2
-
-
Resonator connection for subsystem clock
-
V
PP
-
-
Pin to which high voltage is applied during program
write/verify
-
Remark
PULL: On-chip pull-up resistor
Data Sheet U14527EJ3V0DS
14
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
1.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 1-1. For
the input/output schematic circuit diagram of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuits (1/2)
Pin
Alternate Function
I/O Circuit Type
Recommended Connection of Unused Pins
P00
NMI
P01 to
P04
INTP0 to INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG
P07
INTP6
8-A
P10
SI0/SDA
Note
10-A
P11
SO0
26
P12
SCK0/SCL
Note
10-A
P13
SI1/RXD0
8-A
P14
SO1/TXD0
26
P15
SCK1/ASCK0
10-A
P20
SI2
8-A
P21
SO2
26
P22
SCK2
10-A
P23
RXD1
8-A
P24
TXD1
5-A
P25
ASCK1
P26, P27
TI2/TO2, TI3/TO3
P30, P31
TI00, TI01
P32, P33
TI10, TI11
8-A
P34, P35
TO0/A13, TO1/A14
5-A
P36
TI4/TO4/A15
P37
TI5/TO5
8-A
Input:
Independently connect to V
DD
or V
SS
via a resistor
Output: Leave open
P40 to
P47
AD0 to AD7
P50 to
P57
AD8 to AD15
P60 to
P65
A16 to A21
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
P70 to
P77
ANI0 to ANI7
P80 to
P83
ANI8 to ANI11
9
Connect to AV
SS
or AV
DD
Note
Applies to the
PD70F3015BY and PD70F3017AY only.
Data Sheet U14527EJ3V0DS
15
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Table 1-1. Types of Pin I/O Circuits (2/2)
Pin
Alternate Function
I/O Circuit Type
Recommended Connection of Unused Pins
P90
LBEN/WRL
P91
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
P100 to
P107
RTP0/A5 to RTP7/A12
26
P110 to
P113
A1 to A4
5
Input:
Independently connect to V
DD
or V
SS
via a resistor
Output: Leave open
P114
XT1
16-A
Connect to V
SS
P120
WAIT
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
AV
REF
-
-
Connect to AV
SS
CLKOUT
-
4
Leave open
RESET
-
2
-
X2
-
-
Leave open (when external clock is input to X1 pin)
XT2
-
16-A
Leave open
V
PP
Connect to V
SS
Data Sheet U14527EJ3V0DS
16
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 2
Schmitt-triggered input with hysteresis characteristics
Push-pull output that can be set for high-impedance output
(both P-ch and N-ch off)
IN
Data
Output
disable
P-ch
OUT
V
DD
N-ch
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pullup
enable
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
P-ch
V
DD
Pullup
enable
IN
Comparator
+
V
REF
(threshold voltage)
P-ch
N-ch
Input enable
Type 4
Type 5
Type 9
Type 8-A
Type 5-A
Data Sheet U14527EJ3V0DS
17
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Figure 1-1. Pin Input/Output Circuits (2/2)
Data
Output disable
P-ch
IN/OUT
V
DD
N-ch
P-ch
V
DD
Pullup
enable
Open drain
Data
Output
disable
Open drain
P-ch
IN/OUT
V
DD
N-ch
P-ch
V
DD
Pullup
enable
Type 10-A
Type 26
Type 16-A
XT1
XT2
Data Sheet U14527EJ3V0DS
18
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25 C, V
SS
= 0 V)
Parameter
Symbol
Conditions
Ratings
Unit
V
DD
0.5 to +4.6
V
V
PP
0.5 to +8.5
V
AV
DD
0.5 to +4.6
V
BV
DD
0.5 to +4.6
V
V
SS
0.5 to +0.5
V
AV
SS
0.5 to +0.5
V
Supply voltage
BV
SS
0.5 to +0.5
V
V
I1
Note 1, P114, RESET
0.5 to V
DD
+ 0.5
Note 4
V
Input voltage
V
I2
Note 2
0.5 to BV
DD
+ 0.5
Note 4
V
Clock input voltage
V
K
X1, XT1, XT2, V
DD
= 2.7 to 3.6 V
0.5 to V
DD
+ 1.0
Note 4
V
Analog input voltage
V
IAN
Note 3 (AV
DD
)
0.5 to AV
DD
+ 0.5
Note 4
V
Analog reference input voltage
AV
REF
AV
REF
0.5 to AV
DD
+ 0.5
Note 4
V
Per pin
4.0
mA
Total for P00 to P07, P10 to P15, P20 to P25
25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
25
mA
Output current, low
I
OL
Total for P50 to P57, P60 to P65
25
mA
Per pin
4.0
mA
Total for P00 to P07, P10 to P15, P20 to P25
25
mA
Total for P26, P27, P30 to P37, P100 to
P107, P110 to P113
25
mA
Total for P40 to P47, P90 to P96, P120,
CLKOUT
25
mA
Output current, high
I
OH
Total for P50 to P57, P60 to P65
25
mA
V
O1
Note 1, V
DD
= 2.7 to 3.6 V
0.5 to V
DD
+ 0.5
Note 4
V
Output voltage
V
O2
Note 2, CLKOUT, BV
DD
= 2.7 to 3.6 V
0.5 to BV
DD
+ 0.5
Note 4
V
Normal operating mode
40 to +85
C
Operating ambient temperature
T
A
Flash memory programming mode
10 to 40
C
Storage temperature
T
stg
40 to +125
C
Notes 1. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, P120, and their
alternate-function pins.
2. P40 to P47, P50 to P57, P60 to P65, P90 to P96, and their alternate-function pins.
3. P70 to P77, P80 to P83, and their alternate-function pins.
4. Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Data Sheet U14527EJ3V0DS
19
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Cautions
1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V
DD
, V
CC
,
and GND. Open-drain pins or open-connector pins, however, can be directly connected to
each other. Direct connection of the output pins between an IC product and an external
circuit is possible, if the output pins can be set to the high-impedance state and the output
timing of the external circuit is designed to avoid output conflict.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (T
A
= 25 C, V
DD
= AV
DD
= BV
DD
= V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
15
pF
I/O capacitance
C
IO
15
pF
Output capacitance
C
O
f
C
= 1 MHz
Unmeasured pins returned to 0 V
15
pF
Operating Conditions
(1) Operating frequency, operating voltage
Internal Operation Clock Frequency (
)
Supply Voltage (V
DD
)
2 MHz
f
XX
17 MHz
2.7 to 3.6 V
2 MHz
f
XX
20 MHz
3.0 to 3.6 V
f
XT
= 32.768 kHz
2.7 to 3.6 V
(2) CPU Operating frequency
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 2.7 to 3.6 V
0.25
17
MHz
Operation with main
clock
V
DD
= 3.0 to 3.6 V
0.25
20
MHz
CPU operating frequency
f
CPU
Operation with
subclock
V
DD
= 2.7 to 3.6 V
32.768
kHz
Data Sheet U14527EJ3V0DS
20
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Recommended Oscillator
(1) Main clock oscillator (T
A
= 40 to +85 C)
(a) Connection of ceramic resonator or crystal resonator
X1
X2
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 2.7 to 3.6 V
2
17
MHz
Oscillation frequency
f
XX
V
DD
= 3.0 to 3.6 V
2
20
MHz
Upon reset release
2
19
/f
XX
s
Oscillation stabilization time
Upon STOP mode release
Note
s
Note The TYP value differs depending on the setting of the oscillation stabilization time select register (OSTS).
Caution Ensure that the duty of oscillation waveform is between 45% and 55%.
Remarks 1.
Connect the oscillator as close as possible to the X1 and X2 pins.
2.
Do not route the wiring near broken lines.
3.
For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
(b) External clock input
X1
X2
High-speed CMOS inverter
External clock
Open
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
= 2.7 to 3.6 V
2
17
MHz
Input frequency
f
XX
V
DD
= 3.0 to 3.6 V
2
20
MHz
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the X1 pin.
2. Sufficiently evaluate the matching between the
PD70F3015B, 70F3015BY, 70F3017A,
70F3017AY and the high-speed CMOS inverter.
Data Sheet U14527EJ3V0DS
21
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(2) Subclock oscillator (T
A
= 40 to +85 C)
(a) Connection of crystal resonator
XT1
XT2
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency
f
XT
V
DD
= 2.7 to 3.6 V
32
32.768
35
kHz
Oscillation stabilization time
10
s
Remarks 1.
Connect the oscillator as close as possible to the XT1 and XT2 pins.
2.
Do not route the wiring near broken lines.
3.
For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
(b) External clock input
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input frequency
f
XT
V
DD
= 2.7 to 3.6 V
32
32.768
35
kHz
Cautions
1. Connect the high-speed CMOS inverter as close as possible to the XT2 pin.
2. Sufficiently evaluate the matching between the
PD70F3015B, 70F3015BY, 70F3017A,
70F3017AY and the high-speed CMOS inverter.
XT1
XT2
High-speed CMOS inverter
External clock
Data Sheet U14527EJ3V0DS
22
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
DC Characteristics
(1) Operating Conditions (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
IH1
Pins other than below
0.7V
DD
V
DD
V
V
IH2
Note 1
0.7AV
DD
AV
DD
V
V
IH3
Note 2
0.75V
DD
V
DD
V
Input voltage, high
V
IH4
X1, XT1 (P114), XT2
0.8V
DD
V
DD
V
V
IL1
Pins other than below
V
SS
0.3V
DD
V
V
IL2
Note 1
AV
SS
0.3AV
DD
V
V
IL3
Note 2
V
SS
0.2V
DD
V
Input voltage, low
V
IL4
X1, XT1 (P114), XT2
V
SS
0.2V
DD
V
V
OH1
Note 3
I
OH
= 3 mA
0.8V
DD
V
Output voltage, high
V
OH2
Note 4
I
OH
= 1 mA
0.8V
DD
V
V
OL1
Note 3
I
OL
= 1.6 mA
0.4
V
V
OL2
Note 4
(Except pins P10
and P12)
I
OL
= 1.6 mA
0.4
V
Output voltage, low
V
OL3
P10, P12
I
OL
= 3 mA
0.4
V
V
PP
Supply voltage
V
PP1
Normal operation
0
0.2V
DD
V
I
LIH1
Pins other than
below
5
A
Input leakage current, high
I
LIH2
V
I
= V
DD
= AV
DD
=
BV
DD
X1, XT1, XT2
20
A
I
LIL1
Pins other than
below
5
A
Input leakage current, low
I
LIL2
V
I
= 0 V
X1, XT1, XT2
20
A
Output leakage current, high
I
LOH
V
O
= V
DD
= AV
DD
= BV
DD
5
A
Output leakage current, low
I
LOL
V
O
= 0 V
5
A
I
DD1
Normal operation
f
XX
= 17 MHz
All peripheral
functions operating
30
60
mA
I
DD2
HALT mode
f
XX
= 17 MHz
All peripheral
functions operating
10
25
mA
I
DD3
IDLE mode
f
XX
= 17 MHz
Watch timer
operating
4
8
mA
STOP mode (subclock operating@f
XT
=
32.768 kHz, watch timer operating)
10
100
A
Supply current
Note 5
I
DD4
STOP mode (subclock, stopped (XT1 =
V
SS
))
2
100
A
Data Sheet U14527EJ3V0DS
23
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(1) Operating Conditions (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
I
DD5
Subclock normal operation mode
f
XT
= 32.768 kHz (main system clock
stopped)
250
600
A
Supply current
Note 5
I
DD6
Subclock IDLE mode
f
XT
= 32.768 kHz (main system clock
stopped, watch timer operating)
130
360
A
Pull-up resistance
R
L
V
IN
= 0 V
10
30
100
k
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.
2. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their
alternate-function pins.
3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.
4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternate-
function pins.
5. The TYP value of V
DD
is 3.3 V. The current consumed by the output buffer is not included.
Data Sheet U14527EJ3V0DS
24
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(2) Operating Conditions (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 3.0 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V) (1/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
IH1
Pins other than below
0.7V
DD
V
DD
V
V
IH2
Note 1
0.7AV
DD
AV
DD
V
V
IH3
Note 2
0.75V
DD
V
DD
V
Input voltage, high
V
IH4
X1, XT1 (P114), XT2
0.8V
DD
V
DD
V
V
IL1
Pins other than below
V
SS
0.3V
DD
V
V
IL2
Note 1
AV
SS
0.3AV
DD
V
V
IL3
Note 2
V
SS
0.2V
DD
V
Input voltage, low
V
IL4
X1, XT1 (P114), XT2
V
SS
0.2V
DD
V
V
OH1
Note 3
I
OH
= 3 mA
0.8V
DD
V
Output voltage, high
V
OH2
Note 4
I
OH
= 1 mA
0.8V
DD
V
V
OL1
Note 3
I
OL
= 1.6 mA
0.4
V
V
OL2
Note 4
(Except pins P10
and P12)
I
OL
= 1.6 mA
0.4
V
Output voltage, low
V
OL3
P10, P12
I
OL
= 3 mA
0.4
V
V
PP
supply voltage
V
PP1
Normal operation
0
0.2V
DD
V
I
LIH 1
Pins other than
below
5
A
Input leakage current, high
I
LIH 2
V
I
= V
DD
= AV
DD
=
BV
DD
X1, XT1, XT2
20
A
I
LIL 1
Pins other than
below
5
A
Input leakage current, low
I
LIL 2
V
I
= 0 V
X1, XT1, XT2
20
A
Output leakage current, high
I
LOH 1
V
O
= V
DD
= AV
DD
= BV
DD
5
A
Output leakage current, low
I
LOL
V
O
= 0 V
5
A
I
DD1
Normal operation
f
XX
= 20 MHz All
peripheral functions
operating
32
64
mA
I
DD2
HALT mode
f
XX
= 20 MHz All
peripheral functions
operating
11
26
mA
I
DD3
IDLE mode
f
XX
= 20 MHz Watch
timer operating
4.5
9
mA
STOP mode (subclock operating@f
XT
=
32.768 kHz, watch timer operating)
10
100
A
Supply current
Note 5
I
DD4
STOP mode (subclock stopped (XT1 =
V
SS
))
2
100
A
Data Sheet U14527EJ3V0DS
25
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
(2) Operating Conditions (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 3.0 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V) (2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
I
DD5
Subclock normal operation mode
f
XT
= 32.768 kHz (main system clock
stopped)
250
600
A
Supply current
Note 5
I
DD6
Subclock IDLE mode
f
XT
= 32.768 kHz (main system clock
stopped, watch timer operating)
130
360
A
Pull-up resistance
R
L
V
IN
= 0 V
10
30
100
k
Notes 1. P70 to P77, P80 to P83, and their alternate-function pins.
2.
P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET and their
alternate-function pins.
3. CLKOUT, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P120, and their alternate-function pins.
4. P00 to P07, P10 to P15, P20 to P27, P30 to P37, P100 to P107, P110 to P113, and their alternate-
function pins.
5. The TYP value of V
DD
is 3.3 V. The current consumed by the output buffer is not included.
Data Sheet U14527EJ3V0DS
26
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Data Retention Characteristics (T
A
= 40 to +85 C, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention voltage
V
DDDR
STOP mode
1.8
3.6
V
Data retention current
I
DDDR
V
DD
= V
DDDR
, XT1 = V
SS
2
100
A
Supply voltage rise time
t
RVD
200
s
Supply voltage fall time
t
FVD
200
s
Supply voltage hold time
(from STOP mode setting)
t
HVD
0
ms
STOP mode release signal input time
t
DREL
0
ms
Data retention high-level input voltage
V
IHDR
All input ports
V
IHn
V
DDDR
V
Data retention low-level input voltage
V
ILDR
All input ports
0
V
ILn
V
Remarks 1.
TYP. values are reference values for when T
A
= 25 C.
2.
n = 1 to 4
Note V
DD
= 2.7 V indicates the minimum operating voltage of the V850/SA1 (when f
XX
= 17 MHz).
Caution
Shifting to STOP mode and restoring from STOP mode must be performed at V
DD
= 2.7 V min.
(f
XX
= 17 MHz) and V
DD
= 3.0 V min. (f
XX
= 20 MHz), respectively.
V
DD
2.7 V
Note
Setting STOP mode
t
HVD
t
FVD
RESET
(input)
STOP mode release interrupt (NMI, etc.)
(when STOP mode is released
at falling edge)
STOP mode release interrupt (NMI, etc.)
(when STOP mode is released
at rising edge)
t
RVD
t
DREL
V
DDDR
V
IHDR
V
ILDR
V
IHDR
Data Sheet U14527EJ3V0DS
27
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
AC Characteristics
AC test input measurement points
(1) P11, P14, P21, P24, P34, P35, P40 to P47, P50 to P57, P60 to P65, P90 to P96, P100 to P107, P110 to P113,
P120, and their alternate-function pins
V
DD
0 V
0.7V
DD
0.3V
DD
0.7V
DD
0.3V
DD
Point of measurement
(2) P70 to P77, P80 to P83, and their alternate-function pins
AV
DD
0 V
0.7AV
DD
0.3AV
DD
0.7AV
DD
0.3AV
DD
Point of measurement
(3) P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, RESET, and their
alternate-function pins
V
DD
0 V
0.75V
DD
0.2V
DD
0.75V
DD
0.2V
DD
Point of measurement
(4) X1, XT1 (P114), XT2
V
DD
0 V
0.8V
DD
0.2V
DD
0.8V
DD
0.2V
DD
Point of measurement
AC test output measurement points
0.8V
DD
0.4 V
0.8V
DD
0.4 V
Point of measurement
V
DD
0 V
Data Sheet U14527EJ3V0DS
28
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Load conditions
DUT
(Device under test)
C
L
= 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance
of the device to 50 pF or less by inserting a buffer or by some other means.
Data Sheet U14527EJ3V0DS
29
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Clock Timing
(1)
Operating Conditions (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V,
C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
X1 input cycle
58.8
500
ns
XT1 input cycle
t
CYX
<1>
28.5
31.2
s
X1 input high-level width
26.4
ns
XT1 input high-level width
t
WXH
<2>
12.8
s
X1 input low-level width
26.4
ns
XT1 input low-level width
t
WXL
<3>
12.8
s
X1, XT1 input rise time
t
XR
<4>
0.5 (t
CYX
t
WXH
t
WXL
)
ns
X1, XT1 input fall time
t
XF
<5>
0.5 (t
CYX
t
WXH
t
WXL
)
ns
CLKOUT output cycle
t
CYK
<6>
58.8 ns
31.2
s
CLKOUT high-level width
t
WKH
<7>
0.4t
CYK
10
ns
CLKOUT low-level width
t
WKL
<8>
0.4t
CYK
10
ns
CLKOUT rise time
t
KR
<9>
10
ns
CLKOUT fall time
t
KF
<10>
10
ns
Remark Ensure that the duty is between 45% and 55%.
(2)
Operating Conditions (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 3.0 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V,
C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
X1 input cycle
50.0
500
ns
XT1 input cycle
t
CYX
<1>
28.5
31.2
s
X1 input high-level width
22.5
ns
XT1 input high-level width
t
WXH
<2>
12.8
s
X1 input low-level width
22.5
ns
XT1 input low-level width
t
WXL
<3>
12.8
s
X1, XT1 input rise time
t
XR
<4>
0.5 (t
CYX
t
WXH
t
WXL
)
ns
X1, XT1 input fall time
t
XF
<5>
0.5 (t
CYX
t
WXH
t
WXL
)
ns
CLKOUT output cycle
t
CYK
<6>
50.0 ns
31.2
s
CLKOUT high-level width
t
WKH
<7>
0.4t
CYK
10
ns
CLKOUT low-level width
t
WKL
<8>
0.4t
CYK
10
ns
CLKOUT rise time
t
KR
<9>
10
ns
CLKOUT fall time
t
KF
<10>
10
ns
Remark Ensure that the duty is between 45% and 55%.
Data Sheet U14527EJ3V0DS
30
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Clock Timing
X1, XT1 (input)
CLKOUT (output)
<2>
<4>
<5>
<1>
<3>
<7>
<9>
<10>
<8>
<6>
Timing of pins other than CLKOUT, ports 4, 5, 6, and 9
(T
A
= 40 to +85
C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
=
0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
t
OR
<11>
20
ns
Output fall time
t
OF
<12>
20
ns
Output signal
<11>
<12>
Data Sheet U14527EJ3V0DS
31
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Bus Timing (CLKOUT Asynchronous)
(T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
)
t
SAST
<13>
0.5T
15
ns
Address hold time (from ASTB
)
t
HSTA
<14>
0.5T
15
ns
Address float delay time from DSTB
t
FDA
<15>
2
ns
Data input setup time from address
t
SAID
<16>
(2 + n)T 25
ns
Data input setup time from DSTB
t
SDID
<17>
(1 + n)T 25
ns
Delay time from ASTB
to DSTB
t
DSTD
<18>
0.5T
15
ns
Data input hold time (from DSTB
)
t
HDID
<19>
0
ns
Address output time from DSTB
t
DDA
<20>
(1 + i)T 15
ns
Delay time from DSTB
to ASTB
t
DDST1
<21>
0.5T 15
ns
Delay time from DSTB
to ASTB
t
DDST2
<22>
(1.5 + i)T 15
ns
DSTB low-level width
t
WDL
<23>
(1 + n)T 15
ns
ASTB high-level width
t
WSTH
<24>
T 15
ns
Data output time from DSTB
t
DDOD
<25>
15
ns
Data output setup time (to DSTB
)
t
SODD
<26>
(1 + n)T 20
ns
Data output hold time (from DSTB
)
t
HDOD
<27>
T 15
ns
t
SAWT1
<28>
n
1
1.5T 25
ns
WAIT setup time (to address)
t
SAWT2
<29>
n
1
(1.5 + n)T 25
ns
t
HAWT1
<30>
n
1
(0.5 + n)T
ns
WAIT hold time (from address)
t
HAWT2
<31>
n
1
(1.5 + n)T
ns
t
SSTWT1
<32>
n
1
T 25
ns
WAIT setup time (to ASTB
)
t
SSTWT2
<33>
n
1
(1 + n)T 25
ns
t
HSTWT1
<34>
n
1
nT
ns
WAIT hold time (from ASTB
)
t
HSTWT2
<35>
n
1
(1 + n)T
ns
HLDRQ high-level width
t
WHQH
<36>
T + 10
ns
HLDAK low-level width
t
WHAL
<37>
T 15
ns
Bus output delay time from HLDAK
t
DHAC
<38>
0
ns
Delay time from HLDRQ
to HLDAK
t
DHQHA1
<39>
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
to HLDAK
t
DHQHA2
<40>
0.5T
1.5T + 25
ns
Remarks 1.
T = 1/f
CPU
(f
CPU
: CPU operation clock frequency)
2.
n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3.
i: Number of idle states inserted after the read cycle (0 or 1).
4.
The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.
Data Sheet U14527EJ3V0DS
32
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Bus Timing (CLKOUT Synchronous)
(T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
to address
t
DKA
<41>
0
19
ns
Delay time from CLKOUT
to address
float
t
FKA
<42>
12
7
ns
Delay time from CLKOUT
to ASTB
t
DKST
<43>
12
7
ns
Delay time from CLKOUT
to DSTB
t
DKD
<44>
5
14
ns
Data input setup time (to CLKOUT
)
t
SIDK
<45>
15
ns
Data input hold time (from CLKOUT
)
t
HKID
<46>
5
ns
Data output delay time from CLKOUT
t
DKOD
<47>
19
ns
WAIT setup time (to CLKOUT
)
t
SWTK
<48>
15
ns
WAIT hold time (from CLKOUT
)
t
HKWT
<49>
5
ns
HLDRQ setup time (to CLKOUT
)
t
SHQK
<50>
15
ns
HLDRQ hold time (from CLKOUT
)
t
HKHQ
<51>
5
ns
Delay time from CLKOUT
to bus float
t
DKF
<52>
19
ns
Delay time from CLKOUT
to HLDAK
t
DKHA
<53>
19
ns
Remark
The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
Data Sheet U14527EJ3V0DS
33
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
CLKOUT (output)
A16 to A21 (output),
A1 to A15 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output),
RD (output)
WAIT (input)
T1
T2
TW
T3
<41>
<42>
<43>
<13>
<44>
<21>
<20>
<22>
<18>
<32> <48>
<34>
<33>
<35>
<28>
<30>
<29>
<31>
<49>
<48>
<49>
<17>
<23>
<19>
<43>
<16>
<45>
<46>
Address
Hi-Z
<15>
<44>
<14>
<24>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
Data
Data Sheet U14527EJ3V0DS
34
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
CLKOUT (output)
A16 to A21 (output),
A1 to A15 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output),
WRL (output),
WRH (output)
WAIT (input)
T1
T2
TW
T3
<41>
<47>
<43>
<13>
<44>
<21>
<27>
<18>
<32> <48>
<34>
<33>
<35>
<28>
<30>
<29>
<31>
<49>
<48>
<49>
<26>
<23>
<24>
<14>
<43>
Data
Address
<25>
<44>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
Data Sheet U14527EJ3V0DS
35
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Bus Hold
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A16 to A19 (output), Note
A1 to A15 (output)
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output), RD (output),
WRL (output), WRH (output)
<50>
<51>
<53>
<38>
<37>
<39>
<40>
<50>
<53>
<36>
TH
TH
TH
TI
Hi-Z
Hi-Z
Hi-Z
Data
Hi-Z
Remark R/W (output), UBEN (output), LBEN (output)
<52>
Data Sheet U14527EJ3V0DS
36
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Reset/Interrupt Timing
(T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RESET high-level width
t
WRSH
<54>
500
ns
RESET low-level width
t
WRSL
<55>
500
ns
NMI high-level width
t
WNIH
<56>
500
ns
NMI low-level width
t
WNIL
<57>
500
ns
n = 0 to 3 (analog noise
elimination)
500
ns
INTPn high-level width
t
WITH
<58>
n = 4 to 6 (digital noise
elimination)
3T + 20
ns
n = 0 to 3 (analog noise
elimination)
500
ns
INTPn low-level width
t
WITL
<59>
n = 4 to 6 (digital noise
elimination)
3T + 20
ns
Remark
T = 1/f
XX
Reset
<54>
<55>
RESET (input)
Interrupt
<56>
<57>
NMI (input)
<58>
<59>
INTPn (input)
Remark n = 0 to 6
Data Sheet U14527EJ3V0DS
37
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
TIn Input Timing
(T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
TIn0, TIn1 high-level width
n = 0, 1
2T
sam
+ 20
Note
ns
TIn high-level width
t
TIHn
<60>
n = 2 to 5
3T + 20
ns
TIn0, TIn1 low-level width
n = 0, 1
2T
sam
+ 20
Note
ns
TIn low-level width
t
TILn
<61>
n = 2 to 5
3T + 20
ns
Note T
sam
(count clock cycle) can be selected as follows by setting the PRMn2 to PRMn0 bits of prescaler mode
register n, n1 (PRMn, PRMn1).
When n = 0 (TM0): T
sam
= 2T, 4T, 16T, 64T, 256T or 1/INTWTI cycle
When n = 1 (TM1): T
sam
= 2T, 4T, 16T, 32T, 128T, or 256T cycle
However, when the TIn0 valid edge is selected as the count clock, T
sam
= 2T.
Remark T= 1/f
XX
<60>
<61>
Tln
Remark n = 00, 01, 10, 11, 2 to 5
Data Sheet U14527EJ3V0DS
38
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
CSI Timing
(1) Master mode (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
t
KCY1
<62>
400
ns
SCKn high-/low-level width
t
KH1
, t
KL1
<63>
140
ns
SIn setup time (to SCKn
)
t
SIK1
<64>
50
ns
SIn hold time (from SCKn
)
t
KSI1
<65>
50
ns
Delay time from SCKn
to SOn output
t
KSO1
<66>
60
ns
Remark n = 0 to 2
(2) Slave mode (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
t
KCY2
<62>
400
ns
SCKn high-/low-level width
t
KH2
, t
KL2
<63>
140
ns
SIn setup time (to SCKn
)
t
SIK2
<64>
50
ns
SIn hold time (from SCKn
)
t
KSI2
<65>
50
ns
Delay time from SCKn
to SOn output
t
KSO2
<66>
60
ns
Remark n = 0 to 2
<65>
<66>
<64>
<62>
<63>
<63>
Remark n = 0 to 2
SCKn (I/O)
SIn (input)
SOn (output)
Input data
Output data
Hi-Z
Hi-Z
Data Sheet U14527EJ3V0DS
39
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
UART Timing (T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASCKn cycle time
t
KCY13
<67>
200
ns
ASCKn high-level width
t
KH13
<68>
80
ns
ASCKn low-level width
t
KL13
<69>
80
ns
Remark n = 0 or 1
<68>
<69>
<67>
ASCKn (input)
Remark n = 0 or 1
Data Sheet U14527EJ3V0DS
40
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
I
2
C Bus Mode (
PD70F3015BY, 70F3017AY only)
(T
A
= 40 to +85 C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, C
L
= 50 pF)
Normal Mode
High-Speed Mode
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
Unit
SCL clock frequency
f
CLK
0
100
0
400
kHz
Bus-free time (between
stop/start conditions)
t
BUF
<70>
4.7
1.3
s
Hold time
Note 1
t
HD:STA
<71>
4.0
0.6
s
SCL clock low-level width
t
LOW
<72>
4.7
1.3
s
SCL clock high-level width
t
HIGH
<73>
4.0
0.6
s
Setup time for start/restart
condition
t
SU:STA
<74>
4.7
0.6
s
CBUS
compatible
master
5.0
s
Data hold
time
I
2
C mode
t
HD:DAT
<75>
0
Note 2
0
Note 2
0.9
Note 3
s
Data setup time
t
SU:DAT
<76>
250
100
Note 4
ns
SDA and SCL signal rise
time
t
R
<77>
1000
20 + 0.1Cb
Note 5
300
ns
SDA and SCL signal fall
time
t
F
<78>
300
20 + 0.1Cb
Note 5
300
ns
Stop condition setup time
t
SU:STO
<79>
4.0
0.6
s
Width of spike pulse
suppressed by input filter
t
SP
<80>
0
50
ns
Capacitance load of each
bus line
Cb
400
400
pF
Notes 1. At the start condition, the first clock pulse is generated after the hold time.
2. The system requires a minimum of 300 ns hold time internally for the SDA signal in order to occupy the
undefined area at the falling edge of SCL.
3. If the system does not extend the SCL signal low hold time (t
LOW
), only the maximum data hold time
(t
HD:DAT
) needs to be satisfied.
4. The high-speed mode I
2
C bus can be used in the normal-mode I
2
C bus system. In this case, set the
high-speed mode I
2
C bus so that it meets the following conditions.
If the system does not extend the SCL signal's low state hold time:
t
SU:DAT
250 ns
If the system extends the SCL signal's low state hold time:
Transmit the following data bit to the SDA line prior to the SCL line release (t
Rmax.
+ t
SU:DAT
= 1,000 +
250 = 1,250 ns: Normal mode I
2
C bus specification).
5.
Cb: Total capacitance of one bus line (unit: pF)
Remark The maximum operating frequency of the
PD70F3015BY and PD70F3017AY is f
XX
= 17 MHz.
Data Sheet U14527EJ3V0DS
41
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
I
2
C Bus Mode (
PD70F3015BY, 70F3017AY only)
A/D Converter
(T
A
= 40 to +85 C, V
DD
= AV
DD
= AV
REF
= 2.7 to 3.6 V, V
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
10
10
bit
Overall error
Note 1
0.8
%FSR
Conversion time
t
CONV
5
100
s
Zero-scale error
Note 1
0.4
%FSR
Full-scale error
Note 1
0.4
%FSR
Integral linearity error
Note 2
4
LSB
Differential linearity error
Note 2
4
LSB
Analog reference voltage
AV
REF
AV
REF
=
AV
DD
2.7
3.6
V
Analog input voltage
V
IAN
AV
SS
AV
REF
V
AV
REF
current
AI
REF
360
500
A
AV
DD
Power supply current
AI
DD
1
3
mA
Notes 1. Excluding quantization error (
0.05% FSR).
2. Excluding quantization error (
0.5 LSB)
Remark LSB: Least Significant Bit
FSR: Full Scale Range
Stop
condition
Start
condition
Restart
condition
Stop
condition
SCL (I/O)
SDA (I/O)
<71>
<70>
<72>
<73
<77>
<77>
<78>
<78>
<75>
<76>
<74>
<71>
<79>
<80>
Data Sheet U14527EJ3V0DS
42
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Flash Memory Programming Mode
Write/erase characteristics (T
A
= 10 to 40
C, V
DD
= AV
DD
= BV
DD
= 3.0 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
PP
supply voltage
V
PP2
During flash memory
programming
7.5
7.8
8.1
V
V
DD
supply current
I
DD
When V
PP
= V
PP2
, f
XX
= 20
MHz
67
mA
V
PP
supply current
I
PP
V
PP
= V
PP2
200
mA
Step erase time
t
ER
Note 1
0.2
s
Overall erase time per area
t
ERA
When the step erase time
= 0.2 s, Note 2
20
s/area
Write-back time
t
WB
Note 3
1
ms
Number of write-backs per
write-back command
C
WB
When the write-back time
= 1 ms, Note 4
300
Count/write-
back
command
Number of erase/write-backs
C
ERWB
16
Count
Step writing time
t
WR
Note 5
20
s
Overall writing time per word
t
WRW
When the step writing
time = 20
s (1 word = 4
bytes), Note 6
20
200
s/word
Number of rewrites per area
C
ERWR
1 erase + 1 write after
erase = 1 rewrite, Note 7
20
Count/area
Notes 1.
The recommended setting value of the step erase time is 0.2 s.
2.
The prewrite time prior to erasure and the erase verify time (write-back time) are not included.
3.
The recommended setting value of the write-back time is 1 ms.
4.
Write-back is executed once by the issuance of the write-back command. Therefore, the retry count
must be the maximum value minus the number of commands issued.
5.
The recommended setting value of the step writing time is 20
s.
6.
20
s is added to the actual writing time per word. The internal verify time during and after the writing
is not included.
7.
When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and
"write only".
Example (P: Write, E: Erase)
Shipped product
P E P E P: 3 rewrites
Shipped product
E P E P E P: 3 rewrites
Remarks 1.
When the PG-FP3 is used, a time parameter required for writing/erasing by downloading
parameter files is automatically set. Do not change the settings unless otherwise specified.
2.
Area 0 = 000000H to 01FFFFH (
PD70F3017A, 70F3017AY only)
Area 1 = 020000H to 03FFFFH (
PD70F3017A, 70F3017AY only)
Data Sheet U14527EJ3V0DS
43
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
3. PACKAGE DRAWINGS
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
16.00
0.20
14.00
0.20
0.50 (T.P.)
1.00
J
16.00
0.20
K
C
14.00
0.20
I
0.08
1.00
0.20
L
0.50
0.20
F
1.00
N
P
Q
0.08
1.40
0.05
0.10
0.05
S100GC-50-8EU, 8EA-2
S
1.60 MAX.
H
0.22+0.05
-0.04
M
0.17+0.03
-0.07
R
3
+7
-3
1
25
26
50
100
76
75
51
S
S
N
J
detail of lead end
C
D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
Data Sheet U14527EJ3V0DS
44
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
121-PIN PLASTIC FBGA (12x12)
ITEM
MILLIMETERS
D
12.00
0.10
E
12.00
0.10
0.10
P121F1-80-EA6
INDEX MARK
A
w
0.20
A2
A1
A
1.13
e
0.80
1.48
0.10
0.35
0.06
x
y
0.20
y1
1.20
ZD
1.20
ZE
0.08
ZE
A2
A1
b
ZD
B
A
S
S
w
A
S
w
B
S
y1
S
e
y
13
12
11
10
9
8
7
6
5
4
3
2
1
N M L K J H G F E D C B A
S
x
A B
M
E
D
b
0.50+0.05
-0.10
Data Sheet U14527EJ3V0DS
45
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
4. RECOMMENDED SOLDERING CONDITIONS
The
PD70F3015B, 70F3015BY, 70F3017A, and 70F3017AY should be soldered and mounted under the following
recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your sales representative.
Table 4-1. Surface Mounting Type Soldering Conditions
(1)
PD70F3017AGC-8EU: 100-pin plastic LQFP (fine-pitch) (14 14 mm)
PD70F3017AYGC-8EU: 100-pin plastic LQFP (fine-pitch) (14 14 mm)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235 C, Time: 30 seconds max. (at 210 C or higher),
Count: Two times or less
Exposure limit: 3 days
Note
(after that, prebake at 125 C for 10 hours)
IR35-103-2
VPS
Package peak temperature: 215 C, Time: 40 seconds max. (at 200 C or higher),
Count: Two times or less
Exposure limit: 3 days
Note
(after that, prebake at 125 C for 10 hours)
VP15-103-2
Partial heating
Pin temperature: 300 C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25 C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
(2)
PD70F3015BGC-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
PD70F3015BYGC-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14 mm)
PD70F3017AF1-EA6: 121-pin plastic FBGA (12 12 mm)
PD70F3017AYF1-EA6: 121-pin plastic FBGA (12 12 mm)
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
Package peak temperature: 235 C, Time: 30 seconds max. (at 210 C or higher),
Count: Two times or less
Exposure limit: 7 days
Note
(after that, prebake at 125 C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215 C, Time: 40 seconds max. (at 200 C or higher),
Count: Two times or less
Exposure limit: 7 days
Note
(after that, prebake at 125 C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300 C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25 C or less and 65% RH or less for the allowable storage period.
Data Sheet U14527EJ3V0DS
46
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Caution
The
PD70F3015BY and PD70F3017AY contain an I
2
C bus interface circuit.
Purchase of NEC I
2
C components conveys a license under the Philips I
2
C Patent Rights to use
these components in an I
2
C system, provided that the system conforms to the I
2
C Standard
Specification as defined by Philips.
Data Sheet U14527EJ3V0DS
47
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
PD70F3015B, 70F3015BY, 70F3017A, 70F3017AY
Reference document
Electrical Characteristics for Microcomputer (U15170J)
Note
Note
This document number is that of the Japanese version.
Related document
PD703014A, 703014AY, 703014B, 703014BY, 703015A, 703015AY, 703015B, 703015BY,
703017A, 703017AY Data Sheet (U14526E)
V850 Family and V850/SA1 are trademarks of NEC Corporation.
M8E 00. 4
The information in this document is current as of May, 2001. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
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"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
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