Document Outline
- Cover
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- DIFFERENCES BETWEEN V850/SV1 PRODUCTS
- PIN CONFIGURATION
- PIN IDENTIFICATION
- INTERNAL BLOCK DIAGRAM
- 1. PIN FUNCTIONS
- 1.1 Port Pins
- 1.2 Non-Port Pins
- 1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused
- 2. ELECTRICAL SPECIFICATIONS
- 3. PACKAGE DRAWING
- 4. RECOMMENDED SOLDERING CONDITIONS
DATA SHEET
MOS INTEGRATED CIRCUIT
PD70F3040, 70F3040Y
V850/SV1
TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Document No. U14622EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
PRELIMINARY PRODUCT INFORMATION
PRELIMINARY DATA SHEET
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
DESCRIPTION
The
PD70F3040 and
PD70F3040Y are products that substitute flash memory for the mask ROM of the
PD703039, 703040, 703041 and
PD703039Y, 703040Y, 703041Y, respectively. Since the
PD70F3040 and
70F3040Y can be read and written while mounted on the board, these products are ideal for evaluation during
system development, multiple-version small-scale production or quick product release.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
V850/SV1 User's Manual Hardware:
U14462E
V850 Family
TM
User's Manual Architecture:
U10243E
FEATURES
Pin compatible with
PD703039, 703040, 703041, 703039Y, 703040Y, and 703041Y
For mass production, these can be replaced by a mask ROM version.
PD70F3040
PD703039, 703040, 703041
PD70F3040Y
PD703039Y, 703040Y, 703041Y
ORDERING INFORMATION
Part Number
Package
PD70F3040GM-UEU
PD70F3040YGM-UEU
176-pin plastic LQFP (fine-pitch) (24
24 mm)
176-pin plastic LQFP (fine-pitch) (24
24 mm)
DIFFERENCES BETWEEN V850/SV1 PRODUCTS
Internal ROM
Internal RAM
I
2
C
V
PP
Pin
PD70F3040
None
PD70F3040Y
256 KB (flash memory)
16 KB
Provided
Provided
PD703039
None
PD703039Y
8 KB
Provided
PD703040
None
PD703040Y
256 KB (mask ROM)
16 KB
Provided
PD703041
None
PD703041Y
192 KB (mask ROM)
8 KB
Provided
None
2000
Preliminary Data Sheet U14622EJ1V0DS00
2
PD70F3040, 70F3040Y
PIN CONFIGURATION
176-pin plastic LQFP (fine-pitch) (24
24 mm)
PD70F3040GM-UEU
PD70F3040YGM-UEU
Notes 1. Connect to V
SS
in normal operation mode.
2. SCL0, SCL1, SDA0, and SDA1 are valid only for the
PD70F3040Y.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
P147
P146
P145/RTPTRG1
P144/TI9/INTTI9
P143/INTCP93
P142/INTCP92
P141/INTCP91
P140/INTCP90
P137/TO81
P136/TO80
P135/TCLR8/INTTCLR8
P134/TI8/INTTI8
P133/INTCP83
P132/INTCP82
P131/INTCP81
P130/INTCP80
V
SS
V
DD
P07/INTP6
P06/INTP5/RTPTRG0
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P157/RTP17
P156/RTP16
P12/SCK0/SCL0
Note 2
P13/SI1/RXD0
P14/SO1/TXD0
P15/SCK1/ASCK0
P20/SI2/SDA1
Note 2
P21/SO2
P22/SCK2/SCL1
Note 2
P23/SI3/RXD1
P24/SO3/TXD1
P25/SCK3/ASCK1
P26/TI2/TO2
P27/TI3/TO3
V
DD
V
SS
P30/TI000
P31/TI001
P32/TI010
P33/TI011
P34/TO0
P35/TO1
P36/TI4/TO4
P37/TI5/TO5
P120/SI4
P121/SO4
P122/SCK4
P123/CLO
P124/TI6/TO6
P125/TI7/TO7
P126/TI10/TO10
P127/TI11/TO11
P180
P181
P182
P183
P184
P185
P186
P187
V
DD
V
SS
P190
P191
P192
P193
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
P194
P195
P196
P197
P170/KR0
P171/KR1
P172/KR2
P173/KR3
P174/KR4
P175/KR5
P176/KR6
P177/KR7
P160/PWM0
P161/PWM1
P162/PWM2
P163/PWM3
P164/CSYNCIN
P165/VSOUT
P166/HSOUT0
P167/HSOUT1
V
PP
Note 1
RESET
XT1
XT2
V
DD
X2
X1
V
SS
P100/RTP00
P101/RTP01
P102/RTP02
P103/RTP03
P104/RTP04
P105/RTP05
P106/RTP06
P107/RTP07
V
DD
V
SS
P150/RTP10
P151/RTP11
P152/RTP12
P153/RTP13
P154/RTP14
P155/RTP15
P11/SO0
P10/SI0/SDA0
Note 2
P113
P112
P111
P110
WAIT
CLKOUT
P65/A21
P64/A20
P63/A19
P62/A18
P61/A17
P60/A16
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
BV
SS
BV
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P96/HLDRQ
P95/HLDAK
P94/ASTB
P93/DSTB/RD
P92/R/W/WRH
P91/UBEN
P90/LBEN/WRL
V
SS
V
DD
AV
DD
AV
SS
AV
REF
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
Preliminary Data Sheet U14622EJ1V0DS00
3
PD70F3040, 70F3040Y
PIN IDENTIFICATION
A16 to A21:
Address Bus
P120 to P127:
Port 12
AD0 to AD15:
Address/Data Bus
P130 to P137:
Port 13
ADTRG:
AD Trigger Input
P140 to P147:
Port 14
ANI0 to ANI15:
Analog Input
P150 to P157:
Port 15
ASCK0, ASCK1:
Asynchronous Serial Clock
P160 to P167:
Port 16
ASTB:
Address Strobe
P170 to P177:
Port 17
AV
DD
:
Analog Power Supply
P180 to P187:
Port 18
AV
REF
:
Analog Reference Voltage
P190 to P197:
Port 19
AV
SS
:
Analog Ground
PWM0 to PWM3:
Pulse Width Modulation
BV
DD
:
Bus Interface Power Supply
RD:
Read
BV
SS
:
Bus Interface Ground
RESET:
Reset
CLKOUT:
Clock Output
RTP00 to RTP07,:
Real-time Output Port
CLO:
Clock Output (divided)
RTP10 to RTP17
CSYNCIN:
Csync Input
RTPTRG0, RTPTRG1: RTP Trigger Input
DSTB:
Data Strobe
R/W:
Read/Write Status
HLDAK:
Hold Acknowledge
RXD0, RXD1:
Receive Data
HLDRQ:
Hold Request
SCK0 to SCK4:
Serial Clock
HSOUT0, HSOUT1: Hsync Output
SCL0, SCL1:
Serial Clock
INTCP80 to INTCP83,: Interrupt Request from Peripherals
SDA0, SDA1:
Serial Data
INTCP90 to INTCP93,
SI0 to SI4:
Serial Input
INTP0 to INTP6,
SO0 to SO4:
Serial Output
INTTCLR8,
TCLR8:
Timer Clear
INTTI8, INTTI9
TI000, TI001, TI010,: Timer Input
KR0 to KR7:
Key Return
TI011, TI2 to TI11
LBEN:
Lower Byte Enable
TO0 to TO7, TO80,:
Timer Output
NMI:
Non-Maskable Interrupt Request
TO81, TO10, TO11
P00 to P07:
Port 0
TXD0, TXD1:
Transmit Data
P10 to P15:
Port 1
UBEN:
Upper Byte Enable
P20 to P27:
Port 2
V
DD
:
Power Supply
P30 to P37:
Port 3
V
PP
:
Programming Power Supply
P40 to P47:
Port 4
VSOUT:
Vsync Output
P50 to P57:
Port 5
V
SS
:
Ground
P60 to P65:
Port 6
WAIT:
Wait
P70 to P77:
Port 7
WRH:
Write Strobe High Level Data
P80 to P87:
Port 8
WRL:
Write Strobe Low Level Data
P90 to P96:
Port 9
X1, X2:
Crystal for Main System Clock
P100 to P107:
Port 10
XT1, XT2:
Crystal for Subsystem Clock
P110 to P113:
Port 11
Preliminary Data Sheet U14622EJ1V0DS00
4
PD70F3040, 70F3040Y
INTERNAL BLOCK DIAGRAM
Notes 1. 256 KB (Flash memory)
2. SDA0, SDA1, SCL0, and SCL1 are valid only for the
PD70F3040Y.
3. The I
2
C function is valid only for the
PD70F3040Y.
INTC
ROM
CPU
BCU
ALU
PC
32-bit barrel
shifter
ROM correction
Multiplier
16
16
32
Instruction
queue
System
register
General registers
32 bits
32
RAM
HLDRQ
HLDAK
ASTB
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15
NMI
INTP0 to INTP6
CSYNCIN
KR0 to KR7
PWM0 to PWM3
SO0
SI0/SDA0
Note 2
SCK0/SCL0
Note 2
SO2
SI2/SDA1
Note 2
SCK2/SCL1
Note 2
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
TO0, TO1
TCLR8
TO80, TO81
TI8, TI9
TI000, TI001,
TI010, TI011
HSOUT0, HSOUT1,
VSOUT
TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7
TI10/TO10, TI11/TO11
CLKOUT
CLO
X1
X2
XT1
XT2
RESET
V
DD
V
SS
BV
DD
BV
SS
V
PP
Ports
Watch timer
RTP
RTP00 to RTP07,
RTP10 to RTP17
RTPTRG0,
RTPTRG1
Watchdog timer
A/D
converter
Note 1
16 KB
SIO
CG
CSI0/I
2
C0
Note 3
CSI2/I
2
C1
Note 3
CSI1/UART0
CSI3/UART1
Variable
length CSI4
Key return function
DMAC: 6 ch
PWM
Vsync/Hsync
Timer/counter
16-bit timers:
TM0, TM1
8-bit timers:
TM2 to TM7,
TM10, TM11
24-bit timers:
TM8, TM9
P190 to P197
P180 to P187
P170 to P177
P160 to P167
P150 to P157
P140 to P147
P130 to P137
P120 to P127
P110 to P113
P100 to P107
P90 to P96
P80 to P87
P70 to P77
P60 to P65
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P15
P00 to P07
AV
DD
AV
REF
AV
SS
ANI0 to ANI15
ADTRG
INTCP80 to INTCP83,
INTCP90 to INTCP93
INTTCLR8
INTTI8, INTTI9
Preliminary Data Sheet U14622EJ1V0DS00
5
PD70F3040, 70F3040Y
CONTENTS
1.
PIN FUNCTIONS.................................................................................................................................. 6
1.1
Port Pins.................................................................................................................................................... 6
1.2
Non-Port Pins........................................................................................................................................... 10
1.3
Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins ....................... 14
2.
ELECTRICAL SPECIFICATIONS...................................................................................................... 18
3.
PACKAGE DRAWING ....................................................................................................................... 39
4.
RECOMMENDED SOLDERING CONDITION.................................................................................. 40
6
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
1. PIN FUNCTIONS
1.1 Port Pins
(1/4)
Pin Name
I/O
PULL
Function
Alternate Function
P00
NMI
P01
INTP0
P02
INTP1
P03
INTP2
P04
INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG0
P07
I/O
Yes
Port 0
8-bit I/O port
Input/output mode can be specified in 1-bit units.
INTP6
P10
SI0/SDA0
P11
SO0
P12
SCK0/SCL0
P13
SI1/RXD0
P14
SO1/TXD0
P15
I/O
Yes
Port 1
6-bit I/O port
Input/output mode can be specified in 1-bit units.
SCK1/ASCK0
P20
SI2/SDA1
P21
SO2
P22
SCK2/SCL1
P23
SI3/RXD1
P24
SO3/TXD1
P25
SCK3/ASCK1
P26
TI2/TO2
P27
I/O
Yes
Port 2
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TI3/TO3
P30
TI000
P31
TI001
P32
TI010
P33
TI011
P34
TO0
P35
TO1
P36
TI4/TO4
P37
I/O
Yes
Port 3
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TI5/TO5
P40
AD0
P41
AD1
P42
AD2
P43
AD3
P44
I/O
No
Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD4
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
7
PD70F3040, 70F3040Y
(2/4)
Pin Name
I/O
PULL
Function
Alternate Function
P45
AD5
P46
AD6
P47
I/O
No
Port 4
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD7
P50
AD8
P51
AD9
P52
AD10
P53
AD11
P54
AD12
P55
AD13
P56
AD14
P57
I/O
No
Port 5
8-bit I/O port
Input/output mode can be specified in 1-bit units.
AD15
P60
A16
P61
A17
P62
A18
P63
A19
P64
A20
P65
I/O
No
Port 6
6-bit I/O port
Input/output mode can be specified in 1-bit units.
A21
P70
ANI0
P71
ANI1
P72
ANI2
P73
ANI3
P74
ANI4
P75
ANI5
P76
ANI6
P77
Input
No
Port 7
8-bit input port
ANI7
P80
ANI8
P81
ANI9
P82
ANI10
P83
ANI11
P84
ANI12
P85
ANI13
P86
ANI14
P87
Input
No
Port 8
8-bit input port
ANI15
P90
LBEN/WRL
P91
UBEN
P92
R/W/WRH
P93
I/O
No
Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
DSTB/RD
Remark
PULL: On-chip pull-up resistor
8
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
(3/4)
Pin Name
I/O
PULL
Function
Alternate Function
P94
ASTB
P95
HLDAK
P96
I/O
No
Port 9
7-bit I/O port
Input/output mode can be specified in 1-bit units.
HLDRQ
P100
RTP00
P101
RTP01
P102
RTP02
P103
RTP03
P104
RTP04
P105
RTP05
P106
RTP06
P107
I/O
Yes
Port 10
8-bit I/O port
Input/output mode can be specified in 1-bit units.
RTP07
P110
P111
P112
P113
I/O
No
Port 11
4-bit I/O port
Input/output mode can be specified in 1-bit units.
P120
SI4
P121
SO4
P122
SCK4
P123
CLO
P124
TI6/TO6
P125
TI7/TO7
P126
TI10/TO10
P127
I/O
No
Port 12
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TI11/TO11
P130
INTCP80
P131
INTCP81
P132
INTCP82
P133
INTCP83
P134
TI8/INTTI8
P135
TCLR8/INTTCLR8
P136
TO80
P137
I/O
No
Port 13
8-bit I/O port
Input/output mode can be specified in 1-bit units.
TO81
P140
INTCP90
P141
INTCP91
P142
INTCP92
P143
INTCP93
P144
TI9/INTTI9
P145
RTPTRG1
P146
P147
I/O
No
Port 14
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
9
PD70F3040, 70F3040Y
(4/4)
Pin Name
I/O
PULL
Function
Alternate Function
P150
RTP10
P151
RTP11
P152
RTP12
P153
RTP13
P154
RTP14
P155
RTP15
P156
RTP16
P157
I/O
No
Port 15
8-bit I/O port
Input/output mode can be specified in 1-bit units.
RTP17
P160
PWM0
P161
PWM1
P162
PWM2
P163
PWM3
P164
CSYNCIN
P165
VSOUT
P166
HSOUT0
P167
I/O
No
Port 16
8-bit I/O port
Input/output mode can be specified in 1-bit units.
HSOUT1
P170
KR0
P171
KR1
P172
KR2
P173
KR3
P174
KR4
P175
KR5
P176
KR6
P177
I/O
Yes
Port 17
8-bit I/O port
Input/output mode can be specified in 1-bit units.
KR7
P180
P181
P182
P183
P184
P185
P186
P187
I/O
No
Port 18
8-bit I/O port
Input/output mode can be specified in 1-bit units.
P190
P191
P192
P193
P194
P195
P196
P197
I/O
No
Port 19
8-bit I/O port
Input/output mode can be specified in 1-bit units.
Remark
PULL: On-chip pull-up resistor
10
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
1.2 Non-Port Pins
(1/4)
Pin Name
I/O
PULL
Function
Alternate Function
A16 to A21
Output
No
Address bus 16 to 21
P60 to P65
AD0 to AD7
P40 to P47
AD8 to AD15
I/O
No
Address/data multiplexed bus 0 to 15
P50 to P57
ADTRG
Input
Yes
A/D converter external trigger input
P05/INTP4
ANI0 to ANI7
Input
No
P70 to P77
ANI8 to ANI15
Input
No
Analog input to A/D converter
P80 to P87
ASCK0
P15/SCK1
ASCK1
Input
Yes
Baud rate clock input for UART0 and UART1
P25/SCK3
ASTB
Output
No
External address strobe signal output
P94
AV
DD
Positive power supply for A/D converter and ports used for
alternate functions
AV
REF
Input
Reference voltage input for A/D converter
AV
SS
Ground potential for A/D converter and ports used for alternate
functions
BV
DD
Positive power supply for bus interface and ports used for
alternate functions
BV
SS
Ground potential for bus interface and ports used for alternate
functions
CLKOUT
Output
Internal system clock output
CLO
Output
No
CLO output signal
P123
CSYNCIN
Input
No
Csync signal input
P164
DSTB
Output
No
External data strobe signal output
P93/RD
HLDAK
Output
No
Bus hold acknowledge output
P95
HLDRQ
Input
No
Bus hold request input
P96
HSOUT0
Hsync signal output before compensation
P166
HSOUT1
Output
No
Hsync signal output after compensation
P167
INTCP80 to
INTCP83
Input
No
External capture input for CC80 to CC83
P130 to P133
INTCP90 to
INTCP93
Input
No
External capture input for CP90 to CP93
P140 to P143
INTP0 to INTP3
External interrupt request input (analog noise elimination)
P01 to P04
INTP4
P05/ADTRG
INTP5
External interrupt request input (digital noise elimination)
P06/RTPTRG0
INTP6
Input
Yes
External interrupt request input (digital noise elimination
supporting remote controller)
P07
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
11
PD70F3040, 70F3040Y
(2/4)
Pin Name
I/O
PULL
Function
Alternate Function
INTTCLR8
Input
No
P135/TCLR8
INTTI8
P134/TI8
INTTI9
Input
No
External interrupt request input (digital noise elimination)
P144/TI9
KR0 to KR7
Input
Yes
Key return input
P170 to P177
LBEN
Output
No
Lower byte enable signal output for external data bus
P90/WRL
NMI
Input
Yes
Non-maskable interrupt request input
P00
PWM0 to PWM3
Output
No
Output of PWM channels 0 to 3
P160 to P163
RD
Output
No
Bus read strobe signal output
P93/DSTB
RESET
Input
System reset input
RTP00 to RTP07
P100 to P107
RTP10 to RTP17
Output
Yes
Real-time output port
P150 to P157
RTPTRG0
Yes
P06
RTPTRG1
Input
No
RTP external trigger input
P146
R/W
Output
No
External read/write status output
P92/WRH
RXD0
P13/SI1
RXD1
Input
Yes
Serial receive data input for UART0 and UART1
P23/SI3
SCK0
P12/SCL0
SCK1
P15/ASCK0
SCK2
P22/SCL1
SCK3
Yes
Serial clock I/O for CSI0 to CSI3 (3-wire mode)
P25/ASCK1
SCK4
I/O
No
Variable-length CSI4 serial clock I/O
P122
SCL0
P12/SCK0
SCL1
I/O
Yes
Serial clock I/O for I
2
C0 and I
2
C1
(
PD70F3040Y)
P22/SCK2
SDA0
P10/SI0
SDA1
I/O
Yes
Serial transmit/receive data I/O for I
2
C0 and I
2
C1
(
PD70F3040Y)
P20/SI2
SI0
P10/SDA0
SI1
P13/RXD0
SI2
P20/SDA1
SI3
Yes
Serial receive data input for CSI0 to CSI3 (3-wire mode)
P23/RXD1
SI4
Input
No
Variable-length CSI4 serial receive data input (3-wire mode)
P120
SO0
P11
SO1
P14/TXD0
SO2
P21
SO3
Yes
Serial transmit data output for CSI0 to CSI3
P24/TXD1
SO4
Output
No
Variable-length CSI4 serial transmit data output
P121
TCLR8
Input
No
External clear input for TM8
P135/INTTCLR8
Remark
PULL: On-chip pull-up resistor
12
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
(3/4)
Pin Name
I/O
PULL
Function
Alternate Function
TI000
External count clock input/external capture trigger input for TM0
P30
TI001
External capture trigger input for TM0
P31
TI010
External count clock input/external capture trigger input for TM1
P32
TI011
External capture trigger input for TM1
P33
TI2
External count clock input for TM2
P26/TO2
TI3
External count clock input for TM3
P27/TO3
TI4
External count clock input for TM4
P36/TO4/A15
TI5
Yes
External count clock input for TM5
P37/TO5
TI6
External count clock input for TM6
P124/TO6
TI7
External count clock input for TM7
P125/TO7
TI8
External count clock input for TM8
P134/INTTI8
TI9
External count clock input for TM9
P144/INTTI9
TI10
External count clock input for TM10
P126/TO10
TI11
Input
No
External count clock input for TM11
P127/TO11
TO0
Pulse signal output for TM0
P34
TO1
Pulse signal output for TM1
P35
TO2
Pulse signal output for TM2
P26/TI2
TO3
Pulse signal output for TM3
P27/TI3
TO4
Pulse signal output for TM4
P36/TI4
TO5
Yes
Pulse signal output for TM5
P37/TI5
TO6
Pulse signal output for TM6
P124/TI6
TO7
Pulse signal output for TM7
P125/TI7
TO80
Pulse signal output 0 for TM8
P136
TO81
Pulse signal output 1 for TM8
P137
TO10
Pulse signal output for TM10
P126/TI10
TO11
Output
No
Pulse signal output for TM11
P127/TI11
TXD0
P14/SO1
TXD1
Output
Yes
Serial transmit data output for UART0 and UART1
P24/SO3
UBEN
Output
No
Higher byte enable signal output for external data bus
P91
V
DD
Positive power supply pin
V
PP
High voltage application pin for program write/verify
VSOUT
Output
No
Vsync signal output
P165
V
SS
Ground potential
WAIT
Input
No
External WAIT signal input
WRH
Higher byte write strobe signal output for external data bus
P92/R/W
WRL
Output
No
Lower byte write strobe signal output for external data bus
P90/LBEN
Remark
PULL: On-chip pull-up resistor
Preliminary Data Sheet U14622EJ1V0DS00
13
PD70F3040, 70F3040Y
(4/4)
Pin Name
I/O
PULL
Function
Alternate Function
X1
Input
X2
No
Resonator connection for main system clock
XT1
Input
XT2
No
Resonator connection for subsystem clock
Remark
PULL: On-chip pull-up resistor
14
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins
Table 1-1 shows the input/output circuit type of each pin and the recommended connection of unused pins.
For the input/output configuration of each type, refer to Figure 1-1.
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (1/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Power Supply
Recommended Connection Method
P00
NMI
P01 to P04
INTP0 to INTP3
P05
INTP4/ADTRG
P06
INTP5/RTPTRG0
P07
INTP6
5-W
V
DD
P10
SI0/SDA0
10-F
P11
SO0
10-E
P12
SCK0/SCL0
10-F
P13
SI1/RXD0
5-W
P14
SO1/TXD0
10-E
P15
SCK1/ASCK0
10-F
V
DD
P20
SI2/SDA1
10-F
P21
SO2
10-E
P22
SCK2/SCL1
10-F
P23
SI3/RXD1
5-W
P24
SO3/TXD1
10-E
P25
SCK3/ASCK1
10-F
P26, P27
TI2/TO2, TI3/TO3
5-W
V
DD
P30, P31
TI000, TI001
P32, P33
TI010, TI011
5-W
P34, P35
TO0, TO1
5-A
P36
TI4/TO4
P37
TI5/TO5
5-W
V
DD
Input:
Independently connect to V
DD
or V
SS
via a resistor
Output:
Leave open
P40 to P47
AD0 to AD7
5
BV
DD
P50 to P57
AD8 to AD15
5
BV
DD
P60 to P65
A16 to A21
5
BV
DD
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output:
Leave open
P70 to P77
ANI0 to ANI7
9
AV
DD
P80 to P87
ANI8 to ANI15
9
AV
DD
Connect to AV
SS
P90
LBEN/WRL
P91
UBEN
P92
R/W/WRH
P93
DSTB/RD
P94
ASTB
P95
HLDAK
P96
HLDRQ
5
BV
DD
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output:
Leave open
P100 to P107
RTP00 to RTP07
10-E
V
DD
P110 to P113
5
V
DD
P120
SI4
5-K
V
DD
Input:
Independently connect to V
DD
or V
SS
via a resistor
Output:
Leave open
Preliminary Data Sheet U14622EJ1V0DS00
15
PD70F3040, 70F3040Y
Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (2/2)
Pin
Alternate Function
I/O Circuit
Type
I/O Buffer
Power Supply
Recommended Connection Method
P121
SO4
10-G
P122
SCK4
10-H
P123
CLO
5
P124
TI6/TO6
P125
TI7/TO7
P126
TI10/TO10
P127
TI11/TO11
5-K
V
DD
P130 to P133
INTCP80 to INTCP83
P134
TI8/INTTI8
P135
TCLR8/INTTCLR8
5-K
P136, P137
TO80, TO81
5
V
DD
P140 to P143
INTCP90 to INTCP93
P144
TI9/INTTI9
P145
RTPTRG1
5-K
P146, P147
5
V
DD
P150 to P157
RTP10 to RTP17
5
V
DD
P160 to P163
PWM0 to PWM3
5
P164
CSYNCIN
5-K
P165
VSOUT
P166
HSOUT0
P167
HSOUT1
5
V
DD
P170 to P177
KR0 to KR7
5-K
V
DD
P180 to P187
5
V
DD
P190 to P197
5
V
DD
Input:
Independently connect to V
DD
or V
SS
via a resistor
Output:
Leave open
CLKOUT
4
BV
DD
Leave open
WAIT
1
BV
DD
Connect to V
DD
via a resistor
RESET
2
V
DD
X1
V
DD
X2
V
DD
Leave open
XT1
V
DD
Connect to V
SS
XT2
V
DD
Leave open
AV
REF
Connect to AV
SS
V
PP
Connect to V
SS
V
DD
V
SS
AV
DD
Connect to V
DD
AV
SS
Connect to V
SS
BV
DD
Connect to V
DD
BV
SS
Connect to V
SS
16
Preliminary Data Sheet U14622EJ1V0DS00
PD70F3040, 70F3040Y
Figure 1-1. Pin Input/Output Circuits (1/2)
Type 1
Type 5
Type 2
Type 5-A
Type 4
Type 5-K
Schmitt-triggered input with hysteresis characteristics
Push-pull output that can be set for high impedance output
(both P-ch and N-ch are off)
IN
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pullup
enable
Data
Output
disable
P-ch
OUT
V
DD
N-ch
IN
P-ch
V
DD
N-ch
Preliminary Data Sheet U14622EJ1V0DS00
17
PD70F3040, 70F3040Y
Figure 1-1. Pin Input/Output Circuits (2/2)
Type 5-W
Type 10-F
Type 9
Type 10-G
Type 10-E
Type 10-H
Data
Output
disable
Open drain
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pullup
enable
Data
Output
disable
Open
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pullup
enable
Data
Output
disable
Open
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pullup
enable
IN
Input enable
Comparator
+
V
REF
(Threshold voltage)
P-ch
N-ch
Data
Output
disable
Input
enable
Open drain
P-ch
IN/OUT
V
DD
N-ch
Preliminary Data Sheet U14622EJ1V0DS00
18
PD70F3040, 70F3040Y
2.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25C, V
SS
= 0 V)
Parameter
Symbol
Conditions
Ratings
Unit
V
DD
0.5 to +4.6
V
AV
DD
0.5 to +4.6
V
BV
DD
0.5 to +4.6
V
AV
SS
0.5 to +0.5
V
Supply voltage
BV
SS
0.5 to +0.5
V
V
I1
Note 1 (V
DD
)
0.5 to V
DD
+ 0.5
Note 4
V
V
I2
Note 2 (BV
DD
)
0.5 to BV
DD
+ 0.5
Note 4
V
Input voltage
V
I3
V
PP
0.5 to +8.5
V
Clock input voltage
V
K
X1, XT1, V
DD
= 2.7 to 3.6 V
0.5 to V
DD
+ 1.0
Note 4
V
Analog input voltage
V
IAN
Note 3 (AV
DD
)
0.5 to AV
DD
+ 0.5
Note 4
V
Analog reference input voltage
AV
REF
AV
REF
pin
0.5 to AV
DD
+ 0.5
Note 4
V
Per pin
4.0
mA
Total for P00 to P07 and P150 to P157
25
mA
Total for P100 to P107 and P160 to P167
25
mA
Total for P170 to P177 and P190 to P197
25
mA
Total for P124 to P127 and P180 to P187
25
mA
Total for P30 to P37 and P120 to P123
25
mA
Total for P12 to P15, P20 to 27, and P110
to P113
25
mA
Total for P50 to P57, P60 to P65, and
CLKOUT
25
mA
Total for P40 to P47 and P90 to P96
25
mA
Output current, low
I
OL
Total for P130 to P137 and P140 to P147
25
mA
Per pin
4.0
mA
Total for P00 to P07 and P150 to P157
25
mA
Total for P100 to P107 and P160 to P167
25
mA
Total for P170 to P177 and P190 to P197
25
mA
Total for P124 to P127 and P180 to P187
25
mA
Total for P30 to P37 and P120 to P123
25
mA
Total for P12 to P15, P20 to 27, and P110
to P113
25
mA
Total for P50 to P57, P60 to P65, and
CLKOUT
25
mA
Total for P40 to P47 and P90 to P96
25
mA
Output current, high
I
OH
Total for P130 to P137 and P140 to P147
25
mA
V
O1
Note 1 (V
DD
)
0.5 to V
DD
+ 0.5
Note 4
V
Output voltage
V
O2
Note 2 (BV
DD
)
0.5 to BV
DD
+ 0.5
Note 4
V
Normal operation mode
40 to +85
C
Operating ambient temperature
T
A
Flash programming mode
+10 to +40
C
Storage temperature
T
stg
40 to +125
C
Notes 1. Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, RESET (including alternate-function pins)
2. Ports 4, 5, 6, 9, WAIT (including alternate-function pins)
3. Ports 7, 8 (including alternate-function pins)
4. Be sure not to exceed each absolute maximum rating (MAX.).
Preliminary Data Sheet U14622EJ1V0DS00
19
PD70F3040, 70F3040Y
Cautions
1. Avoid direct connections among the IC device output (or I/O) pins and between V
DD
or V
CC
and GND. However, direct connections among open-drain and open-connector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output contention with pins that become high-impedance.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
Capacitance (T
A
= 25C, V
DD
= V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
15
pF
I/O capacitance
C
IO
15
pF
Output capacitance
C
O
f
C
= 1 MHz
Unmeasured pins returned to 0 V
15
pF
Operating Conditions
(1) CPU Operation Frequency
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
When main system clock is operating
0.5
16
MHz
CPU operation frequency
f
CPU
When subsystem clock is operating
32.768
kHz
(2) Supply Voltage
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
2.7
3.6
V
AV
DD
2.7
3.6
V
Supply voltage
BV
DD
2.7
3.6
V
(3) Operating Frequency for Each Supply Voltage
Internal Operating Clock Frequency
Supply Voltage (V
DD
= AV
DD
= BV
DD
)
4 MHz
f
XX
16 MHz
2.7 to 3.6 V
f
XT
= 32.768 kHz
2.7 to 3.6 V
Preliminary Data Sheet U14622EJ1V0DS00
20
PD70F3040, 70F3040Y
Recommended Oscillator
(1) Main System Clock Oscillator (T
A
=
-
-
-
-
40 to +85
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency
f
XX
4
16
MHz
After reset release
2
19
/f
XX
s
Oscillation stabilization
time
After STOP mode release
Note
s
Note Values vary depending on the settings of the oscillation stabilization selection register (OSTS).
Remarks 1. Place the oscillator as close as possible to X1 and X2.
2. Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
X2
X1
Preliminary Data Sheet U14622EJ1V0DS00
21
PD70F3040, 70F3040Y
(2) Subsystem Clock Oscillator (T
A
=
-
-
-
-
40 to +85
C)
XT1
XT2
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Oscillation frequency
f
XT
32
32.768
35
kHz
Oscillation stabilization time
10
s
Remarks 1.
Place the oscillator as close as possible to XT1 and XT2.
2.
Do not wire other signal lines within the broken lines.
3. For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.
Preliminary Data Sheet U14622EJ1V0DS00
22
PD70F3040, 70F3040Y
DC Characteristics (T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, high
V
IH1
Pins in Note 1, WAIT
0.7BV
DD
BV
DD
V
V
IH2
Pins in Note 2
0.7V
DD
V
DD
V
V
IH3
Pins in Note 3, RESET
0.75V
DD
V
DD
V
V
IH4
Pins in Note 4
0.7AV
DD
AV
DD
V
V
IH5
X1, XT1, XT2
0.8V
DD
V
DD
V
Input voltage, low
V
IL1
Pins in Note 1, WAIT
BV
SS
0.5
0.3BV
DD
V
V
IL2
Pins in Note 2
V
SS
0.5
0.3V
DD
V
V
IL3
Pins in Note 3, RESET
V
SS
0.5
0.3V
DD
V
V
IL4
Pins in Note 4
AV
SS
0.5
0.3AV
DD
V
V
IL5
X1, XT1, XT2
V
SS
0.2V
DD
V
V
OH1
Note 1, CLKOUT
I
OH
= 3 mA
0.8BV
DD
V
Output voltage, high
V
OH2
Notes 2, 3
I
OH
= 1 mA
0.8V
DD
V
V
OL1
Note 1, CLKOUT
0.4
V
V
OL2
Notes 2, 3 (excluding
P10, 12, 20, 22)
0.4
V
Output voltage, low
V
OL3
P10, 12, 20, 22
0.4
V
I
LIH1
Other than X1,
XT1, XT2
5
A
Input leakage current, high
I
LIH2
V
I
= V
DD
= AV
DD
=
BV
DD
X1, XT1, XT2
20
A
I
LIL1
Other than X1,
XT1, XT2
5
A
Input leakage current, low
I
LIL2
V
I
= 0 V
X1, XT1, XT2
20
A
Output leakage current, high
I
LOH
V
O
= V
DD
= AV
DD
= BV
DD
5
A
Output leakage current, low
I
LOL
V
O
= 0 V
5
A
I
DD1
Normal operation (f
XX
= 16 MHz)
45
65
mA
I
DD2
HALT mode (f
XX
= 16 MHz)
20
35
mA
I
DD3
IDLE mode (f
XX
= 16 MHz)
6
14
mA
STOP mode (subsystem clock
operation: f
XT
= 32.768 kHz, watch
timer operation
13
115
A
Supply current
I
DD4
STOP mode (subsystem clock stopped)
1
100
A
Pull-up resistor
R
L
10
30
100
k
Notes 1. Ports 4, 5, 6, 9 (including alternate-function pins)
2. P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147, P150 to
P157, P160 to P163, P165 to P167, P180 to P187, P190 to P197 (including alternate-function pins)
3. P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124
to P127, P130 to P135, P140 to P145, P164, P170 to P177 (including alternate-function pins)
4. Ports 7, 8 (including alternate-function pins)
Caution The TYP. value of V
DD
is 3.3 V. The current that is consumed at output buffers is not included.
Preliminary Data Sheet U14622EJ1V0DS00
23
PD70F3040, 70F3040Y
Data Retention Characteristics (T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V
)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention voltage
V
DDDR
STOP mode
1.8
3.6
V
Data retention current
I
DDDR
V
DDDR
[V]
1
100
A
Supply voltage rise time
t
RVD
200
s
Supply voltage fall time
t
FVD
200
s
Supply voltage hold time
(from STOP mode setting)
t
HVD
0
ms
STOP release signal input time
t
DREL
0
ms
Data retention high-level input voltage
V
IHDR
All input ports
V
IHn
V
DDDR
V
Data retention low-level input voltage
V
ILDR
All input ports
0
V
ILn
V
Remark n = 1 to 5
V
DD
Setting STOP mode
t
HVD
t
FVD
RESET
(input)
NMI, INTP0 to INTP3
(input)
STOP release interrupt (NMI)
(when STOP mode is released
at rising edge)
t
RVD
t
DREL
V
DDDR
V
IHDR
V
ILDR
V
IHDR
Caution Be sure to shift to and return from STOP mode when V
DD
is 2.7 V or higher.
Preliminary Data Sheet U14622EJ1V0DS00
24
PD70F3040, 70F3040Y
AC Characteristics
AC Test Input Waveforms (V
DD
, BV
DD
, AV
DD
)
V
DD
0 V
V
IH
V
IL
V
IH
V
IL
Test points
AC Test Output Test Point (BV
DD
)
V
OH
V
OL
V
OH
V
OL
Test points
Load Conditions
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
C
L
= 50 pF
DUT
(Device under test)
Preliminary Data Sheet U14622EJ1V0DS00
25
PD70F3040, 70F3040Y
Clock Timing
Operating Condition (T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
X1 input cycle
62.5
250
ns
XT1 input cycle
t
CYX
<1>
28.6
31.2
s
X1 input high-level width
31.2
125
ns
XT1 input high-level width
t
WXH
<2>
14.3
15.6
s
X1 input low-level width
31.2
125
ns
XT1 input low-level width
t
WXL
<3>
14.3
15.6
s
X1 input rise time
t
XR
<4>
( < 1 > < 2 > < 3 > ) / 2
ns
X1 input fall time
t
XF
<5>
( < 1 > < 2 > < 3 > ) / 2
ns
CLKOUT output cycle
t
CYK
<6>
62.5 ns
31.2
s
CLKOUT high-level width
t
WKH
<7>
0.4 (T20)
ns
CLKOUT low-level width
t
WKL
<8>
0.4 (T20)
ns
CLKOUT rise time
t
KR
<9>
10
ns
CLKOUT fall time
t
KF
<10>
10
ns
Remark T = t
CYK
Clock Timing
X1, XT1 (input)
CLKOUT (output)
<2>
<4>
<5>
<1>
<3>
<7>
<9>
<10>
<8>
<6>
Timing of Pins Other Than X1 and CLKOUT Pins
(T
A
= 40 to +85
C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V, Output Pin Load Capacitance: C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Output rise time
t
OR
20
ns
Output fall time
t
OF
20
ns
Preliminary Data Sheet U14622EJ1V0DS00
26
PD70F3040, 70F3040Y
Bus Timing (CLKOUT Asynchronous)
(T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
)
t
SAST
<11>
0.5T
20
ns
Address hold time (from ASTB
)
t
HSTA
<12>
0.5T
15
ns
Address float from DSTB
t
FDA
<13>
2
ns
Setup time from address to data input
t
DAID
<14>
(2 + n)T 30
ns
Setup time from DSTB
to data input
t
DDID
<15>
(1 + n)T 30
ns
Delay time from ASTB
to DSTB
t
DSTD
<16>
0.5T
15
ns
Data input hold time (from DSTB
)
t
HDID
<17>
0
ns
Address output time from DSTB
t
DDA
<18>
(1 + i)T 15
ns
Delay time from DSTB
to ASTB
t
DDST1
<19>
0.5T 15
ns
Delay time from DSTB
to ASTB
t
DDST2
<20>
(1.5 + i)T 15
ns
DSTB low-level width
t
WDL
<21>
(1 + n)T 15
ns
ASTB high-level width
t
WSTH
<22>
T 15
ns
Data output time from DSTB
t
DDOD
<23>
15
ns
Data output setup time (to DSTB
)
t
SODD
<24>
(1 + n)T 20
ns
Data output hold time (from DSTB
)
t
HDOD
<25>
T 15
ns
t
SAWT1
<26>
1.5T 30
ns
WAIT setup time (to address)
t
SAWT2
<27>
n
1
(1.5 + n)T 30
ns
t
HAWT1
<28>
(0.5 + n)T
ns
WAIT hold time (from address)
t
HAWT2
<29>
n
1
(1.5 + n)T
ns
t
SSTWT1
<30>
1.5T 25
ns
WAIT setup time (to ASTB
)
t
SSTWT2
<31>
n
1
(1 + n)T 5
ns
t
HSTWT1
<32>
nT + 5
ns
WAIT hold time (from ASTB
)
t
HSTWT2
<33>
n
1
(1 + n)T + 5
ns
HLDRQ high-level width
t
WHQH
<34>
T + 10
ns
HLDAK low-level width
t
WHAL
<35>
T 15
ns
Delay time from HLDAK
to bus output
t
DHAC
<36>
0
ns
Delay time from HLDRQ
to HLDAK
t
DHQHA1
<37>
1.5T
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
to HLDAK
t
DHQHA2
<38>
0.5T
1.5T + 25
ns
Remarks 1.
T = 1/f
CPU
(f
CPU
: CPU operation clock frequency)
2.
n: Number of wait clocks inserted in the bus cycle.
Sampling timing changes when a programmable wait is inserted.
3.
i: Number of idle states inserted after the read cycle (0 or 1).
4.
The specifications described above are the values of when a clock with a duty ratio of 1:1 is input
from X1.
Preliminary Data Sheet U14622EJ1V0DS00
27
PD70F3040, 70F3040Y
Bus Timing (CLKOUT Synchronous)
(T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
to address
t
DKA
<39>
0
19
ns
Delay time from CLKOUT
to address
float
t
FKA
<40>
12
7
ns
Delay time from CLKOUT
to ASTB
t
DKST
<41>
12
7
ns
Delay time from CLKOUT
to DSTB
t
DKD
<42>
5
14
ns
Data input setup time (to CLKOUT
)
t
SIDK
<43>
15
ns
Data input hold time (from CLKOUT
)
t
HKID
<44>
5
ns
Delay time from CLKOUT
to data
output
t
DKOD
<45>
19
ns
WAIT setup time (to CLKOUT
)
t
SWTK
<46>
15
ns
WAIT hold time (from CLKOUT
)
t
HKWT
<47>
5
ns
HLDRQ setup time (to CLKOUT
)
t
SHQK
<48>
15
ns
HLDRQ hold time (from CLKOUT
)
t
HKHQ
<49>
5
ns
Delay time from CLKOUT
to address
float
t
DKF
<50>
19
ns
Delay time from CLKOUT
to HLDAK
t
DKHA
<51>
19
ns
Remark The specifications described above are the values of when a clock with a duty ratio of 1:1 is input from
X1.
Preliminary Data Sheet U14622EJ1V0DS00
28
PD70F3040, 70F3040Y
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
CLKOUT (output)
A16 to A21 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output),
RD (output)
WAIT (input)
T1
T2
TW
T3
<39>
<40>
<41>
<11>
<42>
<19>
<18>
<20>
<16>
<30> <46>
<32>
<31>
<33>
<26>
<28>
<27>
<29>
<47>
<46>
<47>
<15>
<21>
<17>
<41>
<14>
<43>
<44>
Address
Hi-Z
<13>
<42>
<12>
<22>
Note R/W (output), UBEN (output), LBEN (output)
Remark WRL and WRH are high level.
Data
Preliminary Data Sheet U14622EJ1V0DS00
29
PD70F3040, 70F3040Y
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
CLKOUT (output)
A16 to A21 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output),
WRL (output),
WRH (output)
WAIT (input)
T1
T2
TW
T3
<39>
<45>
<41>
<11>
<42>
<19>
<25>
<16>
<30> <46>
<32>
<31>
<33>
<26>
<28>
<27>
<29>
<47>
<46>
<47>
<24>
<21>
<22>
<12>
<41>
Data
Address
<23>
<42>
Note R/W (output), UBEN (output), LBEN (output)
Remark RD is high level.
Preliminary Data Sheet U14622EJ1V0DS00
30
PD70F3040, 70F3040Y
Bus Hold
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A16 to A21 (output), Note
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output), RD (output),
WRL (output), WRH (output)
<48>
<49>
<51>
<50>
<36>
<35>
<37>
<38>
<48>
<51>
<34>
TH
TH
TH
TI
Hi-Z
Hi-Z
Hi-Z
Data
Hi-Z
Note R/W (output), UBEN (output), LBEN (output)
Preliminary Data Sheet U14622EJ1V0DS00
31
PD70F3040, 70F3040Y
Reset/Interrupt Timing
(T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
RESET high-level width
t
WRSH
<52>
500
ns
RESET low-level width
t
WRSL
<53>
500
ns
NMI high-level width
t
WNIH
<54>
500
ns
NMI low-level width
t
WNIL
<55>
500
ns
n = 0 to 3, analog noise elimination
500
ns
n = 4, 5, digital noise elimination
3T + 20
ns
INTPn high-level width
t
WITH
<56>
n = 6, digital noise elimination
3Tsmp + 20
ns
n = 0 to 3, analog noise elimination
500
ns
n = 4, 5, digital noise elimination
3T + 20
ns
INTPn low-level width
t
WITL
<57>
n = 6, digital noise elimination
3Tsmp + 20
ns
Remarks 1.
T = 1/f
XX
2.
Tsmp = Noise elimination sampling clock frequency
Reset
<52>
<53>
RESET (input)
Interrupt
<54>
<55>
NMI (input)
<56>
<57>
INTPn (input)
Remark n = 0 to 6
Preliminary Data Sheet U14622EJ1V0DS00
32
PD70F3040, 70F3040Y
TIn Input Timing
(T
A
= 40 to +85C, V
DD
= AV
DD
=BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Tln0, Tln1 (n = 00, 01)
High-level width
2T
sam
+ 20
Note
ns
Tln (n = 2 to 7, 10, 11)
High-level width
t
TIIH
<58>
3/f
XX
+ 20
ns
Tln0, Tln1 (n = 00, 01)
Low-level width
2T
sam
+ 20
Note
ns
Tln (n = 2 to 7, 10, 11)
Low-level width
t
TIL
<59>
3/f
XX
+ 20
ns
Note T
sam
can be selected by setting the PRMn1 and PRMn0 bits of prescaler mode registers n0, n1 (PRMn0,
PRMn1) (n = 0, 1).
TM0 (PRM00, PRM01 registers): T
sam
= 2/f
XX
, 4/f
XX
, 16/f
XX
, 64/f
XX
, 256/f
XX
, 1/INTWTI period
TM1 (PRM10, PRM11 registers): T
sam
= 2/f
XX
, 4/f
XX
, 16/f
XX
, 32/f
XX
, 128/f
XX
, 256/f
XX
However, when the TIn0 valid edge is selected as the count clock, T
sam
= 4/f
XX
(n = 0, 1).
Remark n = 000, 001, 010, 011, 10, 11, 2 to 7
TIn
<58>
<59>
Preliminary Data Sheet U14622EJ1V0DS00
33
PD70F3040, 70F3040Y
3-Wire SIO Timing
(1) Master Mode (T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
t
KCY1
<60>
400
ns
SCKn high-level width
t
KH1
<61>
140
ns
SCKn low-level width
t
KL1
<62>
140
ns
SIn setup time (to SCKn
)
t
SIK1
<63>
50
ns
SIn hold time (from SCKn
)
t
KSI1
<64>
50
ns
Delay time from SCKn
to SOn output
t
KSO1
<65>
60
ns
Remark n = 0 to 3
(2) Slave Mode (T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
t
KCY2
<60>
400
ns
SCKn high-level width
t
KH2
<61>
140
ns
SCKn low-level width
t
KL2
<62>
140
ns
SIn setup time (to SCKn
)
t
SIK2
<63>
50
ns
SIn hold time (from SCKn
)
t
KSI2
<64>
50
ns
Delay time from SCKn
to SOn output
t
KSO2
<65>
60
ns
Remark n = 0 to 3
SCKn (I/O)
SOn (output)
SIn (input)
<60>
<61>
<62>
<63>
<64>
<65>
Remark n = 0 to 3
Preliminary Data Sheet U14622EJ1V0DS00
34
PD70F3040, 70F3040Y
3-Wire Variable-Length CSI Timing
(1) Master Mode (T
A
= 40 to +85
C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCK4 cycle time
t
KCY1
<66>
400
ns
SCK4 high-level width
t
KH1
<67>
140
ns
SCK4 low-level width
t
KL1
<68>
140
ns
SI4 setup time (to SCK4
)
t
SIK1
<69>
50
ns
SI4 hold time (from SCK4
)
t
KSI1
<70>
50
ns
Delay time from SCK4
to SO4 output
t
KSO1
<71>
60
ns
(2) Slave Mode (T
A
= 40 to +85
C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCK4 cycle time
t
KCY2
<66>
400
ns
SCK4 high-level width
t
KH2
<67>
140
ns
SCK4 low-level width
t
KL2
<68>
140
ns
SI4 setup time (to SCK4
)
t
SIK2
<69>
50
ns
SI4 hold time (from SCK4
)
t
KSI2
<70>
50
ns
Delay time from SCK4
to SO4 output
t
KSO2
<71>
60
ns
SCK4 (I/O)
SO4 (output)
SI4 (input)
<66>
<67>
<68>
<69>
<70>
<71>
Preliminary Data Sheet U14622EJ1V0DS00
35
PD70F3040, 70F3040Y
UART Timing (T
A
= 40 to +85C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASCKn cycle time
t
KCY13
<72>
200
ns
ASCKn high-level width
t
KH13
<73>
80
ns
ASCKn low-level width
t
KL13
<74>
80
ns
Remark n = 0, 1
<73>
<74>
<72>
ASCKn (input)
Remark n = 0, 1
Preliminary Data Sheet U14622EJ1V0DS00
36
PD70F3040, 70F3040Y
I
2
C Bus Mode (Only for
PD70F3040Y)
(T
A
=
-
-
-
-
40 to +85
C, V
DD
= AV
DD
= BV
DD
= 2.7 to 3.6 V, V
SS
= AV
SS
= BV
SS
= 0 V)
Standard Mode
High-Speed Mode
Parameter
Symbol
MIN.
MAX.
MIN.
MAX.
Unit
SCLn clock frequency
f
CLK
0
100
0
400
kHz
Bus free time
(between stop/start conditions)
t
BUF
<75>
4.7
1.3
s
Hold time
Note 1
t
HD : STA
<76>
4.0
0.6
s
SCLn clock low-level width
t
LOW
<77>
4.7
1.3
s
SCLn clock high-level width
t
HIGH
<78>
4.0
0.6
s
Setup time of start/restart conditions
t
SU : STA
<79>
4.7
0.6
s
CBUS-compatible master
5.0
s
Data hold
time
I
2
C mode
t
HD : DAT
<80>
0
Note 2
0
Note 2
0.9
Note 3
s
Data setup time
t
SU : DAT
<81>
250
100
Note 4
ns
Rising time of SDAn and SCLn signals
t
R
<82>
1000
20 + 0.1Cb
Note 5
300
ns
Falling time of SDAn and SCLn signals
t
F
<83>
300
20 + 0.1Cb
Note 5
300
ns
Setup time of stop condition
t
SU : STO
<84>
4.0
0.6
s
Pulse width of spike suppressed by
input filter
t
SP
<85>
0
50
ns
Load capacitance of bus line
Cb
400
400
pF
Notes 1. The first clock pulse in the start condition is generated after the hold time.
2. The system must internally provide at least 300-ns hold time for the SDAn signal (at V
IHmin.
of the SCLn
signal) in order to fill the undefined period that appears at the SCLn falling edge.
3. If the system does not extend the low hold time (t
LOW
), it is required to satisfy only the maximum data
hold time (t
HD
:
DAT
).
4. The high-speed I
2
C bus is available in the standard mode I
2
C bus system. In this case, following
conditions should be satisfied.
When the system does not extend the low-state hold time of the SCLn signal
t
SU
:
DAT
250 ns
When the system extends the low-state hold time of the SCLn signal
Before the SCLn line is released (t
Rmax.
+ t
SU
:
DAT
= 1000 + 250 = 1250 ns: Standard mode I
2
C bus
specification), send the next data bit to the SDAn line.
5. Cb: Total capacitance of one bus line (Unit: pF)
Remark n = 0, 1
Preliminary Data Sheet U14622EJ1V0DS00
37
PD70F3040, 70F3040Y
I
2
C Bus Mode (
PD70F3040Y only)
SCLn
SDAn
Stop
condition
Strat
condition
Restart condition
Stop condition
<77>
<82>
<80>
<78>
<83>
<81>
<79>
<76>
<85>
<84>
<75>
<76>
Remark
n = 0, 1
A/D Converter (T
A
= 40 to +85C, V
DD
= AV
DD
= AV
REF
= 2.7 to 3.6 V, AV
SS
= V
SS
= 0 V, Output Pin Load
Capacitance: C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
10
10
bit
Overall error
Note 1
0.8
%FSR
Conversion time
t
CONV
5
100
s
Zero-scale error
Note 1
0.4
%FSR
Full-scale error
Note 1
0.4
%FSR
Integral linearity error
Note 2
4.0
LSB
Differential linearity error
Note 2
4.0
LSB
Analog reference voltage
AV
REF
AV
REF
= AV
DD
2.7
3.6
V
Analog input voltage
V
IAN
AV
SS
AV
REF
V
AV
REF
current
AI
REF
240
360
A
Supply current
AI
DD
1
3
mA
Notes 1. Excluding quantization error (
0.05%FSR)
2. Excluding quantization error (
0.5LSB)
Remark
LSB: Least Significant Bit
FSR: Full Scale Range
Preliminary Data Sheet U14622EJ1V0DS00
38
PD70F3040, 70F3040Y
Flash Memory Programming Mode
Write/Erase Characteristics (T
A
= 10 to 40
C, V
DD
= 3.0 to 3.6 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
I
DDW
V
DD
pin
67
mA
Write current
I
PPW
When V
PP
= V
PP1
V
PP
pin
100
mA
I
DDE
V
DD
pin
67
mA
Erase current
I
PPE
When V
PP
= V
PP1
V
PP
pin
200
mA
Unit erase time
t
ER
0.2
0.2
0.2
s
Total erase time
t
ERT
20
s
Rewrite count
Note
20
20
20
times
V
PP0
In normal operation mode
0
0.2V
DD
V
V
PP
supply voltage
V
PP1
In flash memory programming mode
7.5
7.8
8.1
V
Operation frequency
4
16
MHz
Note Write/erase is regarded as 1 cycle.
Preliminary Data Sheet U14622EJ1V0DS00
39
PD70F3040, 70F3040Y
3. PACKAGE DRAWING
1
44
176
133
45
88
132
89
S
S
N
176-PIN PLASTIC LQFP (FINE PITCH) (24x24)
J
T
detail of lead end
C
D
A
B
R
K
M
I
S
P
L
U
Q
G
F
NOTE
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
26.0
0.2
24.0
0.2
1.25
26.0
0.2
S176GM-50-UEU
C
24.0
0.2
L
0.5
F
1.25
N
P
Q
S
0.08
1.4
0.1
0.05
1.5
0.1
M
0.17
+
0.03
-
0.07
H
0.22
0.05
I
J
K
0.08
0.5 (T.P.)
1.0
0.2
R
3
+
4
-
3
M
H
Preliminary Data Sheet U14622EJ1V0DS00
40
PD70F3040, 70F3040Y
4. RECOMMENDED SOLDERING CONDITIONS
T.B.D.
Preliminary Data Sheet U14622EJ1V0DS00
41
PD70F3040, 70F3040Y
[MEMO]
Preliminary Data Sheet U14622EJ1V0DS00
42
PD70F3040, 70F3040Y
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Purchase of NEC I
2
C components conveys a license under the Philips I
2
C Patent Rights to use these components in an I
2
C
system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
Related document
PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Data Sheet (U13953E)
Reference document
Electrical Characteristics for Microcomputer (IEI-601)
Note
Note This document number is that of the Japanese version.
The documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850 Family and V850/SV1 are trademarks of NEC Corporation.
Preliminary Data Sheet U14622EJ1V0DS00
43
PD70F3040, 70F3040Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
PD70F3040, 70F3040Y
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
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