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Электронный компонент: UPD70F3706

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Document No. U17718EJ1V0UD00 (1st edition)
Date Published December 2005 N CP(K)
Printed in Japan
Preliminary User's Manual
V850ES/HG2

32-Bit Single-Chip Microcontrollers
Hardware
2005
PD70F3706
PD70F3707

Preliminary User's Manual U17718EJ1V0UD
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[MEMO]
Preliminary User's Manual U17718EJ1V0UD
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
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Preliminary User's Manual U17718EJ1V0UD
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Preliminary User's Manual U17718EJ1V0UD
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PREFACE
Readers
This manual is intended for users who wish to understand the functions of the
V850ES/HG2 and design application systems using the V850ES/HG2.
Purpose
This manual is intended to give users an understanding of the hardware functions of
the V850ES/HG2 shown in the Organization below.
Organization
This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User's Manual).
Hardware
Architecture
Pin functions
Data types
CPU function
Register set
On-chip peripheral functions
Instruction format and instruction set
Flash memory programming
Interrupts and exceptions
Electrical specifications (target)
Pipeline operation
How to Read This Manual
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/HG2
Read this manual according to the CONTENTS.
To find the details of a register where the name is known
Use APPENDIX A REGISTER INDEX.
To understand the details of an instruction function
Refer to the V850ES Architecture User's Manual available separately.
To know the electrical specifications of the V850ES/HG2
See CHAPTER 26 ELECTRICAL SPECIFICATIONS (TARGET).
Register format
The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note
with caution that if "xxx.yyy" is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.