Document No. U17717EJ2V0UD00 (2nd edition)
Date Published November 2005 N CP(K)
Printed in Japan
Preliminary User's Manual
V850ES/HJ2
32-Bit Single-Chip Microcontrollers
Hardware
2005
PD70F3709
PD70F3710
PD70F3711
PD70F3712
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2
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
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MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany.
The information contained in this document is being issued in advance of the production cycle for the
product. The parameters for the product may change before final production or NEC Electronics
Corporation, at its own discretion, may withdraw the product prior to its production.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes
in semiconductor product operation and application examples. The incorporation of these circuits, software and
information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC
Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of
these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and
anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated
"quality assurance program" for a specific application. The recommended applications of an NEC Electronics
products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC
Electronics product before using it in a particular application.
M5D 02. 11-1
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio and
visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life
support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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PREFACE
Readers
This manual is intended for users who wish to understand the functions of the
V850ES/HJ2 and design application systems using the V850ES/HJ2.
Purpose
This manual is intended to give users an understanding of the hardware functions of
the V850ES/HJ2 shown in the Organization below.
Organization
This manual is divided into two parts: Hardware (this manual) and Architecture
(V850ES Architecture User's Manual).
Hardware
Architecture
Pin functions
Data types
CPU function
Register set
On-chip peripheral functions
Instruction format and instruction set
Flash memory programming
Interrupts and exceptions
Electrical specifications (target)
Pipeline operation
How to Read This Manual
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the V850ES/HJ2
Read this manual according to the CONTENTS.
To find the details of a register where the name is known
Use APPENDIX A REGISTER INDEX.
To understand the details of an instruction function
Refer to the V850ES Architecture User's Manual available separately.
To know the electrical specifications of the V850ES/HJ2
See CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET).
Register format
The name of the bit whose number is in angle brackets (<>) in the figure of the
register format of each register is defined as a reserved word in the device file.
The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note
with caution that if "xxx.yyy" is described as is in a program, however, the
compiler/assembler cannot recognize it correctly.
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Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation:
xxx (overscore over pin or signal name)
Memory map address:
Higher addresses on the top and lower addresses on
the bottom
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark: Supplementary
information
Numeric representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
capacity):
K (kilo): 2
10
= 1,024
M (mega): 2
20
= 1,024
2
G (giga): 2
30
= 1,024
3
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Related Documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents related to V850ES/HJ2
Document Name
Document No.
V850ES Architecture User's Manual
U15943E
V850ES/HJ2 Hardware User's Manual
This manual
Documents related to development tools
Document Name
Document No.
Operation
U17293E
C Language
U17291E
Assembly Language
U17292E
CA850 Ver. 3.00 C Compiler Package
Link Directives
U17294E
PM+ Ver. 6.00 Project Manager
U17178E
ID850QB Ver. 3.10 Integrated Debugger
Operation
U17435E
SM850 Ver. 2.50 System Simulator
Operation
U16218E
SM850 Ver. 2.00 or Later System Simulator
External Part User Open
Interface Specification
U14873E
Basics U13430E
Installation U17419E
Technical U13431E
RX850 Ver. 3.20 or Later Real-Time OS
Task Debugger
U17420E
Basics U13773E
Installation U17421E
Technical U13772E
RX850 Pro Ver. 3.20 Real-Time OS
Task Debugger
U17422E
AZ850 Ver. 3.30 System Performance Analyzer
U17423E
PG-FP4 Flash Memory Programmer
U15260E
Preliminary User's Manual U17717EJ2V0UD
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CONTENTS
CHAPTER 1 INTRODUCTION .................................................................................................................17
1.1
General .....................................................................................................................................17
1.2
Features....................................................................................................................................19
1.3
Application Fields ...................................................................................................................19
1.4
Ordering Information ..............................................................................................................20
1.5
Pin Configuration (Top View) .................................................................................................21
1.6
Function Block Configuration................................................................................................23
1.6.1
Internal block diagram ............................................................................................................... 23
1.6.2
Internal units .............................................................................................................................. 24
CHAPTER 2 PIN FUNCTIONS ................................................................................................................26
2.1
Pin Function List .....................................................................................................................26
2.2
Pin Status .................................................................................................................................33
2.3
Description of Pin Functions .................................................................................................34
2.4
Pin I/O Circuit Types and Recommended Connection of Unused Pins ............................43
2.5
Pin I/O Circuits.........................................................................................................................46
2.6
Cautions ...................................................................................................................................47
CHAPTER 3 CPU FUNCTION.................................................................................................................48
3.1
Features....................................................................................................................................48
3.2
CPU Register Set.....................................................................................................................49
3.2.1
Program register set .................................................................................................................. 50
3.2.2
System register set.................................................................................................................... 51
3.3
Operation Modes .....................................................................................................................57
3.3.1
Specifying operation mode ........................................................................................................ 57
3.4
Address Space ........................................................................................................................58
3.4.1
CPU address space................................................................................................................... 58
3.4.2
Wraparound of CPU address space .......................................................................................... 59
3.4.3
Memory map.............................................................................................................................. 60
3.4.4
Areas ......................................................................................................................................... 62
3.4.5
Recommended use of address space ....................................................................................... 66
3.4.6
Peripheral I/O registers.............................................................................................................. 69
3.4.7
Special registers ........................................................................................................................ 80
3.4.8
Cautions .................................................................................................................................... 84
CHAPTER 4 PORT FUNCTIONS............................................................................................................87
4.1
Features....................................................................................................................................87
4.2
Basic Configuration of Ports .................................................................................................87
4.3
Port Functions .........................................................................................................................89
4.3.1
Operation of port function .......................................................................................................... 89
4.3.2
Notes on setting port pins .......................................................................................................... 90
4.3.3
Port 0......................................................................................................................................... 91
4.3.4
Port 1......................................................................................................................................... 97
4.3.5
Port 3....................................................................................................................................... 101
4.3.6
Port 4....................................................................................................................................... 108
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4.3.7
Port 5 .......................................................................................................................................111
4.3.8
Port 6 .......................................................................................................................................117
4.3.9
Port 7 .......................................................................................................................................125
4.3.10
Port 8 .......................................................................................................................................127
4.3.11
Port 9 .......................................................................................................................................131
4.3.12
Port 12 .....................................................................................................................................142
4.3.13
Port CD ....................................................................................................................................144
4.3.14
Port CM ...................................................................................................................................146
4.3.15
Port CS ....................................................................................................................................149
4.3.16
Port CT ....................................................................................................................................152
4.3.17
Port DL ....................................................................................................................................155
4.3.18
Port pins that function alternately as on-chip debug function ...................................................158
4.3.19
Register settings to use port pins as alternate-function pins ....................................................159
4.4
Block Diagrams of Port........................................................................................................ 166
4.5
Cautions ................................................................................................................................ 195
4.5.1
Cautions on setting port pins ...................................................................................................195
CHAPTER 5 BUS CONTROL FUNCTION .......................................................................................... 196
5.1
Features................................................................................................................................. 196
5.2
Bus Control Pins................................................................................................................... 197
5.2.1
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed...............197
5.2.2
Pin status in each operation mode...........................................................................................197
5.3
Memory Block Function....................................................................................................... 198
5.4
Bus Access ........................................................................................................................... 199
5.4.1
Number of clocks for access....................................................................................................199
5.4.2
Bus size setting function ..........................................................................................................199
5.4.3
Access by bus size ..................................................................................................................200
5.5
Wait Function ........................................................................................................................ 207
5.5.1
Programmable wait function ....................................................................................................207
5.5.2
External wait function...............................................................................................................208
5.5.3
Relationship between programmable wait and external wait ................................................... 208
5.5.4
Programmable address wait function.......................................................................................209
5.6
Idle State Insertion Function ............................................................................................... 210
5.7
Bus Hold Function................................................................................................................ 211
5.7.1
Functional outline.....................................................................................................................211
5.7.2
Bus hold procedure..................................................................................................................212
5.7.3
Operation in power save mode ................................................................................................212
5.8
Bus Priority ........................................................................................................................... 213
5.9
Bus Timing ............................................................................................................................ 214
CHAPTER 6 CLOCK GENERATION FUNCTION .............................................................................. 217
6.1
Overview................................................................................................................................ 217
6.2
Configuration ........................................................................................................................ 218
6.3
Registers ............................................................................................................................... 220
6.4
Operation............................................................................................................................... 225
6.4.1
Operation of each clock ...........................................................................................................225
6.4.2
Clock output function ...............................................................................................................225
6.5
PLL Function......................................................................................................................... 226
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6.5.1
Overview ................................................................................................................................. 226
6.5.2
Registers ................................................................................................................................. 226
6.5.3
Usage ...................................................................................................................................... 230
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) .................................................................231
7.1
Overview.................................................................................................................................231
7.2
Functions ...............................................................................................................................231
7.3
Configuration .........................................................................................................................232
7.4
Registers ................................................................................................................................234
7.5
Operation................................................................................................................................248
7.5.1
Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............................................................. 249
7.5.2
External event count mode (TPnMD2 to TPnMD0 bits = 001) ................................................. 259
7.5.3
External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)..................................... 267
7.5.4
One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) .............................................. 279
7.5.5
PWM output mode (TPnMD2 to TPnMD0 bits = 100).............................................................. 286
7.5.6
Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .................................................... 295
7.5.7
Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) ........................................ 312
7.5.8
Timer output operations........................................................................................................... 318
7.6
Timer Tuned Operation Function ........................................................................................319
7.7
Selector Function ..................................................................................................................323
7.8
Cautions .................................................................................................................................325
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) ................................................................326
8.1
Overview.................................................................................................................................326
8.2
Functions ...............................................................................................................................326
8.3
Configuration .........................................................................................................................327
8.4
Registers ................................................................................................................................330
8.5
Operation................................................................................................................................348
8.5.1
Interval timer mode (TQnMD2 to TQnMD0 bits = 000) ............................................................ 349
8.5.2
External event count mode (TQnMD2 to TQnMD0 bits = 001) ................................................ 358
8.5.3
External trigger pulse output mode (TQnMD2 to TQnMD0 bits = 010) .................................... 367
8.5.4
One-shot pulse output mode (TQnMD2 to TQnMD0 bits = 011) ............................................. 380
8.5.5
PWM output mode (TQnMD2 to TQnMD0 bits = 100) ............................................................. 389
8.5.6
Free-running timer mode (TQnMD2 to TQnMD0 bits = 101) ................................................... 400
8.5.7
Pulse width measurement mode (TQnMD2 to TQnMD0 bits = 110)........................................ 420
8.5.8
Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111) .................................................... 426
8.5.9
Timer output operations........................................................................................................... 427
8.6
Timer Tuned Operation Function ........................................................................................428
8.7
Cautions .................................................................................................................................432
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM).............................................................................433
9.1
Overview.................................................................................................................................433
9.2
Configuration .........................................................................................................................434
9.3
Register ..................................................................................................................................435
9.4
Operation................................................................................................................................436
9.4.1
Interval timer mode.................................................................................................................. 436
9.4.2
Cautions .................................................................................................................................. 440
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CHAPTER 10 WATCH TIMER FUNCTIONS ...................................................................................... 441
10.1
Functions............................................................................................................................... 441
10.2
Configuration ........................................................................................................................ 442
10.3
Registers ............................................................................................................................... 444
10.4
Operation............................................................................................................................... 448
10.4.1
Operation as watch timer .........................................................................................................448
10.4.2
Operation as interval timer.......................................................................................................449
10.4.3
Cautions...................................................................................................................................450
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ................................................................... 451
11.1
Functions............................................................................................................................... 451
11.2
Configuration ........................................................................................................................ 452
11.3
Registers ............................................................................................................................... 453
11.4
Operation............................................................................................................................... 456
CHAPTER 12 A/D CONVERTER ......................................................................................................... 457
12.1
Overview................................................................................................................................ 457
12.2
Functions............................................................................................................................... 457
12.3
Configuration ........................................................................................................................ 458
12.4
Registers ............................................................................................................................... 461
12.5
Operation............................................................................................................................... 469
12.5.1
Basic operation ........................................................................................................................469
12.5.2
Trigger mode ...........................................................................................................................470
12.5.3
Operation mode .......................................................................................................................472
12.5.4
Power-fail compare mode ........................................................................................................476
12.6
Cautions ................................................................................................................................ 481
12.7
How to Read A/D Converter Characteristics Table........................................................... 485
CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) ............................................. 489
13.1
Features................................................................................................................................. 490
13.2
Configuration ........................................................................................................................ 491
13.3
Registers ............................................................................................................................... 493
13.4
Interrupt Request Signals.................................................................................................... 499
13.5
Operation............................................................................................................................... 500
13.5.1
Data format ..............................................................................................................................500
13.5.2
SBF transmission/reception format ..........................................................................................502
13.5.3
SBF transmission.....................................................................................................................504
13.5.4
SBF reception ..........................................................................................................................505
13.5.5
UART transmission ..................................................................................................................506
13.5.6
Continuous transmission procedure.........................................................................................507
13.5.7
UART reception .......................................................................................................................509
13.5.8
Reception errors ......................................................................................................................510
13.5.9
Parity types and operations .....................................................................................................512
13.5.10
Receive data noise filter...........................................................................................................513
13.6
Dedicated Baud Rate Generator ......................................................................................... 514
13.7
Cautions ................................................................................................................................ 522
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB).................................................... 523
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14.1
Features..................................................................................................................................523
14.2
Configuration .........................................................................................................................524
14.3
Registers ................................................................................................................................526
14.4
Interrupt Request Signals.....................................................................................................533
14.5
Operation................................................................................................................................534
14.5.1
Single transfer mode (master mode, transmission/reception mode)........................................ 534
14.5.2
Single transfer mode (master mode, reception mode)............................................................. 535
14.5.3
Continuous mode (master mode, transmission/reception mode)............................................. 536
14.5.4
Continuous mode (master mode, reception mode).................................................................. 537
14.5.5
Continuous reception mode (error) .......................................................................................... 538
14.5.6
Continuous mode (slave mode, transmission/reception mode) ............................................... 539
14.5.7
Continuous mode (slave mode, reception mode) .................................................................... 540
14.5.8
Clock timing ............................................................................................................................. 541
14.6
Output Pin Status with Operation Disabled .......................................................................543
14.7
Operation Flow ......................................................................................................................544
14.8
Baud Rate Generator ............................................................................................................550
14.8.1
Baud rate generation ............................................................................................................... 551
14.9
Cautions .................................................................................................................................552
CHAPTER 15 DMA FUNCTION (DMA CONTROLLER) ....................................................................553
15.1
Features..................................................................................................................................553
15.2
Configuration .........................................................................................................................554
15.3
Registers ................................................................................................................................555
15.4
Transfer Targets ....................................................................................................................563
15.5
Transfer Modes......................................................................................................................563
15.6
Transfer Types.......................................................................................................................564
15.7
DMA Channel Priorities ........................................................................................................565
15.8
Time Related to DMA Transfer.............................................................................................565
15.9
DMA Transfer Start Factors .................................................................................................566
15.10
DMA Abort Factors................................................................................................................567
15.11
End of DMA Transfer.............................................................................................................567
15.12
Operation Timing...................................................................................................................567
15.13
Cautions .................................................................................................................................572
CHAPTER 16 INTERRUPT/EXCEPTION PROCESSING FUNCTION ...............................................577
16.1
Features..................................................................................................................................577
16.2
Non-Maskable Interrupts ......................................................................................................581
16.2.1
Operation................................................................................................................................. 583
16.2.2
Restore.................................................................................................................................... 584
16.2.3
NP flag..................................................................................................................................... 585
16.3
Maskable Interrupts ..............................................................................................................586
16.3.1
Operation................................................................................................................................. 586
16.3.2
Restore.................................................................................................................................... 588
16.3.3
Priorities of maskable interrupts .............................................................................................. 589
16.3.4
Interrupt control register (xxICn) .............................................................................................. 593
16.3.5
Interrupt mask registers 0 to 4 (IMR0 to IMR4)........................................................................ 595
16.3.6
In-service priority register (ISPR)............................................................................................. 597
16.3.7
ID flag ...................................................................................................................................... 598
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16.3.8
Watchdog timer mode register 2 (WDTM2) .............................................................................598
16.4
Software Exception .............................................................................................................. 599
16.4.1
Operation .................................................................................................................................599
16.4.2
Restore ....................................................................................................................................600
16.4.3
EP flag .....................................................................................................................................601
16.5
Exception Trap...................................................................................................................... 602
16.5.1
Illegal opcode definition ...........................................................................................................602
16.5.2
Debug trap ...............................................................................................................................604
16.6
External Interrupt Request Input Pins (NMI and INTP0 to INTP14) ................................. 606
16.6.1
Noise elimination .....................................................................................................................606
16.6.2
Edge detection.........................................................................................................................606
16.7
Interrupt Acknowledge Time of CPU .................................................................................. 615
16.8
Periods in Which Interrupts Are Not Acknowledged by CPU .......................................... 616
16.9
Cautions ................................................................................................................................ 616
CHAPTER 17 KEY INTERRUPT FUNCTION ..................................................................................... 617
17.1
Function................................................................................................................................. 617
17.2
Register ................................................................................................................................. 618
17.3
Cautions ................................................................................................................................ 618
CHAPTER 18 STANDBY FUNCTION .................................................................................................. 619
18.1
Overview................................................................................................................................ 619
18.2
Registers ............................................................................................................................... 621
18.3
HALT Mode............................................................................................................................ 624
18.3.1
Setting and operation status ....................................................................................................624
18.3.2
Releasing HALT mode.............................................................................................................624
18.4
IDLE1 Mode ........................................................................................................................... 626
18.4.1
Setting and operation status ....................................................................................................626
18.4.2
Releasing IDLE1 mode ............................................................................................................626
18.5
IDLE2 Mode ........................................................................................................................... 628
18.5.1
Setting and operation status ....................................................................................................628
18.5.2
Releasing IDLE2 mode ............................................................................................................628
18.5.3
Securing setup time when releasing IDLE2 mode ................................................................... 630
18.6
STOP Mode............................................................................................................................ 631
18.6.1
Setting and operation status ....................................................................................................631
18.6.2
Releasing STOP mode ............................................................................................................631
18.6.3
Securing oscillation stabilization time when releasing STOP mode .........................................633
18.7
Subclock Operation Mode ................................................................................................... 634
18.7.1
Setting and operation status ....................................................................................................634
18.7.2 Releasing
subclock operation mode ........................................................................................634
18.8
Sub-IDLE Mode ..................................................................................................................... 636
18.8.1
Setting and operation status ....................................................................................................636
18.8.2
Releasing sub-IDLE mode .......................................................................................................637
CHAPTER 19 RESET FUNCTIONS ..................................................................................................... 639
19.1
Overview................................................................................................................................ 639
19.2
Registers to Check Reset Source....................................................................................... 640
19.3
Operation............................................................................................................................... 641
Preliminary User's Manual U17717EJ2V0UD
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19.3.1
Reset operation via RESET pin ............................................................................................... 641
19.3.2
Reset operation by watchdog timer 2 ...................................................................................... 643
19.3.3
Reset operation by power-on clear circuit................................................................................ 644
19.3.4
Reset operation by low-voltage detector.................................................................................. 644
19.3.5
Reset operation by clock monitor ............................................................................................ 644
CHAPTER 20 CLOCK MONITOR .........................................................................................................645
20.1
Functions ...............................................................................................................................645
20.2
Configuration .........................................................................................................................645
20.3
Register ..................................................................................................................................646
20.4
Operation................................................................................................................................647
CHAPTER 21 POWER-ON CLEAR CIRCUIT .....................................................................................650
21.1
Function .................................................................................................................................650
21.2
Configuration .........................................................................................................................650
21.3
Operation................................................................................................................................651
CHAPTER 22 LOW-VOLTAGE DETECTOR ........................................................................................652
22.1
Functions ...............................................................................................................................652
22.2
Configuration .........................................................................................................................652
22.3
Registers ................................................................................................................................653
22.4
Operation................................................................................................................................655
22.4.1
To use for internal reset signal ................................................................................................ 655
22.4.2
To use for interrupt .................................................................................................................. 657
22.5
RAM Retention Voltage Detection Operation.....................................................................658
22.6
Emulation Function...............................................................................................................659
CHAPTER 23 REGULATOR ..................................................................................................................660
23.1
Overview.................................................................................................................................660
23.2
Operation................................................................................................................................661
CHAPTER 24 FLASH MEMORY...........................................................................................................662
24.1
Features..................................................................................................................................662
24.1.1
Erasure unit ............................................................................................................................. 663
24.2
Rewriting by Dedicated Flash Programmer .......................................................................664
24.2.1
Programming environment ...................................................................................................... 664
24.2.2
Communication mode.............................................................................................................. 665
24.2.3
Flash memory control .............................................................................................................. 670
24.2.4
Selection of communication mode........................................................................................... 671
24.2.5
Communication commands ..................................................................................................... 672
24.2.6
Pin connection ......................................................................................................................... 673
24.2.7
Recommended circuit example for writing ............................................................................... 677
24.3
Rewriting by Self Programming...........................................................................................678
24.3.1
Overview ................................................................................................................................. 678
24.3.2
Features .................................................................................................................................. 679
24.3.3
Standard self programming flow .............................................................................................. 680
24.3.4
Flash functions ........................................................................................................................ 681
24.3.5
Pin processing ......................................................................................................................... 681
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24.3.6
Internal resources used ...........................................................................................................682
CHAPTER 25 OPTION BYTE FUNCTION .......................................................................................... 683
CHAPTER 26 ON-CHIP DEBUG FUNCTION ..................................................................................... 684
26.1
Features................................................................................................................................. 684
26.2
Connection Circuit Example................................................................................................ 685
26.3
Interface Signals ................................................................................................................... 686
26.4
Register ................................................................................................................................. 688
26.5
Operation............................................................................................................................... 689
26.6
ROM Security Function........................................................................................................ 690
26.6.1
Security ID ...............................................................................................................................690
26.6.2
Setting .....................................................................................................................................691
26.7
Cautions ................................................................................................................................ 692
CHAPTER 27 ELECTRICAL SPECIFICATIONS (TARGET).............................................................. 693
27.1
Electrical Specifications ...................................................................................................... 693
27.2
Capacitance........................................................................................................................... 695
27.3
Operating Conditions ........................................................................................................... 695
27.4
Oscillator Characteristics .................................................................................................... 696
27.4.1
Main clock oscillator characteristics .........................................................................................696
27.4.2
Subclock oscillator characteristics ...........................................................................................697
27.4.3
PLL characteristics ..................................................................................................................698
27.4.4
Internal oscillator characteristics ..............................................................................................698
27.5
Voltage Regulator Characteristics...................................................................................... 698
27.6
DC Characteristics ............................................................................................................... 699
27.6.1
I/O level ...................................................................................................................................699
27.6.2
Pin leakage current ..................................................................................................................700
27.6.3
Supply current..........................................................................................................................701
27.7
Data Retention Characteristics ........................................................................................... 703
27.8
AC Characteristics ............................................................................................................... 704
27.8.1
CLKOUT Output Timing...........................................................................................................705
27.8.2
Bus Timing...............................................................................................................................706
27.9
Basic Operation .................................................................................................................... 711
27.10
Flash Memory Programming Characteristics.................................................................... 718
CHAPTER 28 PACKAGE DRAWING .................................................................................................. 719
APPENDIX A REGISTER INDEX ......................................................................................................... 720
APPENDIX B INSTRUCTION SET LIST ............................................................................................. 731
B.1
Conventions .......................................................................................................................... 731
B.2
Instruction Set (in Alphabetical Order) .............................................................................. 734
Preliminary User's Manual U17717EJ2V0UD
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CHAPTER 1 INTRODUCTION
The V850ES/HJ2 is one of the products in the NEC Electronics V850 Series of single-chip microcontrollers
designed for low-power operation for real-time control applications.
1.1 General
The V850ES/HJ2 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral
functions such as ROM/RAM, a timer/counter, serial interfaces, and an A/D converter.
In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/HJ2 features
multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware
multiplier, as optimum instructions for digital servo control applications.
Table 1-1 lists the products of the V850ES/HJ2.
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
18
Table 1-1. V850ES/HJ2 Product List
Part Number
PD70F3709
PD70F3710
PD70F3711
PD70F3712
Flash memory
128 KB
256 KB
376 KB
512 KB
Internal
memory
RAM
12 KB
20 KB
Logical space
64 MB
Memory
space
External memory area
15 MB
External bus interface
Address bus: 16 bits
Data bus: 8/16 bits
Multiplexed bus mode
General-purpose register
32 bits
32 registers
Main clock (oscillation frequency)
Ceramic/crystal/external clock
In PLL mode: f
X
= 4 to 5 MHz
In clock through mode: f
X
= 4 to 5 MHz
Subclock (oscillation frequency)
Crystal/external clock: f
XT
= 32.768 kHz
RC oscillation: 20 kHz
Internal oscillator
f
R
= 200 kHz (TYP.)
Minimum instruction execution time
50 ns (main clock (f
XX
) = 20 MHz operation)
DSP function
32
32 = 64: 200 to 250 ns (at 20 MHz)
32
32 + 32 = 32: 300 ns (at 20 MHz)
16
16 = 32: 50 to 100 ns (at 20 MHz)
16
16 + 32 = 32: 150 ns (at 20 MHz)
I/O port
I/O: 128
Timer
16-bit timer/event counter P: 4 channels
16-bit timer/event counter Q: 3 channels
16-bit interval timer M:
1 channel
Watchdog timer 2:
1 channel
Watch timer:
1 channel
A/D converter
10-bit resolution
24 channels
Serial interface
CSIB: 3
channels
UARTA (for LIN): 3 channels
CSIB: 3
channels
UARTA (for LIN): 4 channels
DMA controller
4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory)
Interrupt source
External: 16 (16)
Note
, internal: 50
External: 16 (16)
Note
, internal: 52
Power save function
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Reset
RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), POC circuit, low-voltage
detector (LVI)
On-chip debug function
Provided (RUN/break)
Operating power supply voltage
3.5 to 5.5 V (A/D converter: 4.0 to 5.5 V)
Operating ambient temperature
-40 to +85C
Package
144-pin plastic LQFP (fine pitch) (20
20 mm)
Note The figure in parentheses indicates the number of external interrupts that can release STOP mode.
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
19
1.2 Features
Minimum instruction execution time: 50 ns (operating with main clock (f
XX
) of 20 MHz)
General-purpose registers:
32 bits
32 registers
CPU features:
Signed multiplication (16
16 32): 1 to 2 clocks
Signed multiplication (32
32 64): 1 to 5 clocks
Saturated operations (overflow and underflow detection functions included)
32-bit shift instruction: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Memory space:
64 MB of linear address space (for programs and data)
External expansion: Up to 256 KB (including 64 KB used as internal ROM/RAM)
Internal memory:
RAM:
12 KB/20 KB (see Table 1-1)
Flash memory: 128 KB/256 KB/376 KB/512 KB (see Table 1-1)
External bus interface: Multiplexed bus output
8-/16-bit data bus sizing function
Wait function
Programmable wait function
External wait function
Idle state function
Bus hold function
Interrupts and exceptions:
Non-maskable interrupts: 2 sources
Maskable interrupts:
64/66 sources (see Table 1-1)
Software exceptions:
32 sources
Exception trap:
2 sources
I/O lines:
I/O ports:
128
Timer function:
16-bit interval timer M (TMM):
1 channel
16-bit timer/event counter P (TMP): 4 channels
16-bit timer/event counter Q (TMQ): 3 channels
Watch timer:
1 channel
Watchdog timer 2:
1 channel
Serial interface:
Asynchronous serial interface A (UARTA)
3-wire variable-length serial interface B (CSIB)
UARTA (supporting LIN): 4 channels (
PD70F3711, 70F3712)
3 channels (
PD70F3709, 70F3710)
CSIB:
3
channels
A/D converter:
10-bit resolution: 24 channels
DMA controller:
4 channels
On-chip debug function:
JTAG interface
Clock generator:
During main clock or subclock operation
7-level CPU clock (f
XX
, f
XX
/2, f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32, f
XT
)
Clock-through mode/PLL mode selectable
Internal oscillation clock:
200 kHz (TYP.)
Power-save functions:
HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode
Package:
144-pin plastic LQFP (fine pitch) (20
20)
1.3 Application
Fields
Consumer devices
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
20
1.4 Ordering
Information
Part Number
Package
On-Chip Flash Memory
PD70F3709GJ-UEN-A
PD70F3710GJ-UEN-A
PD70F3711GJ-UEN-A
PD70F3712GJ-UEN-A
144-pin plastic LQFP (fine pitch) (20
20)
144-pin plastic LQFP (fine pitch) (20
20)
144-pin plastic LQFP (fine pitch) (20
20)
144-pin plastic LQFP (fine pitch) (20
20)
128 KB
256 KB
376 KB
512 KB
Remark Products with -A at the end of the part number are lead-free products.
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
21
1.5 Pin Configuration (Top View)
144-pin plastic LQFP (fine pitch) (20
20)
PD70F3709GJ-UEN-A
PD70F3710GJ-UEN-A
PD70F3711GJ-UEN-A
PD70F3712GJ-UEN-A
AV
REF0
AV
SS
P10/INTP9
P11/INTP10
EV
DD
P00/TIP31/TOP31
P01/TIP30/TOP30
FLMD0
Note 1
V
DD
REGC
Note 2
V
SS
X1
X2
RESET
XT1
XT2
P02/NMI
P03/INTP0/ADTRG
P04/INTP1
P05/INTP2/DRST
P06/INTP3
P40/SIB0
P41/SOB0
P42/SCKB0
P30/TXDA0
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/TOP01
P33/TIP01/TOP01
P34/TIP10/TOP10
P35/TIP11/TOP11
P36
P37
EV
SS
EV
DD
P38/TXDA2
P39/RXDA2/INTP8
PDL3/AD3
PDL2/AD2
PDL1/AD1
PDL0/AD0
BV
DD
BV
SS
PCT7
PCT6/ASTB
PCT5
PCT4/RD
PCT3
PCT2
PCT1/WR1
PCT0/WR0
PCS7
PCS6
PCS5
PCS4
PCM5
PCM4
PCM3/HLDRQ
PCM2/HLDAK
PCM1/CLKOUT
PCM0/WAIT
PCS3/CS3
PCS2/CS2
PCS1/CS1
PCS0/CS0
PCD3
PCD2
PCD1
PCD0
P915/INTP6
P914/INTP5
P913/INTP4/PCL
P912/SCKB2
P50/KR0/TIQ01/TOQ01 P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK P55/KR5/DMS
P60/INTP11 P61/INTP12 P62/INTP13
P63 P64 P65 P66 P67 P68 P69
P610/TIQ20/TOQ20 P611/TIQ21/TOQ21 P612/TIQ22/TOQ22 P613/TIQ23/TOQ23
P614 P615
P80/RXDA3
Note 3
/INTP14
P81/TXDA3
Note 3
P90/KR6/TXDA1 P91/KR7/RXDA1
P92/TIQ11/TOQ11 P93/TIQ12/TOQ12 P94/TIQ13/TOQ13 P95/TIQ10/TOQ10 P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
P98/SOB1
P99/SCKB1
P910/SIB2
P911/SOB2
P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6 P77/ANI7 P78/ANI8 P79/ANI9 P710/ANI10 P711/ANI11 P712/ANI12 P713/ANI13 P714/ANI14 P715/ANI15 P120/ANI16 P121/ANI17 P122/ANI18 P123/ANI19 P124/ANI20 P125/ANI21 P126/ANI22 P127/ANI23 PDL15/AD15 PDL14/AD14 PDL13/AD13 PDL12/AD12 PDL11/AD11 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1 PDL4/AD4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
Notes 1. Connect this pin to V
SS
in the normal mode.
2. Connect the REGC pin to V
SS
via a 4.7
F (preliminary value) capacitor.
3.
PD70F3711, 70F3712 only
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
22
Pin identification
AD0 to AD15:
ADTRG:
ANI0 to ANI23:
ASCKA0:
ASTB:
AV
REF0
:
AV
SS
:
BV
DD
:
BV
SS
:
CLKOUT:
CS0 to CS3:
DCK:
DDI:
DDO:
DMS:
DRST:
EV
DD
:
EV
SS
:
FLMD0, FLMD1:
HLDAK:
HLDRQ:
INTP0 to INTP14:
KR0 to KR7:
NMI:
P00 to P06:
P10, P11:
P30 to P39:
P40 to P42:
P50 to P55:
P60 to P615:
P70 to P715:
P80, P81:
P90 to P915:
P120 to P127:
PCD0 to PCD3:
Address/data bus
A/D trigger input
Analog input
Asynchronous serial clock
Address strobe
Analog reference voltage
Analog V
SS
Power supply for bus interface
Ground for bus interface
Clock output
Chip select
Debug clock
Debug data input
Debug data output
Debug mode select
Debug reset
Power supply for port
Ground for port
Flash programming mode
Hold acknowledge
Hold request
External interrupt request
Key return
Non-maskable interrupt request
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 12
Port CD
PCL:
PCM0 to PCM5:
PCS0 to PCS7:
PCT0 to PCT7:
PDL0 to PDL15:
RD:
REGC:
RESET:
RXDA0 to RXDA3:
SCKB0 to SCKB2:
SIB0 to SIB2:
SOB0 to SOB2:
TIP00, TIP01,
TIP10, TIP11,
TIP20, TIP21,
TIP30, TIP31,
TIQ00 to TIQ03,
TIQ10 to TIQ13,
TIQ20 to TIQ23:
TOP00, TOP01,
TOP10, TOP11,
TOP20, TOP21,
TOP30, TOP31,
TOQ00 to TOQ03,
TOQ10 to TOQ13,
TOQ20 to TOQ23:
TXDA0 to TXDA3:
V
DD
:
V
SS
:
WAIT:
WR0:
WR1:
X1, X2:
XT1, XT2:
Programmable clock output
Port CM
Port CS
Port CT
Port DL
Read strobe
Regulator control
Reset
Receive data
Serial clock
Serial input
Serial output
Timer input
Timer output
Transmit data
Power supply
Ground
Wait
Write strobe low level data
Write strobe high level data
Crystal for main clock
Crystal for subclock
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
23
1.6 Function
Block
Configuration
1.6.1 Internal
block
diagram
NMI
TOQ00 to TOQ03
TOQ10 to TOQ13
TOQ20 to TOQ23
TIQ00 to TIQ03
TIQ10 to TIQ13
TIQ20 to TIQ23
INTP0 to INTP14
INTC
16-bit timer/
counter Q:
3 ch
TOP00 to TOP30,
TOP01 to TOP31
TIP00 to TIP30,
TIP01 to TIP31
16-bit timer/
counter P:
4 ch
SOB0 to SOB2
SIB0 to SIB2
CSIB: 3 ch
KR0 to KR7
DMAC
Key return
function
Note 1
Note 2
RAM
Flash
memory
PC
General-purpose
registers 32 bits
32
Multiplier
16
16 32
ALU
System
registers
32-bit barrel
shifter
CPU
HLDRQ
HLDAK
ASTB
RD
WAIT
WR0, WR1
AD0 to AD15
FLMD0
FLMD1
Ports
CG
Regulator
PLL
LVI
Internal oscillator
CLM
CS0 to CS3
PCS0 to PCS7
PCM0 to PCM5
PCT0 to PCT7
PDH0 to PDH7
PDL0 to PDL15
PCD0 to PCD3
P90 to P915
P80, P81
P70 to P715
P60 to P615
P50 to P55
P40 to P42
P30 to P39
P10, P11
P00 to P06
ANI0 to ANI23
AV
SS
AV
REF0
ADTRG
CLKOUT
XT1
XT2
X1
X2
RESET
V
DD
V
SS
REGC
BV
DD
BV
SS
EV
DD
EV
SS
Instruction
queue
BCU
16-bit
interval
timer M:
1 ch
On-chip
debug
function
DRST
DMS
DDI
DCK
DDO
A/D
converter
POC
SCKB0 to SCKB2
RXDA0 to RXDA3
Note 3
TXDA0 to TXDA3
Note 3
UARTA:
4 ch
Note 3
ASCK0
Watchdog
timer 2
Watch timer
Notes 1.
PD70F3709: 128 KB
PD70F3710: 256 KB
PD70F3711: 376 KB
PD70F3712: 512 KB
2.
PD70F3709, 70F3710: 12 KB
PD70F3711, 70F3712: 20 KB
3.
PD70F3709, 70F3710: 3 channels
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
24
1.6.2 Internal
units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits
16 bits 32 bits) and a barrel shifter (32
bits) contribute to faster complex processing.
(2) Bus control unit (BCU)
The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an
instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue.
(3) ROM
This is a 512 KB/376 KB/256 KB/128 KB flash memory mapped to addresses 0000000H to
007FFFFH/0000000H to 005DFFFH/0000000H to 003FFFFH/0000000H to 001FFFFH. It can be accessed
from the CPU in one clock during instruction fetch.
(4) RAM
This is a 20 KB/12 KB RAM mapped to addresses 3FFA000H to 3FFEFFFH/3FFC000H to 3FFEFFFH. It can
be accessed from the CPU in one clock during data access.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0 to INTP14) from on-chip peripheral hardware
and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and
multiple servicing control can be performed.
(6) Clock generator (CG)
A main clock oscillator that generates the main clock oscillation frequency (f
X
) and a subclock oscillator that
generates the subclock oscillation frequency (f
XT
) are available. As the main clock frequency (f
XX
), f
X
is used as
is in the clock-through mode and is multiplied by four in the PLL mode.
The CPU clock frequency (f
CPU
) can be selected from seven types: f
XX
, f
XX
/2, f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32, and f
XT
.
(7) Internal oscillator
An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP.). An internal oscillator
supplies the clock for watchdog timer 2 and timer M.
(8) Timer/counter
Four-channel 16-bit timer/event counter P (TMP), three-channel 16-bit timer/event counter Q (TMQ), and one-
channel 16-bit interval timer M (TMM) are provided on chip.
(9) Watch timer
This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz from the subclock or
the 32.768 kHz f
BRG
from prescaler 3). The watch timer can also be used as an interval timer for the main
clock.
CHAPTER 1 INTRODUCTION
Preliminary User's Manual U17717EJ2V0UD
25
(10) Watchdog timer 2
A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc.
Either the internal oscillation clock or the main clock can be selected as the source clock.
Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal
(WDT2RES) after an overflow occurs.
(11) Serial
interface
The V850ES/HJ2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA) and 3-
wire variable-length serial interface B (CSIB).
In the case of UARTA, data is transferred via the TXDAn and RXDAn pins.
(n = 0 to 3:
PD70F3711, 70F3712, n = 0 to 2:
PD70F3709, 70F3710)
In the case of CSIB, data is transferred via the SOB0 to SOB3 pins, SIB0 to SIB3 pins, and SCKB0 to
SCKB3 pins.
(12) A/D
converter
This 10-bit A/D converter includes 24 analog input pins. Conversion is performed using the successive
approximation method.
(13) DMA
controller
A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and
on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O.
(14) Key interrupt function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to key input pins (8
channels).
(15) On-chip
debug
function
An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is
provided. Switching between the normal port function and on-chip debugging function is done with the
control pin input level and the on-chip debug mode register (OCDM).
(16) Ports
The general-purpose port functions and control pin functions are provided. For details, see CHAPTER 4
PORT FUNCTIONS.
Preliminary User's Manual U17717EJ2V0UD
26
CHAPTER 2 PIN FUNCTIONS
This section explains the names and functions of the pins of the V850ES/HJ2.
2.1 Pin Function List
Three I/O buffer power supplies, AV
REF0
, BV
DD
, and EV
DD
, are available. The relationship between the power
supplies and the pins is shown below.
Table 2-1. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pin
AV
REF0
Port 7, port 12
BV
DD
Port CD, port CM, port CS, port CT, port DL
EV
DD
Port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, RESET
(1) Port pins
Table 2-2. List of Pins (Port Pins) (1/3)
Pin Name
I/O
Function
Alternate Function
P00
TIP31/TOP31
P01
TIP30/TOP30
P02
NMI
P03
INTP0/ADTRG
P04
INTP1
P05
INTP2/DRST
P06
I/O
Port 0
7-bit I/O port
Input/output can be specified in 1-bit units.
INTP3
P10
INTP9
P11
I/O
Port 1
2-bit I/O port
Input/output can be specified in 1-bit units.
INTP10
P30
TXDA0
P31
RXDA0/INTP7
P32
ASCKA0/TIP00/TOP00/TOP01
P33
TIP01/TOP01
P34
TIP10/TOP10
P35
TIP11/TOP11
P36
-
P37
-
P38
TXDA2
P39
I/O
Port 3
10-bit I/O port
Input/output can be specified in 1-bit units.
RXDA2/INTP8
P40
SIB0
P41
SOB0
P42
I/O
Port 4
3-bit I/O port
Input/output can be specified in 1-bit units.
SCKB0
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Table 2-2. List of Pins (Port Pins) (2/3)
Pin Name
I/O
Function
Alternate Function
P50
KR0/TIQ01/TOQ01
P51
KR1/TIQ02/TOQ02
P52
KR2/TIQ03/TOQ03/DDI
P53
KR3/TIQ00/TOQ00/DDO
P54
KR4/DCK
P55
I/O
Port 5
6-bit I/O port
Input/output can be specified in 1-bit units.
KR5/DMS
P60
INTP11
P61
INTP12
P62
INTP13
P63
P64
P65
P66
P67
P68
P69
P610
TIQ20/TOQ20
P611
TIQ21/TOQ21
P612
TIQ22/TOQ22
P613
TIQ23/TOQ23
P614
P615
I/O
Port 6
16-bit
I/O
port
Input/output can be specified in 1-bit units.
P70 to P715
I/O
Port 7
16-bit
I/O
port
Input/output can be specified in 1-bit units.
ANI0 to ANI15
P80
RXDA3
Note
/INTP14
P81
I/O
Port 8
2-bit I/O port
Input/output can be specified in 1-bit units.
TXDA3
Note
Note
PD70F3711, 70F3712 only
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Table 2-2. List of Pins (Port Pins) (3/3)
Pin Name
I/O
Function
Alternate Function
P90
KR6/TXDA1
P91
KR7/RXDA1
P92
TIQ11/TOQ11
P93
TIQ12/TOQ12
P94
TIQ13/TOQ13
P95
TIQ10/TOQ10
P96
TIP21/TOP21
P97
SIB1/TIP20/TOP20
P98
SOB1
P99
SCKB1
P910
SIB2
P911
SOB2
P912
SCKB2
P913
INTP4/PCL
P914
INTP5
P915
I/O
Port 9
16-bit
I/O
port
Input/output can be specified in 1-bit units.
INTP6
P120 to P127
I/O
Port 12
8-bit I/O port
Input/output can be specified in 1-bit units.
ANI16 to ANI23
PCD0 to PCD3
I/O
Port CD
4-bit I/O port
Input/output can be specified in 1-bit units.
PCM0
WAIT
PCM1
CLKOUT
PCM2
HLDAK
PCM3
HLDRQ
PCM4
PCM5
I/O
Port CM
6-bit I/O port
Input/output can be specified in 1-bit units.
PCS0 to PCS3
CS0 to CS3
PCS4 to PCS7
I/O
Port CS
8-bit I/O port
Input/output can be specified in 1-bit units.
PCT0
WR0
PCT1
WR1
PCT2
PCT3
PCT4
RD
PCT5
PCT6
ASTB
PCT7
I/O
Port CT
8-bit I/O port
Input/output can be specified in 1-bit units.
PDL0 to PDL4
AD0 to AD4
PDL5
AD5/FLMD1
PDL6 to PDL15
I/O
Port DL
16-bit
I/O
port
Input/output can be specified in 1-bit units.
AD6 to AD15
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(2) Non-port pins
Table 2-3. List of Pins (Non-Port Pins) (1/4)
Pin Name
I/O
Function
Alternate Function
NMI
Note 1
Input
External interrupt input
(non-maskable, with analog noise eliminated)
P02
INTP0
P03/ADTRG
INTP1
P04
INTP2
P05/DRST
INTP3
P06
INTP4
P913/PCL
INTP5
P914
INTP6
P915
INTP7
P31/RXDA0
INTP8
P39/RXDA2
INTP9
P10
INTP10
P11
INTP11
P60
INTP12
P61
INTP13
P62
INTP14
Input
External interrupt request input
(maskable, with analog noise eliminated)
P80/RXDA3
Note 2
TIP00
External event/clock input (TMP00)
P32/ASCKA0/TOP00/TOP01
TIP01
External event input (TMP01)
P33/TOP01
TIP10
External event/clock input (TMP10)
P34/TOP10
TIP11
External event input (TMP11)
P35/TOP11
TIP20
External event/clock input (TMP20)
P97/SIB1/TOP20
TIP21
External event input (TMP21)
P96/TOP21
TIP30
External event/clock input (TMP30)
P01/TOP30
TIP31
Input
External event input (TMP31)
P00/TOP31
TOP00 Timer
output
(TMP00)
P32/ASCKA0/TIP00/TOP01
P32/ASCKA0/TIP00/TOP00
TOP01 Timer
output
(TMP01)
P33/TIP01
TOP10 Timer
output
(TMP10)
P34/TIP10
TOP11 Timer
output
(TMP11)
P35/TIP11
TOP20 Timer
output
(TMP20)
P97/SIB1/TIP20
TOP21 Timer
output
(TMP21)
P96/TIP21
TOP30 Timer
output
(TMP30)
P01/TIP30
TOP31
Output
Timer output (TMP31)
P00/TIP31
Notes 1. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset. To enable the
NMI pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is "No edge detected". Select
the NMI pin valid edge using INTF0 and INTR0 registers.
2.
PD70F3711, 70F3712 only
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Table 2-3. List of Pins (Non-Port Pins) (2/4)
Pin Name
I/O
Function
Alternate Function
TIQ00
External event/clock input (TMQ00)
P53/KR3/TOQ00/DDO
TIQ01
External event input (TMQ01)
P50/KR0/TOQ01
TIQ02
External event input (TMQ02)
P51/KR1/TOQ02
TIQ03
External event input (TMQ03)
P52/KR2/TOQ03/DDI
TIQ10 External
event/clock input (TMQ10)
P95/TOQ10
TIQ11
External event input (TMQ11)
P92/TOQ11
TIQ12
External event input (TMQ12)
P93/TOQ12
TIQ13
External event input (TMQ13)
P94/TOQ13
TIQ20
External event/clock input (TMQ20)
P610/TOQ20
TIQ21
External event input (TMQ21)
P611/TOQ21
TIQ22
External event input (TMQ22)
P612/TOQ22
TIQ23
Input
External event input (TMQ23)
P613/TOQ23
TOQ00 Timer
output
(TMQ00)
P53/KR3/TIQ00/DDO
TOQ01 Timer
output
(TMQ01)
P50/KR0/TIQ01
TOQ02 Timer
output
(TMQ02)
P51/KR1/TIQ02
TOQ03 Timer
output
(TMQ03)
P52/KR2/TIQ03/DDI
TOQ10 Timer
output
(TMQ10)
P95/TIQ10
TOQ11 Timer
output
(TMQ11)
P92/TIQ11
TOQ12 Timer
output
(TMQ12)
P93/TIQ12
TOQ13 Timer
output
(TMQ13)
P94/TIQ13
TOQ20 Timer
output
(TMQ20)
P610/TIQ20
TOQ21 Timer
output
(TMQ21)
P611/TIQ21
TOQ22 Timer
output
(TMQ22)
P612/TIQ22
TOQ23
Output
Timer output (TMQ23)
P613/TIQ23
SIB0
Serial receive data input (CSIB0)
P40
SIB1
Serial receive data input (CSIB1)
P97/TIP20/TOP20
SIB2
Input
Serial receive data input (CSIB2)
P910
SOB0
Serial transmit data output (CSIB0)
P41
SOB1
Serial transmit data output (CSIB1)
P98
SOB2
Output
Serial transmit data output (CSIB2)
P911
SCKB0
Serial clock I/O (CSIB0)
P42
SCKB1
Serial clock I/O (CSIB1)
P99
SCKB2
I/O
Serial clock I/O (CSIB2)
P912
RXDA0
Serial receive data input (UARTA0)
P31/INTP7
RXDA1
Serial receive data input (UARTA1)
P91/KR7
RXDA2
Serial receive data input (UARTA2)
P39/INTP8
RXDA3
Note
Input
Serial receive data input (UARTA3)
P80/INTP14
Note
PF70F3711, 70F3712 only
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Table 2-3. List of Pins (Non-Port Pins) (3/4)
Pin Name
I/O
Function
Alternate Function
TXDA0
Serial transmit data output (UARTA0)
P30
TXDA1
Serial transmit data output (UARTA1)
P90/KR6
TXDA2
Serial transmit data output (UARTA2)
P38
TXDA3
Note
Output
Serial transmit data output (UARTA3)
P81
ASCKA0
Input
Baud rate clock input to UARTA0
P32/TIP00/TOP00/TOP01
ANI0 to ANI15
P70 to P715
ANI16 to ANI23
Input
Analog voltage input to A/D converter
P120 to P127
AV
REF0
Input
Reference voltage input to A/D converter,
positive power supply for alternate-function port 7
-
AV
SS
-
Ground potential for A/D and D/A converters (same potential
as V
SS
)
-
ADTRG
Input
A/D converter external trigger input
P03/INTP0
KR0
P50/TIQ01/TOQ01
KR1
P51/TIQ02/TOQ02
KR2
P52/TIQ03/TOQ03/DDI
KR3
P53/TIQ00/TOQ00/DDO
KR4
P54/DCK
KR5
P55/DMS
KR6
P90/TXDA1
KR7
Input
Key interrupt input
P91/RXDA1
DMS Input
Debug
mode
select
P55/KR5
DDI
Input
Debug data input
P52/KR2/TIQ03/TOQ03
DDO
Output
Debug data output
P53/KR3/TIQ00/TOQ00
DCK Input
Debug
clock
input
P54/KR4
DRST
Input
Debug reset input
P05/INTP2
CS0 to CS3
Output
Chip select signal output
PCS0 to PCS3
AD0 to AD4
PDL0 to PDL4
AD5
PDL5/FLMD1
AD6 to AD15
I/O
Address/data bus for external memory
PDL6 to PDL15
ASTB Output
Address strobe signal output for external memory
PCT6
HLDRQ
Input
Bus hold request input
PCM3
HLDAK
Output
Bus hold acknowledge output
PCM2
RD
Output
Read strobe signal output for external memory
PCT4
WAIT Input
External wait input
PCM0
WR0
Write strobe for external memory (lower 8 bits)
PCT0
WR1
Output
Write strove for external memory (higher 8 bits)
PCT1
FLMD0
-
FLMD1
Input
Flash programming mode setting pins
PDL5/AD5
CLKOUT
Output
Internal system clock output
PCM1
Note
PF70F3711, 70F3712 only
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Table 2-3. List of Pins (Non-Port Pins) (4/4)
Pin Name
I/O
Function
Alternate Function
PCL
Output
Clock output (timing output of X1 input clock and subclock)
P913/INTP4
REGC
-
Regulator output stabilizing capacitor connection
-
RESET
Input
System reset input
-
X1 Input
-
X2
-
Main clock resonator connection
-
XT1 Input
-
XT2
-
Subclock resonator connection
-
V
DD
-
Positive power supply pin for internal circuitry
-
V
SS
-
Ground potential for internal circuitry
-
BV
DD
-
Positive power supply pin for bus interface and alternate-function
ports
-
BV
SS
-
Ground potential for bus interface and alternate-function ports
-
EV
DD
-
Positive power supply pin for external circuitry (same potential as V
DD
)
-
EV
SS
-
Ground potential for external circuitry (same potential as V
SS
)
-
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2.2 Pin
Status
The V850ES/HJ2 has an external bus interface function that enables connection of external memories, such as
ROM and RAM, and I/O.
Table 2-4 shows the operating status of each external bus interface pin in each operation mode.
Table 2-4. Pin Operating Status in Each Operation Mode
Bus Control Pin
Reset
HALT Mode and
DMA Transfer
IDLE1, IDLE2, and
STOP Modes
Idle State
Note 2
Bus Hold
AD0 to AD15
Hi-Z
CS0 to CS3
H
Held Hi-Z
WAIT
-
-
-
CLKOUT L
Operating
Operating
WR0, WR1
RD
ASTB
Hi-Z
HLDAK
H H
L
HLDRQ
Hi-Z
Note 1
Operating
-
- Operating
Notes 1. The bus control pins function alternately as port pins and are initialized to the input mode (port mode).
2. Pin status in the idle state that is inserted after the T3 state.
Remark Hi-Z: High impedance
Held: The state during the immediately preceding external bus cycle is held.
L:
Low-level output
H:
High-level output
-:
Input without sampling (not acknowledged)
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2.3 Description of Pin Functions
(1) P00 to P06 (port 0) ... 3-state I/O
P00 to P06 function as a 7-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as NMI input, external interrupt request signal input,
timer/counter I/O, external trigger of the A/D converter, and debug reset input.
This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is specified by
the INTR0 and INTF0 registers.
An on-chip pull-up resistor can be connected to P00 to P06 by using pull-up resistor option register 0 (PU0).
(a) Port mode
P00 to P06 can be set in the input or output mode in 1-bit units, by using port mode register 0 (PM0).
(b) Control mode
(i) NMI (Non-maskable interrupt request) ... input
This pin inputs a non-maskable interrupt request signal.
(ii) INTP0 to INTP3 (External interrupt request) ... input
These pins input external interrupt request signals.
(iii) TIP30, TIP31 (Timer input) ... input
These pins input an external count clock to timer P3 (TMP3).
(iv) TOP30, TOP31 (Timer output) ... output
These pins output a pulse signal from timer P3 (TMP3).
(v) ADTRG (A/D trigger input) ... input
This pin inputs an external trigger to the A/D converter. It is controlled by using A/D converter mode
register 0 (ADA0M0).
(vi) DRST (Debug reset) ... input
This pin inputs a debug reset signal, a negative-logic signal that asynchronously initializes the on-chip
debug circuit. To deassert this signal, reset or invalidate the on-chip debug circuit. Deassert this
signal when the debug function is not used.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
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(2) P10, P11 (port 1) ... 3-state I/O
P10 and P11 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input in the control
mode. This port can be set in the port mode or control mode in 1-bit units. The valid edge of each pin is
specified by INTR1 and INTF1 registers.
An on-chip pull-up resistor can be connected to P10 and P11 by using pull-up resistor option register 1 (PU1).
(a) Port mode
P10 and P11 can be set in the input or output mode in 1-bit units, by using port mode register 1 (PM1).
(b) Control mode
(i) INTP9, INTP10 (External interrupt request) ... input
These pins input an external interrupt request signal.
(3) P30 to P39 (port 3) ... 3-state I/O
P30 to P39 function as a 10-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, serial interface
I/O, and timer/counter I/O. This port can be set in the port mode or control mode in 1-bit units. The valid edge
of each pin is specified by the INTR3 and INTF3 registers.
An on-chip pull-up resistor can be connected to P30 to P39 by using pull-up resistor option register 3 (PU3).
(a) Port mode
P30 to P39 can be set in the input or output mode in 1-bit units, by using port mode register 3 (PM3).
(b) Control mode
(i) RXDA0, RXDA2 (Receive data) ... input
These pins input the serial receive data of UARTA0 and UARTA2.
(ii) TXDA0, TXDA2 (Transmit data) ... output
These pins output the serial transmit data of UARTA0 and UARTA2.
(iii) ASCKA0 (Asynchronous serial clock) ... input
This is an input pin for UARTA0.
(iv) INTP7, INTP8 (External interrupt request) ... input
These pins input an external interrupt request signal.
(v) TIP00, TIP01, TIP10, TIP11 (Timer input) ... input
These are input pins for timers P0 and P1 (TMP0 and TMP1).
(vi) TOP00, TOP01, TOP10, TOP11 (Timer output) ... output
These are output pins for timers P0 and P1 (TMP0 and TMP1).
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(4) P40 to P42 (port 4) ... 3-state I/O
P40 to P42 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O. This port can be set in the port
mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P40 to P42 by using pull-up resistor option register 4 (PU4).
(a) Port mode
P40 to P42 can be set in the input or output mode in 1-bit units, by using port mode register 4 (PM4).
(b) Control mode
(i) SIB0 (Serial input) ... input
This pin inputs the serial receive data of CSIB0.
(ii) SOB0 (Serial output) ... output
This pin outputs the serial transmit data of CSIB0.
(iii) SCKB0 (serial clock) ... 3-state I/O
This pin inputs/outputs the serial clock of CSIB0.
(5) P50 to P55 (Port 5) ... 3-state I/O
P50 to P55 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as timer/counter I/O, debug function I/O, and key
interrupt input. This port can be set in the port mode or control mode in 1-bit units.
An on-chip pull-up resistor can be connected to P50 to P55 by using pull-up resistor option register 5 (PU5).
(a) Port mode
P50 to P55 can be set in the input or output mode in 1-bit units, by using port mode register 5 (PM5).
(b) Control mode
(i) KR0 to KR5 (Key return) ... input
These pins input a key interrupt. Their operation is specified by using the key return mode register
(KRM) in the input port mode.
(ii) TIQ00, TIQ01, TIQ02, TIQ03 (Timer input) ... input
These are input pins for timer Q0 (TMQ0).
(iii) TOQ00, TOQ01, TOQ02, TOQ03 (Timer output) ... output
These are output pins for timer Q0 (TMQ0).
(iv) DDI (Debug data input) ... input
This pin inputs debug data to the on-chip debug circuit.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
(v) DDO (Debug data output) ... output
This pin outputs debug data from the on-chip debug circuit.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
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(iv) DCK (Debug clock input) ... input
This pin inputs a debug clock to the on-chip debug circuit.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
(vii) DMS (Debug mode select) ... input
This pin selects the debug mode of the on-chip debug circuit.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
(6) P60 to P615 (Port 6) ... 3-state I/O
P60 to P615 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input and
timer/counter I/O. P60 to P62 can be set in the port mode or control mode in 1-bit units. The valid edge of
P60 to P615 is specified by INTR6L and INTF6L registers.
An on-chip pull-up resistor can be connected to P60 to P615 by using pull-up resistor option register 6 (PU6).
(a) Port mode
P60 to P615 can be set in the input or output mode in 1-bit units, by using port mode register 6 (PM6).
(b) Control mode
(i) INTP11 to INTP13 (External interrupt request) ... input
These pins input an external interrupt request signal.
(ii) TIQ20, TIQ21, TIQ22, TIQ23 (Timer input) ... input
These are input pins for timer Q2 (TMQ2).
(iii) TOQ20, TOQ21, TOQ22, TOQ23 (Timer output) ... output
These are output pins for timer Q2 (TMQ2).
(7) P70 to P715 (port 7) ... 3-state I/O
P70 to P715 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as analog input to the A/D converter in the control mode.
When using the analog input pins, however, set this port in the input mode. At this time, do not read the port.
(a) Port mode
P70 to P715 can be set in the input or output mode in 1-bit units, by using port mode registers 7L and 7H
(PM7L and PM7H).
(b) Control mode
P70 to P715 function alternately as the ANI0 to ANI15 pins.
(i) ANI0 to ANI15 (Analog input 0 to 15) ... input
These pins input an analog signal to the A/D converter.
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(8) P80 and P81 (port 8) ... 3-state I/O
P80 and P81 function as a 2-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as external interrupt request signal input, and serial
interface I/O. P80 and P81 can be set in the port mode or control mode in 1-bit units. The valid edge of each
pin is specified by INTR8 and INTF8 registers.
An on-chip pull-up resistor can be connected to P80 and P81 by using pull-up resistor option register 8 (PU8).
(a) Port mode
P80 and P81 can be set in the input or output mode in 1-bit units, by using port mode register 8 (PM8).
(b) Control mode
(i) INTP14 (External interrupt request) ... input
This pin inputs an external interrupt request signal.
(ii) RXDA3 (Receive data)
Note
... input
This pin inputs the serial receive data of UARTA3.
(iii) TXDA3 (Transmit data)
Note
... output
This pin outputs the serial transmit data of UARTA3.
Note
PD70F3711 and 70F3712 only
(9) P90 to P915 (port 9) ... 3-state I/O
P90 to P915 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as serial interface I/O, timer/counter I/O, clock output,
external interrupt request signal input, and key interrupt input. This port can be set in the port mode or control
mode in 1-bit units. The valid edge of P913 to P915 is specified by INTR9H and INTF9H registers.
An on-chip pull-up resistor can be connected to P90 to P915 by using pull-up resistor option register 9 (PU9).
(a) Port mode
P90 to P915 can be set in the input or output mode in 1-bit units, by using port mode register 9 (PM9).
(b) Control mode
(i) SIB1, SIB2 (Serial input) ... input
These pins input the serial receive data of CSIB1 and CSIB2.
(ii) SOB1, SOB2 (Serial output) ... output
These pins output the serial transmit data of CSIB1 and CSIB2.
(iii) SCKB1, SCKB2 (Serial clock) ... 3-state I/O
These pins input/output the serial clock of CSIB1 and CSIB2.
(iv) RXDA1 (Receive data) ... input
This pin inputs the serial receive data of UARTA1.
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(v) TXDA1 (Transmit data) ... output
This pin outputs the serial transmit data of UARTA1.
(vi) TIP20, TIP21 (Timer input) ... input
These are input pins for timer P2 (TMP2).
(vii) TOP20, TOP21 (Timer output) ... output
These are output pins for timer P2 (TMP2).
(viii) TIQ10, TIQ11, TIQ12, TIQ13 (Timer input) ... input
These are input pins for timer Q1 (TMQ1).
(ix) TOQ10, TOQ11, TOQ12, TOQ13 (Timer output) ... output
These are output pins for timer Q1 (TMQ1).
(x) PCL (Clock output) ... output
This pin outputs a clock.
(xi) INTP4 to INTP6 (External interrupt request) ... input
These pins input an external interrupt request signal.
(xii) KR6, KR7 (Key return) ... input
These pins input a key interrupt. Their operation is specified by the key return mode register (KRM) in
the input port mode.
(10) P120 to P127 (Port 12) ... 3-state I/O
P120 to P127 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as the analog input pins of the A/D converter in the
control mode. When using this port as analog input pins, however, set the port in the input mode. At this time,
do not read the port.
(a) Port mode
P120 to P127 can be set in the input or output mode in 1-bit units, by using port mode register 12 (PM12).
(b) Control mode
P120 to P127 function alternately as the ANI16 to ANI23 pins.
(i) ANI16 to ANI23 (Analog input 16 to 23) ... input
These pins input an analog signal to the A/D converter.
(11) PCD0 to PCD3 (port CD) ... 3-state I/O
PCD0 to PCD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
(a) Port mode
PCD0 to PCD3 can be set in the input or output mode in 1-bit units, by using port mode register CD
(PMCD).
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(12) PCM0 to PCM5 (port CM) ... 3-state I/O
PCM0 to PCM5 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as bus hold control signal I/O, bus clock output, and a
control signal that inserts a wait cycle in the bus cycle (WAIT), in the control mode.
(a) Port mode
PCM0 to PCM5 can be set in the input or output mode in 1-bit units, by using port mode register CM
(PMCM).
(b) Control mode
(i) HLDAK (Hold acknowledge) ... output
This pin outputs an acknowledge signal that indicates that the V850ES/HJ2 has placed the address
bus, data bus, and control bus in a high-impedance state in response to a bus hold request.
While this signal is active, the address bus, data bus, and control bus go into a high-impedance state.
(ii) HLDRQ (Hold request) ... input
An external device uses this input pin to request the V850ES/HJ2 to release the address bus, data
bus, and control bus. A signal can be input to this pin asynchronously to CLKOUT. When this pin is
asserted, the V850ES/HJ2 places the address bus, data bus, and control bus in a high-impedance
state after completion of a bus cycle under execution, if any, or immediately if no such bus cycle is
under execution. The V850ES/HJ2 then asserts the HLDAK signal and releases the buses.
(iii) CLKOUT (Clock output) ... output
This pin outputs an internally generated bus clock.
(iv) WAIT (Wait) ... input
This is a control signal input pin that inserts a data wait state in the bus cycle. A signal can be input to
this pin asynchronously to the CLKOUT signal. The signal input to this pin is sampled at the falling
edge of the CLKOUT signal in the T2 and TW states of the bus cycle in the multiplexed mode. No
wait state may be inserted if the setup/hold time of the sampling timing is not satisfied.
The wait function is set to on or off by port mode control register CM (PMCCM).
(13) PCS0 to PCS7 (port CS) ... 3-state I/O
PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as chip select signal output in the control mode.
(a) Port mode
PCS0 to PCS7 can be set in the input or output mode in 1-bit units, by using port mode register CS
(PMCS).
(b) Control mode
(i) CS0 to CS3 (Chip select input) ... output
These pins output a chip select signal to external memory and external peripheral I/O.
The CSn signal is assigned to memory block n (n = 0 to 3).
This signal is asserted while a bus cycle for accessing the corresponding memory block is being
executed.
This signal is deasserted in the idle state (TI).
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(14) PCT0 to PCT7 (port CT) ... 3-state I/O
PCT0 to PCT7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as control signal output in the control mode when
memory is externally expanded.
(a) Port mode
PCT0 to PCT7 can be set in the input or output mode in 1-bit units, by using port mode register CT
(PMCT).
(b) Control mode
(i) WR0 (Lower byte write strobe) ... output
This pin outputs the write strobe signal of the lower data of the external 16-bit data bus.
(ii) WR1 (Upper byte write strobe) ... output
This pin outputs the write strobe signal of the higher data of the external 16-bit data bus.
(iii) RD (Read strobe) ... output
This pin outputs the read strobe signal of the external 16-bit data bus.
(iv) ASTB (Address strobe) ... output
This pin outputs the latch strobe signal of the external address bus. The signal output from this pin
goes low at the falling edge of the T1 state of the bus cycle, and goes high at the falling edge of the
T3 state. It goes high while the bus cycle is not active.
(15) PDL0 to PDL15 (port DL) ... 3-state I/O
PDL0 to PDL15 function as a 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, these pins operate as a time-division address/data bus (AD0 to AD15)
when the memory is externally expanded.
PDL5/AD5 also functions as the FLMD1 pin when the flash memory is programmed (when a high level is input
to FLD0). At this time, be sure to input a low level to the FLMD1 pin.
(a) Port mode
PDL0 to PDL15 can be set in the input or output mode in 1-bit units, by using port mode register DL
(PMDL).
(b) Control mode
(i) AD0 to AD15 (Address/Data Bus 0 to 15) ... 3-state I/O
These are multiplexed address/data bus for external access.
(16) RESET (Reset) ... input
RESET input is asynchronous input. When a signal with a fixed low level width is input to the RESET pin
regardless of the operating clock, the system is reset, taking precedence over all the other operations.
This pin is used to release the standby mode (HALT, IDLE, or STOP), as well as for normal initialization/start.
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(17) X1, X2 (Crystal for main clock)
These pins are used to connect the resonator that generates the system clock.
(18) XT1, XT2 (Crystal for subclock)
These pins are used to connect the resonator that generates the subclock.
(19) AV
SS
(Ground for analog)
This is a ground pin for the A/D converter and alternate-function ports.
(20) AV
REF0
(Analog reference voltage) ... input
This pin supplies positive analog power to the A/D converter and alternate-function ports.
It also supplies a reference voltage to the A/D converter.
(21) EV
DD
(Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(22) EV
SS
(Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(23) V
DD
(Power supply)
This pin supplies positive power. Connect all the V
DD
pins to a positive power supply.
(24) V
SS
(Ground)
This is a ground pin. Connect all the V
SS
pins to ground.
(25) FLMD0 (Flash programming mode) ... input
This is a signal input pin for flash memory programming mode.
Connect this pin to V
SS
in the normal operation mode.
(26) BV
DD
(Power supply for port)
This pin supplies positive power to the I/O ports and alternate-function pins.
(27) BV
SS
(Ground for port)
This is a ground pin for the I/O ports and alternate-function pins.
(28) REGC (Regulator control) ... input
This pin connects a capacitor for the regulator.
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2.4 Pin I/O Circuit Types and Recommended Connection of Unused Pins
(1/3)
Pin
I/O Circuit
Type
Recommended Connection
P00/TIP31/TOP31
P01/TIP30/TOP30
P02/NMI
P03/INTP0/ADTRG
P04/INTP1
5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P05/INTP2/DRST 5-AF
Input:
Independently connect to EV
SS
Output: Leave open
P06/INTP3 5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P10/INTP9
P11/INTP10
5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P30/TXDA0 5-A
P31/RXDA0/INTP7
P32/ASCKA0/TIP00/TOP00/
TOP01
P33/TIP01/TOP01
P34/TIP10/TOP10
P35/TIP11/TOP11
5-W
P36
P37
P38/TXDA2
5-A
P39/RXDA2/INTP8 5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P40/SIB0 5-W
P41/SOB0 5-A
P42/SCKB0 5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P50/KR0/TIQ01/TOQ01
P51/KR1/TIQ02/TOQ02
P52/KR2/TIQ03/TOQ03/DDI
P53/KR3/TIQ00/TOQ00/DDO
P54/KR4/DCK
P55/KR5/DMS
5-W
P60/INTP11
P61/INTP12
P62/INTP13
5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
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(2/3)
Pin
I/O Circuit
Type
Recommended Connection
P63
P64
P65
P66
P67
P68
P69
5-A
P610/TIQ20/TOQ20
P611/TIQ21/TOQ21
P612/TIQ22/TOQ22
P613/TIQ23/TOQ23
5-W
P614
P615
5-A
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P70/ANI0 to P79/ANI9
P710/ANI10, P11/ANI11
P712/ANI12 to P715/ANI15
11-G
Input:
Independently connect to AV
REF0
or AV
SS
via a resistor
Output: Leave open
P80/RXDA3
Note
/INTP14 5-W
P81/TXDA3
Note
5-A
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P90/KR6/TXDA1
P91/KR7/RXDA1
P92/TIQ11/TOQ11
P93/TIQ12/TOQ12
P94/TIQ13/TOQ13
P95/TIQ10/TOQ10
P96/TIP21/TOP21
P97/SIB1/TIP20/TOP20
5-W
P98/SOB1 5-A
P99/SCKB1
P910/SIB2
5-W
P911/SOB2 5-A
P912/SCKB2 5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P913/INTP4/PCL
P914/INTP5
P915/INTP6
5-W
Input:
Independently connect to EV
DD
or EV
SS
via a resistor
Output: Leave open
P120/ANI16 to
P127/ANI23
11-G
Input:
Independently connect to AV
REF0
or AV
SS
via a resistor
Output: Leave open
PCD0 to PCD3
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
Note
PD70F3711, 70F3712 only
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(3/3)
Pin I/O
Circuit
Type
Recommended Connection
PCM0/WAIT
PCM1/CLKOUT
PCM2/HLDAK
PCM3/HLDRQ
PCM4
PCM5
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
PCS0/CS0, PCS1/CS1
PCS2/CS2, PCS3/CS3,
PCS4 to PCS7
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
PCT0/WR0
PCT1/WR1
PCT2
PCT3
PCT4/RD
PCT5
PCT6/ASTB
PCT7
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
PDL0/AD0 to PDL4/AD4
PDL5/AD5/FLMD1
PDL6/AD6, PDL7/AD7
PDL8/AD8 to PDL11/AD11
PDL12/AD12, PDL13/AD13
PDL14/AD14, PDL15/AD15
5
Input:
Independently connect to BV
DD
or BV
SS
via a resistor
Output: Leave open
AV
REF0
-
Directly connect to V
DD
AV
SS
-
-
FLMD0
Note
-
Directly connect to V
SS
REGC
-
-
RESET 2
-
X1
-
-
X2
-
-
XT1
16
Connect to V
SS
via a resistor
XT2 16
Leave
open
V
DD
-
-
V
SS
-
-
BV
DD
-
-
BV
SS
-
-
EV
DD
-
-
EV
SS
-
-
Note If noise that exceeds the noise elimination width is input to the RESET pin during self programming, the
flash on-board mode may be entered depending on the capacitance charge end timing when a capacitor is
connected to the FLMD0 pin. Therefore, do not connect a capacitor to the FLMD0 pin.
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2.5 Pin I/O Circuits
Figure 2-1. Pin I/O Circuit Types (1/2)
IN
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Data
Output
disable
AV
REF0
P-ch
IN/OUT
N-ch
P-ch
N-ch
V
REF
(Threshold voltage)
Comparator
Schmitt-triggered input with hysteresis characteristics
Input enable
+
_
AV
SS
AV
SS
Pull-up
enable
Pull-down
enable
Data
Output
disable
Input enable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
N-ch
Type 2
Type 5-AF
Type 5
Type 11-G
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Figure 2-1. Pin I/O Circuit Types (2/2)
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pull-up
enable
Pull-up
enable
Data
Output
disable
Input
enable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
P-ch
Feedback cut-off
XT1
XT2
Type 5-A
Type 5-W
Type 16
2.6 Cautions
Note that the following pin may temporarily output an undefined level, even during reset upon power application.
P53/KR3/TIQ00/TOQ00/DDO pin
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CHAPTER 3 CPU FUNCTION
The CPU of the V850ES/HJ2 is based on RISC architecture and executes almost all instructions with one clock by
using a 5-stage pipeline.
3.1 Features
Minimum instruction execution time: 50 ns (at 20 MHz operation)
Memory space Program (physical address) space: 64 MB linear
Data (logical address) space:
4 GB linear
General-purpose registers: 32 bits
32 registers
Internal 32-bit architecture
5-stage pipeline control
Multiplication/division instruction
Saturation operation instruction
32-bit shift instruction: 1 clock
Load/store instruction with long/short format
Four types of bit manipulation instructions
SET1
CLR1
NOT1
TST1
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3.2 CPU
Register
Set
The registers of the V850ES/HJ2 can be classified into two types: general-purpose program registers and
dedicated system registers. All the registers are 32 bits wide.
For details, refer to the V850ES Architecture User's Manual.
(1) Program register set
(2) System register set
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
r31
(Zero register)
(Assembler-reserved register)
(Stack pointer (SP))
(Global pointer (GP))
(Text pointer (TP))
(Element pointer (EP))
(Link pointer (LP))
PC
(Program counter)
PSW
(Program status word)
ECR
(Interrupt source register)
FEPC
FEPSW
(NMI status saving register)
(NMI status saving register)
EIPC
EIPSW
(Interrupt status saving register)
(Interrupt status saving register)
31
0
31
0
31
0
CTBP
(CALLT base pointer)
DBPC
DBPSW
(Exception/debug trap status saving register)
(Exception/debug trap status saving register)
CTPC
CTPSW
(CALLT execution status saving register)
(CALLT execution status saving register)
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3.2.1
Program register set
The program registers include general-purpose registers and a program counter.
(1) General-purpose registers (r0 to r31)
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a
data variable or an address variable.
However, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are
used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the
SLD and SST instructions as a base pointer when these instructions access the memory. r1, r3 to r5, and r31
are implicitly used by the assembler and C compiler. When using these registers, save their contents for
protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time OS.
If the real-time OS does not use r2, it can be used as a register for variables.
Table 3-1. Program Registers
Name Usage
Operation
r0
Zero register
Always holds 0.
r1
Assembler-reserved register
Used as working register to create 32-bit immediate data
r2
Register for address/data variable (if real-time OS does not use r2)
r3
Stack pointer
Used to create a stack frame when a function is called
r4
Global pointer
Used to access a global variable in the data area
r5
Text pointer
Used as register that indicates the beginning of a text area (area
where program codes are located)
r6 to r29
Register for address/data variable
r30
Element pointer
Used as base pointer to access memory
r31
Link pointer
Used when the compiler calls a function
PC
Program counter
Holds the instruction address during program execution
Remark For furthers details on the r1, r3 to r5, and r31 that are used in the assembler and C compiler, refer
to the CA850 (C Compiler Package) Assembly Language User's Manual.
(2) Program counter (PC)
The program counter holds the instruction address during program execution. The lower 26 bits of this register
are valid. Bits 31 to 26 are fixed to 0. A carry from bit 25 to 26 is ignored even if it occurs.
Bit 0 is fixed to 0. This means that execution cannot branch to an odd address.
31
26 25
1 0
PC
Fixed to 0
Instruction address during program execution
0
Default value
00000000H
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3.2.2
System register set
The system registers control the status of the CPU and hold interrupt information.
These registers can be read or written by using system register load/store instructions (LDSR and STSR), using
the system register numbers listed below.
Table 3-2. System Register Numbers
Operand Specification
System
Register
Number
System Register Name
LDSR Instruction STSR Instruction
0
Interrupt status saving register (EIPC)
Note 1
1
Interrupt status saving register (EIPSW)
Note 1
2
NMI status saving register (FEPC)
Note 1
3
NMI status saving register (FEPSW)
Note 1
4
Interrupt source register (ECR)
5
Program status word (PSW)
6 to 15
Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
16
CALLT execution status saving register (CTPC)
17
CALLT execution status saving register (CTPSW)
18
Exception/debug trap status saving register (DBPC)
Note 2
Note 2
19
Exception/debug trap status saving register (DBPSW)
Note 2
Note 2
20
CALLT base pointer (CTBP)
21 to 31
Reserved for future function expansion (operation is not guaranteed if these
registers are accessed)
Notes 1. Because only one set of these registers is available, the contents of these registers must be saved by
program if multiple interrupts are enabled.
2. These registers can be accessed only during the interval between the execution of the DBTRAP
instruction or illegal opcode and the DBRET instruction.
Caution Even if EIPC or FEPC, or bit 0 of CTPC is set to 1 by the LDSR instruction, bit 0 is ignored when
execution is returned to the main routine by the RETI instruction after interrupt servicing (this is
because bit 0 of the PC is fixed to 0). Set an even value to EIPC, FEPC, and CTPC (bit 0 = 0).
Remark
: Can be accessed
: Access prohibited
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(1) Interrupt status saving registers (EIPC and EIPSW)
EIPC and EIPSW are used to save the status when an interrupt occurs.
If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to
EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to
the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
The address of the instruction next to the instruction under execution, except some instructions (see 16.8
Periods in Which Interrupts Are Not Acknowledged by CPU), is saved to EIPC when a software exception
or a maskable interrupt occurs.
The current contents of the PSW are saved to EIPSW.
Because only one set of interrupt status saving registers is available, the contents of these registers must be
saved by program when multiple interrupts are enabled.
Bits 31 to 26 of EIPC and bits 31 to 8 of EIPSW are reserved for future function expansion (these bits are
always fixed to 0).
The value of EIPC is restored to the PC and the value of EIPSW to the PSW by the RETI instruction.
31
0
EIPC
(Saved PC contents)
0
0
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31
0
EIPSW
(Saved PSW
contents)
0
0
Default value
000000xxH
(x: Undefined)
8 7
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
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(2) NMI status saving registers (FEPC and FEPSW)
FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs.
If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program
status word (PSW) are saved to FEPSW.
The address of the instruction next to the one of the instruction under execution, except some instructions, is
saved to FEPC when an NMI occurs.
The current contents of the PSW are saved to FEPSW.
Because only one set of NMI status saving registers is available, the contents of these registers must be saved
by program when multiple interrupts are enabled.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved for future function expansion (these bits are
always fixed to 0).
The value of FEPC is restored to the PC and the value of FEPSW to the PSW by the RETI instruction.
31
0
FEPC
(Saved PC contents)
0
0
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31
0
FEPSW
(Saved PSW
contents)
0
0
Default value
000000xxH
(x: Undefined)
8 7
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
(3) Interrupt source register (ECR)
The interrupt source register (ECR) holds the source of an exception or interrupt if an exception or interrupt
occurs. This register holds the exception code of each interrupt source. Because this register is a read-only
register, data cannot be written to this register using the LDSR instruction.
31
0
ECR
FECC
EICC
Default value
00000000H
16 15
Bit position
Bit name
Meaning
31 to 16
FECC
Exception code of non-maskable interrupt (NMI)
15 to 0
EICC
Exception code of exception or maskable interrupt
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(4) Program status word (PSW)
The program status word (PSW) is a collection of flags that indicate the status of the program (result of
instruction execution) and the status of the CPU.
If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are
validated immediately after completion of LDSR instruction execution. However if the ID flag is set to 1,
interrupt requests will not be acknowledged while the LDSR instruction is being executed.
Bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0).
(1/2)
31
0
PSW
RFU
Default value
00000020H
8 7
NP
6
EP
5
ID
4
SAT
3
CY
2
OV
1
S Z
Bit position
Flag name
Meaning
31 to 8
RFU
Reserved field. Fixed to 0.
7
NP
Indicates that a non-maskable interrupt (NMI) is being serviced. This bit is set to 1 when an
NMI request is acknowledged, disabling multiple interrupts.
0: NMI is not being serviced.
1: NMI is being serviced.
6
EP
Indicates that an exception is being processed. This bit is set to 1 when an exception
occurs. Even if this bit is set, interrupt requests are acknowledged.
0: Exception is not being processed.
1: Exception is being processed.
5
ID
Indicates whether a maskable interrupt can be acknowledged.
0: Interrupt enabled
1: Interrupt disabled
4
SAT
Note
Indicates that the result of a saturation operation has overflowed and is saturated. Because
this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is
saturated, and is not cleared to 0 even if the subsequent operation result is not saturated.
Use the LDSR instruction to clear this bit. This flag is neither set to 1 nor cleared to 0 by
execution of an arithmetic operation instruction.
0: Not saturated
1: Saturated
3
CY
Indicates whether a carry or a borrow occurs as a result of an operation.
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
2
OV
Note
Indicates whether an overflow occurs during operation.
0: Overflow does not occur.
1: Overflow occurs.
1
S
Note
Indicates whether the result of an operation is negative.
0: The result is positive or 0.
1: The result is negative.
0
Z
Indicates whether the result of an operation is 0.
0: The result is not 0.
1: The result is 0.
Remark Also
read
Note on the next page.
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(2/2)
Note The result of the operation that has performed saturation processing is determined by the contents of the
OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is
performed.
Flag status
Status of operation result
SAT OV S
Result of operation of
saturation processing
Maximum positive value is exceeded
1
1
0
7FFFFFFFH
Maximum negative value is exceeded
1
1
1
80000000H
Positive (maximum value is not exceeded)
0
Negative (maximum value is not exceeded)
Holds value
before operation
0
1
Operation result itself
(5) CALLT execution status saving registers (CTPC and CTPSW)
CTPC and CTPSW are CALLT execution status saving registers.
When the CALLT instruction is executed, the contents of the program counter (PC) are saved to CTPC, and
those of the program status word (PSW) are saved to CTPSW.
The contents saved to CTPC are the address of the instruction next to CALLT.
The current contents of the PSW are saved to CTPSW.
Bits 31 to 26 of CTPC and bits 31 to 8 of CTPSW are reserved for future function expansion (fixed to 0).
31
0
CTPC
(Saved PC contents)
0
0
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31
0
CTPSW
(Saved PSW
contents)
0
0
Default value
000000xxH
(x: Undefined)
8 7
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
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(6) Exception/debug trap status saving registers (DBPC and DBPSW)
DBPC and DBPSW are exception/debug trap status registers.
If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and
those of the program status word (PSW) are saved to DBPSW.
The contents to be saved to DBPC are the address of the instruction next to the one that is being executed
when an exception trap or debug trap occurs.
The current contents of the PSW are saved to DBPSW.
This register can be read or written only during the interval between the execution of the DBTRAP instruction
or illegal opcode and the DBRET instruction.
Bits 31 to 26 of DBPC and bits 31 to 8 of DBPSW are reserved for future function expansion (fixed to 0).
The value of DBPC is restored to the PC and the value of DBPSW to the PSW by the DBRET instruction.
31
0
DBPC
(Saved PC contents)
0
0
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
31
0
DBPSW
(Saved PSW
contents)
0
0
Default value
000000xxH
(x: Undefined)
8 7
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
0
0
0 0 0 0
(7) CALLT base pointer (CTBP)
The CALLT base pointer (CTBP) is used to specify a table address or generate a target address (bit 0 is fixed
to 0).
Bits 31 to 26 of this register are reserved for future function expansion (fixed to 0).
31
0
CTBP
(Base address)
0
0
Default value
0xxxxxxxH
(x: Undefined)
26 25
0 0 0 0
0
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3.3 Operation
Modes
The V850ES/HJ2 has the following operation modes.
(1) Normal operation mode
In this mode, each pin related to the bus interface is set to the port mode after system reset has been released.
Execution branches to the reset entry address of the internal ROM, and then instruction processing is started.
(2) Flash memory programming mode
In this mode, the internal flash memory can be programmed by using a flash programmer.
(3) On-chip debug mode
The V850ES/HJ2 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group)
communication specifications and that is executed via an on-chip debug emulator.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
3.3.1
Specifying operation mode
Specify the operation mode by using the FLMD0 and FLMD1 pins.
In the normal mode, input a low level to the FLMD0 pin when reset is released.
In the flash memory programming mode, a high level is input to the FLMD0 pin from the flash programmer if a flash
programmer is connected, but it must be input from an external circuit in the self-programming mode.
Operation When Reset Is Released
FLMD0 FLMD1
Operation Mode After Reset
L
Normal operation mode
H
L
Flash memory programming mode
H H
Setting
prohibited
Remark L: Low-level input
H: High-level input
: Don't care
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3.4 Address
Space
3.4.1
CPU address space
For instruction addressing, up to a combined total of 16 MB of external memory area and internal ROM area, plus
an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand
addressing (data access), up to 4 GB of a linear address space (data space) is supported. The 4 GB address space,
however, is viewed as 64 images of a 64 MB physical address space. This means that the same 64 MB physical
address space is accessed regardless of the value of bits 31 to 26.
Figure 3-1. Image on Address Space
Program space
Internal RAM area
Use-prohibited area
Use-prohibited area
External memory area
Internal ROM area
(external memory area)
Data space
Image 63
Image 1
Image 0
Peripheral I/O area
Internal RAM area
Use-prohibited area
External memory area
Internal ROM area
(external memory area)
16 MB
4 GB
64 MB
64 MB
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3.4.2
Wraparound of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid.
The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation.
Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are
contiguous addresses. That the highest address and the lowest address of the program space are contiguous
in this way is called wraparound.
Caution Because the 4 KB area of addresses 03FFF000H to 03FFFFFFH is an on-chip peripheral I/O
area, instructions cannot be fetched from this area. Therefore, do not execute an operation in
which the result of a branch address calculation affects this area.
Program space
Program space
(+) direction
(
-) direction
0 0 0 0 0 0 0 1 H
0 0 0 0 0 0 0 0 H
0 3 F F F F F F H
0 3 F F F F F E H
(2) Data space
The result of an operand address calculation operation that exceeds 32 bits is ignored.
Therefore, the highest address of the data space, FFFFFFFFH, and the lowest address, 00000000H, are
contiguous, and wraparound occurs at the boundary of these addresses.
Data space
Data space
(+) direction
(
-) direction
0 0 0 0 0 0 0 1 H
0 0 0 0 0 0 0 0 H
F F F F F F F F H
F F F F F F F E H
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3.4.3 Memory
map
The areas shown below are reserved in the V850ES/HJ2.
Figure 3-2. Data Memory Map (Physical Addresses)
(2 MB)
(80 KB)
Use prohibited
External memory area (64 KB)
Use prohibited
Use prohibited
Internal ROM area
Note 2
(1 MB)
Use prohibited
External memory area (64 KB)
Internal RAM area
(60 KB)
On-chip peripheral I/O area
(4 KB)
Use prohibited
Note 1
0 3 F F F F F F H
0 3 F E C 0 0 0 H
0 0 8 1 0 0 0 0 H
0 0 8 0 F F F F H
External memory area (64 KB)
0 0 4 1 0 0 0 0 H
0 0 4 0 F F F F H
External memory area (64 KB)
0 0 2 1 0 0 0 0 H
0 0 2 0 F F F F H
0 0 8 0 0 0 0 0 0 H
0 0 7 F F F F F F H
0 0 4 0 0 0 0 0 H
0 0 3 F F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 0 0 0 0 0 0 H
0 3 F E B F F F H
0 3 F F F F F F H
0 3 F F F 0 0 0 H
0 3 F F E F F F H
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
Use prohibited
0 3 F E F 0 0 0 H
0 3 F E E F F F H
0 3 F E C 0 0 0 H
0 0 1 F F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 1 1 0 0 0 0 H
0 0 1 0 F F F F H
0 0 0 0 0 0 0 0 H
Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
same area as the on-chip peripheral I/O area.
2.
Fetch access and read access to addresses 00000000H to 000FFFFFH is made to the internal ROM
area. However, data write access to these addresses is made to the external memory area.
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Figure 3-3. Program Memory Map
Internal RAM area (60 KB)
Note
Use prohibited
(program fetch prohibited area)
Use prohibited
(program fetch prohibited area)
External memory area
(14 MB)
External memory area
(1 MB)
Internal ROM area
(1 MB)
0 3 F F F F F F H
0 3 F F F 0 0 0 H
0 3 F F E F F F H
0 1 0 0 0 0 0 0 H
0 0 F F F F F F H
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 0 0 0 0 0 0 H
Note For details, see 3.4.4 (2) Internal RAM area.
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3.4.4 Areas
(1) Internal ROM area
Up to 1 MB is reserved as an internal ROM area.
(a) Internal ROM (128 KB)
128 KB are allocated to addresses 0000000H to 001FFFFH in the
PD70F3709.
Accessing addresses 0020000H to 00FFFFFH is prohibited.
Figure 3-4. Internal ROM Area (128 KB)
00FFFFFH
0020000H
001FFFFH
0000000H
Access-prohibited
area
Internal ROM area
(128 KB)
(b) Internal ROM (256 KB)
256 KB are allocated to addresses 00000000H to 0003FFFFH in the
PD70F3710.
Accessing addresses 00040000H to 000FFFFFH is prohibited.
Figure 3-5. Internal ROM Area (256 KB)
Access-prohibited
area
Internal ROM area
(256 KB)
0 0 4 0 0 0 0 H
0 0 F F F F F H
0 0 3 F F F F H
0 0 0 0 0 0 0 H
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(c) Internal ROM (376 KB)
376 KB are allocated to addresses 00000000H to 0005DFFFH in the
PD70F3711.
Accessing addresses 0005E000H to 000FFFFFH is prohibited.
Figure 3-6. Internal ROM Area (376 KB)
Access-prohibited
area
Internal ROM
(376 KB)
0 0 0 5 E 0 0 0 H
0 0 0 5 D F F F H
0 0 0 0 0 0 0 0 H
0 0 0 F F F F F H
(d) Internal ROM (512 KB)
512 KB are allocated to addresses 00000000H to 0007FFFFH in the
PD70F3712.
Accessing addresses 00080000H to 000FFFFFH is prohibited.
Figure 3-7. Internal ROM Area (512 KB)
Access-prohibited
area
Internal ROM
(512 KB)
0 0 0 8 0 0 0 0 H
0 0 0 7 F F F F H
0 0 0 0 0 0 0 0 H
0 0 0 F F F F F H
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(2) Internal RAM area
Up to 60 KB are reserved as the internal RAM area.
(a) Internal RAM (12 KB)
12 KB are allocated to addresses 03FFC000H to 03FFEFFFH in the following versions.
Accessing addresses 03FF0000H to 03FFBFFFH is prohibited.
PD70F3709, 70F3710
Figure 3-8. Internal RAM Area (12 KB)
Access-prohibited
area
Internal RAM
0 3 F F 0 0 0 0 H
0 3 F F E F F F H
0 3 F F C 0 0 0 H
0 3 F F B F F F H
F F F F C 0 0 0 H
F F F F B F F F H
F F F F 0 0 0 0 H
F F F F E F F F H
Physical address space
Logical address space
(b) Internal RAM (20 KB)
20 KB are allocated to addresses 03FFA000H to 03FFEFFFH in the following versions.
Accessing addresses 03FF0000H to 03FF9FFFH is prohibited.
PD70F3711, 70F3712
Figure 3-9. Internal RAM Area (20 KB)
Access-prohibited
area
Internal RAM
0 3 F F 0 0 0 0 H
0 3 F F E F F F H
0 3 F F A 0 0 0 H
0 3 F F 9 F F F H
F F F F A 0 0 0 H
F F F F 9 F F F H
F F F F 0 0 0 0 H
F F F F E F F F H
Physical address space
Logical address space
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(3) On-chip peripheral I/O area
4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area.
Figure 3-10. On-Chip Peripheral I/O Area
On-chip peripheral I/O area
(4 KB)
0 3 F F F F F F H
0 3 F F F 0 0 0 H
F F F F F F F F H
F F F F F 0 0 0 H
Physical address space
Logical address space
Peripheral I/O registers that have functions to specify the operation mode for and monitor the status of the on-
chip peripheral I/O are mapped to the on-chip peripheral I/O area. Program cannot be fetched from this area.
Cautions 1. When a register is accessed in word units, a word area is accessed twice in halfword
units in the order of lower area and higher area, with the lower 2 bits of the address
ignored.
2. If a register that can be accessed in byte units is accessed in halfword units, the higher 8
bits are undefined when the register is read, and data is written to the lower 8 bits.
3. Addresses not defined as registers are reserved for future expansion. The operation is
undefined and not guaranteed when these addresses are accessed.
(4) External memory area
256 KB are allocated as the external memory area. For details, see CHAPTER 5 BUS CONTROL
FUNCTION.
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3.4.5
Recommended use of address space
The architecture of the V850ES/HJ2 requires that a register that serves as a pointer be secured for address
generation when operand data in the data space is accessed. The address stored in this pointer
32 KB can be
directly accessed by an instruction for operand data. Because the number of general-purpose registers that can be
used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a
pointer value is changed, as many general-purpose registers as possible can be secured for variables, and the
program size can be reduced.
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid.
Regarding the program space, therefore, a 64 MB space of contiguous addresses starting from 00000000H
unconditionally corresponds to the memory map.
To use the internal RAM area as the program space, access following addresses.
Caution If a branch instruction is at the upper limit of the internal RAM area, a prefetch operation
(invalid fetch) straddling the on-chip peripheral I/O area does not occur.
RAM Size
Access Address
20 KB
03FFA000H to 03FFEFFFH
12 KB
03FFC000H to 03FFEFFFH
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(2) Data space
With the V850ES/HJ2, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address
space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated
as an address.
(a) Application example of wraparound
If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H
32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can
be addressed by one pointer.
The zero register (r0) is a register fixed to 0 by hardware, and practically eliminates the need for registers
dedicated to pointers.
Figure 3-11. Wraparound (
PD70F3712)
Access-prohibited
area
8 KB
Internal ROM area
On-chip peripheral
I/O area
Internal RAM area
32 KB
4 KB
20 KB
(R = )
0 0 0 5 F F F F H
0 0 0 0 7 F F F H
0 0 0 0 0 0 0 0 H
F F F F F 0 0 0 H
F F F F E F F F H
F F F F A 0 0 0 H
F F F F 9 F F F H
F F F F 8 0 0 0 H
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Figure 3-12. Recommended Memory Map
Data space
Program space
On-chip
peripheral I/O
On-chip
peripheral I/O
Internal RAM
Internal RAM
Internal ROM
External
memory
Use prohibited
External
memory
Use prohibited
Internal RAM
Program space
64 MB
Internal ROM
Internal ROM
F F F F F F F F H
F F F F F 0 0 0 H
F F F F E F F F H
F F F F 0 0 0 0 H
F F F E F F F F H
0 4 0 0 0 0 0 0 H
0 3 F F F F F F H
0 3 F F F 0 0 0 H
0 3 F F E F F F H
0 3 F F A 0 0 0 H
0 3 F F 9 F F F H
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
0 1 0 0 0 0 0 0 H
0 0 F F F F F F H
0 0 0 8 0 0 0 0 H
0 0 0 7 F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 0 0 0 0 0 0 H
F F F F F F F F H
F F F F F 0 0 0 H
F F F F E F F F H
F F F F A 0 0 0 H
F F F F 9 F F F H
F F F F 0 0 0 0 H
F F F E F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 0 0 0 0 0 0 H
Use prohibited
Remarks 1. indicates the recommended area.
2.
This figure is the recommended memory map of the
PD70F3712.
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3.4.6
Peripheral I/O registers
(1/11)
Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF004H Port
DL
PDL
Undefined
FFFFF004H Port
DLL
PDLL
Undefined
FFFFF005H Port
DLH
PDLH
Undefined
FFFFF008H Port
CS
PCS
Undefined
FFFFF00AH Port
CT
PCT
Undefined
FFFFF00CH Port
CM
PCM
Undefined
FFFFF00EH Port
CD
PCD
Undefined
FFFFF024H
Port mode register DL
PMDL
FFFFH
FFFFF024H
Port mode register DLL
PMDLL
FFH
FFFFF025H
Port mode register DLH
PMDLH
FFH
FFFFF028H
Port mode register CS
PMCS
FFH
FFFFF02AH
Port mode register CT
PMCT
FFH
FFFFF02CH
Port mode register CM
PMCM
FFH
FFFFF02EH
Port mode register CD
PMCD
FFH
FFFFF044H
Port mode control register DL
PMCDL
0000H
FFFFF044H
Port mode control register DLL
PMCDLL
00H
FFFFF045H
Port mode control register DLH
PMCDLH
00H
FFFFF048H
Port mode control register CS
PMCCS
00H
FFFFF04AH
Port mode control register CT
PMCCT
00H
FFFFF04CH
Port mode control register CM
PMCCM
00H
FFFFF066H Bus
size
configuration register
BSC
5555H
FFFFF06EH
System wait control register
VSWC
77H
FFFFF080H
DMA source address register 0L
DSA0L
Undefined
FFFFF082H
DMA source address register 0H
DSA0H
Undefined
FFFFF084H
DMA destination address register 0L
DDA0L
Undefined
FFFFF086H
DMA destination address register 0H
DDA0H
Undefined
FFFFF088H
DMA source address register 1L
DSA1L
Undefined
FFFFF08AH
DMA source address register 1H
DSA1H
Undefined
FFFFF08CH
DMA destination address register 1L
DDA1L
Undefined
FFFFF08EH
DMA destination address register 1H
DDA1H
Undefined
FFFFF090H
DMA source address register 2L
DSA2L
Undefined
FFFFF092H
DMA source address register 2H
DSA2H
Undefined
FFFFF094H
DMA destination address register 2L
DDA2L
Undefined
FFFFF096H
DMA destination address register 2H
DDA2H
Undefined
FFFFF098H
DMA source address register 3L
DSA3L
Undefined
FFFFF09AH
DMA source address register 3H
DSA3H
Undefined
FFFFF09CH
DMA destination address register 3L
DDA3L
Undefined
FFFFF09EH
DMA destination address register 3H
DDA3H
Undefined
FFFFF0C0H
DMA transfer count register 0
DBC0
Undefined
FFFFF0C2H
DMA transfer count register 1
DBC1
Undefined
FFFFF0C4H
DMA transfer count register 2
DBC2
Undefined
FFFFF0C6H
DMA transfer count register 3
DBC3
R/W
Undefined
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(2/11)
Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF0D0H
DMA addressing control register 0
DADC0
0000H
FFFFF0D2H
DMA addressing control register 1
DADC1
0000H
FFFFF0D4H
DMA addressing control register 2
DADC2
0000H
FFFFF0D6H
DMA addressing control register 3
DADC3
0000H
FFFFF0E0H
DMA channel control register 0
DCHC0
00H
FFFFF0E2H
DMA channel control register 1
DCHC1
00H
FFFFF0E4H
DMA channel control register 2
DCHC2
00H
FFFFF0E6H
DMA channel control register 3
DCHC3
00H
FFFFF100H
Interrupt mask register 0
IMR0
FFFFH
FFFFF100H
Interrupt mask register 0L
IMR0L
FFH
FFFFF101H
Interrupt mask register 0H
IMR0H
FFH
FFFFF102H
Interrupt mask register 1
IMR1
FFFFH
FFFFF102H
Interrupt mask register 1L
IMR1L
FFH
FFFFF103H
Interrupt mask register 1H
IMR1H
FFH
FFFFF104H
Interrupt mask register 2
IMR2
FFFFH
FFFFF104H
Interrupt mask register 2L
IMR2L
FFH
FFFFF105H
Interrupt mask register 2H
IMR2H
FFH
FFFFF106H
Interrupt mask register 3
IMR3
FFFFH
FFFFF106H
Interrupt mask register 3L
IMR3L
FFH
FFFFF107H
Interrupt mask register 3H
IMR3H
FFH
FFFFF108H
Interrupt mask register 4
IMR4
FFFFH
FFFFF108H
Interrupt mask register 4L
IMR4L
FFH
FFFFF109H
Interrupt mask register 4H
IMR4H
FFH
FFFFF110H
Interrupt control register
LVIIC
47H
FFFFF112H
Interrupt control register
PIC0
47H
FFFFF114H
Interrupt control register
PIC1
47H
FFFFF116H
Interrupt control register
PIC2
47H
FFFFF118H
Interrupt control register
PIC3
47H
FFFFF11AH
Interrupt control register
PIC4
47H
FFFFF11CH
Interrupt control register
PIC5
47H
FFFFF11EH
Interrupt control register
PIC6
47H
FFFFF120H
Interrupt control register
PIC7
47H
FFFFF122H
Interrupt control register
TQ0OVIC
47H
FFFFF124H
Interrupt control register
TQ0CCIC0
47H
FFFFF126H
Interrupt control register
TQ0CCIC1
47H
FFFFF128H
Interrupt control register
TQ0CCIC2
47H
FFFFF12AH
Interrupt control register
TQ0CCIC3
47H
FFFFF12CH
Interrupt control register
TP0OVIC
47H
FFFFF12EH
Interrupt control register
TP0CCIC0
47H
FFFFF130H
Interrupt control register
TP0CCIC1
47H
FFFFF132H
Interrupt control register
TP1OVIC
47H
FFFFF134H
Interrupt control register
TP1CCIC0
R/W
47H
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF136H
Interrupt control register
TP1CCIC1
47H
FFFFF138H
Interrupt control register
TP2OVIC
47H
FFFFF13AH
Interrupt control register
TP2CCIC0
47H
FFFFF13CH
Interrupt control register
TP2CCIC1
47H
FFFFF13EH
Interrupt control register
TP3OVIC
47H
FFFFF140H
Interrupt control register
TP3CCIC0
47H
FFFFF142H
Interrupt control register
TP3CCIC1
47H
FFFFF144H
Interrupt control register
TM0EQIC0
47H
FFFFF146H
Interrupt control register
CB0RIC
47H
FFFFF148H
Interrupt control register
CB0TIC
47H
FFFFF14AH
Interrupt control register
CB1RIC
47H
FFFFF14CH
Interrupt control register
CB1TIC
47H
FFFFF14EH
Interrupt control register
UA0RIC
47H
FFFFF150H
Interrupt control register
UA0TIC
47H
FFFFF152H
Interrupt control register
UA1RIC
47H
FFFFF154H
Interrupt control register
UA1TIC
47H
FFFFF156H
Interrupt control register
ADIC
47H
FFFFF160H
Interrupt control register
KRIC
47H
FFFFF162H
Interrupt control register
WTIIC
47H
FFFFF164H
Interrupt control register
WTIC
47H
FFFFF166H
Interrupt control register
PIC8
47H
FFFFF168H
Interrupt control register
PIC9
47H
FFFFF16AH
Interrupt control register
PIC10
47H
FFFFF16CH
Interrupt control register
TQ1OVIC
47H
FFFFF16EH
Interrupt control register
TQ1CCIC0
47H
FFFFF170H
Interrupt control register
TQ1CCIC1
47H
FFFFF172H
Interrupt control register
TQ1CCIC2
47H
FFFFF174H
Interrupt control register
TQ1CCIC3
47H
FFFFF176H
Interrupt control register
UA2RIC
47H
FFFFF178H
Interrupt control register
UA2TIC
47H
FFFFF182H
Interrupt control register
DMAIC0
47H
FFFFF184H
Interrupt control register
DMAIC1
47H
FFFFF186H
Interrupt control register
DMAIC2
47H
FFFFF188H
Interrupt control register
DMAIC3
47H
FFFFF18AH
Interrupt control register
PIC11
47H
FFFFF18CH
Interrupt control register
PIC12
47H
FFFFF18EH
Interrupt control register
PIC13
47H
FFFFF190H
Interrupt control register
PIC14
47H
FFFFF192H
Interrupt control register
TQ2OVIC
47H
FFFFF194H
Interrupt control register
TQ2CCIC0
47H
FFFFF196H
Interrupt control register
TQ2CCIC1
47H
FFFFF198H
Interrupt control register
TQ2CCIC2
R/W
47H
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF19AH
Interrupt control register
TQ2CCIC3
47H
FFFFF19CH
Interrupt control register
CB2RIC
47H
FFFFF19EH
Interrupt control register
CB2TIC
47H
FFFFF1A0H
Interrupt control register
UA3RIC
Note
47H
FFFFF1A2H
Interrupt control register
UA3TIC
Note
R/W
47H
FFFFF1FAH
In-service priority register
ISPR
R
00H
FFFFF1FCH Command
register
PRCMD
W
Undefined
FFFFF1FEH
Power save control register
PSC
00H
FFFFF200H
A/D converter mode register 0
ADA0M0
00H
FFFFF201H
A/D converter mode register 1
ADA0M1
00H
FFFFF202H
A/D converter channel specification register
ADA0S
00H
FFFFF203H
A/D converter mode register 2
ADA0M2
00H
FFFFF204H
Power-fail comparison mode register
ADA0PFM
00H
FFFFF205H
Power-fail comparison threshold value register
ADA0PFT
R/W
00H
FFFFF210H
A/D conversion result register 0
ADA0CR0
Undefined
FFFFF211H
A/D conversion result register 0H
ADA0CR0H
Undefined
FFFFF212H
A/D conversion result register 1
ADA0CR1
Undefined
FFFFF213H
A/D conversion result register 1H
ADA0CR1H
Undefined
FFFFF214H
A/D conversion result register 2
ADA0CR2
Undefined
FFFFF215H
A/D conversion result register 2H
ADA0CR2H
Undefined
FFFFF216H
A/D conversion result register 3
ADA0CR3
Undefined
FFFFF217H
A/D conversion result register 3H
ADA0CR3H
Undefined
FFFFF218H
A/D conversion result register 4
ADA0CR4
Undefined
FFFFF219H
A/D conversion result register 4H
ADA0CR4H
Undefined
FFFFF21AH
A/D conversion result register 5
ADA0CR5
Undefined
FFFFF21BH
A/D conversion result register 5H
ADA0CR5H
Undefined
FFFFF21CH
A/D conversion result register 6
ADA0CR6
Undefined
FFFFF21DH
A/D conversion result register 6H
ADA0CR6H
Undefined
FFFFF21EH
A/D conversion result register 7
ADA0CR7
Undefined
FFFFF21FH
A/D conversion result register 7H
ADA0CR7H
Undefined
FFFFF220H
A/D conversion result register 8
ADA0CR8
Undefined
FFFFF221H
A/D conversion result register 8H
ADA0CR8H
Undefined
FFFFF222H
A/D conversion result register 9
ADA0CR9
Undefined
FFFFF223H
A/D conversion result register 9H
ADA0CR9H
Undefined
FFFFF224H
A/D conversion result register 10
ADA0CR10
Undefined
FFFFF225H
A/D conversion result register 10H
ADA0CR10H
Undefined
FFFFF226H
A/D conversion result register 11
ADA0CR11
Undefined
FFFFF227H
A/D conversion result register 11H
ADA0CR11H
Undefined
FFFFF228H
A/D conversion result register 12
ADA0CR12
Undefined
FFFFF229H
A/D conversion result register 12H
ADA0CR12H
R
Undefined
Note
PD70F3711, 70F3712 only
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF22AH
A/D conversion result register 13
ADA0CR13
Undefined
FFFFF22BH
A/D conversion result register 13H
ADA0CR13H
Undefined
FFFFF22CH
A/D conversion result register 14
ADA0CR14
Undefined
FFFFF22DH
A/D conversion result register 14H
ADA0CR14H
Undefined
FFFFF22EH
A/D conversion result register 15
ADA0CR15
Undefined
FFFFF22FH
A/D conversion result register 15H
ADA0CR15H
Undefined
FFFFF230H
A/D conversion result register 16
ADA0CR16
Undefined
FFFFF231H
A/D conversion result register 16H
ADA0CR16H
Undefined
FFFFF232H
A/D conversion result register 17
ADA0CR17
Undefined
FFFFF233H
A/D conversion result register 17H
ADA0CR17H
Undefined
FFFFF234H
A/D conversion result register 18
ADA0CR18
Undefined
FFFFF235H
A/D conversion result register 18H
ADA0CR18H
Undefined
FFFFF236H
A/D conversion result register 19
ADA0CR19
Undefined
FFFFF237H
A/D conversion result register 19H
ADA0CR19H
Undefined
FFFFF238H
A/D conversion result register 20
ADA0CR20
Undefined
FFFFF239H
A/D conversion result register 20H
ADA0CR20H
Undefined
FFFFF23AH
A/D conversion result register 21
ADA0CR21
Undefined
FFFFF23BH
A/D conversion result register 21H
ADA0CR21H
Undefined
FFFFF23CH
A/D conversion result register 22
ADA0CR22
Undefined
FFFFF23DH
A/D conversion result register 22H
ADA0CR22H
Undefined
FFFFF23EH
A/D conversion result register 23
ADA0CR23
Undefined
FFFFF23FH
A/D conversion result register 23H
ADA0CR23H
R
Undefined
FFFFF300H
Key return mode register
KRM
00H
FFFFF308H
Selector operation control register 0
SELCNT0
00H
FFFFF318H
Noise elimination control register
NFC
00H
FFFFF400H Port
0
P0
Undefined
FFFFF402H Port
1
P1
Undefined
FFFFF406H Port
3
P3
Undefined
FFFFF406H Port
3L
P3L
Undefined
FFFFF407H Port
3H
P3H
Undefined
FFFFF408H Port
4
P4
Undefined
FFFFF40AH Port
5
P5
Undefined
FFFFF40CH Port
6
P6
Undefined
FFFFF40CH Port
6L
P6L
Undefined
FFFFF40DH Port
6H
P6H
Undefined
FFFFF40EH Port
7L
P7L
Undefined
FFFFF40FH Port
7H
P7H
Undefined
FFFFF410H Port
8
P8
Undefined
FFFFF412H Port
9
P9
Undefined
FFFFF412H Port
9L
P9L
Undefined
FFFFF413H Port
9H
P9H
Undefined
FFFFF418H Port
12
P12
R/W
Undefined
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF420H
Port mode register 0
PM0
FFH
FFFFF422H
Port mode register 1
PM1
FFH
FFFFF426H
Port mode register 3
PM3
FFFFH
FFFFF426H
Port mode register 3L
PM3L
FFH
FFFFF427H
Port mode register 3H
PM3H
FFH
FFFFF428H
Port mode register 4
PM4
FFH
FFFFF42AH
Port mode register 5
PM5
FFH
FFFFF42CH
Port mode register 6
PM6
FFFFH
FFFFF42CH
Port mode register 6L
PM6L
FFH
FFFFF42DH
Port mode register 6H
PM6H
FFH
FFFFF42EH
Port mode register 7L
PM7L
FFH
FFFFF42FH
Port mode register 7H
PM7H
FFH
FFFFF430H
Port mode register 8
PM8
FFH
FFFFF432H
Port mode register 9
PM9
FFFFH
FFFFF432H
Port mode register 9L
PM9L
FFH
FFFFF433H
Port mode register 9H
PM9H
FFH
FFFFF438H
Port mode register 12
PM12
FFH
FFFFF440H
Port mode control register 0
PMC0
00H
FFFFF442H
Port mode control register 1
PMC1
00H
FFFFF446H
Port mode control register 3
PMC3
0000H
FFFFF446H
Port mode control register 3L
PMC3L
00H
FFFFF447H
Port mode control register 3H
PMC3H
00H
FFFFF448H
Port mode control register 4
PMC4
00H
FFFFF44AH
Port mode control register 5
PMC5
00H
FFFFF44CH
Port mode control register 6
PMC6
0000H
FFFFF44CH
Port mode control register 6L
PMC6L
00H
FFFFF44DH
Port mode control register 6H
PMC6H
00H
FFFFF450H
Port mode control register 8
PMC8
00H
FFFFF452H
Port mode control register 9
PMC9
0000H
FFFFF452H
Port mode control register 9L
PMC9L
00H
FFFFF453H
Port mode control register 9H
PMC9H
00H
FFFFF460H
Port function control register 0
PFC0
00H
FFFFF466H
Port function control register 3L
PFC3L
00H
FFFFF46AH
Port function control register 5
PFC5
00H
FFFFF46CH
Port function control register 6
PFC6
0000H
FFFFF46CH
Port function control register 6L
PFC6L
00H
FFFFF46DH
Port function control register 6H
PFC6H
00H
FFFFF472H
Port function control register 9
PFC9
0000H
FFFFF472H
Port function control register 9L
PFC9L
00H
FFFFF473H
Port function control register 9H
PFC9H
00H
FFFFF484H
Data wait control register 0
DWC0
7777H
FFFFF488H
Address wait control register
AWC
R/W
FFFFH
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF48AH
Bus cycle control register
BCC
AAAAH
FFFFF540H
TMQ0 control register 0
TQ0CTL0
00H
FFFFF541H
TMQ0 control register 1
TQ0CTL1
00H
FFFFF542H
TMQ0 I/O control register 0
TQ0IOC0
00H
FFFFF543H
TMQ0 I/O control register 1
TQ0IOC1
00H
FFFFF544H
TMQ0 I/O control register 2
TQ0IOC2
00H
FFFFF545H
TMQ0 option register 0
TQ0OPT0
00H
FFFFF546H
TMQ0 capture/compare register 0
TQ0CCR0
0000H
FFFFF548H
TMQ0 capture/compare register 1
TQ0CCR1
0000H
FFFFF54AH
TMQ0 capture/compare register 2
TQ0CCR2
0000H
FFFFF54CH
TMQ0 capture/compare register 3
TQ0CCR3
R/W
0000H
FFFFF54EH
TMQ0 counter read buffer register
TQ0CNT
R
0000H
FFFFF590H
TMP0 control register 0
TP0CTL0
00H
FFFFF591H
TMP0 control register 1
TP0CTL1
00H
FFFFF592H
TMP0 I/O control register 0
TP0IOC0
00H
FFFFF593H
TMP0 I/O control register 1
TP0IOC1
00H
FFFFF594H
TMP0 I/O control register 2
TP0IOC2
00H
FFFFF595H
TMP0 option register 0
TP0OPT0
00H
FFFFF596H
TMP0 capture/compare register 0
TP0CCR0
0000H
FFFFF598H
TMP0 capture/compare register 1
TP0CCR1
R/W
0000H
FFFFF59AH
TMP0 counter read buffer register
TP0CNT
R
0000H
FFFFF5A0H
TMP1 control register 0
TP1CTL0
00H
FFFFF5A1H
TMP1 control register 1
TP1CTL1
00H
FFFFF5A2H
TMP1 I/O control register 0
TP1IOC0
00H
FFFFF5A3H
TMP1 I/O control register 1
TP1IOC1
00H
FFFFF5A4H
TMP1 I/O control register 2
TP1IOC2
00H
FFFFF5A5H
TMP1 option register 0
TP1OPT0
00H
FFFFF5A6H
TMP1 capture/compare register 0
TP1CCR0
0000H
FFFFF5A8H
TMP1 capture/compare register 1
TP1CCR1
R/W
0000H
FFFFF5AAH
TMP1 counter read buffer register
TP1CNT
R
0000H
FFFFF5B0H
TMP2 control register 0
TP2CTL0
00H
FFFFF5B1H
TMP2 control register 1
TP2CTL1
00H
FFFFF5B2H
TMP2 I/O control register 0
TP2IOC0
00H
FFFFF5B3H
TMP2 I/O control register 1
TP2IOC1
00H
FFFFF5B4H
TMP2 I/O control register 2
TP2IOC2
00H
FFFFF5B5H
TMP2 option register 0
TP2OPT0
00H
FFFFF5B6H
TMP2 capture/compare register 0
TP2CCR0
0000H
FFFFF5B8H
TMP2 capture/compare register 1
TP2CCR1
R/W
0000H
FFFFF5BAH
TMP2 counter read buffer register
TP2CNT
R
0000H
FFFFF5C0H
TMP2 control register 0
TP3CTL0
00H
FFFFF5C1H
TMP2 control register 1
TP3CTL1
00H
FFFFF5C2H
TMP3 I/O control register 0
TP3IOC0
R/W
00H
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF5C3H
TMP3 I/O control register 1
TP3IOC1
00H
FFFFF5C4H
TMP3 I/O control register 2
TP3IOC2
00H
FFFFF5C5H
TMP3 option register 0
TP3OPT0
00H
FFFFF5C6H
TMP3 capture/compare register 0
TP3CCR0
0000H
FFFFF5C8H
TMP3 capture/compare register 1
TP3CCR1
R/W
0000H
FFFFF5CAH
TMP3 counter read buffer register
TP3CNT
R
0000H
FFFFF610H
TMQ1 control register 0
TQ1CTL0
00H
FFFFF611H
TMQ1 control register 1
TQ1CTL1
00H
FFFFF612H
TMQ1 I/O control register 0
TQ1IOC0
00H
FFFFF613H
TMQ1 I/O control register 1
TQ1IOC1
00H
FFFFF614H
TMQ1 I/O control register 2
TQ1IOC2
00H
FFFFF615H
TMQ1 timer option register 0
TQ1OPT0
00H
FFFFF616H
TMQ1 capture/compare register 0
TQ1CCR0
0000H
FFFFF618H
TMQ1 capture/compare register 1
TQ1CCR1
0000H
FFFFF61AH
TMQ1 capture/compare register 2
TQ1CCR2
0000H
FFFFF61CH
TMQ1 capture/compare register 3
TQ1CCR3
R/W
0000H
FFFFF61EH
TMQ1 counter read buffer register
TQ1CNT
R
0000H
FFFFF620H
TMQ2 control register 0
TQ2CTL0
00H
FFFFF621H
TMQ2 control register 1
TQ2CTL1
00H
FFFFF622H
TMQ2 I/O control register 0
TQ2IOC0
00H
FFFFF623H
TMQ2 I/O control register 1
TQ2IOC1
00H
FFFFF624H
TMQ2 I/O control register 2
TQ2IOC2
00H
FFFFF625H
TMQ2 timer option register 0
TQ2OPT0
00H
FFFFF626H
TMQ2 capture/compare register 0
TQ2CCR0
0000H
FFFFF628H
TMQ2 capture/compare register 1
TQ2CCR1
0000H
FFFFF62AH
TMQ2 capture/compare register 2
TQ2CCR2
0000H
FFFFF62CH
TMQ2 capture/compare register 3
TQ2CCR3
R/W
0000H
FFFFF62EH
TMQ2 counter read buffer register
TQ2CNT
R
0000H
FFFFF680H
Watch timer operation mode register
WTM
00H
FFFFF690H
TMM0 control register 0
TM0CTL0
00H
FFFFF694H
TMM0 compare register 0
TM0CMP0
0000H
FFFFF6C0H
Oscillation stabilization time select register
OSTS
06H
FFFFF6C1H
PLL lockup time specification register
PLLS
03H
FFFFF6D0H
Watchdog timer mode register 2
WDTM2
67H
FFFFF6D1H
Watchdog timer enable register
WDTE
9AH
FFFFF706H
Port function control expansion register 3L
PFCE3L
00H
FFFFF70AH
Port function control expansion register 5
PFCE5
00H
FFFFF712H
Port function control expansion register 9
PFCE9
0000H
FFFFF712H
Port function control expansion register 9L
PFCE9L
00H
FFFFF713H
Port function control expansion register 9H
PFCE9H
00H
FFFFF802H System
status
register
SYS
00H
FFFFF80CH
Internal oscillation mode register
RCM
R/W
00H
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFF810H
DMA trigger source register 0
DTFR0
00H
FFFFF812H
DMA trigger source register 1
DTFR1
00H
FFFFF814H
DMA trigger source register 2
DTFR2
00H
FFFFF816H
DMA trigger source register 3
DTFR3
00H
FFFFF820H
Power save mode register
PSMR
R/W
00H
FFFFF824H Lock
register
LOCKR
R
00H
FFFFF828H
Processor clock control register
PCC
03H
FFFFF82CH
PLL control register
PLLCTL
R/W
01H
FFFFF82EH
CPU operating clock status register
CCLS
R
00H
FFFFF82FH
Programmable clock mode register
PCLM
00H
FFFFF870H
Clock monitor mode register
CLM
00H
FFFFF888H
Reset source flag register
RESF
00H
FFFFF890H
Low-voltage detection register
LVIM
00H
FFFFF891H
Low-voltage detection level select register
LVIS
00H
FFFFF892H
Internal RAM data status register
RAMS
01H
FFFFF8B0H
Prescaler mode register 0
PRSM0
00H
FFFFF8B1H
Prescaler compare register 0
PRSCM0
00H
FFFFF9FCH
On-chip debug mode register
OCDM
01H
FFFFF9FEH Peripheral
emulation register 1
PEMU1
00H
FFFFFA00H
UARTA0 control register 0
UA0CTL0
10H
FFFFFA01H
UARTA0 control register 1
UA0CTL1
00H
FFFFFA02H
UARTA0 control register 2
UA0CTL2
FFH
FFFFFA03H
UARTA0 option control register 0
UA0OPT0
14H
FFFFFA04H UARTA0
status
register
UA0STR
R/W
00H
FFFFFA06H
UARTA0 receive data register
UA0RX
R
FFH
FFFFFA07H
UARTA0 transmit data register
UA0TX
FFH
FFFFFA10H
UARTA1 control register 0
UA1CTL0
10H
FFFFFA11H
UARTA1 control register 1
UA1CTL1
00H
FFFFFA12H
UARTA1 control register 2
UA1CTL2
FFH
FFFFFA13H
UARTA1 option control register 0
UA1OPT0
14H
FFFFFA14H UARTA1
status
register
UA1STR
R/W
00H
FFFFFA16H
UARTA1 receive data register
UA1RX
R
FFH
FFFFFA17H
UARTA1 receive data register
UA1TX
FFH
FFFFFA20H
UARTA2 control register 0
UA2CTL0
10H
FFFFFA21H
UARTA2 control register 1
UA2CTL1
00H
FFFFFA22H
UARTA2 control register 2
UA2CTL2
FFH
FFFFFA23H
UARTA2 option control register 0
UA2OPT0
14H
FFFFFA24H UARTA2
status
register
UA2STR
R/W
00H
FFFFFA26H
UARTA2 receive data register
UA2RX
R
FFH
FFFFFA27H
UARTA2 transmit data register
UA2TX
R/W
FFH
Caution For details of the OCDM register, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
CHAPTER 3 CPU FUNCTION
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Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFFA30H
UARTA3 control register 0
UA3CTL0
Note
10H
FFFFFA31H
UARTA3 control register 1
UA3CTL1
Note
00H
FFFFFA32H
UARTA3 control register 2
UA3CTL2
Note
FFH
FFFFFA33H
UARTA3 option control register 0
UA3OPT0
Note
14H
FFFFFA34H UARTA3
status
register
UA3STR
Note
R/W
00H
FFFFFA36H
UARTA3 receive data register
UA3RX
Note
R
FFH
FFFFFA37H
UARTA3 transmit data register
UA3TX
Note
FFH
FFFFFB00H
TIP00 pin noise elimination control register
P00NFC
00H
FFFFFB04H
TIP01 pin noise elimination control register
P01NFC
00H
FFFFFB08H
TIP10 pin noise elimination control register
P10NFC
00H
FFFFFB0CH
TIP11 pin noise elimination control register
P11NFC
00H
FFFFFB10H
TIP20 pin noise elimination control register
P20NFC
00H
FFFFFB14H
TIP21 pin noise elimination control register
P21NFC
00H
FFFFFB18H
TIP30 pin noise elimination control register
P30NFC
00H
FFFFFB1CH
TIP31 pin noise elimination control register
P31NFC
00H
FFFFFB50H
TIQ00 pin noise elimination control register
Q00NFC
00H
FFFFFB54H
TIQ01 pin noise elimination control register
Q01NFC
00H
FFFFFB58H
TIQ02 pin noise elimination control register
Q02NFC
00H
FFFFFB5CH
TIQ03 pin noise elimination control register
Q03NFC
00H
FFFFFB60H
TIQ10 pin noise elimination control register
Q10NFC
00H
FFFFFB64H
TIQ11 pin noise elimination control register
Q11NFC
00H
FFFFFB68H
TIQ12 pin noise elimination control register
Q12NFC
00H
FFFFFB6CH
TIQ13 pin noise elimination control register
Q13NFC
00H
FFFFFB70H
TIQ20 pin noise elimination control register
Q20NFC
00H
FFFFFB74H
TIQ21 pin noise elimination control register
Q21NFC
00H
FFFFFB78H
TIQ22 pin noise elimination control register
Q22NFC
00H
FFFFFB7CH
TIQ23 pin noise elimination control register
Q23NFC
00H
FFFFFC00H
External interrupt falling edge specification register 0
INTF0
00H
FFFFFC02H
External interrupt falling edge specification register 1
INTF1
00H
FFFFFC06H
External interrupt falling edge specification register 3
INTF3
0000H
FFFFFC06H
External interrupt falling edge specification register 3L INTF3L
00H
FFFFFC07H
External interrupt falling edge specification register 3H INTF3H
00H
FFFFFC0CH
External interrupt falling edge specification register 6L INTF6L
00H
FFFFFC10H
External interrupt falling edge specification register 8
INTF8
00H
FFFFFC13H
External interrupt falling edge specification register 9H INTF9H
00H
FFFFFC20H
External interrupt rising edge specification register 0
INTR0
00H
FFFFFC22H
External interrupt rising edge specification register 1
INTR1
R/W
00H
Note
PD70F3711, 70F3712 only
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(11/11)
Manipulatable Bits
Address Function
Register
Name Symbol
R/W
1 8 16
Default Value
FFFFFC26H
External interrupt rising edge specification register 3
INTR3
0000H
FFFFFC26H External interrupt rising edge specification register 3L
INTR3L
00H
FFFFFC27H External interrupt rising edge specification register 3H
INTR3H
00H
FFFFFC2CH
External interrupt rising edge specification register 6L
INTR6L
00H
FFFFFC30H
External interrupt rising edge specification register 8
INTR8
00H
FFFFFC33H
External interrupt rising edge specification register 9H
INTR9H
00H
FFFFFC40H
Pull-up resistor option register 0
PU0
00H
FFFFFC42H
Pull-up resistor option register 1
PU1
00H
FFFFFC46H
Pull-up resistor option register 3
PU3
0000H
FFFFFC46H Pull-up resistor option register 3L
PU3L
00H
FFFFFC47H Pull-up resistor option register 3H
PU3H
00H
FFFFFC48H
Pull-up resistor option register 4
PU4
00H
FFFFFC4AH
Pull-up resistor option register 5
PU5
00H
FFFFFC4CH
Pull-up resistor option register 6
PU6
0000H
FFFFFC4CH Pull-up resistor option register 6L
PU6L
00H
FFFFFC4DH Pull-up resistor option register 6H
PU6H
00H
FFFFFC50H
Pull-up resistor option register 8
PU8
00H
FFFFFC52H
Pull-up resistor option register 9
PU9
0000H
FFFFFC52H Pull-up resistor option register 9L
PU9L
00H
FFFFFC53H Pull-up resistor option register 9H
PU9H
00H
FFFFFD00H
CSIB0 control register 0
CB0CTL0
01H
FFFFFD01H
CSIB0 control register 1
CB0CTL1
00H
FFFFFD02H
CSIB0 control register 2
CB0CTL2
00H
FFFFFD03H CSIB0
status
register
CB0STR
R/W
00H
FFFFFD04H
CSIB0 receive data register
CB0RX
0000H
FFFFFD04H CSIB0 receive data register L
CB0RXL
R
00H
FFFFFD06H
CSIB0 transmit data register
CB0TX
0000H
FFFFFD06H CSIB0 transmit data register L
CB0TXL
00H
FFFFFD10H
CSIB1 control register 0
CB1CTL0
01H
FFFFFD11H
CSIB1 control register 1
CB1CTL1
00H
FFFFFD12H
CSIB1 control register 2
CB1CTL2
00H
FFFFFD13H CSIB1
status
register
CB1STR
R/W
00H
FFFFFD14H
CSIB1 receive data register
CB1RX
0000H
FFFFFD14H CSIB1 receive data register L
CB1RXL
R
00H
FFFFFD16H
CSIB1 transmit data register
CB1TX
0000H
FFFFFD16H CSIB1 transmit data register L
CB1TXL
00H
FFFFFD20H
CSIB2 control register 0
CB2CTL0
01H
FFFFFD21H
CSIB2 control register 1
CB2CTL1
00H
FFFFFD22H
CSIB2 control register 2
CB2CTL2
00H
FFFFFD23H CSIB2
status
register
CB2STR
R/W
00H
FFFFFD24H
CSIB2 receive data register
CB2RX
0000H
FFFFFD24H CSIB2 receive data register L
CB2RXL
R
00H
FFFFFD26H
CSIB2 transmit data register
CB2TX
0000H
FFFFFD26H CSIB2 transmit data register L
CB2TXL
R/W
00H
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3.4.7 Special
registers
Special registers are registers that are protected from being written with illegal data due to a program hang-up.
V850ES/HJ2 has the following seven special registers.
Power save control register (PSC)
Processor clock control register (PCC)
Clock monitor mode register (CLM)
Reset source flag register (RESF)
Low-voltage detection register (LVIM)
Internal RAM data status register (RAMS)
On-chip debug mode register (OCDM)
In addition, the PRCDM register is provided to protect against a write access to the special registers so that the
application system does not inadvertently stop due to a program hang-up. A write access to the special registers is
made in a specific sequence, and an illegal store operation is reported to the SYS register.
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(1) Setting data to special registers
Set data to the special registers in the following sequence.
<1>
Disable DMA operation.
<2>
Prepare data to be set to the special register in a general-purpose register.
<3>
Write the data prepared in <2> to the PRCMD register.
<4>
Write the setting data to the special register (by using the following instructions).
Store instruction (ST/SST instruction)
Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
(<5> to <9> Insert NOP instructions (5 instructions).)
Note
<10>
Enable DMA operation if necessary.
[Example] With PSC register (setting standby mode)
ST.B r11, PSMR[r0] ;
Set PSMR register (setting IDLE1, IDLE2, and STOP modes).
<1>CLR1 0, DCHCn[r0]
;
Disable DMA operation. n = 0 to 3
<2>MOV0x02, r10
<3>ST.B r10, PRCMD[r0] ;
Write PRCMD register.
<4>ST.B r10, PSC[r0]
;
Set PSC register.
<5>NOP
Note
;
Dummy instruction
<6>NOP
Note
;
Dummy instruction
<7>NOP
Note
;
Dummy instruction
<8>NOP
Note
;
Dummy instruction
<9>NOP
Note
;
Dummy instruction
<10>SET1 0, DCHCn[r0] ;
Enable DMA operation. n = 0 to 3
(next instruction)
There is no special sequence to read a special register.
Note Five NOP instructions or more must be inserted immediately after setting the IDLE1 mode, IDLE2
mode, or STOP mode (by setting the PSC.STP bit to 1).
Cautions 1. When a store instruction is executed to store data in the command register, interrupts are
not acknowledged. This is because it is assumed that steps <3> and <4> above are
performed by successive store instructions. If another instruction is placed between <3>
and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may
not be established, causing malfunction.
2. Although dummy data is written to the PRCMD register, use the same general-purpose
register used to set the special register (<4> in Example) to write data to the PRCMD
register (<3> in Example). The same applies when a general-purpose register is used for
addressing.
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(2) Command register (PRCMD)
The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application
system from being written, so that the system does not inadvertently stop due to a program hang-up. The first
write access to a special register is valid after data has been written in advance to the PRCMD register. In this
way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register
from an illegal write access.
The PRCMD register is write-only, in 8-bit units (undefined data is read when this register is read).
7
REG7
PRCMD
6
REG6
5
REG5
4
REG4
3
REG3
2
REG2
1
REG1
0
REG0
After reset: Undefined W Address: FFFFF1FCH
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(3) System status register (SYS)
Status flags that indicate the operation status of the overall system are allocated to this register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
Protection error did not occur
Protection error occurred
PRERR
0
1
Detects protection error
SYS
0
0
0
0
0
0
PRERR
After reset: 00H R/W Address: FFFFF802H
The PRERR flag operates under the following conditions.
(a) Set condition (PRERR flag = 1)
(i) When data is written to a special register without writing anything to the PRCMD register (when <4> is
executed without executing <3> in 3.4.7 (1) Setting data to special registers)
(ii) When data is written to an on-chip peripheral I/O register other than a special register (including
execution of a bit manipulation instruction) after writing data to the PRCMD register (if <4> in 3.4.7 (1)
Setting data to special registers is not the setting of a special register)
Remark Even if an on-chip peripheral I/O register is read (except by a bit manipulation instruction)
between an operation to write the PRCMD register and an operation to write a special register,
the PRERR flag is not set, and the set data can be written to the special register.
(b) Clear condition (PRERR flag = 0)
(i) When 0 is written to the PRERR flag
(ii) When the system is reset
Cautions 1. If 0 is written to the PRERR bit of the SYS register, which is not a special register,
immediately after a write access to the PRCMD register, the PRERR bit is cleared to 0
(the write access takes precedence).
2. If data is written to the PRCMD register, which is not a special register, immediately
after a write access to the PRCMD register, the PRERR bit is set to 1.
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3.4.8 Cautions
(1) Registers to be set first
Be sure to set the following registers first when using the V850ES/HJ2.
System wait control register (VSWC)
On-chip debug mode register (OCDM)
Watchdog timer mode register 2 (WDTM2)
After setting the VSWC, OCDM, and WDTM2 registers, set the other registers as necessary.
When using the external bus, set each pin to the alternate-function bus control pin mode by using the port-
related registers after setting the above registers.
(a) System wait control register (VSWC)
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers.
Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The
V850ES/HJ2 requires wait cycles according to the operating frequency. Set the following value to the
VSWC register in accordance with the frequency used.
The VSWC register can be read or written in 8-bit units (address: FFFFF06EH, default value: 77H).
Operating Frequency (f
CLK
)
Set Value of VSWC
Number of Waits
32 kHz
f
CLK
< 16.6 MHz
00H
0 (no waits)
16.6 MHz
f
CLK
20 MHz
01H
1
(b) On-chip debug mode register (OCDM)
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
(c) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and the operation clock of watchdog timer 2.
Watchdog timer 2 automatically starts in the reset mode after reset is released. Write the WDTM2 register
to activate this operation.
For details, see CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.
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(2) Accessing specific on-chip peripheral I/O registers
This product has two types of internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware.
The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and
an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. If there is
a possibility of a conflict, the number of cycles for accessing the CPU changes when the peripheral hardware is
accessed, so that correct data is transferred. As a result, the CPU does not start processing of the next
instruction but enters the wait state. If this wait state occurs, the number of clocks required to execute an
instruction increases by the number of wait clocks shown below.
This must be taken into consideration if real-time processing is required.
When specific on-chip peripheral I/O registers are accessed, more wait states may be required in addition to
the wait states set by the VSWC register.
The access conditions and how to calculate the number of wait states to be inserted (number of CPU clocks)
at this time are shown below.
Peripheral Function
Register Name
Access
k
TPnCNT
Read
1 or 2
Write
1st access: No wait
Continuous write: 3 or 4
16-bit timer/event counter P (TMP)
(n = 0 to 3)
TPnCCR0, TPnCCR1
Read
1 or 2
TQmCNT
Read
1 or 2
Write
1st access: No wait
Continuous write: 3 or 4
16-bit timer/event counter Q (TMQ)
(m = 0 to 2)
TQmCCR0 to TQmCCR3
Read
1 or 2
Watchdog timer 2 (WDT2)
WDTM2
Write
(when WDT2 operating)
3
ADA0M0
Read
1 or 2
ADA0CR0 to ADA0CR23
Read
1 or 2
A/D converter
ADA0CR0H to ADA0CR23H
Read
1 or 2
Number of clocks necessary for access = 3 + i + j + (2 + j)
k
Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is
generated, it can only be cleared by a reset.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
Remark i: Values (0 or 1) of higher 4 bits of VSWC register
j: Values (0 or 1) of lower 4 bits of VSWC register
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(3) Restriction on conflict between sld instruction and interrupt request
(a) Description
If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld
instruction following an instruction in <1> and an interrupt request before the instruction in <1> is
complete, the execution result of the instruction in <1> may not be stored in a register.
Instruction <1>
ld instruction:
ld.b, ld.h, ld.w, ld.bu, ld.hu
sld instruction:
sld.b, sld.h, sld.w, sld.bu, sld.hu
Multiplication instruction: mul, mulh, mulhi, mulu
Instruction <2>
mov reg1, reg2
satadd reg1, reg2
and reg1, reg2
add reg1, reg2
mulh reg1, reg2
not reg1, reg2
satadd imm5, reg2
tst reg1, reg2
add imm5, reg2
shr imm5, reg2
satsubr reg1, reg2
or reg1, reg2
subr reg1, reg2
cmp reg1, reg2
sar imm5, reg2
satsub reg1, reg2
xor reg1, reg2
sub reg1, reg2
cmp imm5, reg2
shl imm5, reg2
<Example>
<i> ld.w [r11], r10
If the decode operation of the mov instruction <ii> immediately before the sld
instruction <iii> and an interrupt request conflict before execution of the ld
instruction <i> is complete, the execution result of instruction <i> may not be
stored in a register.
<ii> mov r10, r28
<iii> sld.w 0x28, r10
(b) Countermeasure
<1> When compiler (CA850) is used
Use CA850 Ver. 2.61 or later because generation of the corresponding instruction sequence can be
automatically suppressed.
<2> Countermeasure by assembler
When executing the sld instruction immediately after instruction <ii>, avoid the above operation using
either of the following methods.
Insert a nop instruction immediately before the sld instruction.
Do not use the same register as the sld instruction destination register in the above instruction <ii>
executed immediately before the sld instruction.
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CHAPTER 4 PORT FUNCTIONS
4.1 Features
O I/O ports: 128
O Port pins function alternately as other peripheral-function I/O pins
O Can be set in input or output mode in 1-bit units.
4.2 Basic Configuration of Ports
The V850ES/HJ2 has a total of 128 I/O ports, ports 0, 1, 3 to 9, 12, CD, CM, CS, CT, and DL. The port
configuration is shown below.
Figure 4-1. Port Configuration
P00
P06
Port 0
PCD0
PCD3
Port CD
PCM0
PCM5
Port CM
PCS0
PCS7
PCT0
PCT7
Port CS
Port CT
P90
P915
Port 9
P120
P127
Port 12
PDL0
PDL15
Port DL
P30
P39
Port 3
Port 1
P40
P42
Port 4
P50
P55
Port 5
P60
P615
P70
P715
P80
P81
Port 6
P10
P11
Port 7
Port 8
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Table 4-1. Configuration of Ports
Item Configuration
Port mode register (PMn: n = 0, 1, 3, 4, 5, 6, 7L, 7H, 8, 9, 12, CD, CM, CS, CT, or DL)
Port mode control register (PMCn: n = 0, 1, 3, 4, 5, 6, 8, 9, CD, CM, CS, CT, or DL)
Port function control register (PFCn: n = 0, 3L, 5, 6, or 9)
Port function control expansion register (PFCEn: n = 3L, 5, or 9)
Control registers
Pull-up resistor option register (PUn: n = 0, 1, 3, 4, 5, 6, 8, or 9)
Ports 128
Table 4-2. Pin I/O Buffer Power Supplies
Power Supply
Corresponding Pin
AV
REF0
Port 7, port 12
BV
DD
Port CD, port CM, port CS, port CT, port DL
EV
DD
Port 0, port 1, port 3, port 4, port 5, port 6, port 8, port 9, RESET
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4.3 Port
Functions
4.3.1
Operation of port function
The operation of a port differs depending on setting of the input or output mode, as follows.
(1) Writing to I/O port
(a) In output mode
A value can be written to the output latch by using a transfer instruction. The contents of the output latch
are output from the pin. Once data has been written to the output latch, it is retained until new data is
written to the output latch.
(b) In input mode
A value can be written to the output latch by using a transfer instruction. Because the output buffer is off,
however, the status of the pin remains unchanged.
Once data has been written to the output latch, it is retained until new data is written to the output latch.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in
8-bit units. If a port has a mixture of input and output pins, therefore, the contents of the
output latch of a pin set in the input mode become undefined, even if the pin is not
subject to manipulation.
(2) Reading from I/O port
(a) In output mode
The contents of the output latch can be read by using a transfer instruction. The contents of the output
latch are not changed.
(b) In input mode
The status of the pin can be read by using a transfer instruction. The contents of the output latch are not
changed.
(3) Operation of I/O port
(a) In output mode
An operation is performed on the contents of the output latch and the result is written to the output latch.
The contents of the output latch are output from the pin.
Once data has been written to the output latch, it is retained until new data is written to the output latch.
(b) In input mode
The contents of the output latch become undefined. Because the output buffer is off, however, the status
of the pin remains unchanged.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in
8-bit units. If a port has a mixture of input and output pins, therefore, the contents of the
output latch of a pin set in the input mode become undefined, even if the pin is not
subject to manipulation.
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4.3.2
Notes on setting port pins
(1) The number of ports and alternate functions differs depending on the product. Set the registers related to the
unavailable ports and alternate functions to the value after reset.
(2) Set the registers of the ports using the following procedure.
<1> Set port function control register n (PFCn) and port function control expansion register n (PFCEn).
<2> Set port mode control register n (PMCn).
<3> Set external interrupt falling edge specification register n (INTFn) and external interrupt rising edge
specification register n (INTRn).
If the PFCn and PFCEn registers are set after the PMCn register was set, an unexpected peripheral function
pin may be set while the PFCn and PFCEn registers are being set.
(3) The PUnm bit (which connects an on-chip pull-up resistor) of the PUn register is valid only in the input mode
(PMnm bit of PMn register = 1). In the output mode (PMnm bit of PMn register = 0), the on-chip pull-up
register is disconnected by hardware.
(4) Reading the pin level and port latch is controlled by the port mode register (PMn). The same applies when an
alternate function is used.
(5) The Schmitt (SHMT)-trigger input buffer does not operate as an SHMT buffer when it is read in the port mode.
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4.3.3 Port
0
Port 0 is a 7-bit port (P00 to P06) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 0
The input/output data of the port can be specified in 1-bit units.
Specified by port register 0 (P0)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 0 (PM0)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 0 (PMC0)
Control mode 1 or control mode 2 can be specified in 1-bit units.
Specified by port function control register 0 (PFC0)
An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 0 (PU0)
The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 0 (INTF0) and external interrupt rising edge
specification register 0 (INTR0)
Port 0 functions alternately as the following pins.
Table 4-3. Alternate-Function Pins of Port 0
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P00 TP31/TOP31
G-1
P01 TP30/TOP30
G-1
P02 NMI
Note 1
L-1
P03 INTP0/ADTRG
N-1
P04 INTP1
L-1
P05 INTP2/DRST
Note 2
AA-1
Port 0
P06 INTP3
I/O
L-1
Notes 1. The NMI pin alternately functions as the P02 pin. It functions as the P02 pin after reset.
To enable the NMI pin, set the PMC0.PMC02 bit to 1. The initial setting of the NMI pin is "No edge
detected". Select the NMI pin valid edge using INTF0 and INTR0 registers.
2. The alternate function of the P05 pin is the on-chip debug function. After external reset, the
P05/INTP2/DRST pin is initialized as the on-chip debug pin (DRST). To use the P05 pin as a port
pin, not as an on-chip debug pin, the following actions must be taken.
<1> Clear the OCDM0 bit of the OCDM register (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the
above actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in
handling the P05 pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is
not necessary to manipulate the OCDM0 bit of the OCDM register.
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Because a pull-down resistor (30 k
TYP) is connected to the buffer of the P05/INTP2/DRST pin,
the pin does not have to be fixed to the low level by an external source. The pull-down resistor is
disconnected by clearing the OCDM0 bit to 0.
Caution The P00 to P06 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
(2) Registers
(a) Port register 0 (P0)
Port register 0 (P0) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF400H
7 6 5 4 3 2 1 0
P0 0 P06 P05 P04 P03 P02 P01 P00
P0n
Control of output data (in output mode) (n = 0 to 6)
0
Output
0.
1
Output
1.
(b) Port mode register 0 (PM0)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF420H
7 6 5 4 3 2 1 0
PM0
1
PM06 PM05 PM04 PM03 PM02 PM01 PM00
PM0n
Control of input/output mode (n = 0 to 6)
0
Output
mode
1
Input
mode
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(c) Port mode control register 0 (PMC0)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After
reset:
00H
R/W
Address:
FFFFF440H
7 6 5 4 3 2 1 0
PMC0
0
PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00
PMC06
Specification of operation mode of P06 pin
0
I/O
port
1
INTP3
input
PMC05
Specification of operation mode of P05 pin
0
I/O
port
1
INTP2/DRST
input
PMC04
Specification of operation mode of P04 pin
0
I/O
port
1
INTP1
input
PMC03
Specification of operation mode of P03 pin
0
I/O
port
1
INTP0/ADTRG
input
PMC02
Specification of operation mode of P02 pin
0
I/O
port
1
NMI
input
PMC01
Specification of operation mode of P01 pin
0
I/O
port
1
TIP30/TOP30
I/O
PMC00
Specification of operation mode of P00 pin
0
I/O
port
1
TIP31/TOP31
I/O
Caution The P05/INTP2/DRST pin functions as the DRST pin when the OCDM.OCDM0 bit is 1,
regardless of the value of the PMC05 bit.
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(d) Port function control register 0 (PFC0)
This is an 8-bit register that specifies control mode 1 or control mode 2. It can be read or written in 8-bit or
1-bit units.
After
reset:
00H
R/W
Address:
FFFFF460H
7 6 5 4 3 2 1 0
PFC0 0
0
0
0 PFC03 0 PFC01
PFC00
PFC03 Specification
of
operation
mode when P03 pin is in control mode
0
INTP0
input
1
ADTRG
input
PFC01 Specification
of
operation
mode when P01 pin is in control mode
0
TIP30
input
1
TOP30
output
PFC00 Specification
of
operation
mode when P00 pin is in control mode
0
TIP31
input
1
TOP31
output
(e) Pull-up resistor option register 0 (PU0)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After
reset:
00H
R/W
Address:
FFFFFC40H
7 6 5 4 3 2 1 0
PU0
0
PU06 PU05 PU04 PU03 PU02 PU01 PU00
PU0n
Control of on-chip pull-up resistor connection (n = 0 to 6)
0
Not
connected
1
Connected
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(f) External interrupt falling edge specification register 0 (INTF0)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF0n and
INTR0n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, see
CHAPTER 16 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
After
reset:
00H
R/W
Address:
FFFFFC00H
7 6 5 4 3 2 1 0
INTF0
0
INTF06 INTF05 INTF04 INTF03 INTF02
0
0
Remark See
Table 4-4 for how to specify a valid edge.
(g) External interrupt rising edge specification register 0 (INTR0)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF0n and
INTR0n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
3. For how to set the internal noise filter (analog delay/digital delay) of INTP3, see
CHAPTER 16 INTERRUPT/EXCEPTION PROCESSING FUNCTION.
After
reset:
00H
R/W
Address:
FFFFFC20H
7 6 5 4 3 2 1 0
INTR0
0
INTR06 INTR05 INTR04 INTR03 INTR02
0
0
Remark See
Table 4-4 for how to specify a valid edge.
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Table 4-4. Valid Edge Specification
INTF0n Bit
INTR0n Bit
Valid Edge Specification (n = 2 to 6)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1 1
Both
edges
Remark n = 2: Control of NMI pin
n = 3: Control of INTP0 pin
n = 4: Control of INTP1 pin
n = 5: Control of INTP2 pin
n = 6: Control of INTP3 pin
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4.3.4 Port
1
Port 1 is a 2-bit port (P10, P11) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 1
O The input/output data of the port can be specified in 1-bit units.
Specified by port register 1 (P1)
O The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 1 (PM1)
O Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 1 (PMC1)
O An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 1 (PU1)
O The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 1 (INTF1) and external interrupt rising edge
specification register 1 (INTR1)
Port 1 functions alternately as the following pins.
Table 4-5. Alternate-Function Pins of Port 1
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P10 INTP9
L-1
Port 1
P11 INTP10
I/O
L-1
Caution The P10 and P11 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 1 (P1)
Port register 1 (P1) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF402H
7 6 5 4 3 2 1 0
P1
0 0 0 0 0 0
P11
P10
P1n
Control of output data (in output mode) (n = 0, 1)
0
Output
0.
1
Output
1.
(b) Port mode register 1 (PM1)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF422H
7 6 5 4 3 2 1 0
PM1
1 1 1 1 1 1
PM11
PM10
PM1n
Control of input/output mode (n = 0, 1)
0
Output
mode
1
Input
mode
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(c) Port mode control register 1 (PMC1)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After
reset:
00H
R/W
Address:
FFFFF442H
7 6 5 4 3 2 1 0
PMC1
0 0 0 0 0 0
PMC11
PMC10
PMC11
Specification of operation mode of P11 pin
0
I/O
port
1
INTP10
input
PMC10
Specification of operation mode of P10 pin
0
I/O
port
1
INTP9
input
(d) Pull-up resistor option register 1 (PU1)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After
reset:
00H
R/W
Address:
FFFFFC42H
7 6 5 4 3 2 1 0
PU1
0 0 0 0 0 0
PU11
PU10
PU1n
Control of on-chip pull-up resistor connection (n = 0, 1)
0
Not
connected
1
Connected
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(e) External interrupt falling edge specification register 1 (INTF1)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF1n and
INTR1n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After
reset:
00H
R/W
Address:
FFFFFC02H
7 6 5 4 3 2 1 0
INTF1
0 0 0 0 0 0
INTF11
INTF10
Remark See
Table 4-6 for how to specify a valid edge.
(f) External interrupt rising edge specification register 1 (INTR1)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF1n and
INTR1n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After
reset:
00H
R/W
Address:
FFFFFC22H
7 6 5 4 3 2 1 0
INTR1
0 0 0 0 0 0
INTR11
INTR10
Remark See
Table 4-6 for how to specify a valid edge.
Table 4-6. Valid Edge Specification
INTF1n Bit
INTR1n Bit
Valid Edge Specification (n = 0, 1)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1 1
Both
edges
Remark n = 0: Control of INTP9 pin
n = 1: Control of INTP10 pin
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4.3.5 Port
3
Port 3 is a 10-bit port (P30 to P39) for which I/O settings can be controlled in 1-bit units.
(1) Function of port 3
The input/output data of the port can be specified in 1-bit units.
Specified by port register 3 (P3)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 3 (PM3)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 3 (PMC3)
Control mode can be specified in 1-bit units.
Specified by port function control register 3 (PFC3) and port function control expansion register 3L
(PFCE3L)
An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 3 (PU3)
The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 3 (INTF3) and external interrupt rising edge
specification register 3 (INTR3)
Port 3 functions alternately as the following pins.
Table 4-7. Alternate-Function Pins of Port 3
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P30 TXDA0
E-2
P31 RXDA0/INTP7
L-2
P32 ASCKA0/TIP00/TOP00/TOP01
U-13
P33 TIP01/TOP01
G-1
P34 TIP10/TOP10
G-1
P35 TIP11/TOP11
G-1
P36
-
C-1
P37
-
C-1
P38 TXDA2
E-2
Port 3
P39 RXDA2/INTP8
I/O
L-2
Caution The P31 to P35, and P39 pins have hysteresis characteristics in the input mode of the
alternate function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 3 (P3)
Port register 3 (P3) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P3 register are used as the P3H register, and the lower 8 bits as the P3L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF406H, FFFFF407H
15 14 13 12 11 10 9 8
P3 (P3H
Note
)
0 0 0 0 0 0
P39
P38
7 6 5 4 3 2 1 0
(P3L)
P37 P36 P35 P34 P33 P32 P31 P30
P3n
Control of output data (in output mode) (n = 0 to 9)
0
Output
0.
1
Output
1.
Note To read or write bits 8 to 15 of the P3 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P3H register.
(b) Port mode register 3 (PM3)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM3 register are used as the PM3H register, and the lower 8 bits as the PM3L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH
R/W
Address: FFFFF426H, FFFFF427H
15 14 13 12 11 10 9 8
PM3 (PM3H
Note
)
1 1 1 1 1 1
PM39
PM38
7 6 5 4 3 2 1 0
(PM3L)
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
Control of I/O mode (n = 0 to 9)
0
Output
mode
1
Input
mode
Note To read or write bits 8 to 15 of the PM3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM3H register.
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(c) Port mode control register 3 (PMC3)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC3 register are used as the PMC3H register, and the lower 8 bits as the
PMC3L register, however, these registers can be read or written in 8-bit or 1-bit units.
(1/2)
After reset: 0000H
R/W
Address: FFFFF446H, FFFFF447H
15 14 13 12 11 10 9 8
PMC3 (PMC3H
Note 1
)
0 0 0 0 0 0
PMC39
PMC38
7 6 5 4 3 2 1 0
(PMC3L) 0
0
PMC35 PMC34 PMC33 PMC32 PMC31 PMC30
PMC39
Specification of operation mode of P39 pin
0
I/O
port
1
RXDA2/INTP8
input
Note 2
PMC38
Specification of operation mode of P38 pin
0
I/O
port
1
TXDA2
output
PMC35
Specification of operation mode of P35 pin
0
I/O
port
1
TIP11/TOP11
I/O
PMC34
Specification of operation mode of P34 pin
0
I/O
port
1
TIP10/TOP10
I/O
Notes 1. To read or write bits 8 to 15 of the PMC3 register in 8-bit or 1-bit units, specify these bits as
bits 0 to 7 of the PMC3H register.
2. The INTP8 pin functions alternately as the RXDA2 pin. To use as the RXDA2 pin, invalidate
the edge detection function of the alternate-function INTP8 pin (by fixing the INTF3.INTF39
bit to 0 and the INTR3.INTR39 bit to 0). To use as the INTP8 pin, stop the reception
operation of UARTA2 (by clearing the UA2CTL0.UA2RXE bit to 0).
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(2/2)
PMC33
Specification of operation mode of P33 pin
0
I/O
port
1
TIP01/TOP01
I/O
PMC32
Specification of operation mode of P32 pin
0
I/O
port
1
ASCKA0/TIP00/TOP00/TOP01
I/O
PMC31
Specification of operation mode of P31 pin
0
I/O
port
1
RXDA0/INTP7
input
Note
PMC30
Specification of operation mode of P30 pin
0
I/O
port
1
TXDA0
output
Note The INTP7 pin functions alternately as the RXDA0 pin. To use as the RXDA0 pin, invalidate
the edge detection function of the alternate-function INTP7 pin (by fixing the INTF3.INTF31
and INTR3.INTR31 bits to 0). To use as the INTP7 pin, stop the reception operation of
UARTA0 (by clearing the UA0CTL0.UA0RXE bit to 0).
(d) Port function control register 3L (PFC3L)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After
reset:
00H
R/W
Address:
FFFFF466H
7 6 5 4 3 2 1 0
PFC3L
0
0
PFC35 PFC34 PFC33 PFC32
0
0
Remark For how to specify a control mode, see 4.3.5 (2) (f) Setting of control mode of P3 pin.
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(e) Port function control expansion register 3L (PFCE3L)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After
reset:
00H
R/W
Address:
FFFFF706H
7 6 5 4 3 2 1 0
PFCE3L
0 0 0 0 0
PFCE32
0 0
Remark For how to specify a control mode, see 4.3.5 (2) (f) Setting of control mode of P3 pin.
(f) Setting of control mode of P3 pin
PFC35
Specification of control mode of P35 pin
0 TIP11
input
1 TOP11
output
PFC34
Specification of control mode of P34 pin
0 TIP10
input
1 TOP10
output
PFC33
Specification of control mode of P33 pin
0 TIP01
input
1 TOP01
output
PFCE32
PFC32
Specification of control mode of P32 pin
0 0
ASCKA0
input
0 1
TOP01
output
1 0
TIP00
input
1 1
TOP00
output
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(g) Pull-up resistor option register 3 (PU3)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16- or 1-bit units.
If the higher 8 bits of the PU3 register are used as the PU3H register, and the lower 8 bits as the PU3L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 00H
R/W
Address: FFFFFC46H, FFFFFC47H
15 14 13 12 11 10 9 8
PU3 (PU3H
Note
)
0 0 0 0 0 0
PU39
PU38
7 6 5 4 3 2 1 0
(PU3L)
PU37 PU36 PU35 PU34 PU33 PU32 PU31 PU30
PU3n
Control of on-chip pull-up resistor connection (n = 0 to 9)
0
Not
connected
1
Connected
Note To read/write bits 8 to 15 of the PU3 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU3H register.
(h) External interrupt falling edge specification register 3 (INTF3)
This is a 16-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 16-bit units.
If the higher 8 bits of the INTF3 register are used as the INTF3H register, and the lower 8 bits as the
INTF3L register, however, these registers can be read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF3n and
INTR3n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC06H, FFFFFC07H
15 14 13 12 11 10 9 8
INTF3 (INTF3H
Note
)
0 0 0 0 0 0
INTF39
0
7 6 5 4 3 2 1 0
(INTF3L)
0 0 0 0 0 0
INTF31
0
Note To read/write bits 8 to 15 of the INTF3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the INTF3H register.
Remark See Table 4-8 for how to specify a valid edge.
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(i) External interrupt rising edge specification register 3 (INTR3)
This is a 16-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 16-bit units.
If the higher 8 bits of the INTR3 register are used as the INTR3H register, and the lower 8 bits as the
INTR3L register, however, these registers can be read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF3n and
INTR3n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC26H, FFFFFC27H
15 14 13 12 11 10 9 8
INTR3 (INTR3H
Note
)
0 0 0 0 0 0
INTR39
0
7 6 5 4 3 2 1 0
(INTR3L)
0 0 0 0 0 0
INTR31
0
Note To read/write bits 8 to 15 of the INTR3 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the INTR3H register.
Remark See Table 4-8 for how to specify a valid edge.
Table 4-8. Valid Edge Specification
INTF3n Bit
INTR3n Bit
Valid Edge Specification (n = 1, 9)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1 1
Both
edges
Remark n = 1: Control of INTP7 pin
n = 9: Control of INTP8 pin
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4.3.6 Port
4
Port 4 is a 3-bit port (P40 to P42) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 4
The input/output data of the port can be specified in 1-bit units.
Specified by port register 4 (P4)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 4 (PM4)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 4 (PMC4)
An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 4 (PU4)
Port 4 functions alternately as the following pins.
Table 4-9. Alternate-Function Pins of Port 4
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P40 SIB0
E-1
P41 SOB0
E-2
Port 4
P42 SCKB0
I/O
E-3
Caution The P40 and P42 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 4 (P4)
Port register 4 (P4) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF408H
7 6 5 4 3 2 1 0
P4
0 0 0 0 0
P42
P41
P40
P4n
Control of output data (in output mode) (n = 0 to 2)
0
Output
0.
1
Output
1.
(b) Port mode register 4 (PM4)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF428H
7 6 5 4 3 2 1 0
PM4
1 1 1 1 1
PM42
PM41
PM40
PM4n
Control of input/output mode (n = 0 to 2)
0
Output
mode
1
Input
mode
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(c) Port mode control register 4 (PMC4)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After
reset:
00H
R/W
Address:
FFFFF448H
7 6 5 4 3 2 1 0
PMC4
0 0 0 0 0
PMC42
PMC41
PMC40
PMC42
Specification of operation mode of P42 pin
0
I/O
port
1
SCKB0
I/O
PMC41
Specification of operation mode of P41 pin
0
I/O
port
1
SOB0
output
PMC40
Specification of operation mode of P40 pin
0
I/O
port
1
SIB0
input
(d) Pull-up resistor option register 4 (PU4)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After
reset:
00H
R/W
Address:
FFFFFC48H
7 6 5 4 3 2 1 0
PU4
0 0 0 0 0
PU42
PU41
PU40
PU4n
Control of on-chip pull-up resistor connection (n = 0 to 2)
0
Not
connected
1
Connected
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4.3.7 Port
5
Port 5 is a 6-bit port (P50 to P55) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 5
The input/output data of the port can be specified in 1-bit units.
Specified by port register 5 (P5)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 5 (PM5)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 5 (PMC5)
Control mode can be specified in 1-bit units.
Specified by port function control register 5 (PFC5) or port function control expansion register 5 (PFCE5)
An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 5 (PU5)
Port 5 functions alternately as the following pins.
Table 4-10. Alternate-Function Pins of Port 5
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P50 KR0/TIQ01/TOQ01
U-4
P51 KR1/TIQ02/TOQ02
U-4
P52 KR2/TIQ03/TOQ03/DDI
Note
U-5
P53 KR3/TIQ00/TOQ00/DDO
Note
U-6
P54 KR4/DCK
Note
G-2
Port 5
P55 KR5/DMS
Note
I/O
G-2
Note The DDI, DDO, DCK, and DMS pins are for the on-chip debug function. To use the DDI, DDO, DCK,
and DMS pins as port pins, not as on-chip debug pins, the following actions must be taken.
<1> Clear the OCDM0 bit of the OCDM register (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the above
actions are taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05
pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not
necessary to manipulate the OCDM.OCDM0 bit.
Because a pull-down resistor (30 k
TYP) is connected to the buffer of the P05/INTP2/DRST pin, the
pin does not have to be fixed to the low level by an external source. The pull-down resistor is
disconnected by clearing the OCDM0 bit to 0.
Caution The P50 to P55 pins have hysteresis characteristics in the input mode of the alternate
function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 5 (P5)
Port register 5 (P5) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF40AH
7 6 5 4 3 2 1 0
P5 0
0 P55 P54 P53 P52 P51 P50
P5n
Control of output data (in output mode) (n = 0 to 5)
0
Output
0.
1
Output
1.
(b) Port mode register 5 (PM5)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF42AH
7 6 5 4 3 2 1 0
PM5
1
1
PM55 PM54 PM53 PM52 PM51 PM50
PM5n
Control of I/O mode (n = 0 to 5)
0
Output
mode
1
Input
mode
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(c) Port mode control register 5 (PMC5)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
Caution If the control mode is specified by using the PMC5 register when the PFC5.PFC5n and
PFCE5.PFCE5n bits are the default values (0), the output becomes undefined.
For this reason, first set the PFC5.PFC5n and PFCE5.PFCE5n bits, and then set the
PMC5n bit to 1 to set the control mode.
After
reset:
00H
R/W
Address:
FFFFF44AH
7 6 5 4 3 2 1 0
PMC5
0
0
PMC55 PMC54 PMC53 PMC52 PMC51 PMC50
PMC55
Specification of operation mode of P55 pin
0
I/O
port
1
KR5
input
PMC54
Specification of operation mode of P54 pin
0
I/O
port
1
KR4
input
PMC53
Specification of operation mode of P53 pin
0
I/O
port
1
KR3/TIQ00/TOQ00
I/O
PMC52
Specification of operation mode of P52 pin
0
I/O
port
1
KR2/TIQ03/TOQ03
I/O
PMC51
Specification of operation mode of P51 pin
0
I/O
port
1
KR1/TIQ02/TOQ02
I/O
PMC50
Specification of operation mode of P50 pin
0
I/O
port
1
KR0/TIQ01/TOQ01
I/O
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(d) Port function control register 5 (PFC5)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After
reset:
00H
R/W
Address:
FFFFF46AH
7 6 5 4 3 2 1 0
PFC5
0
0
PFC55 PFC54 PFC53 PFC52 PFC51 PFC50
Remark For how to specify a control mode, see 4.3.7 (2) (f) Setting of control mode of P5 pin.
(e) Port function control expansion register 5 (PFCE5)
This is an 8-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 8-bit or 1-bit
units.
After
reset:
00H
R/W
Address:
FFFFF70AH
7 6 5 4 3 2 1 0
PFCE5
0
0
0
0
PFCE53 PFCE52 PFCE51 PFCE50
Remark For how to specify a control mode, see 4.3.7 (2) (f) Setting of control mode of P5 pin.
(f) Setting of control mode of P5 pin
Caution If the control mode is specified by using the PMC5 register when the PFC5.PFC5n and
PFCE5.PFCE5n bits are the default values (0), the output becomes undefined.
For this reason, first set the PFC5.PFC5n and PFCE5.PFCE5n bits, and then set the
PMC5n bit to 1 to set the control mode.
PFC55
Specification of control mode of P55 pin
0 Setting
prohibited
1 KR5
input
PFC54
Specification of control mode of P54 pin
0 Setting
prohibited
1 KR4
input
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PFCE53
PFC53
Specification of control mode of P53 pin
0 0
Setting
prohibited
0 1
TIQ00/KR3
Note
input
1 0
TOQ00
output
1 1
Setting
prohibited
PFCE52
PFC52
Specification of control mode of P52 pin
0 0
Setting
prohibited
0 1
TIQ03/KR2
Note
input
1 0
TOQ03
output
1 1
Setting
prohibited
PFCE51
PFC51
Specification of control mode of P51 pin
0 0
Setting
prohibited
0 1
TIQ02/KR1
Note
input
1 0
TOQ02
output
1 1
Setting
prohibited
PFCE50
PFC50
Specification of control mode of P50 pin
0 0
Setting
prohibited
0 1
TIQ01/KR0
Note
input
1 0
TOQ01
output
1 1
Setting
prohibited
Note The KRn pin functions alternately as the TIQ0m pin. To use this pin as the TIQ0m pin, invalidate the key
return detection function of the alternate-function KRn pin (by clearing the KRM.KRMn bit to 0). To use
this pin as the KRn pin, invalidate the edge detection function of the alternate-function TIQ0m pin (n = 0
to 3, m = 0 to 3).
Pin Name
Use as TIQ0m Pin
Use as KRn Pin
KR0/TIQ01
KRM0 bit of KRM register = 0
TQ0TIG2, TQ0TIG3 bit of TQ0IOC1 register = 0
KR1/TIQ02
KRM1 bit of KRM register = 0
TQ0TIG4, TQ0TIG5 bit of TQ0IOC1 register = 0
KR2/TIQ03
KRM2 bit of KRM register = 0
TQ0TIG6, TQ0TIG7 bit of TQ0IOC1 register = 0
KR3/TIQ00
KRM3 bit of KRM register = 0
TQ0TIG0, TQ0TIG1 bit of TQ0IOC1 register = 0
TQ0EES0, TQ0EES1 bit of TQ0IOC2 register = 0
TQ0ETS0, TQ0ETS1 bit of TQ0IOC2 register = 0
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(g) Pull-up resistor option register 5 (PU5)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After
reset:
00H
R/W
Address:
FFFFFC4AH
7 6 5 4 3 2 1 0
PU5
0
0
PU55 PU54 PU53 PU52 PU51 PU50
PU5n
Control of on-chip pull-up resistor connection (n = 0 to 5)
0
Not
connected
1
Connected
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4.3.8 Port
6
Port 6 is a 16-bit port (P60 to P615) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 6
The input/output data of the port can be specified in 1-bit units.
Specified by port register 6 (P6)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 6 (PM6)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 6 (PMC6)
Control mode 1 or control mode 2 can be specified in 1-bit units.
Specified by port function control register 6 (PFC6)
An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 6 (PU6)
The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 6L (INTF6L) and external interrupt rising
edge specification register 6L (INTR6L)
Port 6 functions alternately as the following pins.
Table 4-11. Alternate-Function Pins of Port 6
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P60 INTP11
N-2
P61 INTP12
N-2
P62 INTP13
N-2
P63
C-1
P64
C-1
P65
C-1
P66
C-1
P67
C-1
P68
C-1
P69
C-1
P610 TIQ20/TOQ20
G-1
P611 TIQ21/TOQ21
G-1
P612 TIQ22/TOQ22
G-1
P613 TIQ23/TOQ23
G-1
P614
C-1
Port 6
P615
I/O
C-1
Caution The P60 to P62, and P610 to P613 pins have hysteresis characteristics in the input mode of
the alternate function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 6 (P6)
Port register 6 (P6) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P6 register are used as the P6H register, and the lower 8 bits as the P6L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF40CH, FFFFF40DH
15 14 13 12 11 10 9 8
P6 (P6H
Note
)
P615 P614 P613 P612 P611 P610 P69 P68
7 6 5 4 3 2 1 0
(P6L)
P67 P66 P65 P64 P63 P62 P61 P60
P6n
Control of output data (in output mode) (n = 0 to 15)
0
Output
0.
1
Output
1.
Note To read or write bits 8 to 15 of the P6 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P6H register.
(b) Port mode register 6 (PM6)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM6 register are used as the PM6H register, and the lower 8 bits as the PM6L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFH
R/W
Address: FFFFF42CH, FFFFF42DH
15 14 13 12 11 10 9 8
PM6 (PM6H
Note
)
PM615 PM614 PM613 PM612 PM611 PM610 PM69 PM68
7 6 5 4 3 2 1 0
(PM6L)
PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60
PM6n
Control of I/O mode (n = 0 to 15)
0
Output
mode
1
Input
mode
Note To read or write bits 8 to 15 of the PM6 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM6H register.
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(c) Port mode control register 6 (PMC6)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC6 register are used as the PMC6H register, and the lower 8 bits as the
PMC6L register, however, these registers can be read or written in 8-bit or 1-bit units.
Caution If the control mode is specified by using the PMC6 register when the PFC6.PFC6n bit is
the default value (0), the output becomes undefined (n = 0 to 8).
For this reason, first set the PFC6.PFC6n bit to 1, and then set the PMC6n bit to 1 to set
the control mode.
(1/2)
After reset: 0000H
R/W
Address: FFFFF44CH, FFFFF44DH
15 14 13 12 11 10 9 8
PMC6 (PMC6H
Note
) 0
0 PMC613
PMC612
PMC611
PMC610 0
0
7 6 5 4 3 2 1 0
(PMC6L)
0 0 0 0 0
PMC62
PMC61
PMC60
PMC613
Specification of operation mode of P613 pin
0
I/O
port
1
TIQ23/TOQ23
I/O
PMC612
Specification of operation mode of P612 pin
0
I/O
port
1
TIQ22/TOQ22
I/O
PMC611
Specification of operation mode of P611 pin
0
I/O
port
1
TIQ21/TOQ21
I/O
PMC610
Specification of operation mode of P610 pin
0
I/O
port
1
TIQ20/TOQ20
I/O
Note To read or write bits 8 to 15 of the PMC6 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PMC6H register.
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(2/2)
PMC62
Specification of operation mode of P62 pin
0
I/O
port
1
INTP13
input
PMC61
Specification of operation mode of P61 pin
0
I/O
port
1
INTP12
input
PMC60
Specification of operation mode of P60 pin
0
I/O
port
1
INTP11
input
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(d) Port function control register 6 (PFC6)
This is a 16-bit register that specifies control mode 1 or 2. It can be read or written in 16-bit units.
If the higher 8 bits of the PFC6 register are used as the PFC6H register, and the lower 8 bits as the PFC6L
register, however, these registers can be read or written in 8-bit or 1-bit units.
Caution If the control mode is specified by using the PMC6 register when the PFC6.PFC6n bit is
the default value (0), the output becomes undefined (n = 0 to 8).
For this reason, first set the PFC6.PFC6n bit to 1, and then set the PMC6n bit to 1 to set
the control mode.
(1/2)
After reset: 0000H
R/W
Address: FFFFF46CH, FFFFF46DH
15 14 13 12 11 10 9 8
PFC6 (PFC6H
Note
) 0
0 PFC613
PFC612
PFC611
PFC610 0
0
7 6 5 4 3 2 1 0
(PFC6L)
0 0 0 0 0
PFC62
PFC61
PFC60
PFC613
Specification of control mode of P613 pin
0
TIQ23
input
1
TOQ23
output
PFC612
Specification of control mode of P612 pin
0
TIQ22
input
1
TOQ22
output
PFC611
Specification of control mode of P611 pin
0
TIQ21
input
1
TOQ21
output
PFC610
Specification of control mode of P610 pin
0
TIQ20
input
1
TOQ20
output
Note To read or write bits 8 to 15 of the PFC6 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PFC6H register.
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(2/2)
PFC62
Specification of control mode of P62 pin
0
Setting
prohibited
1
INTP13
input
PFC61
Specification of control mode of P61 pin
0
Setting
prohibited
1
INTP12
input
PFC60
Specification of control mode of P60 pin
0
Setting
prohibited
1
INTP11
input
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(e) Pull-up resistor option register 6 (PU6)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16-bit units.
If the higher 8 bits of the PU6 register are used as the PU6H register, and the lower 8 bits as the PU6L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFFC4CH, FFFFFC4DH
15 14 13 12 11 10 9 8
PU6 (PU6H
Note
) PU615 PU614 PU613 PU612 PU611 PU610 PU69
PU68
7 6 5 4 3 2 1 0
(PU6L)
PU67 PU66 PU65 PU64 PU63 PU62 PU61 PU60
PU6n
Control of on-chip pull-up resistor connection (n = 0 to 15)
0
Not
connected
1
Connected
Note To read/write bits 8 to 15 of the PU6 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU6H register.
(f) External interrupt falling edge specification register 6L (INTF6L)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF6n and
INTR6n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After
reset:
00H
R/W
Address:
FFFFFC0CH
7 6 5 4 3 2 1 0
INTF6L
0 0 0 0 0
INTF62
INTF61
INTF60
Remark See Table 4-12 for how to specify a valid edge.
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(g) External interrupt rising edge specification register 6L (INTR6L)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF6n and
INTR6n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After
reset:
00H
R/W
Address:
FFFFFC2CH
7 6 5 4 3 2 1 0
INTR6L
0 0 0 0 0
INTR62
INTR61
INTR60
Remark See Table 4-12 for how to specify a valid edge.
Table 4-12. Valid Edge Specification
INTF6n Bit
INTR6n Bit
Valid Edge Specification (n = 0 to 2)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1 1
Both
edges
Remark n = 0: Control of INTP11 pin
n = 1: Control of INTP12 pin
n = 2: Control of INTP13 pin
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4.3.9 Port
7
Port 7 is a 16-bit port (P70 to P715) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 7
The input/output data of the port can be specified in 1-bit units.
Specified by port registers 7L, 7H (P7L, P7H)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode registers 7L, 7H (PM7L, PM7H)
Port 7 functions alternately as the following pins.
Table 4-13. Alternate-Function Pins of Port 7
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P70 ANI0
A-1
P71 ANI1
A-1
P72 ANI2
A-1
P73 ANI3
A-1
P74 ANI4
A-1
P75 ANI5
A-1
P76 ANI6
A-1
P77 ANI7
A-1
P78 ANI8
A-1
P79 ANI9
A-1
P710 ANI10
A-1
P711 ANI11
A-1
P712 ANI12
A-1
P713 ANI13
A-1
P714 ANI14
A-1
Port 7
P715 ANI15
I/O
A-1
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(2) Registers
(a) Port register 7H, port register 7L (P7H, P7L)
Port registers 7H and 7L (P7H and P7L) are 8-bit registers that control reading the pin level and writing the
output level. These registers can be read or written in 8-bit or 1-bit units.
They cannot be accessed in 16-bit units.
After reset: Undefined
R/W
Address: FFFFF40FH, FFFFF40EH
7 6 5 4 3 2 1 0
P7H P715 P714 P713 P712 P711 P710 P79 P78
7 6 5 4 3 2 1 0
P7L P77 P76 P75 P74 P73 P72 P71 P70
P7n
Control of output data (in output mode) (n = 0 to 15)
0
Output
0.
1
Output
1.
Caution Do not read the P7H and P7L registers during A/D conversion.
(b) Port mode registers 7H, 7L (PM7H, PM7L)
These are 8-bit registers that specify an input or output mode. They can be read or written in 8-bit or 1-bit
units.
These registers cannot be accessed in 16-bit units.
After reset: FFH
R/W
Address: FFFFF42FH, FFFFF42EH
7 6 5 4 3 2 1 0
PM7H PM715 PM714 PM713 PM712 PM711 PM710 PM79 PM78
7 6 5 4 3 2 1 0
PM7L PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70
PM7n
Control of I/O mode (n = 0 to 15)
0
Output
mode
1
Input
mode
Caution To use the alternate function of P7n (ANIn), set PM7n to 1.
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4.3.10 Port 8
Port 8 is a 2-bit port (P80, P81)
Note
for which I/O settings can be controlled in 1-bit units.
Note In the
PD70F3709 and 70F3710, the alternate functions of the P80 and P81 pins (RXDA3 and TXDA3) are
not available.
The alternate function of the P80 pin in the
PD70F3709 and 70F3710 is INTP14 only.
(1) Functions of port 8
O The input/output data of the port can be specified in 1-bit units.
Specified by port register 8 (P8)
O The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 8 (PM8)
O Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 8 (PMC8)
O An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 8 (PU8)
O The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 8 (INTF8) and external interrupt rising edge
specification register 8 (INTR8)
Port 8 functions alternately as the following pins.
Table 4-14. Alternate-Function Pins of Port 8
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P80 RXDA3/INTP14
L-2
Note 1
Port 8
P81 TXDA3
I/O
E-2
Note 2
Notes 1. Block type for
PD70F3709, 70F3710: L-1
2. Block type for
PD70F3709, 70F3710: C-1
Caution The P80 pin has hysteresis characteristics in the input mode of the alternate function, but
does not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 8 (P8)
Port register 8 (P8) is an 8-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF410H
7 6 5 4 3 2 1 0
P8
0 0 0 0 0 0
P81
P80
P8n
Control of output data (in output mode) (n = 0, 1)
0
Output
0.
1
Output
1.
(b) Port mode register 8 (PM8)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF430H
7 6 5 4 3 2 1 0
PM8
1 1 1 1 1 1
PM81
PM80
PM8n
Control of I/O mode (n = 0, 1)
0
Output
mode
1
Input
mode
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(c) Port mode control register 8 (PMC8)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After
reset:
00H
R/W
Address:
FFFFF450H
(i)
PD70F3709,
70F3710
7 6 5 4 3 2 1 0
PMC8
0 0 0 0 0 0 0
PMC80
(ii)
PD70F3711,
70F3712
7 6 5 4 3 2 1 0
PMC8
0 0 0 0 0 0
PMC81
PMC80
PMC81
Specification of operation mode of P81 pin
0
I/O
port
1
TXDA3
output
PMC80
Specification of operation mode of P80 pin
0
I/O
port
1
RXDA3/INTP14
input
Note
Note The
PD70F3709 and 70F3710 do not have RXDA3.
The INTP14 pin of the
PD70F3711 and 70F3712 functions alternately as the RXDA3 pin. To
use this pin as the RXDA3 pin, invalidate the edge detection function of the alternate-function
INTP14 pin (by clearing the INTF8.INTF80 bit to 0 and the INTR8.INTR80 bit to 0). To use
this pin as the INTP14 pin, stop the reception operation of UARTA3 (by clearing the
UA3CTL0.UA3RXE bit to 0).
(d) Pull-up resistor option register 8 (PU8)
This is an 8-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
8-bit or 1-bit units.
After
reset:
00H
R/W
Address:
FFFFFC50H
7 6 5 4 3 2 1 0
PU8
0 0 0 0 0 0
PU81
PU80
PU8n
Control of on-chip pull-up resistor connection (n = 0, 1)
0
Not
connected
1
Connected
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(e) External interrupt falling edge specification register 8 (INTF8)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF80 and
INTR80 bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After
reset:
00H
R/W
Address
FFFFFC10H
7 6 5 4 3 2 1 0
INTF8
0 0 0 0 0 0 0
INTF80
Remark See Table 4-15 for how to specify a valid edge.
(f) External interrupt rising edge specification register 8 (INTR8)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF80 and
INTR80 bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After
reset:
00H
R/W
Address
FFFFFC30H
7 6 5 4 3 2 1 0
INTR8
0 0 0 0 0 0 0
INTR80
Remark See Table 4-15 for how to specify a valid edge.
Table 4-15. Valid Edge Specification
INTF80 Bit
INTR80 Bit
Valid Edge Specification
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1 1
Both
edges
Remark Control of INTP14 pin
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4.3.11 Port 9
Port 9 is a 9-bit or 16-bit port (P90 to P915) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 9
The input/output data of the port can be specified in 1-bit units.
Specified by port register 9 (P9)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 9 (PM9)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register 9 (PMC9)
Control mode can be specified in 1-bit units.
Specified by port function control register 9 (PFC9) and port function control expansion register 9 (PFCE9)
An on-chip pull-up resistor can be connected in 1-bit units.
Specified by pull-up resistor option register 9 (PU9)
The valid edge of the external interrupt (alternate function) can be specified in 1-bit units.
Specified by external interrupt falling edge specification register 9H (INTF9H) and external interrupt rising
edge specification register 9H (INTR9H)
Port 9 functions alternately as the following pins.
Table 4-16. Alternate-Function Pins of Port 9
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P90 KR6/TXDA1
U-12
P91 KR7/RXDA1
U-7
P92 TIQ11/TOQ11
U-11
P93 TIQ12/TOQ12
U-11
P94 TIQ13/TOQ13
U-11
P95 TIQ10/TOQ10
U-11
P96 TIP21/TOP21
U-9
P97 SIB1/TIP20/TOP20
U-8
P98 SOB1
G-3
P99 SCKB1
G-5
P910 SIB2
G-4
P911 SOB2
G-3
P912 SCKB2
G-5
P913 INTP4/PCL
W-1
P914 INTP5
N-2
Port 9
P915 INTP6
I/O
N-2
Caution The P90 to P97, P99, P910, and P912 to P915 pins have hysteresis characteristics in the input
mode of the alternate function, but do not have hysteresis characteristics in the port mode.
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(2) Registers
(a) Port register 9 (P9)
Port register 9 (P9) is a 16-bit register that controls reading the pin level and writing the output level. This
register can be read or written in 16-bit units.
If the higher 8 bits of the P9 register are used as the P9H register, and the lower 8 bits as the P9L register,
however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF412H, FFFFF413H
15 14 13 12 11 10 9 8
P9 (P9H
Note
)
P915 P914 P913 P912 P911 P910 P99 P98
7 6 5 4 3 2 1 0
(P9L)
P97 P96 P95 P94 P93 P92 P91 P90
P9n
Control of output data (in output mode) (n = 0 to 15)
0
Output
0.
1
Output
1.
Note To read or write bits 8 to 15 of the P9 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the P9H register.
(b) Port mode register 9 (PM9)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PM9 register are used as the PM9H register, and the lower 8 bits as the PM9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH
R/W
Address: FFFFF432H, FFFFF433H
15 14 13 12 11 10 9 8
PM9 (PM9H
Note
)
PM915 PM914 PM913 PM912 PM911 PM910 PM99 PM98
7 6 5 4 3 2 1 0
(PM9L)
PM97 PM96 PM95 PM94 PM93 PM92 PM91 PM90
PM9n
Control of I/O mode (n = 0 to 15)
0
Output
mode
1
Input
mode
Note To read or write bits 8 to 15 of the PM9 register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PM9H register.
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(c) Port mode control register 9 (PMC9)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMC9 register are used as the PMC9H register, and the lower 8 bits as the
PMC9L register, however, these registers can be read or written in 8-bit or 1-bit units.
Caution If the control mode is specified by using the PMC9 register when the PFC9.PFC9n bit
and the PFCE9.PFCE9n bit are the default values (0), the output becomes undefined.
For this reason, first set the PFC9.PFC9n bit and the PFCE9.PFCE9n bit to 1, and then
set the PMC9n bit to 1 to set the control mode.
(1/3)
After reset: 0000H
R/W
Address: FFFFF452H, FFFFF453H
15 14 13 12 11 10 9 8
PMC9 (PMC9H
Note
) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98
7 6 5 4 3 2 1 0
(PMC9L)
PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90
PMC915
Specification of operation mode of P915 pin
0
I/O
port
1
INTP6
input
PMC914
Specification of operation mode of P914 pin
0
I/O
port
1
INTP5
input
PMC913
Specification of operation mode of P913 pin
0
I/O
port
1
INTP4/PCL
I/O
PMC912
Specification of operation mode of P912 pin
0
I/O
port
1
SCKB2
I/O
Note To read or write bits 8 to 15 of the PMC9 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PMC9H register.
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(2/3)
PMC911
Specification of operation mode of P911 pin
0
I/O
port
1
SOB2
output
PMC910
Specification of operation mode of P910 pin
0
I/O
port
1
SIB2
input
PMC99
Specification of operation mode of P99 pin
0
I/O
port
1
SCKB1
I/O
PMC98
Specification of operation mode of P98 pin
0
I/O
port
1
SOB1
output
PMC97
Specification of operation mode of P97 pin
0
I/O
port
1
SIB1/TIP20/TOP20
I/O
PMC96
Specification of operation mode of P96 pin
0
I/O
port
1
TIP21/TOP21
I/O
PMC95
Specification of operation mode of P95 pin
0
I/O
port
1
TIQ10/TOQ10
I/O
PMC94
Specification of operation mode of P94 pin
0
I/O
port
1
TIQ13/TOQ13
I/O
PMC93
Specification of operation mode of P93 pin
0
I/O
port
1
TIQ12/TOQ12
I/O
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(3/3)
PMC92
Specification of operation mode of P92 pin
0
I/O
port
1
TIQ11/TOQ11
I/O
PMC91
Specification of operation mode of P91 pin
0
I/O
port
1
KR7/RXDA1
input
PMC90
Specification of operation mode of P90 pin
0
I/O
port
1
KR6/TXDA1
I/O
(d) Port function control register 9 (PFC9)
This is a 16-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 16-bit units.
If the higher 8 bits of the PFC9 register are used as the PFC9H register, and the lower 8 bits as the PFC9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFF472H, FFFFF473H
15 14 13 12 11 10 9 8
PFC9 (PFC9H
Note
) PFC915 PFC914 PFC913 PFC912 PFC911 PFC910 PFC99 PFC98
7 6 5 4 3 2 1 0
(PFC9L)
PFC97 PFC96 PFC95 PFC94 PFC93 PFC92 PFC91 PFC90
Note To read or write bits 8 to 15 of the PFC9 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PFC9H register.
Remark For how to specify a control mode, see 4.3.11 (2) (f) Setting of control mode of P9 pin.
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(e) Port function control expansion register 9 (PFCE9)
This is a 16-bit register that specifies control mode 1, 2, 3, or 4. It can be read or written in 16-bit units.
If the higher 8 bits of the PFC9 register are used as the PFC9H register, and the lower 8 bits as the PFC9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFF712H, FFFFF713H
15 14 13 12 11 10 9 8
PFCE9 (PFCE9H
Note
)
0 0
PFCE913
0 0 0 0 0
7 6 5 4 3 2 1 0
(PFCE9L) PFCE97 PFCE96 PFCE95 PFCE94 PFCE93 PFCE92 PFCE91 PFCE90
Note To read or write bits 8 to 15 of the PFCE9 register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PFCE9H register.
Remark For how to specify a control mode, see 4.3.11 (2) (f) Setting of control mode of
P9 pin
.
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(f) Setting of control mode of P9 pin
Caution If the control mode is specified by using the PFC9 register when the PFC9.PFC9n and
PFCE9.PFCE9n bits are the default values (0), the output becomes undefined.
For this reason, first set the PFC9.PFC9n and PFCE9.PFCE9n bits, and then set the
PMC9n bit to 1 to set the control mode.
PFC915
Specification of control mode of P915 pin
0 Setting
prohibited
1 INTP6
input
PFC914
Specification of control mode of P914 pin
0 Setting
prohibited
1 INTP5
input
PFCE913
PFC913
Specification of control mode of P913 pin
0 0
Setting
prohibited
0 1
INTP4
input
1 0
PCL
output
1 1
Setting
prohibited
PFC912
Specification of control mode of P912 pin
0 Setting
prohibited
1 SCKB2
I/O
PFC911
Specification of control mode of P911 pin
0 Setting
prohibited
1 SOB2
output
PFC910
Specification of control mode of P910 pin
0 Setting
prohibited
1 SIB2
input
PFC99
Specification of control mode of P99 pin
0 Setting
prohibited
1 SCKB1
I/O
PFC98
Specification of control mode of P98 pin
0 Setting
prohibited
1 SOB1
input
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PFCE97
PFC97
Specification of control mode of P97 pin
0 0
Setting
prohibited
0 1
SIB1
input
1 0
TIP20
input
1 1
TOP20
output
PFCE96
PFC96
Specification of control mode of P96 pin
0 0
Setting
prohibited
0 1
Setting
prohibited
1 0
TIP21
input
1 1
TOP21
output
PFCE95
PFC95
Specification of control mode of P95 pin
0 0
Setting
prohibited
0 1
TIQ10
input
1 0
TOQ10
output
1 1
Setting
prohibited
PFCE94
PFC94
Specification of control mode of P94 pin
0 0
Setting
prohibited
0 1
TIQ13
input
1 0
TOQ13
output
1 1
Setting
prohibited
PFCE93
PFC93
Specification of control mode of P93 pin
0 0
Setting
prohibited
0 1
TIQ12
input
1 0
TOQ12
output
1 1
Setting
prohibited
PFCE92
PFC92
Specification of control mode of P92 pin
0 0
Setting
prohibited
0 1
TIQ11
input
1 0
TOQ11
output
1 1
Setting
prohibited
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PFCE91
PFC91
Specification of control mode of P91 pin
0 0
Setting
prohibited
0 1
KR7
input
1 0
KR7/RXDA1
input
Note
1 1
Setting
prohibited
PFCE90
PFC90
Specification of control mode of P90 pin
0 0
Setting
prohibited
0 1
KR6
input
1 0
TXDA1
output
1 1
Setting
prohibited
Note The KR7 pin and RXDA1 pin are alternate-function pins.
When using the pin as the RXDA1 pin, disable KR7 pin key return detection. (Clear the KRM7 bit of the
KRM register to 0.) Also, when using the pin as the KR7 pin, it is recommended to set the PFC91 bit to
1 and clear the PFCE91 bit to 0.
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(g) Pull-up resistor option register 9 (PU9)
This is a 16-bit register that specifies connection of an on-chip pull-up resistor. It can be read or written in
16-bit units.
If the higher 8 bits of the PU9 register are used as the PU9H register, and the lower 8 bits as the PU9L
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFFC52H, FFFFFC53H
15 14 13 12 11 10 9 8
PU9 (PU9H
Note
)
PU915 PU914 PU913 PU912 PU911 PU910 PU99 PU98
7 6 5 4 3 2 1 0
(PU9L)
PU97 PU96 PU95 PU94 PU93 PU92 PU91 PU90
PU9n
Control of on-chip pull-up resistor connection (n = 0 to 15)
0
Not
connected
1
Connected
Note To read/write bits 8 to 15 of the PU9 register in 8-bit or 1-bit units, specify these bits as bits 0 to
7 of the PU9H register.
(h) External interrupt falling edge specification register 9H (INTF9H)
This is an 8-bit register that specifies detection of the falling edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF9n and
INTR9n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC13H
7 6 5 4 3 2 1 0
INTF9H
INTF915
INTF914
INTF913
0 0 0 0 0
Remark See Table 4-17 for how to specify a valid edge.
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(i) External interrupt rising edge specification register 9H (INTR9H)
This is an 8-bit register that specifies detection of the rising edge of the external interrupt pin. It can be
read or written in 8-bit or 1-bit units.
Cautions 1. When the external interrupt function (alternate function) is switched to the port
function, an edge may be detected. Set the port mode after clearing the INTF9n and
INTR9n bits to 0.
2. An analog-delay-based noise eliminator is connected to the external interrupt input
pin.
After reset: 00H
R/W
Address: FFFFFC33H
7 6 5 4 3 2 1 0
INTR9H
INTR915
INTR914
INTR913
0
0
0
0
0
Remark See Table 4-17 for how to specify a valid edge.
Table 4-17. Valid Edge Specification
INTF9n Bit
INTR9n Bit
Valid Edge Specification (n = 13 to 15)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1 1
Both
edges
Remark n = 13: Control of INTP4 pin
n = 14: Control of INTP5 pin
n = 15: Control of INTP6 pin
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4.3.12 Port 12
Port 12 is an 8-bit port (P120 to P127) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port 12
The input/output data of the port can be specified in 1-bit units.
Specified by port register 12 (P12)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register 12 (PM12)
Port 12 functions alternately as the following pins.
Table 4-18. Alternate-Function Pins of Port 12
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
P120 ANI16
A-1
P121 ANI17
A-1
P122 ANI18
A-1
P123 ANI19
A-1
P124 ANI20
A-1
P125 ANI21
A-1
P126 ANI22
A-1
Port 12
P127 ANI23
I/O
A-1
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(2) Registers
(a) Port register 12 (P12)
Port register 12 (P12) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF418H
7 6 5 4 3 2 1 0
P12 P127 P126 P125 P124 P123 P122 P121 P120
P12n
Control of output data (in output mode) (n = 0 to 7)
0
Output
0.
1
Output
1.
(b) Port mode register 12 (PM12)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF438H
7 6 5 4 3 2 1 0
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
PM12n
Control of I/O mode (n = 0 to 7)
0
Output
mode
1
Input
mode
Caution To use the alternate function of P12n (ANIn), set PM12n to 1.
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4.3.13 Port CD
Port CD is a 4-bit port (PCD0 to PCD3) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port CD
The input/output data of the port can be specified in 1-bit units.
Specified by port register CD (PCD)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CD (PMCD)
Port CD functions alternately as the following pins.
Table 4-19. Alternate-Function Pins of Port CD
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
PCD0
B-1
PCD1
B-1
PCD2
B-1
Port CD
PCD3
I/O
B-1
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(2) Registers
(a) Port register CD (PCD)
Port register CD (PCD) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF00EH
7 6 5 4 3 2 1 0
PCD
0
0
0
0
PCD3
PCD2
PCD1
PCD0
PCDn
Control of output data (in output mode) (n = 0 to 3)
0
Output
0.
1
Output
1.
(b) Port mode register CD (PMCD)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF02EH
7 6 5 4 3 2 1 0
PMCD
1
1
1
1
PMCD3
PMCD2
PMCD1
PMCD0
PMCDn
Control of I/O mode (n = 0 to 3)
0
Output
mode
1
Input
mode
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4.3.14 Port CM
Port CM is a 6-bit port (PCM0 to PCM5) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port CM
The input/output data of the port can be specified in 1-bit units.
Specified by port register CM (PCM)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CM (PMCM)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register CM (PMCCM)
Port CM functions alternately as the following pins.
Table 4-20. Alternate-Function Pins of Port CM
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
PCM0 WAIT
D-1
PCM1 CLKOUT
D-2
PCM2 HLDAK
D-2
PCM3 CLDRQ
D-1
PCM4
B-1
Port CM
PCM5
I/O
B-1
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(2) Registers
(a) Port register CM (PCM)
Port register CM (PCM) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF00CH
7 6 5 4 3 2 1 0
PCM
0
0
PCM5 PCM4 PCM3 PCM2 PCM1 PCM0
PCMn
Control of output data (in output mode) (n = 0 to 5)
0
Output
0.
1
Output
1.
(b) Port mode register CM (PMCM)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF02CH
7 6 5 4 3 2 1 0
PMCM
1
1
PMCM5 PMCM4 PMCM3 PMCM2 PMCM1 PMCM0
PMCMn
Control of I/O mode (n = 0 to 5)
0
Output
mode
1
Input
mode
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(c) Port mode control register CM (PMCCM)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After
reset:
00H
R/W
Address:
FFFFF04CH
7 6 5 4 3 2 1 0
PMCCM
0
0
0
0
PMCCM3
PMCCM2
PMCCM1
PMCCM0
PMCCM3
Specification of operation mode of PCM3 pin
0
I/O
port
1
HLDRQ
input
PMCCM2
Specification of operation mode of PCM2 pin
0
I/O
port
1
HLDAK
output
PMCCM1
Specification of operation mode of PCM1 pin
0
I/O
port
1
CLKOUT
output
PMCCM0
Specification of operation mode of PCM0 pin
0
I/O
port
1
WAIT
input
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4.3.15 Port CS
Port CS is an 8-bit port (PCS0 to PCS7) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port CS
The input/output data of the port can be specified in 1-bit units.
Specified by port register CS (PCS)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CS (PMCS)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register CS (PMCCS)
Port CS functions alternately as the following pins.
Table 4-21. Alternate-Function Pins of Port CS
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
PCS0 CS0
D-2
PCS1 CS1
D-2
PCS2 CS2
D-2
PCS3 CS3
D-2
PCS4
B-1
PCS5
B-1
PCS6
B-1
Port CS
PCS7
I/O
B-1
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(2) Registers
(a) Port register CS (PCS)
Port register CS (PCS) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF008H
7 6 5 4 3 2 1 0
PCS PCS7 PCS6 PCS5 PCS4 PCS3 PCS2 PCS1 PCS0
PCSn
Control of output data (in output mode) (n = 0 to 7)
0
Output
0.
1
Output
1.
(b) Port mode register CS (PMCS)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF028H
7 6 5 4 3 2 1 0
PMCS PMCS7 PMCS6 PMCS5 PMCS4 PMCS3 PMCS2 PMCS1 PMCS0
PMCSn
Control of I/O mode (n = 0 to 7)
0
Output
mode
1
Input
mode
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(c) Port mode control register CS (PMCCS)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF048H
7 6 5 4 3 2 1 0
PMCCS
0 0 0 0
PMCCS3
PMCCS2
PMCCS1
PMCCS0
PMCCS3
Specification of operation mode of PCS3 pin
0
I/O
port
1
CS3
output
PMCCS2
Specification of operation mode of PCS2 pin
0
I/O
port
1
CS2
output
PMCCS1
Specification of operation mode of PCS1 pin
0
I/O
port
1
CS1
output
PMCCS0
Specification of operation mode of PCS0 pin
0
I/O
port
1
CS0
output
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4.3.16 Port CT
Port CT is an 8-bit port (PCT0 to PCT7) for which I/O settings can be controlled in 1-bit units.
(1) Functions of port CT
The input/output data of the port can be specified in 1-bit units.
Specified by port register CT (PCT)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register CT (PMCT)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register CT (PMCCT)
Port CT functions alternately as the following pins.
Table 4-22. Alternate-Function Pins of Port CT
Pin Name
Alternate-Function Pin Name
I/O
Remark
Block Type
PCT0 WR0
D-2
PCT1 WR1
D-2
PCT2
B-1
PCT3
B-1
PCT4 RD
D-2
PCT5
B-1
PCT6 ASTB
D-2
Port CT
PCT7
I/O
B-1
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(2) Registers
(a) Port register CT (PCT)
Port register CT (PCT) is an 8-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 8-bit or 1-bit units.
After
reset:
Undefined
R/W
Address:
FFFFF00AH
7 6 5 4 3 2 1 0
PCT PCT7 PCT6 PCT5 PCT4 PCT3 PCT2 PCT1 PCT0
PCTn
Control of output data (in output mode) (n = 0 to 7)
0
Output
0.
1
Output
1.
(b) Port mode register CT (PMCT)
This is an 8-bit register that specifies the input or output mode. It can be read or written in 8-bit or 1-bit
units.
After
reset:
FFH
R/W
Address:
FFFFF02AH
7 6 5 4 3 2 1 0
PMCT
PMCT7
PMCT6
PMCT5
PMCT4 PMCT3 PMCT2 PMCT1 PMCT0
PMCTn
Control of I/O mode (n = 0 to 7)
0
Output
mode
1
Input
mode
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(c) Port mode control register CT (PMCCT)
This is an 8-bit register that specifies the port mode or control mode. It can be read or written in 8-bit or 1-
bit units.
After reset: 00H
R/W
Address: FFFFF04AH
7 6 5 4 3 2 1 0
PMCCT 0 PMCCT6 0 PMCCT4 0
0 PMCCT1
PMCCT0
PMCCT6
Specification of operation mode of PCT3 pin
0
I/O
port
1
ASTB
output
PMCCT4
Specification of operation mode of PCT2 pin
0
I/O
port
1
RD
output
PMCCT1
Specification of operation mode of PCT1 pin
0
I/O
port
1
WR1
output
PMCCT0
Specification of operation mode of PCT0 pin
0
I/O
port
1
WR0
output
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4.3.17 Port DL
Port DL is a 16-bit port (PDL0 to PDL15) for which I/O settings can be controlled in 1-bit units.
(1) Function of port DL
The input/output data of the port can be specified in 1-bit units.
Specified by port register DL (PDL)
The input/output mode of the port can be specified in 1-bit units.
Specified by port mode register DL (PMDL)
Port mode or control mode (alternate function) can be specified in 1-bit units.
Specified by port mode control register DL (PMCDL)
Port DL functions alternately as the following pins.
Table 4-23. Alternate-Function Pins of Port DL
Pin Name
Alternate-Function Pin Name
I/O
Remark
PDL0 AD0
D-3
PDL1 AD1
D-3
PDL2 AD2
D-3
PDL3 AD3
D-3
PDL4 AD4
D-3
PDL5 AD5/FLMD1
Note
D-3
PDL6 AD6
D-3
PDL7 AD7
D-3
PDL8 AD8
D-3
PDL9 AD9
D-3
PDL10 AD10
D-3
PDL11 AD11
D-3
PDL12 AD12
D-3
PDL13 AD13
D-3
PDL14 AD14
D-3
Port DL
PDL15 AD15
I/O
D-3
Note Because the FLMD1 pin is used in the flash programming mode, it does not have to be manipulated
by using a port control register. For details, see CHAPTER 24 FLASH MEMORY.
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(2) Registers
(a) Port register DL (PDL)
Port register DL (PDL) is a 16-bit register that controls reading the pin level and writing the output level.
This register can be read or written in 16-bit units.
If the higher 8 bits of the PDL register are used as the PDLH register, and the lower 8 bits as the PDLL
register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: Undefined
R/W
Address: FFFFF004H, FFFFF005H
15 14 13 12 11 10 9 8
PDL (PDLH
Note
)
PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8
7 6 5 4 3 2 1 0
(PDLL)
PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0
PDLn
Control of output data (in output mode) (n = 0 to 15)
0
Output
0.
1
Output
1.
Note To read or write bits 8 to 15 of the PDL register in 8-bit or 1-bit units, specify these bits as bits 0
to 7 of the PDLH register.
(b) Port mode register DL (PMDL)
This is a 16-bit register that specifies the input or output mode. It can be read or written in 16-bit units.
If the higher 8 bits of the PMDL register are used as the PMDLH register, and the lower 8 bits as the
PMDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: FFFFH
R/W
Address: FFFFF024H, FFFFF025H
15 14 13 12 11 10 9 8
PMDL (PMDLH
Note
) PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10 PMDL9 PMDL8
7 6 5 4 3 2 1 0
(PMDLL)
PMDL7 PMDL6 PMDL5 PMDL4 PMDL3 PMDL2 PMDL1 PMDL0
PMDLn
Control of I/O mode (n = 0 to 15)
0
Output
mode
1
Input
mode
Note To read or write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify these bits as bits
0 to 7 of the PMDLH register.
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(c) Port mode control register DL (PMCDL)
This is a 16-bit register that specifies the port mode or control mode. It can be read or written in 16-bit
units.
If the higher 8 bits of the PMCDL register are used as the PMCDLH register, and the lower 8 bits as the
PMCDLL register, however, these registers can be read or written in 8-bit or 1-bit units.
After reset: 0000H
R/W
Address: FFFFF044H, FFFFF045H
15 14 13 12 11 10 9 8
PMCDL (PMCDLH
Note
) PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10
PMCDL9 PMCDL8
7 6 5 4 3 2 1 0
(PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0
PMCDLn
Specification of operation mode of PDL15 pin (n = 0 to 15)
0
I/O
port
1
ADn I/O (address/data bus I/O)
Note To read or write bits 8 to 15 of the PMCDL register in 8-bit or 1-bit units, specify these bits as
bits 0 to 7 of the PMCDLH register.
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4.3.18 Port pins that function alternately as on-chip debug function
The pins shown in Table 4-24 function alternately as on-chip debug pins. After an external reset, these pins are
initialized as on-chip debug pins (DRST, DDI, DDO, DCK, and DMS).
Table 4-24. On-Chip Debug Pins
Pin Name
Alternate Function Pin
P05 INTP2/DRST
P52 KR2/TIQ03/TOQ03/DDI
P53 KR3/TIQ00/TOQ00/DDO
P54 KR4/DCK
P55 KR5/DMS
To use these pins as port pins, not as on-chip debug pins, the following actions must be taken after an external
reset.
<1> Clear the OCDM0 bit of the OCDM register (special register) to 0.
<2> Fix the P05/INTP2/DRST pin to the low level until the above action has been taken.
When the on-chip debug function is not used, inputting a high level to the DRST pin before the above actions are
taken may cause a malfunction (CPU deadlock). Exercise utmost care in handling the P05 pin.
When a high level is not input to the P05/INTP2/DRST pin (when this pin is fixed to low level), it is not necessary to
manipulate the OCDM.OCDM0 bit.
Because a pull-down resistor (30 k
TYP) is connected to the buffer of the P05/INTP2/DRST pin, the pin does not
have to be fixed to the low level by an external source. The pull-down resistor is disconnected by clearing the OCDM0
bit to 0.
For details, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
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4.3.19 Register settings to use port pins as alternate-function pins
Table 4-25. Register Settings to Use Port Pins as Alternate-Function Pins (1/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
TIP31 Input
Setting not required
PMC00 = 1
PFC00 = 0
P00
TOP31 Output
Setting not required
PMC00 = 1
PFC00 = 1
TIP30 Input
Setting not required
PMC01 = 1
PFC01 = 0
P01
TOP30 Output
Setting not required
PMC01 = 1
PFC01 = 1
P02 NMI Input
Setting not required
PMC02 = 1
INTP0 Input
Setting not required
PMC03 = 1
PFC03 = 0
INTx03 (INTx0)
P03
ADTRG Output
Setting not required
PMC03 = 1
PFC03 = 1
P04 INTP1 Input
Setting not required
PMC04 = 1
INTx04 (INTx0)
INTP2 Input
Setting not required
PMC05 = 1
INTx05 (INTx0)
P05
Note
DRST Input
Setting not required
Setting not required
OCDM0 (OCDM) = 1
P06 INTP3 Input
Setting not required
PMC06 = 1
INTx06 (INTx0)
P10 INTP9 Input
Setting not required
PMC10 = 1
INTx10 (INTx1)
P11 INTP10
Input
Setting not required
PMC11 = 1
INTx11 (INTx1)
Note After an external reset, the P05/INTP2/DRST pin is initialized as an on-chip debug pin (DRST). To not use the
P05/INTP2/DRST pin as an on-chip debug pin, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-25. Register Settings to Use Port Pins as Alternate-Function Pins (2/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register
PFCm Register PFCEm Register
Other Bits (Register)
P30 TXDA0
Output
Setting not required
PMC30 = 1
RXDA0 Input
Setting not required
PMC31 = 1
Note 1
P31
INTP7 Input
Setting not required
PMC31 = 1
Note 1, INTx31 (INTx3)
ASCKA0 Input Setting not required
PMC32 = 1
PFC32 = 0
PFCE32 = 0
TOP01 Output
Setting not required
PMC32 = 1
PFC32 = 1
PFCE32 = 0
TIP00 Input
Setting not required
PMC32 = 1
PFC32 = 0
PFCE32 = 1
P32
TOP00 Output
Setting not required
PMC32 = 1
PFC32 = 1
PFCE32 = 1
TIP01 Input
Setting not required
PMC33 = 1
PFC33 = 0
P33
TOP01 Output
Setting not required
PMC33 = 1
PFC33 = 1
TIP10
Input
Setting not required
PMC34 = 1
PFC34 = 0
P34
TOP10 Output
Setting not required
PMC34 = 1
PFC34 = 1
TIP11 Input
Setting not required
PMC35 = 1
PFC35 = 0
P35
TOP11 Output
Setting not required
PMC35 = 1
PFC35 = 1
P38 TXDA2
Output
Setting not required
PMC38 = 1
RXDA2 Input
Setting not required
PMC39 = 1
Note 2
P39
INTP8 Input
Setting not required
PMC39 = 1
Note 2, INTx39 (INTx3)
P40 SIB0 Input
Setting not required
PMC40 = 1
P41 SOB0 Output
Setting not required
PMC41 = 1
P42 SCKB0
I/O
Setting not required
PMC42 = 1
Notes 1. The INTP7 pin functions alternately as the RXDA0 pin. To use this pin as the RXDA0 pin, invalidate the
edge detection function of the alternate-function INTP7 pin (by clearing the INTF31 bit of the INTF3 register
to 0 and the INTR31 bit of the INTR3 register to 0). To use this pin as the INTP7 pin, stop the reception
operation of UARTA0 (by clearing the UA0RXE bit of the UA0CTL0 register to 0).
2. The INTP8 pin functions alternately as the RXDA2 pin. To use this pin as the RXDA2 pin, invalidate the
edge detection function of the alternate-function INTP8 pin (by clearing the INTF39 bit of the INTF3 register
to 0 and the INTR39 bit of the INTR3 register to 0). To use this pin as the INTP8 pin, stop the reception
operation of UARTA2 (by clearing the UA2RXE bit of the UA2CTL0 register to 0).
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-25. Register Settings to Use Port Pins as Alternate-Function Pins (3/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
KR0 Input
Setting not required
PMC50 = 1
PFC50 = 1
PFCE50 = 0
Note 1
TIQ01 Input
Setting not required
PMC50 = 1
PFC50 = 1
PFCE50 = 0
Note 1
P50
TOQ01 Output
Setting not required
PMC50 = 1
PFC50 = 0
PFCE50 = 1
KR1 Input
Setting not required
PMC51 = 1
PFC51 = 1
PFCE54 = 0
Note 1
TIQ02 Input
Setting not required
PMC51 = 1
PFC51 = 1
PFCE51 = 0
Note 1
P51
TOQ02 Output
Setting not required
PMC51 = 1
PFC51 = 0
PFCE51 = 1
KR2 Input
Setting not required
PMC52 = 1
PFC52 = 1
PFCE52 = 0
Note 1
TIQ03 Input
Setting not required
PMC52 = 1
PFC52 = 1
PFCE52 = 0
Note 1
TOQ03 Output
Setting not required
PMC52 = 1
PFC52 = 0
PFCE52 = 1
P52
DDI
Note 2
Input
Setting not required
Setting not required
Setting not required
Setting not required
OCDM0 (OCDM) = 1
KR3 Input
Setting not required
PMC53 = 1
PFC53 = 1
PFCE53 = 0
Note 1
TIQ00 Input
Setting not required
PMC53 = 1
PFC53 = 1
PFCE53 = 0
Note 1
TOQ00 Output
Setting not required
PMC53 = 1
PFC53 = 0
PFCE53 = 1
P53
DDO
Note 2
Output
Setting not required
Setting not required
Setting not required
Setting not required
OCDM0 (OCDM) = 1
KR4 Input
Setting not required
PMC54 = 1
PFC54 = 1
P54
DCK
Note 2
Output
Setting not required
Setting not required
Setting not required
OCDM0 (OCDM) = 1
KR5 Input
Setting not required
PMC55 = 1
PFC55 = 1
P55
DMS
Note 2
Output
Setting not required
Setting not required
Setting not required
OCDM0 (OCDM) = 1
Notes 1. The KR7 pin functions alternately as the TIQ0m pin. To use this pin as the TIQ0m pin, invalidate the key
return detection function of the alternate-function KRn pin (by clearing the KRMn bit of the KRM register to
0). To use this pin as the KRn pin, invalidate the edge detection function of the alternate-function TIQ0m
pin (n = 0 to 3, m = 0 to 3).
Pin Name
When Used as TIQ0m Pin
When Used as KRn Pin
KR0/TIQ01
KRM0 bit of KRM register = 0
TQ0TIG2, TQ0TIG3 bits of TQ0IOC1 register = 0
KR1/TIQ02
KRM1 bit of KRM register = 0
TQ0TIG4, TQ0TIG5 bits of TQ0IOC1 register = 0
KR2/TIQ03
KRM2 bit of KRM register = 0
TQ0TIG6, TQ0TIG7 bits of TQ0IOC1 register = 0
KR3/TIQ00
KRM3 bit of KRM register = 0
TQ0TIG0, TQ0TIG1 bits of TQ0IOC1 register = 0
TQ0EES0, TQ0EES1 bits of TQ0IOC2 register = 0
TQ0ETS0, TQ0ETS1 bits of TQ0IOC2 register = 0
2. The DDI, DDO, DCK, and DMS pins are on-chip debug pins. To not use these pins as on-chip debug pins
after an external reset, see CHAPTER 26 ON-CHIP DEBUG FUNCTION.
Caution If the control mode is specified by using the PMC5 register when the PFC5.PFC5n bit and the
PFCE5.PFCE5n bit are the default values (0), the output becomes undefined.
For this reason, first set the PFC5.PFC5n bit and the PFCE5.PFCE5n bit, and then set the PMC5n bit
to 1 to set the control mode.
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-25. Register Settings to Use Port Pins as Alternate-Function Pins (4/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
P60 INTP11
Input
Setting not required
PMC60 = 1
PFC60 = 1
INTx60 (INTx6L)
P61 INTP12
Input
Setting not required
PMC61 = 1
PFC61 = 1
INTx61 (INTx6L)
P62 INTP13
Input
Setting not required
PMC62 = 1
PFC62 = 1
INTx62 (INTx6L)
TIQ20 Input
Setting not required
PMC610 = 1
PFC610 = 0
P610
TOQ20 Output
Setting not required
PMC610 = 1
PFC610 = 1
TIQ21 Input
Setting not required
PMC611 = 1
PFC611 = 0
P611
TOQ21 Output
Setting not required
PMC611 = 1
PFC611 = 1
TIQ22 Input
Setting not required
PMC612 = 1
PFC612 = 0
P612
TOQ22 Output
Setting not required
PMC612 = 1
PFC612 = 1
TIQ23 Input
Setting not required
PMC613 = 1
PFC613 = 0
P613
TOQ23 Output
Setting not required
PMC613 = 1
PFC613 = 1
P70
ANI0
Input
PM70 = 1
Note
P71
ANI1
Input
PM71 = 1
Note
P72
ANI2
Input
PM72 = 1
Note
P73
ANI3
Input
PM73 = 1
Note
P74
ANI4
Input
PM74 = 1
Note
P75
ANI5
Input
PM75 = 1
Note
P76
ANI6
Input
PM76 = 1
Note
P77
ANI7
Input
PM77 = 1
Note
P78
ANI8
Input
PM78 = 1
Note
P79
ANI9
Input
PM79 = 1
Note
P710
ANI10
Input
PM710 = 1
Note
P711
ANI11
Input
PM711 = 1
Note
P712
ANI12
Input
PM712 = 1
Note
P713
ANI13
Input
PM713 = 1
Note
P714
ANI14
Input
PM714 = 1
Note
P715
ANI15
Input
PM715 = 1
Note
Note Set PM7n to 1 to use the alternate function of P7n (ANIn).
Caution If the control mode is specified by using the PMC6 register when the PFC6.PFC6n bit (n = 0 to 8) is
the default value (0), the output becomes undefined.
For this reason, first set the PFC6.PFC6n bit and then set the PMC6n bit to 1 to set the control mode.
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-25. Register Settings to Use Port Pin as Alternate-Function Pins (5/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register PFCm Register PFCEm Register
Other Bits (Register)
RXDA3 Input
Setting not required
PMC80 = 1
Note 2
P80
INTP14 Input
Setting not required
PMC80 = 1
Note 2, INTx80 (INTx8)
P81 TXDA3
Output
Setting not required
PMC81 = 1
KR6 Input
Setting not required
PMC90 = 1
PFC90 = 1
PFCE90 = 0
P90
TXDA1 Output
Setting not required
PMC90 = 1
PFC90 = 0
PFCE90 = 1
PFC91 = 1
PFCE91 = 0
KR7
Note 1
Input
Setting not required
PMC91 = 1
PFC91 = 0
PFCE91 = 1
P91
RXDA1 Input
Setting not required
PMC91 = 1
PFC91 = 0
PFCE91 = 1
TIQ11 Input
Setting not required
PMC92 = 1
PFC92 = 1
PFCE92 = 0
P92
TOQ11 Output
Setting not required
PMC92 = 1
PFC92 = 0
PFCE92 = 1
TIQ12 Input
Setting not required
PMC93 = 1
PFC93 = 1
PFCE93 = 0
P93
TOQ12 Output
Setting not required
PMC93 = 1
PFC93 = 0
PFCE93 = 1
TIQ13 Input
Setting not required
PMC94 = 1
PFC94 = 1
PFCE94 = 0
P94
TOQ13 Output
Setting not required
PMC94 = 1
PFC94 = 0
PFCE94 = 1
TIQ10 Input
Setting not required
PMC95 = 1
PFC95 = 1
PFCE95 = 0
P95
TOQ10 Output
Setting not required
PMC95 = 1
PFC95 = 0
PFCE95 = 1
TIP21 Input
Setting not required
PMC96 = 1
PFC96 = 0
PFCE96 = 1
P96
TOP21 Output
Setting not required
PMC96 = 1
PFC96 = 1
PFCE96 = 1
SIB1 Input
Setting not required
PMC97 = 1
PFC97 = 1
PFCE97 = 0
TIP20 Input
Setting not required
PMC97 = 1
PFC97 = 0
PFCE97 = 1
P97
TOP20 Output
Setting not required
PMC97 = 1
PFC97 = 1
PFCE97 = 1
P98 SOB1 Output
Setting not required
PMC98 = 1
PFC98 = 1
P99 SCKB1
I/O
Setting not required
PMC99 = 1
PFC99 = 1
P910 SIB2 Input
Setting not required
PMC910 = 1
PFC910 = 1
P911 SOB2 Output
Setting not required
PMC911 = 1
PFC911 = 1
P912 SCKB2 I/O Setting not required
PMC912 = 1
PFC912 = 1
INTP4 Input
Setting not required
PMC913 = 1
PFC913 = 1
PFCE913 = 0
INTx913 (INTx9H)
P913
PCL Output
Setting not required
PMC913 = 1
PFC913 = 0
PFCE913 = 1
P914 INTP5 Input
Setting not required
PMC914 = 1
PFC914 = 1
INTx914 (INTx9H)
P915 INTP6 Input
Setting not required
PMC915 = 1
PFC915 = 1
INTx915 (INTx9H)
Notes 1. The KR7 pin and RXDA1 pin are alternate-function pins.
When using the pin as the RXDA1 pin, disable KR7 pin key return detection. (Clear the KRM.KRM7 bit to
0.)
Also, when using the pin as the KR7 pin, it is recommended to set the PFC91 bit to 1 and clear the
PFCE91 bit to 0.
2. The INTP14 pin functions alternately as the RXDA3 pin. To use this pin as the RXDA3 pin, invalidate the
edge detection function of the alternate-function INTP14 pin (by clearing the INTF8.INTF80 bit to 0 and the
INTR8.INTR80 bit to 0). To use this pin as the INTP14 pin, stop the reception operation of UARTA3 (by
clearing the UA3CTL0.UA3RXE bit to 0).
Caution If the control mode is specified by using the PMC9 register when the PFC9.PFC9n bit and the
PFCE9.PFCE9n bit are the default values (0), the output becomes undefined.
For this reason, first set the PFC9.PFC9n bit and the PFCE9.PFCE9n bit, and then set the PMC9n bit
to 1 to set the control mode.
Remarks 1. The port register (Pn) does not have to be set when the alternate function is used.
2. INTxn = INTFn, INTRn
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Table 4-25. Register Settings to Use Port Pins as Alternate-Function Pins (6/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register
PFCm Register PFCEm Register
Other Bits (Register)
P120
ANI16
Input
PM120 = 1
Note
P121
ANI17
Input
PM121 = 1
Note
P122
ANI18
Input
PM122 = 1
Note
P123
ANI19
Input
PM123 = 1
Note
P124
ANI20
Input
PM124 = 1
Note
P125
ANI21
Input
PM125 = 1
Note
P126
ANI22
Input
PM126 = 1
Note
P127
ANI23
Input
PM127 = 1
Note
PCM0 WAIT
Input
Setting not required
PMCCM0 = 1
PCM1 CLKOUT
Output
Setting not required
PMCCM1 = 1
PCM2 HLDAK Output
Setting not required
PMCCM2 = 1
PCM3 HLDRQ Input
Setting not required
PMCCM3 = 1
PCS0 CS0
Output
Setting not required
PMCCS0 = 1
PCS1 CS1
Output
Setting not required
PMCCS1 = 1
PCS2 CS2
Output
Setting not required
PMCCS2 = 1
PCS3 CS3
Output
Setting not required
PMCCS3 = 1
PCT0 WR0
Output
Setting not required
PMCCT0 = 1
PCT1 WR1
Output
Setting not required
PMCCT1 = 1
PCT4 RD
Output
Setting not required
PMCCT4 = 1
PCT6 ASTB Output
Setting not required
PMCCT6 = 1
Note Set PM12n to 1 to use the alternate function of P12n (ANIn).
Remark The port register (Pn) does not have to be set when the alternate function is used.
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Table 4-25. Register Settings to Use Port Pins as Alternate-Function Pins (7/7)
Alternate-Function Pin
Pin
Name
Name I/O
PMn Register
PMCn Register
PFCm Register PFCEm Register
Other Bits (Register)
PDL0 AD0
I/O Setting not required
PMCDL0 = 1
PDL1 AD1
I/O Setting not required
PMCDL1 = 1
PDL2 AD2
I/O Setting not required
PMCDL2 = 1
PDL3 AD3
I/O Setting not required
PMCDL3 = 1
PDL4 AD4
I/O Setting not required
PMCDL4 = 1
AD5 I/O
Setting not required
PMCDL5 = 1
PDL5
FLMD1 Input
Setting not required
Setting not required
Note
PDL6 AD6
I/O Setting not required
PMCDL6 = 1
PDL7 AD7
I/O Setting not required
PMCDL7 = 1
PDL8 AD8
I/O Setting not required
PMCDL8 = 1
PDL9 AD9
I/O Setting not required
PMCDL9 = 1
PDL10 AD10
I/O Setting not required
PMCDL10 = 1
PDL11 AD11
I/O Setting not required
PMCDL11 = 1
PDL12 AD12
I/O Setting not required
PMCDL12 = 1
PDL13 AD13
I/O Setting not required
PMCDL13 = 1
PDL14 AD14
I/O Setting not required
PMCDL14 = 1
PDL15 AD15
I/O Setting not required
PMCDL15 = 1
Note The FLMD1 pin does not have to be manipulated by using a port control register because it is used in the flash
programming mode. For details, see CHAPTER 24 FLASH MEMORY.
Remark The port register (Pn) does not have to be set when the alternate function is used.
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4.4 Block Diagrams of Port
Figure 4-2. Block Diagram of Type A-1
Address
RD
A/D input signal
WR
PM
PMmn
WR
PORT
Pmn
Pmn
P-ch
N-ch
Inter
nal b
u
s
Selector
Selector
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Figure 4-3. Block Diagram of Type B-1
RD
WR
PM
PMmn
WR
PORT
Pmn
Pmn
Inter
nal b
u
s
Selector
Selector
Address
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Figure 4-4. Block Diagram of Type C-1
Address
RD
WR
PORT
Pmn
WR
PU
PUmn
WR
PM
PMmn
Pmn
P-ch
Inter
nal b
u
s
Selector
Selector
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Figure 4-5. Block Diagram of Type D-1
WR
PORT
Pmn
WR
PM
PMmn
WR
PMC
PMCmn
RD
Input signal when
alternate function is used
Pmn
Inter
nal b
u
s
Selector
Selector
Address
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Figure 4-6. Block Diagram of Type D-2
WR
PORT
Pmn
WR
PM
PMmn
WR
PMC
PMCmn
RD
Output signal when
alternate function is used
Pmn
Inter
nal b
u
s
Selector
Selector
Selector
Address
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Figure 4-7. Block Diagram of Type D-3
WR
PORT
Pmn
WR
PM
PMmn
WR
PMC
PMCmn
RD
Pmn
Output signal when
alternate function is used
Input signal when
alternate function is used
Output enable signal
of address/data bus
Input enable signal of
address data bus
Output buffer off signal
Inter
nal b
u
s
Selector
Selector
Selector
Selector
Address
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Figure 4-8. Block Diagram of Type E-1
Address
Input signal when
alternate function is used
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
PU
PUmn
WR
PM
PMmn
Pmn
Note
EV
DD
P-ch
Inter
nal b
u
s
Selector
Selector
Note Hysteresis characteristics are not available in port mode.
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Figure 4-9. Block Diagram of Type E-2
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
PU
PUmn
WR
PM
PMmn
Pmn
EV
DD
P-ch
Output signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
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Figure 4-10. Block Diagram of Type E-3
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
PU
PUmn
WR
PM
PMmn
Pmn
Note
EV
DD
P-ch
Output enable signal when
alternate function is used
Output signal when
alternate function is used
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
Note Hysteresis characteristics are not available in port mode.
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Figure 4-11. Block Diagram of Type G-1
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
Note
EV
DD
P-ch
Output signal when
alternate function is used
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
Note Hysteresis characteristics are not available in port mode.
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Figure 4-12. Block Diagram of Type G-2
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PM
PMmn
Pmn
Input signal when
on-chip debugging
Note
EV
DD
P-ch
On-chip debug mode signal
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Noise
elimination
Note Hysteresis characteristics are not available in port mode.
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Figure 4-13. Block Diagram of Type G-3
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
EV
DD
P-ch
Output signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
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Figure 4-14. Block Diagram of Type G-4
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
Note
EV
DD
P-ch
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Note Hysteresis characteristics are not available in port mode.
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Figure 4-15. Block Diagram of Type G-5
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
Note
WR
PU
PUmn
EV
DD
P-ch
Output signal when
alternate function is used
Output enable signal when
alternate function is used
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
Note Hysteresis characteristics are not available in port mode.
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Figure 4-16. Block Diagram of Type L-1
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
INTR
INTRmn
Note 1
WR
INTF
INTFmn
Note 1
WR
PU
PUmn
WR
PM
PMmn
Pmn
Note 2
EV
DD
P-ch
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Edge
detection
Noise
elimination
Notes 1. See
16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14).
2. Hysteresis characteristics are not available in port mode.
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Figure 4-17. Block Diagram of Type L-2
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
INTR
INTRmn
Note 1
WR
INTF
INTFmn
Note 1
WR
PU
PUmn
WR
PM
PMmn
Pmn
Note 2
EV
DD
P-ch
Input signal 1-1 when
alternate function is used
Input signal 1-2 when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Edge
detection
Noise
elimination
Notes 1. See
16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14).
2. Hysteresis characteristics are not available in port mode.
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Figure 4-18. Block Diagram of Type N-1
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
INTR
INTRmn
Note 1
WR
INTF
INTFmn
Note 1
WR
PU
PUmn
WR
PM
WR
PFC
PFCmn
PMmn
Pmn
Note 2
EV
DD
P-ch
Input signal 1 when
alternate function is used
Input signal 2 when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Edge
detection
Noise
elimination
Selector
Notes 1. See
16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14).
2. Hysteresis characteristics are not available in port mode.
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Figure 4-19. Block Diagram of Type N-2
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
INTR
INTRmn
Note 1
WR
INTF
INTFmn
Note 1
WR
PU
PUmn
WR
PM
WR
PFC
PFCmn
PMmn
Pmn
Note 2
EV
DD
P-ch
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Edge
detection
Noise
elimination
Notes 1. See
16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14).
2. Hysteresis characteristics are not available in port mode.
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Figure 4-20. Block Diagram of Type U-4
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
WR
PFCE
PFCEmn
Note
EV
DD
P-ch
Input signal 1-1 when
alternate function is used
Output signal when
alternate function is used
Input signal 1-2 when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
Noise
elimination
Note Hysteresis characteristics are not available in port mode.
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Figure 4-21. Block Diagram of Type U-5
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
WR
PFCE
PFCEmn
Note
EV
DD
P-ch
Output signal when
alternate function is used
On-chip debug
mode signal
Inter
nal b
u
s
Selector
Selector
Selector
Input signal 1-2 when
alternate function is used
Input signal when
on-chip debugging
Input signal 1-1 when
alternate function is used
Noise
elimination
Note Hysteresis characteristics are not available in port mode.
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Figure 4-22. Block Diagram of Type U-6
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
WR
PFCE
PFCEmn
Note
EV
DD
P-ch
Pmn
Output signal when
alternate function is used
Output signal when
on-chip debugging
On-chip debug
mode signal
Inter
nal b
u
s
Selector
Selector
Selector
Selector
Input signal 1-2 when
alternate function is used
Input signal 1-1 when
alternate function is used
Noise
elimination
Note Hysteresis characteristics are not available in port mode.
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Figure 4-23. Block Diagram of Type U-7
Address
RD
WR
PORT
WR
PMC
PMmn
PFCEmn
PFCmn
WR
PU
PUmn
WR
PM
WR
PFC
WR
PFCE
PMCmn
Pmn
Pmn
Note
EV
DD
P-ch
Inter
nal b
u
s
Selector
Selector
Selector
Input signal 2-1 when
alternate function is used
Input signal 2-2 when
alternate function is used
Input signal 1 when
alternate function is used
Noise
elimination
Noise
elimination
Note Hysteresis characteristics are not available in port mode.
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Figure 4-24. Block Diagram of Type U-8
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
WR
PFCE
PFCEmn
Note
EV
DD
P-ch
Inter
nal b
u
s
Selector
Selector
Selector
Selector
Input signal 2 when
alternate function is used
Input signal 1 when
alternate function is used
Output signal when
alternate function is used
Note Hysteresis characteristics are not available in port mode.
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Figure 4-25. Block Diagram of Type U-9
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
Pmn
WR
PFCE
PFCEmn
Note
EV
DD
P-ch
Inter
nal b
u
s
Selector
Selector
Selector
Input signal when
alternate function is used
Output signal when
alternate function is used
Note Hysteresis characteristics are not available in port mode.
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Figure 4-26. Block Diagram of Type U-11
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
WR
PFCE
PFCEmn
Note
Pmn
EV
DD
P-ch
Inter
nal b
u
s
Selector
Selector
Selector
Input signal when
alternate function is used
Output signal when
alternate function is used
Note Hysteresis characteristics are not available in port mode.
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Figure 4-27. Block Diagram of Type U-12
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
WR
PFCE
PFCEmn
Note
Pmn
EV
DD
P-ch
Input signal when
alternate function is used
Output signal
when alternate
function is used
Inter
nal b
u
s
Selector
Selector
Selector
Noise
elimination
Note Hysteresis characteristics are not available in port mode.
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Figure 4-28. Block Diagram of Type U-13
Address
RD
WR
PORT
Pmn
WR
PFC
PFCmn
WR
PF
PFmn
WR
PMC
PMCmn
WR
PM
PMmn
WR
PFCE
PFCEmn
Note
Pmn
EV
DD
P-ch
Input signal 1 when
alternate function is used
Input signal 2 when
alternate function is used
Output signal 2 when
alternate function is used
Output signal 1 when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
Selector
Selector
Note Hysteresis characteristics are not available in port mode.
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Figure 4-29. Block Diagram of Type W-1
Address
RD
WR
PORT
Pmn
WR
PMC
PMCmn
WR
INTR
INTRmn
Note 1
WR
INTF
INTFmn
Note 1
WR
PF
PFmn
WR
PM
WR
PFC
PFCmn
WR
PFCE
PFCEmn
PMmn
Note 2
Pmn
EV
DD
P-ch
Input signal when
alternate function is used
Output signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Selector
Edge
detection
Noise
elimination
Notes 1. See
16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14).
2. Hysteresis characteristics are not available in port mode.
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Figure 4-30. Block Diagram of Type AA-1
Address
Reset signal by POC
On-chip debug
mode signal
RD
WR
PORT
Pmn
WR
INTF
INTFmn
Note 1
WR
PU
PUmn
WR
PMC
PMCmn
WR
PM
PMmn
N-ch
WR
INTR
INTRmn
Note 1
EV
SS
Note 2
Pmn
EV
DD
P-ch
Input signal when
on-chip debugging
Input signal when
alternate function is used
Inter
nal b
u
s
Selector
Selector
Edge
detection
Noise
elimination
Notes 1. See
16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14).
2. Hysteresis characteristics are not available in port mode.
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4.5 Cautions
4.5.1
Cautions on setting port pins
(1) In the V850ES/HJ2, the general-purpose port function and several peripheral function I/O pin share a pin. To
switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function
mode), set by the PMCn register. In regards to this register setting sequence, note with caution the following.
(a) Cautions on switching from port mode to alternate-function mode
To switch from the port mode to alternate-function mode in the following order.
<1> Set the PFn register
Note
:
N-ch open-drain setting
<2> Set the PFCn and PFCEn registers: Alternate-function
selection
<3> Set the corresponding bit of the PMCn register to 1: Switch to alternate-function mode
If the PMCn register is set first, note with caution that, at that moment or depending on the change of the
pin states in accordance with the setting of the PFn, PFCn, and PFCEn registers, unexpected operations
may occur.
Note N-ch open-drain output pin only
Caution Regardless of the port mode/alternate-function mode, the Pn register is read and written
as follows.
Pn register read: Read the port output latch value (when PMn.PMnm bit = 0), or read
the pin states (PMn.PMnm bit = 1).
Pn register write: Write to the port output latch
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CHAPTER 5 BUS CONTROL FUNCTION
The V850ES/HJ2 is provided with an external bus interface function by which external memories such as ROM and
RAM, and I/O can be connected.
5.1 Features
Multiplexed bus with a minimum of 3 bus cycles
8-bit/16-bit data bus selectable
Wait function
Programmable wait function of up to 7 states
External wait function using WAIT pin
Idle state function
Bus hold function
External devices can be connected using alternate-function port pins
Misaligned access possible
Chip select function (4 spaces)
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5.2 Bus
Control
Pins
The pins used to connect an external device are listed in the table below.
Table 5-1. Bus Control Pins (Multiplexed Bus)
Bus Control Pin
Alternate-Function Pin
I/O
Function
AD0 to AD15
PDL0 to PDL15
I/O
Address/data bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD PCT4
Output
Read
strobe
signal
ASTB PCT6
Output
Address
strobe
signal
HLDRQ PCM3
Input
HLDAK PCM2
Output
Bus hold control
CS0 to CS3
PCS0 to PCS3
Output
Chip select
5.2.1
Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed
When the internal ROM, internal RAM, or on-chip peripheral I/O are accessed, the status of each pin is as follows.
Table 5-2. Pin Statuses When Internal ROM, Internal RAM, or On-Chip Peripheral I/O Is Accessed
Address/data bus (AD15 to AD0)
Undefined
Control signal
Inactive
Caution When a write access is performed to the internal ROM area, address, data, and control signals
are activated in the same way as access to the external memory area.
5.2.2
Pin status in each operation mode
For the pin status of the V850ES/HJ2 in each operation mode, see 2.2 Pin Status.
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5.3 Memory
Block
Function
The 256 KB external memory space is divided into memory blocks of (lower) 64 KB, 64 KB, 64 KB, and 64 KB. The
programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in
one-block units.
Figure 5-1. Data Memory Map: Physical Address
CS3
CS2
CS1
CS0
(80 KB)
Use prohibited
Use prohibited
Use prohibited
Use prohibited
External memory area (64 KB)
Internal ROM area
Note 2
(1 MB)
External memory area (64 KB)
Internal RAM area
(60 KB)
On-chip peripheral
I/O area (4 KB)
External memory area (64 KB)
External memory area (64 KB)
(2 MB)
0 3 F F F F F F H
0 3 F E C 0 0 0 H
0 3 F E B F F F H
0 0 8 1 0 0 0 0 H
0 0 8 0 F F F F H
0 0 8 0 0 0 0 0 H
0 0 7 F F F F F H
0 0 4 0 0 0 0 0 H
0 0 3 F F F F F H
0 0 4 1 0 0 0 0 H
0 0 4 0 F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 2 1 0 0 0 0 H
0 0 2 0 F F F F H
0 0 0 0 0 0 0 0 H
0 3 F F F F F F H
0 3 F F F 0 0 0 H
0 3 F F E F F F H
0 0 1 F F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 1 1 0 0 0 0 H
0 0 1 0 F F F F H
0 0 0 0 0 0 0 0 H
Use prohibited
Note 1
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
0 3 F E C 0 0 0 H
Notes 1. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
same area as the on-chip peripheral I/O area.
2.
This area is an external memory area in the case of a data write access.
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5.4 Bus
Access
5.4.1
Number of clocks for access
The following table shows the number of basic clocks required for accessing each resource.
Area (Bus Width)
Bus Cycle Type
Internal ROM (32 Bits)
Internal RAM (32 Bits)
External Memory (16 Bits)
Instruction fetch (normal access)
1
1
Note
3 + n
Instruction fetch (branch)
2
2
Note
3 + n
Operand data access
3
1
3 + n
Note Increases by 1 if a conflict with a data access occurs.
Remark Unit:
Clocks/access
5.4.2
Bus size setting function
Each external memory area selected by CSn can be set by using the BSC register. However, the bus size can be
set to 8 bits and 16 bits only.
The external memory area of the V850ES/HJ2 is selected by CS0 to CS3.
(1) Bus size configuration register (BSC)
The BSC register can be read or written in 16-bit units.
Reset sets this register to 5555H.
Caution Write to the BSC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the BSC register are complete.
After reset: 5555H R/W Address: FFFFF066H
0
0
BSn0
0
1
8 bits
16 bits
BSC
1
BS30
0
0
1
BS20
0
0
1
BS10
0
0
1
BS00
8
9
10
11
12
13
Data bus width of CSn space (n = 0 to 3)
14
15
1
2
3
4
5
6
7
0
CS0
CS3
CS2
CS1
Caution Be sure to set bits 14, 12, 10, and 8 to "1", and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to "0".
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5.4.3
Access by bus size
The V850ES/HJ2 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus
size is as follows.
The bus size of the on-chip peripheral I/O is fixed to 16 bits.
The bus size of the external memory is selectable from 8 bits or 16 bits (by using the BSC register).
The operation when each of the above is accessed is described below. All data is accessed starting from the lower
side.
The V850ES/HJ2 supports only the little-endian format.
Figure 5-2. Little-Endian Address in Word
000BH
000AH
0009H
0008H
0007H
0006H
0005H
0004H
0003H
0002H
0001H
0000H
31
24 23
16 15
8 7
0
(1) Data space
The V850ES/HJ2 has an address misalign function.
With this function, data can be placed at all addresses, regardless of the format of the data (word data or
halfword data). However, if the word data or halfword data is not aligned at the boundary, a bus cycle is
generated at least twice, causing the bus efficiency to drop.
(a) Halfword-length data access
A byte-length bus cycle is generated twice if the least significant bit of the address is 1.
(b) Word-length data access
(i) A byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that
order if the least significant bit of the address is 1.
(ii) A halfword-length bus cycle is generated twice if the lower 2 bits of the address are 10.
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(2) Byte access (8 bits)
(a) 16-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
7
0
7
0
Byte data
15
8
External data
bus
2n
Address
7
0
7
0
15
8
2n + 1
Address
Byte data
External data
bus
(b) 8-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
7
0
7
0
2n
Address
Byte data
External data
bus
7
0
7
0
2n + 1
Address
Byte data
External data
bus
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(3) Halfword access (16 bits)
(a) With 16-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
7
0
7
0
15
8
2n
Address
15
8
2n + 1
Halfword data External data
bus
First access
Second access
7
0
7
0
15
8
15
8
7
0
7
0
15
8
15
8
2n + 2
Halfword data
External data
bus
2n
Address
Halfword data
External data
bus
Address
2n + 1
(b) 8-bit data bus width
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
First access
Second access
7
0
7
0
15
8
Address
7
0
7
0
15
8
2n + 1
Address
2n
Halfword data External data
bus
Halfword data External data
bus
First access
Second access
7
0
7
0
15
8
7
0
7
0
15
8
2n + 2
2n + 1
Address
Address
Halfword data External data
bus
Halfword data External data
bus
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(4) Word access (32 bits)
(a) 16-bit data bus width (1/2)
<1> Access to address (4n)
First access
Second access
7
0
7
0
15
8
4n
15
8
4n + 1
23
16
31
24
7
0
7
0
15
8
4n + 2
15
8
4n + 3
23
16
31
24
Word data
External data
bus
Address
Word data
External data
bus
Address
<2> Access to address (4n + 1)
First
access
Second
access Third
access
7
0
7
0
15
8
15
8
4n + 1
23
16
31
24
7
0
7
0
15
8
4n + 2
15
8
4n + 3
23
16
31
24
7
0
7
0
15
8
4n + 4
15
8
23
16
31
24
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
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(a) 16-bit data bus width (2/2)
<3> Access to address (4n + 2)
First access
Second access
7
0
7
0
15
8
4n + 2
15
8
4n + 3
23
16
31
24
7
0
7
0
15
8
4n + 4
15
8
4n + 5
23
16
31
24
Word data
External data
bus
Address
Word data
External data
bus
Address
<4> Access to address (4n + 3)
First
access
Second
access Third
access
7
0
7
0
15
8
15
8
4n + 3
23
16
31
24
7
0
7
0
15
8
4n + 4
15
8
4n + 5
23
16
31
24
7
0
7
0
15
8
4n + 6
15
8
23
16
31
24
Word data
External data
bus
Address
Word data
External data
bus
Address
Word data
External data
bus
Address
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(b) 8-bit data bus width (1/2)
<1> Access to address (4n)
First access
Second access
Third access
Fourth access
7
0
7
0
15
8
4n
23
16
31
24
7
0
7
0
4n + 1
15
8
23
16
31
24
7
0
7
0
4n + 2
15
8
23
16
31
24
7
0
7
0
4n + 3
15
8
23
16
31
24
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
<2> Access to address (4n + 1)
First access
Second access
Third access
Fourth access
7
0
7
0
15
8
4n + 1
23
16
31
24
7
0
7
0
4n + 2
15
8
23
16
31
24
7
0
7
0
4n + 3
15
8
23
16
31
24
7
0
7
0
4n + 4
15
8
23
16
31
24
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
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(b) 8-bit data bus width (2/2)
<3> Access to address (4n + 2)
First access
Second access
Third access
Fourth access
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
7
0
7
0
15
8
4n + 2
23
16
31
24
7
0
7
0
4n + 3
15
8
23
16
31
24
7
0
7
0
4n + 4
15
8
23
16
31
24
7
0
7
0
4n + 5
15
8
23
16
31
24
<4> Access to address (4n + 3)
First access
Second access
Third access
Fourth access
7
0
7
0
15
8
4n + 3
23
16
31
24
7
0
7
0
4n + 4
15
8
23
16
31
24
7
0
7
0
4n + 5
15
8
23
16
31
24
7
0
7
0
4n + 6
15
8
23
16
31
24
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
Word data External data
bus
Address
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5.5 Wait Function
5.5.1
Programmable wait function
(1) Data wait control register 0 (DWC0)
To realize interfacing with a low-speed memory or I/O, up to seven data wait states can be inserted in the bus
cycle that is executed for each CS space.
The number of wait states can be programmed by using the DWC0 register. Immediately after system reset, 7
data wait states are inserted for all the blocks.
The DWC0 register can be read or written in 16-bit units.
Reset sets this register to 7777H.
Cautions 1. The internal ROM and internal RAM areas are not subject to programmable wait, and are
always accessed without a wait state. The on-chip peripheral I/O area is also not subject
to programmable wait, and only wait control from each peripheral function is performed.
2. Write to the DWC0 register after reset, and then do not change the set values. Also, do
not access an external memory area until the initial settings of the DWC0 register are
complete.
After reset: 7777H R/W Address: FFFFF484H
0
0
DWn2
0
0
0
0
1
1
1
1
DWn1
0
0
1
1
0
0
1
1
DWn0
0
1
0
1
0
1
0
1
Not inserted
1
2
3
4
5
6
7
DWC0
DW32
DW12
DW31
DW11
DW30
DW10
0
0
DW22
DW02
DW21
DW01
DW20
DW00
8
9
10
11
12
13
Number of wait states inserted in
CSn space (n = 0 to 3)
14
15
1
2
3
4
5
6
7
0
CS0
CS3
CS2
CS1
Caution Be sure to clear bits 15, 11, 7, and 3 to "0".
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5.5.2
External wait function
To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can
be inserted in the bus cycle by using the external wait pin (WAIT).
When the PCM0 pin is set to alternate function, the external wait function is enabled.
Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the
external wait function, in the same manner as the programmable wait function.
The WAIT signal can be input asynchronously to CLKOUT, and is sampled at the falling edge of the clock in the T2
and TW states of the bus cycle. If the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in
the next state, or not inserted at all.
5.5.3 Relationship
between
programmable wait and external wait
Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the
programmable wait and the wait cycles controlled by the WAIT pin.
Wait control
Programmable wait
Wait via WAIT pin
For example, if the timing of the programmable wait and the WAIT pin signal is as illustrated below, three wait
states will be inserted in the bus cycle.
Figure 5-3. Inserting Wait Example
CLKOUT
T1
T2
TW
TW
TW
T3
WAIT pin
Wait via WAIT pin
Programmable wait
Wait control
Remark The circles indicate the sampling timing.
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5.5.4
Programmable address wait function
Address-setup or address-hold waits to be inserted in each bus cycle can be set by using the AWC register.
Address wait insertion is set for each chip select area (CS0 to CS3).
If an address setup wait is inserted, it seems that the high-clock period of the T1 state is extended by 1 clock. If an
address hold wait is inserted, it seems that the low-clock period of the T1 state is extended by 1 clock.
(1) Address wait control register (AWC)
The AWC register can be read or written in 16-bit units.
Reset sets this register to FFFFH.
Cautions 1. Address setup wait and address hold wait cycles are not inserted when the internal ROM
area, internal RAM area, and on-chip peripheral I/O areas are accessed.
2. Write to the AWC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the AWC register are
complete.
After reset: FFFFH R/W Address: FFFFF488H
1
AHW3
AWC
1
ASW3
1
AHW2
1
ASW2
1
AHW1
1
ASW1
1
AHW0
1
ASW0
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
0
ASWn
0
1
Not inserted
Inserted
Specifies insertion of address setup wait (n = 0 to 3)
CS0
CS3
CS2
CS1
AHWn
0
1
Not inserted
Inserted
Specifies insertion of address hold wait (n = 0 to 3)
Caution Be sure to set bits 15 to 8 to "1".
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5.6 Idle State Insertion Function
To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus
cycle that is executed for each space selected by the chip select function. By inserting an idle state, the data output
float delay time of the memory can be secured during read access (an idle state cannot be inserted during write
access).
Whether the idle state is to be inserted can be programmed by using the BCC register.
An idle state is inserted for all the areas immediately after system reset.
(1) Bus cycle control register (BCC)
The BCC register can be read or written in 16-bit units.
Reset sets this register to AAAAH.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
state insertion.
2. Write to the BCC register after reset, and then do not change the set values. Also, do not
access an external memory area until the initial settings of the BCC register are complete.
After reset: AAAAH R/W Address: FFFFF48AH
1
BC31
BCn1
0
1
Not inserted
Inserted
BCC
0
0
1
BC21
0
0
1
BC11
0
0
1
BC01
0
0
8
9
10
11
12
13
Specifies insertion of idle state (n = 0 to 3)
14
15
1
2
3
4
5
6
7
0
CS0
CS3
CS2
CS1
Caution Be sure to set bits 15, 13, 11, and 9 to "1", and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to "0".
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5.7 Bus
Hold
Function
5.7.1 Functional
outline
The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set in the control mode.
When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the
external address/data bus goes into a high-impedance state and is released (bus hold status). If the request for the
bus mastership is cleared and the HLDRQ pin is deasserted (high level), driving these pins is started again.
During the bus hold period, execution of the program in the internal ROM and internal RAM is continued until an
on-chip peripheral I/O register or the external memory is accessed.
The bus hold status is indicated by assertion of the HLDAK pin (low level). The bus hold function enables the
configuration of multi-processor type systems in which two or more bus masters exist.
Note that the bus hold request is not acknowledged during a multiple-access cycle initiated by the bus sizing
function or a bit manipulation instruction.
Status Data
Bus
Width
Access Type
Timing at Which Bus Hold Request
Is Not Acknowledged
Word access to even address
Between first and second access
Between first and second access
Word access to odd address
Between second and third access
16 bits
Halfword access to odd address
Between first and second access
Between first and second access
Between second and third access
Word access
Between third and fourth access
CPU bus lock
8 bits
Halfword access
Between first and second access
Read-modify-write access of bit
manipulation instruction
-
-
Between read access and write
access
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5.7.2
Bus hold procedure
The bus hold status transition procedure is shown below.
<1> HLDRQ = 0 acknowledged
<2> All bus cycle start requests inhibited
<3> End of current bus cycle
<4> Shift to bus idle status
<5> HLDAK = 0
<6> HLDRQ = 1 acknowledged
<7> HLDAK = 1
<8> Bus cycle start request inhibition released
<9> Bus cycle starts
Normal status
Bus hold status
Normal status
HLDAK (output)
HLDRQ (input)
<1> <2>
<5>
<3><4>
<7><8><9>
<6>
5.7.3
Operation in power save mode
Because the internal system clock is stopped in the STOP, IDLE1, and IDLE2 modes, the bus hold status is not
entered even if the HLDRQ pin is asserted.
In the HALT mode, the HLDAK pin is asserted as soon as the HLDRQ pin has been asserted, and the bus hold
status is entered. When the HLDRQ pin is later deasserted, the HLDAK pin is also deasserted, and the bus hold
status is cleared.
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5.8 Bus
Priority
Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are
executed in the external bus cycle.
Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and
instruction fetch (successive).
An instruction fetch may be inserted between the read access and write access in a read-modify-write access.
If an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between
accesses due to bus size limitations.
Table 5-3. Bus Priority
Priority
External Bus Cycle
Bus Master
Bus hold
External device
DMA transfer
DMAC
Operand data access
CPU
Instruction fetch (branch)
CPU
High
Low
Instruction fetch (successive)
CPU
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5.9 Bus
Timing
Figure 5-4. Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access)
A1
A2
A3
D1
D2
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
Programmable
wait
External
wait
Idle state
CLKOUT
ASTB
CS3 to CS0
WAIT
AD15 to AD0
RD
8-bit access
AD15 to AD8
AD7 to AD0
Odd address
Active
Hi-Z
Even address
Hi-Z
Active
Remark The broken lines indicate high impedance.
Figure 5-5. Bus Read Timing (Bus Size: 8 Bits)
A1
A2
A3
D1
D2
A3
A2
A1
T1
T2
T3
T1
T2
TW
TW
T3
TI
T1
Programmable
wait
External
wait
Idle state
CLKOUT
AD15 to AD8
ASTB
CS3 to CS0
WAIT
AD7 to AD0
RD
Remark The broken lines indicate high impedance.
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Figure 5-6. Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access)
A1
11
00
11
11
00
11
A2
A3
D1
D2
T2
T3
T1
T1
T2
TW
TW
T3
T1
Programmable
wait
External
wait
CLKOUT
ASTB
CS3 to CS0
WAIT
AD15 to AD0
WR1, WR0
WR1, WR0
01
10
8-bit access
AD15 to AD8
AD7 to AD0
Odd address
Active
Undefined
Even address
Undefined
Active
Figure 5-7. Bus Write Timing (Bus Size: 8 Bits)
A1
11
10
11
11
10
11
A2
A3
D1
D2
A3
A2
A1
T2
T3
T1
T1
T2
TW
TW
T3
T1
Programmable
wait
External
wait
CLKOUT
AD15 to AD8
ASTB
CS3 to CS0
WAIT
AD7 to AD0
WR1, WR0
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Figure 5-8. Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access)
T1
A1
T2
T3
TI
Note
TH
TH
TH
TH
TI
Note
T1
T2
T3
D1
CLKOUT
HLDRQ
HLDAK
ASTB
CS3 to CS0
AD15 to AD0
RD
Undefined
Undefined
A2
D2
1111
1111
Note This idle state (TI) does not depend on the BCC register settings.
Remarks 1. See
Table 2-4 for the pin statuses in the bus hold mode.
2. The broken lines indicate high impedance.
Figure 5-9. Address Wait Timing (Bus Size: 16 Bits, 16-Bit Access)
TASW
T1
TAHW
T2
CLKOUT
ASTB
AD15 to AD0
CS3 to CS0
WAIT
RD
A1
T1
T2
CLKOUT
ASTB
AD15 to AD0
CS3 to CS0
WAIT
RD
D1
D1
A1
Remarks 1. TASW (address setup wait): Image of high-level width of T1 state expanded.
2. TAHW (address hold wait): Image of low-level width of T1 state expanded.
3. The broken lines indicate high impedance.
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CHAPTER 6 CLOCK GENERATION FUNCTION
6.1 Overview
The following clock generation functions are available.
Main clock oscillator
In clock-through mode
f
X
= 4 to 5 MHz (f
XX
= 4 to 5 MHz)
In PLL mode
f
X
= 4 to 5 MHz (f
XX
= 16 to 20 MHz)
Subclock oscillator (crystal oscillation or RC oscillation selectable by option byte function)
32.768 kHz (crystal resonator)
20 kHz (RC oscillator)
Multiply (
4) function by PLL (Phase Locked Loop)
Clock-through mode/PLL mode selectable
Internal oscillator
f
R
= 200 kHz (TYP.)
Internal system clock generation
7 steps (f
XX
, f
XX
/2, f
XX
/4, f
XX
/8, f
XX
/16, f
XX
/32, f
XT
)
Peripheral clock generation
Clock output function
Programmable clock (PCL) output function
Remark f
X
: Main clock oscillation frequency
f
XX
: Main clock frequency
f
R
: Internal oscillation clock frequency
f
XT
: Subclock frequency
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6.2 Configuration
Figure 6-1. Clock Generator
FRC bit
MFRC
bit
MCK
bit
CK2 to CK0
bits
SELPLL
bit
PLLON bit
PCK1,
PCK0
bits
CLS, CK3
bits
STOP mode
Subclock
oscillator
Port CM
Prescaler 1
Prescaler 2
IDLE
control
HALT
control
HALT
mode
CPU clock
Watch timer clock
Timer M clock
Watch timer clock,
watchdog timer 2 clock
Peripheral clock,
watchdog timer 2 clock
Watchdog timer 2 clock,
timer M clock
Internal
system clock
Prescaler 3
Main clock
oscillator
Main clock
oscillator
stop control
RSTOP bit
Internal
oscillator
1/8 divider
XT1
XT2
CLKOUT
X1
X2
PCL
IDLE mode
PLL
f
XX
/32
f
XX
/16
f
XX
/8
f
XX
/4
f
XX
/2
f
XX
f
CPU
f
CLK
f
XX
to f
XX
/1024
f
X
to f
X
/1024
Watchdog timer 2 clock
f
BRG
= f
X
/2 to f
X
/2
12
f
XT
f
XT
f
XX
f
X
f
R
f
R
/8
IDLE
control
Note
Prescaler 4
Selector
Selector
Selector
Selector
Selector
Note The internal oscillation clock is selected when watchdog timer 2 overflows during the oscillation
stabilization time.
Remark f
X
:
Main clock oscillation frequency
f
XX
: Main clock frequency
f
CLK
: Internal system clock frequency
f
XT
: Subclock frequency
f
CPU
: CPU clock frequency
f
BRG
: Watch timer clock frequency
f
R
:
Internal oscillation clock frequency
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(1) Main clock oscillator
The main resonator oscillates the following frequencies (f
X
).
In clock-through mode
f
X
= 4 to 5 MHz
In PLL mode
f
X
= 4 to 5 MHz (f
XX
= 16 to 20 MHz)
(2) Subclock oscillator
The sub-resonator oscillates a frequency (f
XT
) of 32.768 kHz or 20 kHz.
(3) Main clock oscillator stop control
This circuit generates a control signal that stops oscillation of the main clock oscillator.
Oscillation of the main clock oscillator is stopped in the STOP mode or when the PCC.MCK bit = 1 (valid only
when the PCC.CLS bit = 1).
(4) Internal oscillator
Oscillates a frequency (f
R
) of 200 kHz (TYP.).
(5) Prescaler 1
This circuit generates the clock (f
XX
to f
XX
/1,024) to be supplied to the following on-chip peripheral functions:
TMP0 to TMP3, TMQ0 to TMQ2, TMM0, CSIB0 to CSIB2, UARTA0 to UARTA3
Note
, ADC, and WDT2
Note UART3:
PD70F3711, 70F3712 only
(6) Prescaler 2
This circuit divides the main clock (f
XX
).
The clock generated by prescaler 2 (f
XX
to f
XX
/32) is supplied to the selector that generates the CPU clock
(f
CPU
) and internal system clock (f
CLK
).
f
CLK
is the clock supplied to the INTC, ROM, and RAM blocks, and can be output from the CLKOUT pin.
(7) Prescaler 3
This circuit divides the clock generated by the main clock oscillator (f
X
) to a specific frequency (32.768 kHz)
and supplies that clock to the watch timer block.
For details, see CHAPTER 10 WATCH TIMER FUNCTIONS.
(8) Prescaler 4
This circuit generates the clock (f
X
to f
X
/1,024) to be supplied to on-chip peripheral function.
The block to be supplied is WDT2 only.
(9) PLL
This circuit multiplies the clock generated by the main clock oscillator (f
X
) by 4.
It operates in two modes: clock-through mode in which f
X
is output as is, and PLL mode in which a multiplied
clock is output. These modes can be selected by using the PLLCTL.SELPLL bit.
Whether the clock is multiplied by 4 is selected by the CKC.CKDIV0 bit, and PLL is started or stopped by the
PLLCTL.PLLON bit.
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6.3 Registers
(1) Processor clock control register (PCC)
The PCC register is a special register. Data can be written to this register only in combination of specific
sequences (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 03H.
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FRC
Used
Not used
FRC
0
1
Use of subclock on-chip feedback resistor
PCC
MCK
MFRC
CLS
Note
CK3
CK2
CK1
CK0
Oscillation enabled
Oscillation stopped
MCK
0
1
Main clock oscillator control
Used
Not used
MFRC
0
1
Use of main clock on-chip feedback resistor
After reset: 03H R/W Address: FFFFF828H
Main clock operation
Subclock operation
CLS
Note
0
1
Status of CPU clock (f
CPU
)
Even if the MCK bit is set (1) while the system is operating with the main clock as
the CPU clock, the operation of the main clock does not stop. It stops after the
CPU clock has been changed to the subclock.
Before setting the MCK bit from 0 to 1, stop the on-chip peripheral functions
operating with the main clock.
When the main clock is stopped and the device is operating with the subclock,
clear (0) the MCK bit and secure the oscillation stabilization time by software
before switching the CPU clock to the main clock or operating the on-chip
peripheral functions.
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
Setting prohibited
f
XT
CK2
0
0
0
0
1
1
1
Clock selection (f
CLK
/f
CPU
)
CK1
0
0
1
1
0
0
1
CK0
0
1
0
1
0
1
CK3
0
0
0
0
0
0
0
1
Note The CLS bit is a read-only bit.
Cautions 1. Do not change the CPU clock (by using the CK3 to CK0 bits) while CLKOUT is being
output.
2. Use a bit manipulation instruction to manipulate the CK3 bit. When using an 8-bit
manipulation instruction, do not change the set values of the CK2 to CK0 bits.
Remark
: don't care
CHAPTER 6 CLOCK GENERATION FUNCTION
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(a) Example of setting main clock operation
subclock operation
<1> CK3
bit
1:
Use of a bit manipulation instruction is recommended. Do not change the CK2
to CK0 bits.
<2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the
following time after the CK3 bit is set until subclock operation is started.
Max.: 1/f
XT
(1/subclock frequency)
<3> MCK
bit
1:
Set the MCK bit to 1 only when stopping the main clock.
Cautions 1. When stopping the main clock, stop the PLL. Also stop the operations of the on-chip
peripheral functions operating with the main clock.
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
conditions are satisfied, then change to the subclock operation mode.
Internal system clock (f
CLK
) > Subclock (f
XT
: 32.768 kHz)
4
Remark Internal system clock (f
CLK
): Clock generated from the main clock (f
XX
) by setting bits CK2 to
CK0
[Description example]
_DMA_DISABLE:
clrl 0,
DCHCn[r0]
-- DMA operation disabled. n = 0 to 3
<1> _SET_SUB_RUN :
st.b r0,
PRCMD[r0]
set1 3,
PCC[r0]
-- CK3 bit
1
<2> _CHECK_CLS :
tst1 4,
PCC[r0]
-- Wait until subclock operation starts.
bz _CHECK_CLS
<3> _STOP_MAIN_CLOCK :
st.b r0,
PRCMD[r0]
set1 6,
PCC[r0]
-- MCK bit
1, main clock is stopped.
_DMA_ENABLE:
setl 0,
DCHCn[r0]
-- DMA operation enabled. n = 0 to 3
Remark The description above is simply an example. Note that in <2> above, the CLS bit is read in a
closed loop.
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(b) Example of setting subclock operation
main clock operation
<1> MCK
bit
0:
Main clock starts oscillating
<2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses.
<3> CK3
bit
0:
Use of a bit manipulation instruction is recommended. Do not change the
CK2 to CK0 bits.
<4> Main clock operation: It takes the following time after the CK3 bit is set until main clock operation
is started.
Max.:
1/f
XT
(1/subclock frequency)
Therefore, insert one NOP instruction immediately after setting the CK3 bit
to 0 or read the CLS bit to check if main clock operation has started.
Caution Enable operation of the on-chip peripheral functions operating with the main clock only
after the oscillation of the main clock stabilizes. If their operations are enabled before
the lapse of the oscillation stabilization time, a malfunction may occur.
[Description example]
_DMA_DISABLE:
clrl 0,
DCHCn[r0]
-- DMA operation disabled. n = 0 to 3
<1> _START_MAIN_OSC :
st.b r0,
PRCMD[r0]
-- Release of protection of special registers
clr1 6,
PCC[r0]
-- Main clock starts oscillating.
<2> movea
0x55, r0, r11
-- Wait for oscillation stabilization time.
_WAIT_OST :
nop
nop
nop
addi
-1, r11, r11
cmp r0,
r11
bne
_WAIT_OST
<3> st.b r0,
PRCMD[r0]
clr1 3,
PCC[r0]
--
CK3
0
<4> _CHECK_CLS :
tst1 4,
PCC[r0]
-- Wait until main clock operation starts.
bnz _CHECK_CLS
_DMA_ENABLE:
setl 0,
DCHCn[r0]
-- DMA operation enabled. n = 0 to 3
Remark The description above is simply an example. Note that in <4> above, the CLS bit is read in a
closed loop.
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(2) Internal oscillation mode register (RCM)
The RCM register is an 8-bit register that sets the operation mode of the internal oscillator.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
RCM
0
0
0
0
0
0
RSTOP
Internal oscillator oscillation
Internal oscillator stopped
RSTOP
0
1
Oscillation/stop of internal oscillator
After reset: 00H R/W Address: FFFFF80CH
Cautions 1. The settings of the RCM register are valid by setting the option byte.
For details, see CHAPTER 25 OPTION BYTE FUNCTION.
2. The internal oscillator cannot be stopped while the CPU is operating on the internal
oscillation clock (CCLS.CCLSF bit = 1). Do not set the RSTOP bit to 1.
3. The internal oscillator oscillates if the CCLS.CCLSF bit is set to 1 (when WDT overflow
occurs during oscillation stabilization) even when the RSTOP bit is set to 1. At this time,
the RSTOP bit remains being set to 1.
(3) CPU operation clock status register (CCLS)
The CCLS register indicates the status of the CPU operation clock.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
CCLS
0
0
0
0
0
0
CCLSF
After reset: 00H
Note
R Address: FFFFF82EH
Operating on main clock (f
X
) or subclock (f
XT
).
Operating on internal oscillation clock (f
R
).
CCLSF
0
1
CPU operation clock status
Note If WDT overflow occurs during oscillation stabilization after a reset is released, the CCLSF bit is set
to 1 and the reset value is 01H.
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6.4 Operation
6.4.1
Operation of each clock
The following table shows the operation status of each clock.
Table 6-1. Operation Status of Each Clock
PCC Register
CLK Bit = 0, MCK Bit = 0
CLS Bit = 1,
MCK Bit = 0
CLS Bit = 1,
MCK Bit = 1
Register Setting and
Operation Status
Target Clock
During
Reset
During
Oscillation
Stabilization
Time Count
HALT
Mode
IDLE1,
IDLE2
Mode
STOP
Mode
Subclock
Mode
Sub-IDLE
Mode
Subclock
Mode
Sub-IDLE
Mode
Main clock oscillator (f
X
)
Subclock oscillator (f
XT
)
CPU clock (f
CPU
)
Internal system clock (f
CLK
)
Main clock (in PLL mode, f
XX
)
Note 1
Note 2
Peripheral clock (f
XX
to f
XX
/1,024)
WT clock (main)
WT clock (sub)
WDT2 clock (internal oscillation)
WDT2 clock (main)
Notes 1. Oscillation starts after time 1/2 of the oscillation stabilization time, and the stable clock is supplied after
lockup time.
2. Operable in the IDLE1 mode. Stopped in the IDLE2 mode.
Remark
: Operable
: Stopped
6.4.2
Clock output function
The clock output function is used to output the internal system clock (f
CLK
) from the CLKOUT pin.
The internal system clock (f
CLK
) is selected by using the PCC.CK3 to PCC.CK0 bits.
The CLKOUT pin functions alternately as the PCM1 pin and functions as a clock output pin if so specified by the
control register of port CM.
The status of the CLKOUT pin is the same as the internal system clock in Table 6-1 and the pin can output the
clock when it is in the operable status. It outputs a low level in the stopped status. However, the CLKOUT pin is in
the port mode (PCM1 pin: input mode) after reset and until it is set in the output mode. Therefore, the status of the pin
is Hi-Z.
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6.5 PLL
Function
6.5.1 Overview
In the V850ES/HJ2, an operating clock that is 4 times higher than the oscillation frequency output by the PLL
function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral
functions.
When PLL function is used:
Input clock = 4 to 5 MHz (output: 16 to 20 MHz)
Clock-through mode:
Input clock = 4 to 5 MHz (output: 4 to 5 MHz)
6.5.2 Registers
(1) PLL control register (PLLCTL)
The PLLCTL register is an 8-bit register that controls the PLL function.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
0
PLLCTL
0
0
0
0
0
SELPLL
PLLON
PLL stopped
PLL operating
(After PLL operation starts, a lockup time is required for frequency stabilization)
PLLON
0
1
PLL operation stop register
Clock-through mode
PLL mode
SELPLL
0
1
CPU operation clock selection register
After reset: 01H R/W Address: FFFFF82CH
Cautions 1. When the PLLON bit is cleared to 0, the SELPLL bit is automatically cleared to 0 (clock-
through mode).
2. The SELPLL bit can be set to 1 only when the PLL clock frequency is stabilized. If not
(unlocked), "0" is written to the SELPLL bit if data is written to it.
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(2) Lock register (LOCKR)
Phase lock occurs at a given frequency following power application or immediately after the STOP mode is
released, and the time required for stabilization is the lockup time (frequency stabilization time). This state
until stabilization is called the lockup status, and the stabilized state is called the locked status.
The LOCKR register includes a LOCK bit that reflects the PLL frequency stabilization status.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
LOCKR
0
0
0
0
0
0
LOCK
Locked status
Unlocked status
LOCK
0
1
PLL lock status check
After reset: 00H R Address: FFFFF824H
Caution The LOCK register does not reflect the lock status of the PLL in real time. The set/clear
conditions are as follows.
[Set conditions]
Upon system reset
Note
In IDLE2 or STOP mode
Upon setting of PLL stop (clearing of PLLCTL.PLLON bit to 0)
Upon stopping main clock and using CPU with subclock (setting of PCC.CK3 bit to 1 and setting of
PCC.MCK bit to 1)
Note This register is set to 01H by reset and cleared to 00H after the reset has been released and the
oscillation stabilization time has elapsed.
[Clear conditions]
Upon overflow of oscillation stabilization time following reset release (OSTS register default time (see 18.2
(3) Oscillation stabilization time select register (OSTS)))
Upon oscillation stabilization timer overflow (time set by OSTS register) following STOP mode release,
when the STOP mode was set in the PLL operating status
Upon PLL lockup time timer overflow (time set by PLLS register) when the PLLCTL.PLLON bit is changed
from 0 to 1
After the setup time inserted upon release of the IDLE2 mode is released (time set by the OSTS register)
when the IDLE2 mode is set during PLL operation.
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(3) PLL lockup time specification register (PLLS)
The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is
changed from 0 to 1.
This register can be read or written in 8-bit units.
Reset sets this register to 03H.
0
2
10
/f
X
2
11
f
X
2
12
/f
X
2
13
/f
X
(default value)
PLLS1
0
0
1
1
PLLS0
0
1
0
1
Selection of PLL lockup time
PLLS
0
0
0
0
0
PLLS1
PLLS0
After reset: 03H R/W Address: FFFFF6C1H
Cautions 1. Set so that the lockup time is 800
s or longer.
2. Do not change the PLLS register setting during the lockup period.
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(4) Programmable clock mode register (PCLM)
The PCLM register is an 8-bit register used to control the PCL output.
This register can be read or written in 8-bit or 1-bit units.
After reset: 00H R/W Address: FFFFF82FH
0
PCLE
0
1
PCL pin output disabled (PCL pin is fixed to low level)
PCL pin output enabled
Selection of PCL pin output operation
PCLM
0
0
PCLE
0
0
PCK1
PCK0
Caution Set the port-related control registers (PM, PMC, PFC, and PFCE registers, etc.) first, and then
set the PCLE bit to 1.
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
PCK1
0
0
1
1
PCK0
0
1
0
1
Selection of PLL output clock
Caution Set the PCLE bit to 1 only during PLL operation. To stop the PLL, clear the PCLE bit to 0.
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6.5.3 Usage
(1) When PLL is used
After the reset signal has been released, the PLL operates (PLLCTL.PLLON bit = 1), but because the default
mode is the clock-through mode (PLLCTL.SELPLL bit = 0), select the PLL mode (SELPLL bit = 1).
To enable PLL operation, first set the PLLON bit to 1, and then set the SELPLL bit to 1 after the
LOCKR.LOCK bit = 0. To stop the PLL, first select the clock-through mode (SELPLL bit = 0), wait for 8
clocks or more, and then stop the PLL (PLLON bit = 0).
The PLL stops during transition to IDLE2 or STOP mode regardless of the setting and is restored from
IDLE2 or STOP mode to the status before transition. The time required for restoration is as follows.
(a) When transiting to IDLE2 or STOP mode from the clock through mode
STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
IDLE2 mode: Set the OSTS register so that the setup time is 350
s (min.) or longer.
(b) When shifting to the IDLE 2 or STOP mode while remaining in the PLL operation mode
STOP mode: Set the OSTS register so that the oscillation stabilization time is 1 ms (min.) or longer.
IDLE2 mode: Set the OSTS register so that the setup time is 800
s (min.) or longer.
When shifting to the IDLE1 mode, the PLL does not stop. Stop the PLL if necessary.
(2) When PLL is not used
The clock-through mode (SELPLL bit = 0) is selected after the reset signal has been released, but the PLL is
operating (PLLON bit = 1) and must therefore be stopped (PLLON bit = 0).
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CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Timer P (TMP) is a 16-bit timer/event counter.
The V850ES/HJ2 has four timer/event counter channels, TMP0 to TMP3.
7.1 Overview
An outline of TMPn is shown below.
Clock selection: 8 ways
Capture/trigger input pins: 2
External event count input pins: 1
External trigger input pins: 1
Timer/counters: 1
Capture/compare registers: 2
Capture/compare match interrupt request signals: 2
Timer output pins: 2
Remark n = 0 to 3
7.2 Functions
TMPn has the following functions.
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
Remark n = 0 to 3
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7.3 Configuration
TMPn includes the following hardware.
Table 7-1. Configuration of TMPn
Item Configuration
Timer register
16-bit counter
Registers
TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1)
TMPn counter read buffer register (TPnCNT)
CCR0, CCR1 buffer registers
Timer inputs
2 (TIPn0
Note 1
, TIPn1 pins)
Timer outputs
2 (TOPn0, TOPn1 pins)
Control registers
Note 2
TMPn control registers 0, 1 (TPnCTL0, TPnCTL1)
TMPn I/O control registers 0 to 2 (TPnIOC0 to TPnIOC2)
TMPn option register 0 (TPnOPT0)
Notes 1. The TIPn0 pin functions alternately as a capture trigger input signal, external event count
input signal, and external trigger input signal.
2. When using the functions of the TIPn0, TIPn1, TOPn0, and TOPn1 pins, see Table 4-25
Using Port Pin as Alternate-Function Pin.
Remark n = 0 to 3
Figure 7-1. Block Diagram of TMPn
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
Note 1
, f
XT
Note 2
Selector
Internal bus
Internal bus
TOPn0
TOPn1
TIPn0
TIPn1
Selector
Edge
detector
CCR0
buffer
register
CCR1
buffer
register
TPnCCR0
TPnCCR1
16-bit counter
TPnCNT
INTTPnOV
INTTPnCC0
INTTPnCC1
Output
controller
Clear
Notes 1. TMP0,
TMP2
2. TMP1, TMP3 (Counting operation cannot be performed with the subclock when the main clock is
stopped.)
Remark f
XX
: Main clock frequency
f
XT
: Subclock frequency
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(1) 16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TPnCNT register.
When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at
this time, 0000H is read.
Reset sets the TPnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
(2) CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TPnCCR0 register is used as a compare register, the value written to the TPnCCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the
CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset, as the TPnCCR0 register is cleared to 0000H.
(3) CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TPnCCR1 register is used as a compare register, the value written to the TPnCCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the
CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset, as the TPnCCR1 register is cleared to 0000H.
(4) Edge detector
This circuit detects the valid edges input to the TIPn0 and TIPn1 pins. No edge, rising edge, falling edge, or
both the rising and falling edges can be selected as the valid edge by using the TPnIOC1 and TPnIOC2
registers.
(5) Output controller
This circuit controls the output of the TOPn0 and TOPn1 pins. The output controller is controlled by the
TPnIOC0 register.
(6) Selector
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event
can be selected as the count clock.
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7.4 Registers
The registers that control TMPn are as follows.
TMPn control register 0 (TPnCTL0)
TMPn control register 1 (TPnCTL1)
TMPn I/O control register 0 (TPnIOC0)
TMPn I/O control register 1 (TPnIOC1)
TMPn I/O control register 2 (TPnIOC2)
TMPn option register 0 (TPnOPT0)
TMPn capture/compare register 0 (TPnCCR0)
TMPn capture/compare register 1 (TPnCCR1)
TMPn counter read buffer register (TPnCNT)
Remarks 1. When using the functions of the TIPn0, TIPn1, TOPn0, and TOPn1 pins, see Table 4-25 Using Port
Pin as Alternate-Function Pin.
2. n = 0 to 3
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(1) TMPn control register 0 (TPnCTL0)
The TPnCTL0 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TPnCTL0 register by software.
TPnCE
TMPn operation disabled (TMPn reset asynchronously
Note 1
).
TMPn operation enabled. TMPn operation started.
TPnCE
0
1
TMPn operation control
TPnCTL0
(n = 0 to 3)
0
0
0
0
TPnCKS2 TPnCKS1 TPnCKS0
6
5
4
3
2
1
After reset: 00H R/W Address:
TP0CTL0 FFFFF590H, TP1CTL0 FFFFF5A0H,
TP2CTL0 FFFFF5B0H, TP3CTL0 FFFFF5C0H
7
0
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
f
XT
Note 2
TPnCKS2
0
0
0
0
1
1
1
1
Internal count clock selection
n = 0, 2
n = 1, 3
TPnCKS1
0
0
1
1
0
0
1
1
TPnCKS0
0
1
0
1
0
1
0
1
Notes 1. TPn0PT0.TPnOVF bit, 16-bit counter, timer output (TOPn0, TOPn1 pins)
2. Counting operation cannot be performed with the subclock when the main
clock is stopped.
Cautions 1. Set the TPnCKS2 to TPnCKS0 bits when the TPnCE bit = 0.
When the value of the TPnCE bit is changed from 0 to 1, the
TPnCKS2 to TPnCKS0 bits can be set simultaneously.
2. Be sure to clear bits 3 to 6 to "0".
Remark f
XX
: Main clock frequency
f
XT
: Subclock frequency
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(2) TMPn control register 1 (TPnCTL1)
The TPnCTL1 register is an 8-bit register that controls the operation of TMPn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
TPnSYE
TPnEST
0
1
Software trigger control
Slave timer
TPnCTL1
(n = 0 to 3)
TPnEST
TPnEEE
0
0
TPnMD2 TPnMD1 TPnMD0
6
5
4
3
2
1
After reset: 00H R/W Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H,
TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H
Generate a valid signal for external trigger input.
In one-shot pulse output mode: A one-shot pulse is output with writing
1 to the TPnEST bit as the trigger.
In external trigger pulse output mode: A PWM waveform is output with
writing 1 to the TPnEST bit as the
trigger.
7
0
-
TPnSYE
0
1
Tuned operation mode enable control
Tuned operation mode (specification of slave operation)
In this mode, timer P can operate in synchronization with a master timer.
Independent operation mode (asynchronous operation mode)
For the tuned operation mode, see 7.6 Timer Tuned Operation
Function.
Caution Be sure to clear the TP0SYE and TP2SYE bits to 0.
Master timer
TMP0
TMP2
TMQ1
TMP1
TMP3
TMQ2
-
TMQ0
-
Cautions 1. The TPnEST bit is valid only in the external trigger pulse output
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
2. Be sure to clear bits 3 and 4 to "0".
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(2/2)
Disable operation with external event count input.
(Perform counting with the count clock selected by the TPnCTL0.TPnCK0
to TPnCK2 bits.)
TPnEEE
0
1
Count clock selection
The TPnEEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Setting prohibited
TPnMD2
0
0
0
0
1
1
1
1
Timer mode selection
TPnMD1
0
0
1
1
0
0
1
1
TPnMD0
0
1
0
1
0
1
0
1
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
Cautions 1. External event count input is selected in the external event count mode
regardless of the value of the TPnEEE bit.
2. Set the TPnEEE and TPnMD2 to TPnMD0 bits when the TPnCTL0.TPnCE
bit = 0. (The same value can be written when the TPnCE bit = 1.) The
operation is not guaranteed when rewriting is performed with the TPnCE
bit = 1. If rewriting was mistakenly performed, clear the TPnCE bit to 0
and then set the bits again.
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(3) TMPn I/O control register 0 (TPnIOC0)
The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TPnOL1
0
1
TOPn1 pin output level setting
TOPn1 pin output inversion disabled
TOPn1 pin output inversion enabled
TPnIOC0
(n = 0 to 3)
0
0
0
TPnOL1 TPnOE1
TPnOL0
TPnOE0
6
5
4
3
2
1
After reset: 00H R/W Address:
TP0IOC0 FFFFF592H, TP1IOC0 FFFFF5A2H,
TP2IOC0 FFFFF5B2H, TP3IOC0 FFFFF5C2H
TPnOE1
0
1
TOPn1 pin output setting
Timer output disabled
When TPnOL1 bit = 0: Low level is output from the TOPn1 pin
When TPnOL1 bit = 1: High level is output from the TOPn1 pin
TPnOL0
0
1
TOPn0 pin output level setting
TOPn0 pin output inversion disabled
TOPn0 pin output inversion enabled
TPnOE0
0
1
TOPn0 pin output setting
Timer output disabled
When TPnOL0 bit = 0: Low level is output from the TOPn0 pin
When TPnOL0 bit = 1: High level is output from the TOPn0 pin
7
0
Timer output enabled (a square wave is output from the TOPn1 pin).
Timer output enabled (a square wave is output from the TOPn0 pin).
Cautions 1. Rewrite the TPnOL1, TPnOE1, TPnOL0, and TPnOE0 bits
when the TPnCTL0.TPnCE bit = 0. (The same value can be
written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then
set the bits again.
2. Even if the TPnOLm bit is manipulated when the TPnCE
and TPnOEm bits are 0, the TOPnm pin output level varies
(m = 0, 1).
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(4) TMPn I/O control register 1 (TPnIOC1)
The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0,
TIPn1 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TPnIS3
0
0
1
1
TPnIS2
0
1
0
1
Capture trigger input signal (TIPn1 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TPnIOC1
(n = 0 to 3)
0
0
0
TPnIS3
TPnIS2
TPnIS1
TPnIS0
6
5
4
3
2
1
After reset: 00H R/W Address:
TP0IOC1 FFFFF593H, TP1IOC1 FFFFF5A3H,
TP2IOC1 FFFFF5B3H, TP3IOC1 FFFFF5C3H
TPnIS1
0
0
1
1
TPnIS0
0
1
0
1
Capture trigger input signal (TIPn0 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7
0
Cautions
1.
Rewrite the TPnIS3 to TPnIS0 bits when the
TPnCTL0.TPnCE bit = 0. (The same value can be written
when the TPnCE bit = 1.) If rewriting was mistakenly
performed, clear the TPnCE bit to 0 and then set the bits
again.
2. The TPnIS3 to TPnIS0 bits are valid only in the free-
running timer mode and the pulse width measurement
mode. In all other modes, a capture operation is not
possible.
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(5) TMPn I/O control register 2 (TPnIOC2)
The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIPn0 pin) and external trigger input signal (TIPn0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TPnEES1
0
0
1
1
TPnEES0
0
1
0
1
External event count input signal (TIPn0 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TPnIOC2
(n = 0 to 3)
0
0
0
TPnEES1 TPnEES0 TPnETS1 TPnETS0
6
5
4
3
2
1
After reset: 00H R/W Address:
TP0IOC2 FFFFF594H, TP1IOC2 FFFFF5A4H,
TP2IOC2 FFFFF5B4H, TP3IOC2 FFFFF5C4H
TPnETS1
0
0
1
1
TPnETS0
0
1
0
1
External trigger input signal (TIPn0 pin) valid edge setting
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7
0
Cautions 1. Rewrite the TPnEES1, TPnEES0, TPnETS1, and TPnETS0
bits when the TPnCTL0.TPnCE bit = 0. (The same value
can be written when the TPnCE bit = 1.) If rewriting was
mistakenly performed, clear the TPnCE bit to 0 and then
set the bits again.
2. The TPnEES1 and TPnEES0 bits are valid only when the
TPnCTL1.TPnEEE bit = 1 or when the external event
count mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits
= 001) has been set.
3. The TPnETS1 and TPnETS0 bits are valid only when the
external trigger pulse output mode (TPnCTL1.TPnMD2 to
TPnCTL1.TPnMD0 bits = 010) or the one-shot pulse
output mode (TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 =
011) is set.
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(6) TMPn option register 0 (TPnOPT0)
The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TPnCCS1
0
1
TPnCCR1 register capture/compare selection
The TPnCCS1 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TPnOPT0
(n = 0 to 3)
0
TPnCCS1 TPnCCS0
0
0
0
TPnOVF
6
5
4
3
2
1
After reset: 00H R/W Address:
TP0OPT0 FFFFF595H, TP1OPT0 FFFFF5A5H,
TP2OPT0 FFFFF5B5H, TP3OPT0 FFFFF5C5H
TPnCCS0
0
1
TPnCCR0 register capture/compare selection
The TPnCCS0 bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TPnOVF
Set (1)
Reset (0)
TMPn overflow detection flag
The TPnOVF bit is set to 1 when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
An interrupt request signal (INTTPnOV) is generated at the same time that the
TPnOVF bit is set to 1. The INTTPnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
The TPnOVF bit is not cleared even when the TPnOVF bit or the TPnOPT0
register are read when the TPnOVF bit = 1.
The TPnOVF bit can be both read and written, but the TPnOVF bit cannot be set
to 1 by software. Writing 1 has no influence on the operation of TMPn.
Overflow occurred
TPnOVF bit 0 written or TPnCTL0.TPnCE bit = 0
7
0
Cautions 1. Rewrite the TPnCCS1 and TPnCCS0 bits when the TPnCE
bit = 0. (The same value can be written when the TPnCE
bit = 1.) If rewriting was mistakenly performed, clear the
TPnCE bit to 0 and then set the bits again.
2. Be sure to clear bits 1 to 3, 6, and 7 to "0".
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(7) TMPn capture/compare register 0 (TPnCCR0)
The TPnCCR0 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TPnOPT0.TPnCCS0 bit. In the pulse width measurement mode, the TPnCCR0
register can be used only as a capture register. In any other mode, this register can be used only as a
compare register.
The TPnCCR0 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TPnCCR0 register is prohibited in the following statuses. For details, see 3.4.8
(2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TPnCCR0
(n = 0 to 3)
12
10
8
6
4
2
After reset: 0000H R/W Address:
TP0CCR0 FFFFF596H, TP1CCR0 FFFFF5A6H,
TP2CCR0 FFFFF5B6H, TP3CCR0 FFFFF5C6H
14
0
13
11
9
7
5
3
15
1
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(a) Function as compare register
The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1.
The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the
16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTPnCC0) is generated. If TOPn0 pin output is enabled at this time, the output of the TOPn0 pin is
inverted.
When the TPnCCR0 register is used as a cycle register in the interval timer mode, external event count
mode, external trigger pulse output mode, one-shot pulse output mode, or PWM output mode, the value of
the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0 buffer register.
(b) Function as capture register
When the TPnCCR0 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TPnCCR0 register if the valid edge of the capture trigger input pin
(TIPn0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TPnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIPn0) is detected.
Even if the capture operation and reading the TPnCCR0 register conflict, the correct value of the
TPnCCR0 register can be read.
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Table 7-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
-
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(8) TMPn capture/compare register 1 (TPnCCR1)
The TPnCCR1 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TPnOPT0.TPnCCS1 bit. In the pulse width measurement mode, the TPnCCR1
register can be used only as a capture register. In any other mode, this register can be used only as a
compare register.
The TPnCCR1 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TPnCCR1 register is prohibited in the following statuses. For details, see 3.4.8
(2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TPnCCR1
(n = 0 to 3)
12
10
8
6
4
2
After reset: 0000H R/W Address:
TP0CCR1 FFFFF598H, TP1CCR1 FFFFF5A8H,
TP2CCR1 FFFFF5B8H, TP3CCR1 FFFFF5C8H
14
0
13
11
9
7
5
3
15
1
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(a) Function as compare register
The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1.
The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the
16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTPnCC1) is generated. If TOPn1 pin output is enabled at this time, the output of the TOPn1 pin is
inverted.
(b) Function as capture register
When the TPnCCR1 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TPnCCR1 register if the valid edge of the capture trigger input pin
(TIPn1 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TPnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIPn1) is detected.
Even if the capture operation and reading the TPnCCR1 register conflict, the correct value of the
TPnCCR1 register can be read.
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Table 7-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
-
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(9) TMPn counter read buffer register (TPnCNT)
The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter.
If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read.
This register is read-only, in 16-bit units.
The value of the TPnCNT register is cleared to 0000H when the TPnCE bit = 0. If the TPnCNT register is read
at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read.
The value of the TPnCNT register is cleared to 0000H after reset, as the TPnCE bit is cleared to 0.
Caution Accessing the TPnCNT register is prohibited in the following statuses. For details, see 3.4.8
(2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TPnCNT
(n = 0 to 3)
12
10
8
6
4
2
After reset: 0000H R Address:
TP0CNT FFFFF59AH, TP1CNT FFFFF5AAH,
TP2CNT FFFFF5BAH, TP3CNT FFFFF5CAH
14
0
13
11
9
7
5
3
15
1
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(10) TIPnm pin noise elimination control register (PnmNFC)
The PnmNFC register is an 8-bit register that sets the digital noise filter of the timer P input pin for noise
elimination.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: P00NFC : FFFFFB00H (TIP00 pin)
P01NFC : FFFFFB04H (TIP01 pin)
P10NFC : FFFFFB08H (TIP10 pin)
P11NFC : FFFFFB0CH (TIP11 pin)
P20NFC : FFFFFB10H (TIP20 pin)
P21NFC : FFFFFB14H (TIP21 pin)
P30NFC : FFFFFB18H (TIP30 pin)
P31NFC : FFFFFB1CH (TIP31 pin)
7 6 5 4 3 2 1 0
PnmNFC
0
NFSTS
0 0 0
NFC2
NFC1
NFC0
(n = 0 to 3, m = 0, 1)
NFSTS
Setting of number of times of sampling by digital noise filter
0
3
times
1
2
times
Sampling clock
NFC2 NFC1 NFC0
n = 0, 2
n = 1, 3
0
0
0
f
XX
0
0
1
f
XX
/2
0
1
0
f
XX
/4
0
1
1
f
XX
/16 f
XX
/8
1
0
0
f
XX
/32 f
XX
/16
1
0
1
f
XX
/64 f
XT
Other than above
Setting prohibited
Cautions 1. Be sure to clear bits 3 to 5 and 7 to "0".
2. A signal input to the timer input pin (TIPnm) before the PnmNFC
register is set is output with digital noise eliminated.
Therefore, set the sampling clock (NFC2 to NFC0) and the number of
times of sampling (NFSTS) by using the PnmNFC register, wait for
initialization time = (Sampling clock)
(Number of times of
sampling), and enable the timer operation.
Remark The width of the noise that can be accurately eliminated is (Sampling clock)
(Number of times of sampling 1). Even noise with a width narrower than
this may cause a miscount if it is synchronized with the sampling clock.
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7.5 Operation
TMPn can perform the following operations.
Operation
TPnCTL1.TPnEST Bit
(Software Trigger Bit)
TIPn0 Pin
(External Trigger Input)
Capture/Compare
Register Setting
Compare Register
Write
Interval timer mode
Invalid
Invalid
Compare only
Anytime write
External event count mode
Note 1
Invalid Invalid Compare
only
Anytime
write
External trigger pulse output mode
Note 2
Valid Valid Compare
only
Batch
write
One-shot pulse output mode
Note 2
Valid Valid Compare
only
Anytime
write
PWM output mode
Invalid
Invalid
Compare only
Batch write
Free-running timer mode
Invalid
Invalid
Switching enabled
Anytime write
Pulse width measurement mode
Note 2
Invalid Invalid Capture
only
Not
applicable
Notes 1. To use the external event count mode, specify that the valid edge of the TIPn0 pin capture trigger input is
not detected (by clearing the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to "00").
2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width
measurement mode, select the internal clock as the count clock (by clearing the TPnCTL1.TPnEEE bit
to 0).
Remark n = 0 to 3
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7.5.1
Interval timer mode (TPnMD2 to TPnMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the
TPnCTL0.TPnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOPn0
pin.
Usually, the TPnCCR1 register is not used in the interval timer mode.
Figure 7-2. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer register
TPnCE bit
TPnCCR0 register
Count clock
selection
Clear
Match signal
TOPn0 pin
INTTPnCC0 signal
Remark n = 0 to 3
Figure 7-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
D
0
D
0
D
0
D
0
D
0
Interval (D
0
+ 1)
Interval (D
0
+ 1)
Interval (D
0
+ 1)
Interval (D
0
+ 1)
Remark n = 0 to 3
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When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally,
the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
cleared to 0000H, the output of the TOPn0 pin is inverted, and a compare match interrupt request signal
(INTTPnCC0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TPnCCR0 register + 1)
Count clock cycle
Remark n = 0 to 3
Figure 7-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
Select count clock
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
(b) TMPn control register 1 (TPnCTL1)
0
0
0/1
Note
0
0
TPnCTL1
0, 0, 0:
Interval timer mode
0: Operate on count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count with external
event count input signal
0
0
0
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
TPnSYE
Note This bit can be set to 1 only when the interrupt request signals (INTTPnCC0 and INTTPnCC1) are
masked by the interrupt mask flags (TPnCCMK0 and TPnCCMK1) and timer output (TOPn1) is
performed at the same time. However, set the TPnCCR0 and TPnCCR1 registers to the same value (see
7.5.1 (2) (d) Operation of TPnCCR1 register).
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Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2)
(c) TMPn I/O control register 0 (TPnIOC0)
0
0
0
0
0/1
TPnIOC0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
0/1
0/1
0/1
TPnOE1
TPnOL0
TPnOE0
TPnOL1
(d) TMPn counter read buffer register (TPnCNT)
By reading the TPnCNT register, the count value of the 16-bit counter can be read.
(e) TMPn capture/compare register 0 (TPnCCR0)
If the TPnCCR0 register is set to D
0
, the interval is as follows.
Interval = (D
0
+ 1)
Count clock cycle
(f) TMPn capture/compare register 1 (TPnCCR1)
Usually, the TPnCCR1 register is not used in the interval timer mode. However, the set value of the
TPnCCR1 register is transferred to the CCR1 buffer register. A compare match interrupt request signal
(INTTPnCC1) is generated when the count value of the 16-bit counter matches the value of the CCR1
buffer register.
Therefore, mask the interrupt request by using the corresponding interrupt mask flag (TPnCCMK1).
Remarks 1. TMPn I/O control register 1 (TPnIOC1), TMPn I/O control register 2 (TPnIOC2), and TMPn
option register 0 (TPnOPT0) are not used in the interval timer mode.
2. n = 0 to 3
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(1) Interval timer mode operation flow
Figure 7-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
D
0
D
0
D
0
D
0
<1>
<2>
TPnCE bit = 1
TPnCE bit = 0
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnCCR0 register
Initial setting of these registers is performed
before setting the TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits can be
set at the same time when counting has
been started (TPnCE bit = 1).
The counter is initialized and counting is
stopped by clearing the TPnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0 to 3
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(2) Interval timer mode operation timing
(a) Operation if TPnCCR0 register is set to 0000H
If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock
subsequent to the first count clock, and the output of the TOPn0 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
0000H
Interval time
Count clock cycle
Interval time
Count clock cycle
FFFFH
0000H
0000H
0000H
0000H
Remark n = 0 to 3
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(b) Operation if TPnCCR0 register is set to FFFFH
If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the
output of the TOPn0 pin is inverted. At this time, an overflow interrupt request signal (INTTPnOV) is not
generated, nor is the overflow flag (TPnOPT0.TPnOVF bit) set to 1.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
FFFFH
Interval time
10000H
count clock cycle
Interval time
10000H
count clock cycle
Interval time
10000H
count clock cycle
Remark n = 0 to 3
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(c) Notes on rewriting TPnCCR0 register
To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TPnOL0 bit
TOPn0 pin output
INTTPnCC0 signal
D
1
D
2
D
1
D
1
D
2
D
2
D
2
L
Interval time (1)
Interval time (NG)
Interval
time (2)
Remarks 1. Interval time (1): (D
1
+ 1)
Count clock cycle
Interval time (NG): (10000H + D
2
+ 1)
Count clock cycle
Interval time (2): (D
2
+ 1)
Count clock cycle
2. n = 0 to 3
If the value of the TPnCCR0 register is changed from D
1
to D
2
while the count value is greater than D
2
but
less than D
1
, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register
has been rewritten. Consequently, the value of the 16-bit counter that is compared is D
2
.
Because the count value has already exceeded D
2
, however, the 16-bit counter counts up to FFFFH,
overflows, and then counts up again from 0000H. When the count value matches D
2
, the INTTPnCC0
signal is generated and the output of the TOPn0 pin is inverted.
Therefore, the INTTPnCC0 signal may not be generated at the interval time "(D
1
+ 1)
Count clock cycle"
or "(D
2
+ 1)
Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D
2
+ 1)
Count clock period".
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(d) Operation of TPnCCR1 register
Figure 7-6. Configuration of TPnCCR1 Register
CCR0 buffer register
TPnCCR0 register
TPnCCR1 register
CCR1 buffer register
TOPn0 pin
INTTPnCC0 signal
TOPn1 pin
INTTPnCC1 signal
16-bit counter
Output
controller
TPnCE bit
Count clock
selection
Clear
Match signal
Output
controller
Match signal
Remark n = 0 to 3
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If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the
INTTPnCC1 signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted.
The TOPn1 pin outputs a square wave with the same cycle as that output by the TOPn0 pin.
Figure 7-7. Timing Chart When D
01
D
11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D
01
D
11
D
01
D
11
D
11
D
11
D
11
D
01
D
01
D
01
Remark n = 0 to 3
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If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count
value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the
INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed.
Figure 7-8. Timing Chart When D
01
< D
11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
TOPn0 pin output
INTTPnCC0 signal
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D
01
D
11
D
01
D
01
D
01
D
01
L
Remark n = 0 to 3
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7.5.2
External event count mode (TPnMD2 to TPnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified
number of edges have been counted. The TOPn0 pin cannot be used.
Usually, the TPnCCR1 register is not used in the external event count mode.
Figure 7-9. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer register
TPnCE bit
TPnCCR0 register
Edge
detector
Clear
Match signal
INTTPnCC0 signal
TIPn0 pin
(external event
count input)
Remark n = 0 to 3
Figure 7-10. Basic Timing in External Event Count Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
D
0
D
0
D
0
D
0
16-bit counter
TPnCCR0 register
INTTPnCC0 signal
External event
count input
(TIPn0 pin input)
D
0
External
event
count
interval
(D
0
+ 1)
D
0
- 1
D
0
0000
0001
External
event
count
interval
(D
0
+ 1)
External
event
count
interval
(D
0
+ 1)
Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of
the external event count input.
2. n = 0 to 3
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When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0
register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
cleared to 0000H, and a compare match interrupt request signal (INTTPnCC0) is generated.
The INTTPnCC0 signal is generated each time the valid edge of the external event count input has been detected
(set value of TPnCCR0 register + 1) times.
Figure 7-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
0: Stop counting
1: Enable counting
0
0
0
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
(b) TMPn control register 1 (TPnCTL1)
0
0
0
0
0
TPnCTL1
0, 0, 1:
External event count mode
0
0
1
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
TPnSYE
(c) TMPn I/O control register 0 (TPnIOC0)
0
0
0
0
0
TPnIOC0
0: Disable TOPn0 pin output
0: Disable TOPn1 pin output
0
0
0
TPnOE1
TPnOL0
TPnOE0
TPnOL1
(d) TMPn I/O control register 2 (TPnIOC2)
0
0
0
0
0/1
TPnIOC2
Select valid edge
of external event
count input
0/1
0
0
TPnEES0 TPnETS1 TPnETS0
TPnEES1
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Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2)
(e) TMPn counter read buffer register (TPnCNT)
The count value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare register 0 (TPnCCR0)
If D
0
is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request
signal (INTTPnCC0) is generated when the number of external event counts reaches (D
0
+ 1).
(g) TMPn capture/compare register 1 (TPnCCR1)
Usually, the TPnCCR1 register is not used in the external event count mode. However, the set value of
the TPnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit
counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTPnCC1) is generated.
Therefore, mask the interrupt signal by using the interrupt mask flag (TPnCCMK1).
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not
used in the external event count mode.
2. n = 0 to 3
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(1) External event count mode operation flow
Figure 7-12. Flow of Software Processing in External Event Count Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
D
0
D
0
D
0
D
0
<1>
<2>
TPnCE bit = 1
TPnCE bit = 0
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR0 register,
Initial setting of these registers
is performed before setting the
TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits can
be set at the same time when counting
has been started (TPnCE bit = 1).
The counter is initialized and counting
is stopped by clearing the TPnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0 to 3
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(2) Operation timing in external event count mode
Cautions 1. In the external event count mode, do not set the TPnCCR0 register to 0000H.
2. In the external event count mode, use of the timer output is disabled. If performing timer
output using external event count input, set the interval timer mode, and select the
operation enabled by the external event count input for the count clock
(TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 bits = 000, TPnCTL1.TPnEEE bit = 1).
(a) Operation if TPnCCR0 register is set to FFFFH
If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of
the external event count signal has been detected. The 16-bit counter is cleared to 0000H in
synchronization with the next count-up timing, and the INTTPnCC0 signal is generated. At this time, the
TPnOPT0.TPnOVF bit is not set.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
FFFFH
External event
count signal
interval
External event
count signal
interval
External event
count signal
interval
Remark n = 0 to 3
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(b) Notes on rewriting the TPnCCR0 register
To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
D
1
D
2
D
1
D
1
D
2
D
2
D
2
External event
count signal
interval (1)
(D
1
+ 1)
External event count signal
interval (NG)
(10000H + D
2
+ 1)
External event
count signal
interval (2)
(D
2
+ 1)
Remark n = 0 to 3
If the value of the TPnCCR0 register is changed from D
1
to D
2
while the count value is greater than D
2
but
less than D
1
, the count value is transferred to the CCR0 buffer register as soon as the TPnCCR0 register
has been rewritten. Consequently, the value that is compared with the 16-bit counter is D
2
.
Because the count value has already exceeded D
2
, however, the 16-bit counter counts up to FFFFH,
overflows, and then counts up again from 0000H. When the count value matches D
2
, the INTTPnCC0
signal is generated.
Therefore, the INTTPnCC0 signal may not be generated at the valid edge count of "(D
1
+ 1) times" or "(D
2
+ 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D
2
+ 1) times".
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(c) Operation of TPnCCR1 register
Figure 7-13. Configuration of TPnCCR1 Register
CCR0 buffer register
TPnCE bit
TPnCCR0 register
16-bit counter
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
INTTPnCC1 signal
Edge
detector
TIPn0 pin
Remark n = 0 to 3
If the set value of the TPnCCR1 register is smaller than the set value of the TPnCCR0 register, the
INTTPnCC1 signal is generated once per cycle.
Figure 7-14. Timing Chart When D
01
D
11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
D
01
D
11
D
01
D
11
D
11
D
11
D
11
D
01
D
01
D
01
Remark n = 0 to 3
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If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the
INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the
TPnCCR1 register do not match.
Figure 7-15. Timing Chart When D
01
< D
11
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
D
01
D
11
D
01
D
01
D
01
D
01
L
Remark n = 0 to 3
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7.5.3
External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)
In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the
TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event
counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a
software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the
TOPn0 pin.
Figure 7-16. Configuration in External Trigger Pulse Output Mode
CCR0 buffer register
TPnCE bit
TPnCCR0 register
16-bit counter
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
Output
controller
(RS-FF)
Output
controller
TOPn1 pin
INTTPnCC1 signal
TOPn0 pin
Count
clock
selection
Count
start
control
Edge
detector
Software trigger
generation
TIPn0 pin
Transfer
Transfer
S
R
Remark n = 0 to 3
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Figure 7-17. Basic Timing in External Trigger Pulse Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D
1
D
0
D
0
D
1
D
1
D
1
D
1
D
0
D
0
D
0
Wait
for
trigger
Active level
width (D
1
)
Cycle (D
0
+ 1)
Cycle (D
0
+ 1)
Cycle (D
0
+ 1)
Active level
width (D
1
)
Active level
width (D
1
)
16-bit timer/event counter P waits for a trigger when the TPnCE bit is set to 1. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOPn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOPn0 pin is inverted. The TOPn1 pin outputs a high level regardless of the status
(high/low) when a trigger occurs.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TPnCCR1 register)
Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1)
Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
The compare match request signal INTTPnCC0 is generated when the 16-bit counter counts next time after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches the value
of the CCR1 buffer register.
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-
bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used
as the trigger.
Remark n = 0 to 3, m = 0, 1
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Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
Select count clock
Note 1
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
(b) TMPn control register 1 (TPnCTL1)
0
0/1
0/1
0
0
TPnCTL1
0: Operate on count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count with external
event input signal
Generate software trigger
when 1 is written
0
1
0
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
0, 1, 0:
External trigger pulse
output mode
(c) TMPn I/O control register 0 (TPnIOC0)
0
0
0
0
0/1
TPnIOC0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Settings of output level while
operation of TOPn0 pin is disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Specifies active level of TOPn1
pin output
0: Active-high
1: Active-low
0/1
0/1
0/1
Note 2
TPnOE1
TPnOL0
TPnOE0
TPnOL1
TOPn1 pin output
16-bit counter
When TPnOL1 bit = 0
TOPn1 pin output
16-bit counter
When TPnOL1 bit = 1
Notes 1. The setting is invalid when the TPnCTL1.TPnEEE bit = 1.
2. Clear this bit to 0 when the TOPn0 pin is not used in the external trigger pulse output mode.
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Figure 7-18. Setting of Registers in External Trigger Pulse Output Mode (2/2)
(d) TMPn I/O control register 2 (TPnIOC2)
0
0
0
0
0/1
TPnIOC2
Select valid edge of
external trigger input
Select valid edge of
external event count input
0/1
0/1
0/1
TPnEES0 TPnETS1 TPnETS0
TPnEES1
(e) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
If D
0
is set to the TPnCCR0 register and D
1
to the TPnCCR1 register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D
0
+ 1)
Count clock cycle
Active level width = D
1
Count clock cycle
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not
used in the external trigger pulse output mode.
2. n = 0 to 3
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(1) Operation flow in external trigger pulse output mode
Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
CCR0 buffer register
INTTPnCC0 signal
TPnCCR1 register
CCR1 buffer register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D
10
D
00
D
00
D
01
D
00
D
00
D
10
D
10
D
11
D
10
D
10
D
10
D
11
D
10
D
01
D
00
D
10
D
10
D
00
D
10
D
00
D
11
D
11
D
01
D
01
D
01
<1>
<2>
<3>
<4>
<5>
Remark n = 0 to 3
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Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
TPnCE bit = 1
Setting of TPnCCR0 register
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR0 register,
TPnCCR1 register
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting is
enabled (TPnCE bit = 1).
Trigger wait status
TPnCCR1 register write
processing is necessary
only when the set
cycle is changed.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
START
Setting of TPnCCR1 register
<1> Count operation start flow
<2> TPnCCR0 and TPnCCR1 register
setting change flow
Setting of TPnCCR0 register
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to
the CCRm buffer register.
Setting of TPnCCR1 register
<4> TPnCCR0, TPnCCR1 register
setting change flow
Only writing of the TPnCCR1
register must be performed when
the set duty factor is changed.
When the counter is cleared after
setting, the value of the
TPnCCRm register is transferred
to the CCRm buffer register.
Setting of TPnCCR1 register
<3> TPnCCR0, TPnCCR1 register
setting change flow
TPnCE bit = 0
Counting is stopped.
STOP
<5> Count operation stop flow
Remark n = 0 to 3
m = 0, 1
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(2) External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TPnCCR1 register last.
Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
CCR0 buffer register
INTTPnCC0 signal
TPnCCR1 register
CCR1 buffer register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D
10
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
11
D
01
D
10
D
10
D
00
D
00
D
11
D
11
D
01
D
01
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In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register
must be written.
To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the
TPnCCR0 register and then set the active level width to the TPnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write
the same value to the TPnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TPnCCR1 register has
to be set.
After data is written to the TPnCCR1 register, the value written to the TPnCCRm register is transferred to
the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value
compared with the 16-bit counter.
To write the TPnCCR0 or TPnCCR1 register again after writing the TPnCCR1 register once, do so after the
INTTPnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined
because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts
with writing the TPnCCRm register.
Remark n = 0 to 3
m = 0, 1
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is
FFFFH, the INTTPnCC1 signal is generated periodically.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D
0
0000H
D
0
0000H
D
0
0000H
D
0
- 1
D
0
0000
FFFF
0000
D
0
- 1
D
0
0000
0001
Remark n = 0 to 3
To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register.
If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D
0
D
0
+ 1
D
0
D
0
+ 1
D
0
D
0
+ 1
D
0
- 1
D
0
0000
FFFF
0000
D
0
- 1
D
0
0000
0001
Remark n = 0 to 3
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(c) Conflict between trigger detection and match with TPnCCR1 register
If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is
immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D
1
D
1
- 1
0000
FFFF
0000
Shortened
Remark n = 0 to 3
If the trigger is detected immediately before the INTTPnCC1 signal is generated, the INTTPnCC1 signal is
not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the
TOPn1 pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D
1
D
1
- 2
D
1
- 1
D
1
0000
FFFF
0000
0001
Extended
Remark n = 0 to 3
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(d) Conflict between trigger detection and match with TPnCCR0 register
If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is
cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by
time from generation of the INTTPnCC0 signal to trigger detection.
16-bit counter
TPnCCR0 register
INTTPnCC0 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D
0
D
0
- 1
D
0
0000
FFFF
0000
0000
Extended
Remark n = 0 to 3
If the trigger is detected immediately before the INTTPnCC0 signal is generated, the INTTPnCC0 signal is
not generated. The 16-bit counter is cleared to 0000H, the TOPn1 pin is asserted, and the counter
continues counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
TPnCCR0 register
INTTPnCC0 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
D
0
D
0
- 1
D
0
0000
FFFF
0000
0001
Shortened
Remark n = 0 to 3
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(e) Generation timing of compare match interrupt request signal (INTTPnCC1)
The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from
the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the
16-bit counter matches the value of the TPnCCR1 register.
Count clock
16-bit counter
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D
1
D
1
- 2
D
1
- 1
D
1
D
1
+ 1
D
1
+ 2
Remark n = 0 to 3
Usually, the INTTPnCC1 signal is generated in synchronization with the next count up, after the count
value of the 16-bit counter matches the value of the TPnCCR1 register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the
timing is changed to match the timing of changing the output signal of the TOPn1 pin.
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7.5.4
One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011)
In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is
set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and
outputs a one-shot pulse from the TOPn1 pin.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software
trigger is used, the TOPn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when
the counter is stopped (waiting for a trigger).
Figure 7-20. Configuration in One-Shot Pulse Output Mode
CCR0 buffer register
TPnCE bit
TPnCCR0 register
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
Output
controller
(RS-FF)
TOPn1 pin
INTTPnCC1 signal
TOPn0 pin
Count clock
selection
Count start
control
Edge
detector
Software trigger
generation
TIPn0 pin
Transfer
Transfer
S
R
Output
controller
(RS-FF)
S
R
16-bit counter
Remark n = 0 to 3
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Figure 7-21. Basic Timing in One-Shot Pulse Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D
1
D
0
D
0
D
1
D
1
D
1
D
0
D
0
Delay
(D
1
)
Delay
(D
1
)
Delay
(D
1
)
Active
level width
(D
0
- D
1
+ 1)
Active
level width
(D
0
- D
1
+ 1)
Active
level width
(D
0
- D
1
+ 1)
When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOPn1 pin.
After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a
trigger is generated again while the one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TPnCCR1 register)
Count clock cycle
Active level width = (Set value of TPnCCR0 register
- Set value of TPnCCR1 register + 1) Count clock cycle
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPnCC1
is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
The valid edge of an external trigger input or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the
trigger.
Remark n = 0 to 3
m = 0, 1
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Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
Select count clock
Note 1
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
(b) TMPn control register 1 (TPnCTL1)
0
0/1
0/1
0
0
TPnCTL1
0: Operate on count clock
selected by TPnCKS0 to
TPnCKS2 bits
1: Count external event
input signal
Generate software trigger
when 1 is written
0
1
1
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
TPnSYE
0, 1, 1:
One-shot pulse output mode
(c) TMPn I/O control register 0 (TPnIOC0)
0
0
0
0
0/1
TPnIOC0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level while
operation of TOPn0 pin is disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Specifies active level of
TOPn1 pin output
0: Active-high
1: Active-low
0/1
0/1
Note 2
0/1
Note 2
TPnOE1
TPnOL0
TPnOE0
TPnOL1
TOPn1 pin output
16-bit counter
When TPnOL1 bit = 0
TOPn1 pin output
16-bit counter
When TPnOL1 bit = 1
Notes 1. The setting is invalid when the TPnCTL1.TPnEEE bit = 1.
2. Clear this bit to 0 when the TOPn0 pin is not used in the one-shot pulse output mode.
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Figure 7-22. Setting of Registers in One-Shot Pulse Output Mode (2/2)
(d) TMPn I/O control register 2 (TPnIOC2)
0
0
0
0
0/1
TPnIOC2
Select valid edge of
external trigger input
Select valid edge of
external event count input
0/1
0/1
0/1
TPnEES0 TPnETS1 TPnETS0
TPnEES1
(e) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
If D
0
is set to the TPnCCR0 register and D
1
to the TPnCCR1 register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D
1
- D
0
+ 1)
Count clock cycle
Output delay period = (D
1
)
Count clock cycle
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not
used in the one-shot pulse output mode.
2.
n = 0 to 3
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(1) Operation flow in one-shot pulse output mode
Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
<1>
<3>
TPnCE bit = 1
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR0 register,
TPnCCR1 register
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting has been
started (TPnCE bit = 1).
Trigger wait status
START
<1> Count operation start flow
TPnCE bit = 0
Count operation is
stopped
STOP
<3> Count operation stop flow
D
10
D
00
D
11
D
01
D
00
D
10
D
11
<2>
D
01
Setting of TPnCCR0, TPnCCR1
registers
As rewriting the
TPnCCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTPnCCR0 signal
is recommended.
<2> TPnCCR0, TPnCCR1 register setting change flow
Remark n = 0 to 3
m = 0, 1
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(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TPnCCRm register
To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TPnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
External trigger input
(TIPn0 pin input)
TOPn0 pin output
(only when software
trigger is used)
D
10
D
11
D
00
D
01
D
00
D
10
D
10
D
10
D
01
D
11
D
00
D
00
Delay
(D
10
)
Delay
(D
10
)
Active level width
(D
00
- D
10
+ 1)
Active level width
(D
00
- D
10
+ 1)
Delay
(10000H + D
11
)
Active level width
(D
01
- D
11
+ 1)
When the TPnCCR0 register is rewritten from D
00
to D
01
and the TPnCCR1 register from D
10
to D
11
where
D
00
> D
01
and D
10
> D
11
, if the TPnCCR1 register is rewritten when the count value of the 16-bit counter is
greater than D
11
and less than D
10
and if the TPnCCR0 register is rewritten when the count value is greater
than D
01
and less than D
00
, each set value is reflected as soon as the register has been rewritten and
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
11
, the counter generates the INTTPnCC1 signal and asserts the TOPn1
pin. When the count value matches D
01
, the counter generates the INTTPnCC0 signal, deasserts the
TOPn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark n = 0 to 3
m = 0, 1
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(b) Generation timing of compare match interrupt request signal (INTTPnCC1)
The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other
INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter
matches the value of the TPnCCR1 register.
Count clock
16-bit counter
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D
1
D
1
- 2
D
1
- 1
D
1
D
1
+ 1
D
1
+ 2
Remark n = 0 to 3
Usually, the INTTPnCC1 signal is generated when the 16-bit counter counts up next time after its count
value matches the value of the TPnCCR1 register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOPn1 pin.
Remark n = 0 to 3
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7.5.5
PWM output mode (TPnMD2 to TPnMD0 bits = 100)
In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1.
In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOPn0 pin.
Figure 7-24. Configuration in PWM Output Mode
CCR0 buffer register
TPnCE bit
TPnCCR0 register
16-bit counter
TPnCCR1 register
CCR1 buffer register
Clear
Match signal
Match signal
INTTPnCC0 signal
Output
controller
(RS-FF)
Output
controller
TOPn1 pin
INTTPnCC1 signal
TOPn0 pin
Count
clock
selection
Count
start
control
Transfer
Transfer
S
R
Remark n = 0 to 3
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Figure 7-25. Basic Timing in PWM Output Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
CCR0 buffer register
INTTPnCC0 signal
TOPn0 pin output
TPnCCR1 register
CCR1 buffer register
INTTPnCC1 signal
TOPn1 pin output
D
10
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
11
D
01
D
10
D
10
D
00
D
00
D
11
D
11
D
01
D
01
Active period
(D
10
)
Cycle
(D
00
+ 1)
Inactive period
(D
00
- D
10
+ 1)
When the TPnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a
PWM waveform from the TOPn1 pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TPnCCR1 register)
Count clock cycle
Cycle = (Set value of TPnCCR0 register + 1)
Count clock cycle
Duty factor = (Set value of TPnCCR1 register)/(Set value of TPnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TPnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts next time
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal INTTPnCC1 is generated when the count value of the 16-bit counter matches
the value of the CCR1 buffer register.
The value set to the TPnCCRm register is transferred to the CCRm buffer register when the count value of the 16-
bit counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
Remark n = 0 to 3, m = 0, 1
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Figure 7-26. Setting of Registers in PWM Output Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
Select count clock
Note 1
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
(b) TMPn control register 1 (TPnCTL1)
0
0
0/1
0
0
TPnCTL1
1
0
0
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
TPnSYE
1, 0, 0:
PWM output mode
0: Operate on count clock
selected by TPnCKS0 to
TPnCKS2 bits
1: Count external event
input signal
(c) TMPn I/O control register 0 (TPnIOC0)
0
0
0
0
0/1
TPnIOC0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level while
operation of TOPn0 pin is disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Specifies active level of TOPn1
pin output
0: Active-high
1: Active-low
0/1
0/1
0/1
Note 2
TPnOE1
TPnOL0
TPnOE0
TPnOL1
TOPn1 pin output
16-bit counter
When TPnOL1 bit = 0
TOPn1 pin output
16-bit counter
When TPnOL1 bit = 1
Notes 1. The setting is invalid when the TPnCTL1.TPnEEE bit = 1.
2. Clear this bit to 0 when the TOPn0 pin is not used in the PWM output mode.
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Figure 7-26. Register Setting in PWM Output Mode (2/2)
(d) TMPn I/O control register 2 (TPnIOC2)
0
0
0
0
0/1
TPnIOC2
Select valid edge
of external event
count input.
0/1
0
0
TPnEES0 TPnETS1 TPnETS0
TPnEES1
(e) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
If D
0
is set to the TPnCCR0 register and D
1
to the TPnCCR1 register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D
0
+ 1)
Count clock cycle
Active level width = D
1
Count clock cycle
Remarks 1. TMPn I/O control register 1 (TPnIOC1) and TMPn option register 0 (TPnOPT0) are not
used in the PWM output mode.
2. n = 0 to 3
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(1) Operation flow in PWM output mode
Figure 7-27. Software Processing Flow in PWM Output Mode (1/2)
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
CCR0 buffer register
INTTPnCC0 signal
TOPn0 pin output
TPnCCR1 register
CCR1 buffer register
INTTPnCC1 signal
TOPn1 pin output
D
10
D
00
D
00
D
01
D
00
D
00
D
10
D
10
D
11
D
10
D
10
D
10
D
11
D
10
D
01
D
00
D
10
D
10
D
00
D
10
D
00
D
11
D
11
D
01
D
01
D
01
<2>
<3>
<4>
<5>
<1>
Remark n = 0 to 3
m = 0, 1
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Figure 7-27. Software Processing Flow in PWM Output Mode (2/2)
TPnCE bit = 1
Setting of TPnCCR0 register
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnCCR0 register,
TPnCCR1 register
Initial setting of these
registers is performed
before setting the
TPnCE bit to 1.
The TPnCKS0 to
TPnCKS2 bits can be
set at the same time
when counting is
enabled (TPnCE bit = 1).
TPnCCR1 write
processing is necessary
only when the set cycle
is changed.
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to the
CCRm buffer register.
START
Setting of TPnCCR1 register
<1> Count operation start flow
<2> TPnCCR0, TPnCCR1 register
setting change flow
Setting of TPnCCR0 register
When the counter is
cleared after setting,
the value of the TPnCCRm
register is transferred to the
CCRm buffer register.
Setting of TPnCCR1 register
<4> TPnCCR0, TPnCCR1 register
setting change flow
Only writing of the TPnCCR1
register must be performed
when the set duty factor is
changed. When the counter is
cleared after setting, the
value of compare register m
is transferred to the CCRm
buffer register.
Setting of TPnCCR1 register
<3> TPnCCR0, TPnCCR1 register
setting change flow
TPnCE bit = 0
Counting is stopped.
STOP
<5> Count operation stop flow
Remark n = 0 to 3
m = 0, 1
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(2) PWM output mode operation timing
(a) Changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TPnCCR1 register last.
Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
CCR0 buffer register
TPnCCR1 register
CCR1 buffer register
TOPn1 pin output
INTTPnCC0 signal
D
10
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
11
D
01
D
10
D
10
D
00
D
00
D
11
D
11
D
01
D
01
To transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be
written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the
TPnCCR0 register and then set the active level to the TPnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TPnCCR0 register, and then write
the same value to the TPnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, only the TPnCCR1 register has
to be set.
After data is written to the TPnCCR1 register, the value written to the TPnCCRm register is transferred to
the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value
compared with the 16-bit counter.
To write the TPnCCR0 or TPnCCR1 register again after writing the TPnCCR1 register once, do so after the
INTTPnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become undefined
because the timing of transferring data from the TPnCCRm register to the CCRm buffer register conflicts
with writing the TPnCCRm register.
Remark n = 0 to 3, m = 0, 1
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is
FFFFH, the INTTPnCC1 signal is generated periodically.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D
00
0000H
D
00
0000H
D
00
0000H
D
00
- 1
D
00
0000
FFFF
0000
D
00
- 1
D
00
0000
0001
Remark n = 0 to 3
To output a 100% waveform, set a value of (set value of TPnCCR0 register + 1) to the TPnCCR1 register.
If the set value of the TPnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TPnCE bit
TPnCCR0 register
TPnCCR1 register
INTTPnCC0 signal
INTTPnCC1 signal
TOPn1 pin output
D
00
D
00
+ 1
D
00
D
00
+ 1
D
00
D
00
+ 1
D
00
- 1
D
00
0000
FFFF
0000
D
00
- 1
D
00
0000
0001
Remark n = 0 to 3
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(c) Generation timing of compare match interrupt request signal (INTTPnCC1)
The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other
INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter
matches the value of the TPnCCR1 register.
Count clock
16-bit counter
TPnCCR1 register
TOPn1 pin output
INTTPnCC1 signal
D
1
D
1
- 2
D
1
- 1
D
1
D
1
+ 1
D
1
+ 2
Remark n = 0 to 3
Usually, the INTTPnCC1 signal is generated in synchronization with the next counting up after the count
value of the 16-bit counter matches the value of the TPnCCR1 register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed
to match the change timing of the output signal of the TOPn1 pin.
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7.5.6
Free-running timer mode (TPnMD2 to TPnMD0 bits = 101)
In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to
1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the
setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Figure 7-28. Configuration in Free-Running Timer Mode
TPnCCR0 register
(capture)
TPnCE bit
TPnCCR1 register
(compare)
16-bit counter
TPnCCR1 register
(compare)
TPnCCR0 register
(capture)
Output
controller
TPnCCS0, TPnCCS1 bits
(capture/compare selection)
TOPn0 pin output
Output
controller
TOPn1 pin output
Edge
detector
Count
clock
selection
Edge
detector
Edge
detector
TIPn0 pin
(external event
count input/
capture
trigger input)
TIPn1 pin
(capture
trigger input)
Internal count clock
0
1
0
1
INTTPnOV signal
INTTPnCC1 signal
INTTPnCC0 signal
Remark n = 0 to 3
m = 0, 1
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When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0
and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the
TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the
TOPnm pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
The TPnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
at that time, and compared with the count value.
Figure 7-29. Basic Timing in Free-Running Timer Mode (Compare Function)
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TOPn0 pin output
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
INTTPnOV signal
TPnOVF bit
D
00
D
01
D
10
D
11
D
00
D
10
D
10
D
11
D
11
D
11
D
00
D
01
D
01
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Remark n = 0 to 3
m = 0, 1
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When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is
detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request
signal (INTTPnCCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTPnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
Figure 7-30. Basic Timing in Free-Running Timer Mode (Capture Function)
FFFFH
16-bit counter
0000H
TPnCE bit
TIPn0 pin input
TPnCCR0 register
INTTPnCC0 signal
TIPn1 pin input
TPnCCR1 register
INTTPnCC1 signal
INTTPnOV signal
TPnOVF bit
D
00
D
01
D
02
D
03
D
10
D
00
D
01
D
02
D
03
D
11
D
12
D
13
D
10
D
11
D
12
D
13
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Remark n = 0 to 3
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Figure 7-31. Register Setting in Free-Running Timer Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1
(b) TMPn control register 1 (TPnCTL1)
0
0
0/1
0
0
TPnCTL1
1
0
1
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count on external
event count input signal
(c) TMPn I/O control register 0 (TPnIOC0)
0
0
0
0
0/1
TPnIOC0
0: Disable TOPn0 pin output
1: Enable TOPn0 pin output
Setting of output level with
operation of TOPn0 pin disabled
0: Low level
1: High level
0: Disable TOPn1 pin output
1: Enable TOPn1 pin output
Setting of output level with
operation of TOPn1 pin disabled
0: Low level
1: High level
0/1
0/1
0/1
TPnOE1
TPnOL0
TPnOE0
TPnOL1
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Figure 7-31. Register Setting in Free-Running Timer Mode (2/2)
(d) TMPn I/O control register 1 (TPnIOC1)
0
0
0
0
0/1
TPnIOC1
Select valid edge
of TIPn0 pin input
Select valid edge
of TIPn1 pin input
0/1
0/1
0/1
TPnIS2
TPnIS1
TPnIS0
TPnIS3
(e) TMPn I/O control register 2 (TPnIOC2)
0
0
0
0
0/1
TPnIOC2
Select valid edge of
external event count input
0/1
0
0
TPnEES0 TPnETS1 TPnETS0
TPnEES1
(f) TMPn option register 0 (TPnOPT0)
0
0
0/1
0/1
0
TPnOPT0
Overflow flag
Specifies if TPnCCR0
register functions as
capture or compare register
Specifies if TPnCCR1
register functions as
capture or compare register
0
0
0/1
TPnCCS0
TPnOVF
TPnCCS1
(g) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(h) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
These registers function as capture registers or compare registers depending on the setting of the
TPnOPT0.TPnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIPnm pin is detected.
When the registers function as compare registers and when D
m
is set to the TPnCCRm register, the
INTTPnCCm signal is generated when the counter reaches (D
m
+ 1), and the output signal of the
TOPnm pin is inverted.
Remark n = 0 to 3
m = 0, 1
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(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TOPn0 pin output
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
INTTPnOV signal
TPnOVF bit
D
00
D
01
D
10
D
11
D
00
D
10
D
10
D
11
D
11
D
11
D
00
D
01
D
01
Cleared to 0 by
CLR instruction
Set value changed
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<1>
<2>
<2>
<2>
<3>
Set value changed
Remark n = 0 to 3
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Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
TPnCE bit = 1
Read TPnOPT0 register
(check overflow flag).
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC0 register,
TPnIOC2 register,
TPnOPT0 register,
TPnCCR0 register,
TPnCCR1 register
Initial setting of these registers
is performed before setting the
TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits
can be set at the same time
when counting has been started
(TPnCE bit = 1).
START
Execute instruction to clear
TPnOVF bit (CLR TPnOVF).
<1> Count operation start flow
<2> Overflow flag clear flow
TPnCE bit = 0
Counter is initialized and
counting is stopped by
clearing TPnCE bit to 0.
STOP
<3> Count operation stop flow
TPnOVF bit = 1
NO
YES
Remark n = 0 to 3
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(b) When using capture/compare register as capture register
Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
FFFFH
16-bit counter
0000H
TPnCE bit
TIPn0 pin input
TPnCCR0 register
INTTPnCC0 signal
TIPn1 pin input
TPnCCR1 register
INTTPnCC1 signal
INTTPnOV signal
TPnOVF bit
D
00
0000
0000
D
01
D
02
D
03
D
10
D
00
D
01
D
02
D
03
D
11
D
12
D
10
0000
D
11
D
12
0000
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<3>
<1>
<2>
<2>
Remark n = 0 to 3
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Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
TPnCE bit = 1
Read TPnOPT0 register
(check overflow flag).
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits)
TPnCTL1 register,
TPnIOC1 register,
TPnOPT0 register
Initial setting of these registers
is performed before setting the
TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits can
be set at the same time when counting
has been started (TPnCE bit = 1).
START
Execute instruction to clear
TPnOVF bit (CLR TPnOVF).
<1> Count operation start flow
<2> Overflow flag clear flow
TPnCE bit = 0
Counter is initialized and
counting is stopped by
clearing TPnCE bit to 0.
STOP
<3> Count operation stop flow
TPnOVF bit = 1
NO
YES
Remark n = 0 to 3
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(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTPnCCm signal has been detected.
FFFFH
16-bit counter
0000H
TPnCE bit
TPnCCR0 register
INTTPnCC0 signal
TOPn pin output
TPnCCR1 register
INTTPnCC1 signal
TOPn1 pin output
D
00
D
01
D
02
D
03
D
04
D
05
D
10
D
00
D
11
D
01
D
12
D
04
D
13
D
02
D
03
D
11
D
10
D
12
D
13
D
14
Interval period
(D
10
+ 1)
Interval period
(10000H +
D
11
- D
10
)
Interval period
(10000H +
D
12
- D
11
)
Interval period
(10000H +
D
13
- D
12
)
Interval period
(D
00
+ 1)
Interval period
(10000H +
D
01
- D
00
)
Interval period
(D
02
- D
01
)
Interval period
(10000H +
D
03
- D
02
)
Interval period
(10000H +
D
04
- D
03
)
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TPnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTPnCCm signal is detected.
The set value for re-setting the TPnCCRm register can be calculated by the following expression, where
"D
m
" is the interval period.
Compare register default value: D
m
- 1
Value set to compare register second and subsequent time: Previous set value + D
m
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark n = 0 to 3
m = 0, 1
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305
(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TPnCCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTPnCCm signal has
been detected and for calculating an interval.
FFFFH
16-bit counter
0000H
TPnCE bit
TIPn0 pin input
TPnCCR0 register
INTTPnCC0 signal
TIPn1 pin input
TPnCCR1 register
INTTPnCC1 signal
INTTPnOV signal
TPnOVF bit
0000H
D
00
D
01
D
02
D
03
D
04
D
10
D
00
D
11
D
01
D
12
D
04
D
13
D
02
D
03
D
10
0000H
D
11
D
12
D
13
Pulse interval
(D
00
)
Pulse interval
(10000H +
D
01
- D
00
)
Pulse interval
(D
02
- D
01
)
Pulse interval
(10000H +
D
03
- D
02
)
Pulse interval
(10000H +
D
04
- D
03
)
Pulse interval
(D
10
)
Pulse interval
(10000H +
D
11
- D
10
)
Pulse interval
(10000H +
D
12
- D
11
)
Pulse interval
(10000H +
D
13
- D
12
)
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
When executing pulse width measurement in the free-running timer mode, two pulse widths can be
measured with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TPnCCRm
register in synchronization with the INTTPnCCm signal, and calculating the difference between the read
value and the previously read value.
Remark n = 0 to 3
m = 0, 1
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(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an
example of incorrect processing is shown below.
Example of incorrect processing when two capture registers are used
FFFFH
16-bit counter
0000H
TPnCE bit
TIPn0 pin input
TPnCCR0 register
TIPn1 pin input
TPnCCR1 register
INTTPnOV signal
TPnOVF bit
D
00
D
01
D
10
D
11
D
10
<1>
<2>
<3>
<4>
D
00
D
11
D
01
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input).
<2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input).
<3> Read the TPnCCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
01
- D
00
).
<4> Read the TPnCCR1 register.
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
11
- D
10
) (incorrect).
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the
other capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
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(1/2)
Example when two capture registers are used (using overflow interrupt)
FFFFH
16-bit counter
0000H
TPnCE bit
INTTPnOV signal
TPnOVF bit
TPnOVF0 flag
Note
TIPn0 pin input
TPnCCR0 register
TPnOVF1 flag
Note
TIPn1 pin input
TPnCCR1 register
D
10
D
11
D
00
D
01
D
10
<1>
<2>
<5> <6>
<3>
<4>
D
00
D
11
D
01
Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
<1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input).
<2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input).
<3> An overflow occurs. Set the TPnOVF0 and TPnOVF1 flags to 1 in the overflow interrupt servicing,
and clear the overflow flag to 0.
<4> Read the TPnCCR0 register.
Read the TPnOVF0 flag. If the TPnOVF0 flag is 1, clear it to 0.
Because the TPnOVF0 flag is 1, the pulse width can be calculated by (10000H + D
01
- D
00
).
<5> Read the TPnCCR1 register.
Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0 (the TPnOVF0 flag is cleared in
<4>, and the TPnOVF1 flag remains 1).
Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D
11
- D
10
)
(correct).
<6> Same as <3>
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(2/2)
Example when two capture registers are used (without using overflow interrupt)
FFFFH
16-bit counter
0000H
TPnCE bit
INTTPnOV signal
TPnOVF bit
TPnOVF0 flag
Note
TIPn0 pin input
TPnCCR0 register
TPnOVF1 flag
Note
TIPn1 pin input
TPnCCR1 register
D
10
D
11
D
00
D
01
D
10
<1>
<2>
<5> <6>
<3>
<4>
D
00
D
11
D
01
Note The TPnOVF0 and TPnOVF1 flags are set on the internal RAM by software.
<1> Read the TPnCCR0 register (setting of the default value of the TIPn0 pin input).
<2> Read the TPnCCR1 register (setting of the default value of the TIPn1 pin input).
<3> An overflow occurs. Nothing is done by software.
<4> Read the TPnCCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TPnOVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
01
- D
00
).
<5> Read the TPnCCR1 register.
Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read.
Read the TPnOVF1 flag. If the TPnOVF1 flag is 1, clear it to 0.
Because the TPnOVF1 flag is 1, the pulse width can be calculated by (10000H + D
11
- D
10
)
(correct).
<6> Same as <3>
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(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an
overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect
processing is shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH
16-bit counter
0000H
TPnCE bit
TIPnm pin input
TPnCCRm register
INTTPnOV signal
TPnOVF bit
D
m0
D
m1
D
m0
D
m1
<1> <2>
<3> <4>
1 cycle of 16-bit counter
Pulse width
The following problem may occur when long pulse width is measured in the free-running timer mode.
<1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TPnCCRm register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
m1
- D
m0
)
(incorrect).
Actually, the pulse width must be (20000H + D
m1
- D
m0
) because an overflow occurs twice.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may
not be obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or
use software. An example of how to use software is shown next.
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Example when capture trigger interval is long
FFFFH
16-bit counter
0000H
TPnCE bit
TIPnm pin input
TPnCCRm register
INTTPnOV signal
TPnOVF bit
Overflow
counter
Note
D
m0
D
m1
1H
0H
2H
0H
D
m0
D
m1
<1> <2>
<3> <4>
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TPnCCRm register (setting of the default value of the TIPnm pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
interrupt servicing.
<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag
to 0 in the overflow interrupt servicing.
<4> Read the TPnCCRm register.
Read the overflow counter.
When the overflow counter is "N", the pulse width can be calculated by (N 10000H + D
m1
D
m0
).
In this example, the pulse width is (20000H + D
m1
D
m0
) because an overflow occurs twice.
Clear the overflow counter (0H).
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(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF
bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
(iii) Operation to clear to 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TPnOVF bit)
Read
Write
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TPnOVF bit)
Read
Write
0 write signal
Overflow
set signal
0 write signal
Overflow
set signal
Overflow flag
(TPnOVF bit)
Overflow flag
(TPnOVF bit)
L
H
L
Remark n = 0 to 3
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear
instruction.
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7.5.7
Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110)
In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit
is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is
stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TPnCCRm register after a capture interrupt request
signal (INTTPnCCm) occurs.
Select either the TIPn0 or TIPn1 pin as the capture trigger input pin. Specify "No edge detected" by using the
TPnIOC1 register for the unused pins.
When an external clock is used as the count clock, measure the pulse width of the TIPn1 pin because the external
clock is fixed to the TIPn0 pin. At this time, clear the TPnIOC1.TPnIS1 and TPnIOC1.TPnIS0 bits to 00 (capture
trigger input (TIPn0 pin): No edge detected).
Figure 7-34. Configuration in Pulse Width Measurement Mode
TPnCCR0 register
(capture)
TPnCE bit
TPnCCR1 register
(capture)
Edge
detector
Count
clock
selection
Edge
detector
Edge
detector
TIPn0 pin
(external
event count
input/capture
trigger input)
TIPn1 pin
(capture
trigger input)
Internal count clock
Clear
INTTPnOV
signal
INTTPnCC0
signal
INTTPnCC1
signal
16-bit counter
Remark n = 0 to 3
m = 0, 1
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Figure 7-35. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TPnCE bit
TIPnm pin input
TPnCCRm register
INTTPnCCm signal
INTTPnOV signal
TPnOVF bit
D
0
0000H
D
1
D
2
D
3
Cleared to 0 by
CLR instruction
Remark n = 0 to 3
m = 0, 1
When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is
later detected, the count value of the 16-bit counter is stored in the TPnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTPnCCm) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value
Count clock cycle
If the valid edge is not input to the TIPnm pin even when the 16-bit counter counted up to FFFFH, an overflow
interrupt request signal (INTTPnOV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TPnOPT0.TPnOVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H
TPnOVF bit set (1) count + Captured value) Count clock cycle
Remark n = 0 to 3
m = 0, 1
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Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2)
(a) TMPn control register 0 (TPnCTL0)
0/1
0
0
0
0
TPnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TPnCKS2 TPnCKS1 TPnCKS0
TPnCE
Note Setting is invalid when the TPnEEE bit = 1.
(b) TMPn control register 1 (TPnCTL1)
0
0
0/1
0
0
TPnCTL1
1
1
0
TPnMD2 TPnMD1 TPnMD0
TPnEEE
TPnEST
TPnSYE
1, 1, 0:
Pulse width measurement mode
0: Operate with count
clock selected by
TPnCKS0 to TPnCKS2 bits
1: Count external event
count input signal
(c) TMPn I/O control register 1 (TPnIOC1)
0
0
0
0
0/1
TPnIOC1
Select valid edge
of TIPn0 pin input
Select valid edge
of TIPn1 pin input
0/1
0/1
0/1
TPnIS2
TPnIS1
TPnIS0
TPnIS3
(d) TMPn I/O control register 2 (TPnIOC2)
0
0
0
0
0/1
TPnIOC2
Select valid edge of
external event count input
0/1
0
0
TPnEES0 TPnETS1 TPnETS0
TPnEES1
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Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2)
(e) TMPn option register 0 (TPnOPT0)
0
0
0
0
0
TPnOPT0
Overflow flag
0
0
0/1
TPnCCS0
TPnOVF
TPnCCS1
(f) TMPn counter read buffer register (TPnCNT)
The value of the 16-bit counter can be read by reading the TPnCNT register.
(g) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1)
These registers store the count value of the 16-bit counter when the valid edge input to the TIPnm pin
is detected.
Remarks 1. TMPn I/O control register 0 (TPnIOC0) is not used in the pulse width measurement mode.
2. n = 0 to 3
m = 0, 1
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(1) Operation flow in pulse width measurement mode
Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode
<1>
<2>
Set TPnCTL0 register
(TPnCE bit = 1)
TPnCE bit = 0
Register initial setting
TPnCTL0 register
(TPnCKS0 to TPnCKS2 bits),
TPnCTL1 register,
TPnIOC1 register,
TPnIOC2 register,
TPnOPT0 register
Initial setting of these registers
is performed before setting the
TPnCE bit to 1.
The TPnCKS0 to TPnCKS2 bits can
be set at the same time when counting
has been started (TPnCE bit = 1).
The counter is initialized and counting
is stopped by clearing the TPnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
FFFFH
16-bit counter
0000H
TPnCE bit
TIPn0 pin input
TPnCCR0 register
INTTPnCC0 signal
D
0
0000H
0000H
D
1
D
2
Remark n = 0 to 3
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(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF
bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
(iii) Operation to clear to 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TPnOVF bit)
Read
Write
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TPnOVF bit)
Read
Write
0 write signal
Overflow
set signal
0 write signal
Overflow
set signal
Overflow flag
(TPnOVF bit)
Overflow flag
(TPnOVF bit)
L
H
L
Remark n = 0 to 3
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear
instruction.
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7.5.8 Timer
output
operations
The following table shows the operations and output levels of the TOPn0 and TOPn1 pins.
Table 7-4. Timer Output Control in Each Mode
Operation Mode
TOPn1 Pin
TOPn0 Pin
Interval timer mode
Square wave output
External event count mode
Square wave output
-
External trigger pulse output mode
External trigger pulse output
One-shot pulse output mode
One-shot pulse output
PWM output mode
PWM output
Square wave output
Free-running timer mode
Square wave output (only when compare function is used)
Pulse width measurement mode
-
Remark n = 0 to 3
Table 7-5. Truth Table of TOPn0 and TOPn1 Pins Under Control of Timer Output Control Bits
TPnIOC0.TPnOLm Bit
TPnIOC0.TPnOEm Bit
TPnCTL0.TPnCE Bit
Level of TOPnm Pin
0
Low-level output
0 Low-level
output
0
1
1
Low level immediately before counting, high
level after counting is started
0
High-level output
0 High-level
output
1
1
1
High level immediately before counting, low level
after counting is started
Remark n = 0 to 3
m = 0, 1
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7.6 Timer Tuned Operation Function
Timer P and timer Q have a timer tuned operation function.
The timers that can be synchronized are listed in Table 7-6.
Table 7-6. Tuned Operation Mode of Timers
Master Timer
Slave Timer
TMP0 TMP1
TMP2 TMP3 TMQ0
TMQ1 TMQ2
Cautions 1. The tuned operation mode is enabled or disabled by the TPmCTL1.TPmSYE and
TQnCTL1.TQnSYE bits. For TMP2, either or both TMP3 and TMQ0 can be specified as slaves.
2. Set the tuned operation mode using the following procedure.
<1> Set the TPmCTL1.TPmSYE and TQnCTL1.TQnSYE bits of the slave timer to enable the
tuned operation.
Set the TPmCTL1.TPmMD2 to TPmCTL1.TPmMD0 and TQnCTL1.TPnMD2 to
TQnCTL1.TPnMD0 bits of the slave timer to the free-running mode.
<2> Set the timer mode by using the TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 and
TQnCTL1.TPnMD2 to TQnCTL1.TPnMD0 bits.
At this time, do not set the TPnCTL1.TPnSYE and TQnCTL1.TQnSYE bits of the master
timer.
<3> Set the compare register value of the master and slave timers.
<4> Set the TPmCTL0.TPmCE and TQnCTL0.TQnCE bits of the slave timer to enable
operation on the internal operating clock.
<5> Set the TPnCTL0.TPnCE and TQnCTL0.TQnCE bits of the master timer to enable
operation on the internal operating clock.
Remark m = 1, 3, n = 0, 2
Tables 7-7 and 7-8 show the timer modes that can be used in the tuned operation mode (
: Settable, : Not
settable).
Table 7-7. Timer Modes Usable in Tuned Operation Mode
Master Timer
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
TMP0
TMP2
TMQ1
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Table 7-8. Timer Output Functions
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
Tuned
Channel
Timer Pin
Tuning OFF
Tuning ON
Tuning OFF
Tuning ON
Tuning OFF
Tuning ON
TOP00 PPG
Toggle
N/A
TMP0
(master)
TOP01 PPG
PWM
N/A
TOP10 PGP
Toggle PWM N/A
Ch0
TMP1
(slave)
TOP11 PPG
PWM
N/A
TOP20 PPG
Toggle PWM
N/A
TMP2
(master)
TOP21 PPG
PWM
N/A
TOP30 PPG
Toggle PWM N/A
TMP3
(slave)
TOP31 PPG
PWM
N/A
TOQ00 PPG
Toggle PWM
Toggle N/A
Ch1
TMQ0
(slave)
TOQ01 to TOQ03
PPG
PWM
Triangular
wave PWM
N/A
TOQ10 PPG
Toggle
Toggle
TMQ1
(master)
TOQ11 to TOQ13
PPG
PWM
Triangular
wave PWM
TOQ20 PPG
Toggle PWM Toggle
Triangular
wave PWM
Ch2
TMQ2
(slave)
TOQ21 to TOQ23
PPG
PWM
Triangular
wave PWM
Remark The timing of transmitting data from the compare register of the master timer to the compare register of
the slave timer is as follows.
PPG:
CPU write timing
Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOPn0
and TOQm0 (n = 0 to 3, m = 0 to 2)
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Figure 7-38. Tuned Operation Image (TMP2, TMP3, TMQ0)
TMP2
TMP2 (master) + TMP3 (slave) + TMQ0 (slave)
TOP21 (PWM output)
16-bit timer/counter
Unit operation
Tuned operation
Five PWM outputs are available
when PWM is operated as a single unit.
16-bit capture/compare
16-bit capture/compare
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TMP3
TOP31 (PWM output)
TMQ0
TOQ01 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
TOP21 (PWM output)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOP30 (PWM output)
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOP31 (PWM output)
TOQ01 (PWM output)
TOQ00 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
Seven PWM outputs are available when
PWM is operated in tuned operation mode.
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Figure 7-39. Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0)
TOP20
TOP21
TOP30
TOQ00
TOQ01
TOQ02
TOQ03
TOP31
TP2CCR0
TP2CE
INTTP2CC0
match interrupt
INTTP2CC1
match interrupt
INTTP3CC0
match interrupt
INTTP3CC1
match interrupt
INTTQ0CC0
match interrupt
INTTQ0CC1
match interrupt
INTTQ0CC2
match interrupt
INTTQ0CC3
match interrupt
TP3CE
TQ0CE
FFFFH
0000H
TMP2
16-bit
counter
D
00
D
00
D
70
D
60
D
50
D
40
D
30
D
20
D
10
D
00
D
70
D
60
D
50
D
40
D
30
D
20
D
10
TP2CCR1
D
10
TP3CCR0
D
20
TP3CCR1
D
30
TQ0CCR0
D
40
TQ0CCR1
D
50
TQ0CCR2
D
60
TQ0CCR3
D
70
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7.7 Selector
Function
In the V850ES/HJ2, the alternate-function pins of port and peripheral I/O (TMP, TMM0, or UARTA) can be used to
select the capture trigger input of TMP.
By using this function, the following is possible.
The TIP10 and TIP11 input signals of TMP1 can be selected from the port/timer alternate-function pins (TIP10
and TIP11 pins) and the UARTA reception alternate-function pins (RXDA0 and RXDA1). The TIP31 input signal
of TMP3 can be selected from a port/timer alternate-function pin (TIP31 pin) and the UARTA reception alternate-
function pin (RXDA3).
When the RXDA0, RXDA1, or RXDA3 signal of UARTA0, UARTA1, or UARTA3 is selected, the baud rate error
of the UARTA LIN reception transfer can be calculated.
The TIP01 input signal of TMP0 can be selected from the port/timer alternate-function pin (TIP01 pin) and the
INTTM0EQ0 signal of TMM0.
Cautions 1. When using the selector function, set the capture trigger input of TMP before connecting
the timer.
2. When setting the selector function, first disable the peripheral I/O to be connected (TMP,
TMM0, or UARTA).
The capture input for the selector function is specified by the following register.
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(1) Selector operation control register 0 (SELCNT0)
The SELCNT0 register is an 8-bit register that selects the capture trigger for TMP0, TMP1, and TMP3.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TIP31 pin input
RXDA3 pin input
ISEL06
Note 1
0
1
Selection of TIP31 input signal (TMP3)
SELCNT0
ISEL06
ISEL05
ISEL04
ISEL03
ISEL02
0
0
TIP11 pin input
RXDA1 pin input
ISEL04
0
1
Selection of TIP11 input signal (TMP1)
TIP10 pin input
RXDA0 pin input
ISEL03
0
1
Selection of TIP10 input signal (TMP1)
TIP01 pin input
INTTM0EQ0 interrupt of TMM0
ISEL02
Note 2
0
1
Selection of TIP01 input signal (TMP0)
TIP30 pin input
RXDA2 pin input
ISEL05
0
1
Selection of TIP30 input signal (TMP3)
After reset: 00H R/W Address: FFFFF308H
Notes 1. The
PD70F3709 and 70F3710 do not have the RXDA3 pin. Fix the ISEL06
bit of these products to 0.
2. Use the INTTM0EQ0 interrupt signal as the TIP01 input signal under the
following condition.
TMM operation clock
TMP operation clock 4
Caution To set the ISEL02 to ISEL06 bits to 1, set the corresponding pin in the
capture input mode.
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7.8 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may
be captured in the TPnCCR0 and TPnCCR1 registers if the capture trigger is input immediately after the
TPnCE bit is set to 1.
(a) Free-running timer mode
Count clock
0000H
FFFFH
TPnCE bit
TPnCCR0 register
FFFFH
0001H
0000H
TIPn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX
)
Capture
trigger input
(b) Pulse width measurement mode
0000H
FFFFH
FFFFH
0002H
0000H
Count clock
TPnCE bit
TPnCCR0 register
TIPn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX
)
Capture
trigger input
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CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
Timer Q (TMQ) is a 16-bit timer/event counter.
The V850ES/HJ2 incorporates TMQ0 to TMQ2.
8.1 Overview
An outline of TMQn is shown below.
Clock selection: 8 ways
Capture/trigger input pins: 4
External event count input pins: 1
External trigger input pins: 1
Timer/counters: 1
Capture/compare registers: 4
Capture/compare match interrupt request signals: 4
Timer output pins: 4
Remark n = 0 to 2
8.2 Functions
TMQn has the following functions.
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
Triangular wave PWM output
Timer tuned operation function
Remark n = 0 to 2
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8.3 Configuration
TMQ0 to TMQ2 include the following hardware.
Table 8-1. Configuration of TMQ0 to TMQ2
Item Configuration
Timer register
16-bit counter
Registers
TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
TMQn counter read buffer register (TQnCNT)
CCR0 to CCR3 buffer registers
Timer inputs
4 (TIQn0
Note 1
to TIQn3 pins)
Timer outputs
4 (TOQn0 to TOQn3 pins)
Control registers
Note 2
TMQn control registers 0, 1 (TQnCTL0, TQnCTL1)
TMQn I/O control registers 0 to 2 (TQnIOC0 to TQnIOC2)
TMQn option register 0 (TQnOPT0)
Notes 1. The TIQn0 pin functions alternately as a capture trigger input signal, external event count
input signal, and external trigger input signal.
2. When using the functions of the TIQn0 to TIQn3 and TOQn0 to TOQn3 pins, see Table 4-25
Using Port Pin as Alternate-Function Pin.
Figure 8-1. Block Diagram of TMQ0 to TMQ2
TQnCNT
TQnCCR0
TQnCCR1
TQnCCR2
TOQn0
INTTQnOV
CCR2
buffer
register
TQnCCR3
CCR3
buffer
register
TOQn1
TOQn2
TOQn3
INTTQnCC0
INTTQnCC1
INTTQnCC2
INTTQnCC3
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
TIQn0
TIQn1
TIQn2
TIQn3
Selector
Internal bus
Internal bus
Selector
Edge detector
CCR0
buffer
register
CCR1
buffer
register
16-bit counter
Output
controller
Clear
Remarks 1. f
XX
: Main clock frequency
2.
n = 0 to 2
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(1) 16-bit counter
This 16-bit counter can count internal clocks or external events.
The count value of this counter can be read by using the TQnCNT register.
When the TQnCTL0.TQnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TQnCNT register is read at
this time, 0000H is read.
Reset sets the TQnCE bit to 0. Therefore, the 16-bit counter is set to FFFFH.
(2) CCR0 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR0 register is used as a compare register, the value written to the TQnCCR0 register is
transferred to the CCR0 buffer register. When the count value of the 16-bit counter matches the value of the
CCR0 buffer register, a compare match interrupt request signal (INTTQnCC0) is generated.
The CCR0 buffer register cannot be read or written directly.
The CCR0 buffer register is cleared to 0000H after reset, as the TQnCCR0 register is cleared to 0000H.
(3) CCR1 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR1 register is used as a compare register, the value written to the TQnCCR1 register is
transferred to the CCR1 buffer register. When the count value of the 16-bit counter matches the value of the
CCR1 buffer register, a compare match interrupt request signal (INTTQnCC1) is generated.
The CCR1 buffer register cannot be read or written directly.
The CCR1 buffer register is cleared to 0000H after reset, as the TQnCCR1 register is cleared to 0000H.
(4) CCR2 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR2 register is used as a compare register, the value written to the TQnCCR2 register is
transferred to the CCR2 buffer register. When the count value of the 16-bit counter matches the value of the
CCR2 buffer register, a compare match interrupt request signal (INTTQnCC2) is generated.
The CCR2 buffer register cannot be read or written directly.
The CCR2 buffer register is cleared to 0000H after reset, as the TQnCCR2 register is cleared to 0000H.
(5) CCR3 buffer register
This is a 16-bit compare register that compares the count value of the 16-bit counter.
When the TQnCCR3 register is used as a compare register, the value written to the TQnCCR3 register is
transferred to the CCR3 buffer register. When the count value of the 16-bit counter matches the value of the
CCR3 buffer register, a compare match interrupt request signal (INTTQnCC3) is generated.
The CCR3 buffer register cannot be read or written directly.
The CCR3 buffer register is cleared to 0000H after reset, as the TQnCCR3 register is cleared to 0000H.
(6) Edge detector
This circuit detects the valid edges input to the TIQn0 and TIQn3 pins. No edge, rising edge, falling edge, or
both the rising and falling edges can be selected as the valid edge by using the TQnIOC1 and TQnIOC2
registers.
(7) Output controller
This circuit controls the output of the TOQn0 to TOQn3 pins. The output controller is controlled by the
TQnIOC0 register.
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(8) Selector
This selector selects the count clock for the 16-bit counter. Eight types of internal clocks or an external event
can be selected as the count clock.
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8.4 Registers
The registers that control TMQn are as follows.
TMQn control register 0 (TQnCTL0)
TMQn control register 1 (TQnCTL1)
TMQn I/O control register 0 (TQnIOC0)
TMQn I/O control register 1 (TQnIOC1)
TMQn I/O control register 2 (TQnIOC2)
TMQn option register 0 (TQnOPT0)
TMQn capture/compare register 0 (TQnCCR0)
TMQn capture/compare register 1 (TQnCCR1)
TMQn capture/compare register 2 (TQnCCR2)
TMQn capture/compare register 3 (TQnCCR3)
TMQn counter read buffer register (TQnCNT)
Remark When using the functions of the TIQn0 to TIQn3 and TOQn0 to TOQn3 pins, see Table 4-25 Using Port
Pin as Alternate-Function Pin.
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(1) TMQn control register 0 (TQnCTL0)
The TQnCTL0 register is an 8-bit register that controls the operation of TMQn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TQnCTL0 register by software.
TQnCE
TMQn operation disabled (TMQn reset asynchronously
Note
).
TMQn operation enabled. TMQn operation started.
TQnCE
0
1
TMQn operation control
TQnCTL0
(n = 0 to 2)
0
0
0
0
TQnCKS2 TQnCKS1 TQnCKS0
6
5
4
3
2
1
After reset: 00H R/W Address:
TQ0CTL0 FFFFF540H, TQ1CTL0 FFFFF610H,
TQ2CTL0 FFFFF620H
7
0
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
TQnCKS2
0
0
0
0
1
1
1
1
Internal count clock selection
TQnCKS1
0
0
1
1
0
0
1
1
TQnCKS0
0
1
0
1
0
1
0
1
Note TQnOPT0.TQnOVF bit, 16-bit counter, timer output (TOQn0 to TOQn3 pins)
Cautions 1. Set the TQnCKS2 to TQnCKS0 bits when the TQnCE bit = 0. When
the value of the TQnCE bit is changed from 0 to 1, the TQnCKS2 to
TQnCKS0 bits can be set simultaneously.
2. Be sure to clear bits 3 to 6 to "0".
Remark f
XX
: Main clock frequency
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(2) TMQn control register 1 (TQnCTL1)
The TQnCTL1 register is an 8-bit register that controls the operation of TMQn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
TQnSYE
TQnEST
0
1
Software trigger control
TQnCTL1
(n = 0 to 2)
TQnEST TQnEEE
0
0
TQnMD2 TQnMD1 TQnMD0
6
5
4
3
2
1
After reset: 00H R/W Address: TQ0CTL1 FFFFF541H, TQ1CTL1 FFFFF611H,
TQ2CTL1 FFFFF621H
Generate a valid signal for external trigger input.
In one-shot pulse output mode: A one-shot pulse is output with writing
1 to the TQnEST bit as the trigger.
In external trigger pulse output mode: A PWM waveform is output with
writing 1 to the TQnEST bit as
the trigger.
7
0
-
Slave timer
TQnSYE
0
1
Tuned operation mode enable control
Tuned operation mode (specification of slave operation)
In this mode, timer P can operate in synchronization with a master timer.
Independent operation mode (asynchronous operation mode)
For the tuned operation mode, see 8.6 Timer Tuned Operation
Function.
Master timer
TMP2
TMQ1
TMP3
TMQ2
TMQ0
-
Cautions 1. The TQnEST bit is valid only in the external trigger pulse output
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
2. Be sure to clear bits 3 and 4 to "0".
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(2/2)
Disable operation with external event count input.
(Perform counting with the count clock selected by the TQnCTL0.TQnCK0
to TQnCK2 bits.)
TQnEEE
0
1
Count clock selection
The TQnEEE bit selects whether counting is performed with the internal count clock
or the valid edge of the external event count input.
Interval timer mode
External event count mode
External trigger pulse output mode
One-shot pulse output mode
PWM output mode
Free-running timer mode
Pulse width measurement mode
Triangular wave PWM mode
TQnMD2
0
0
0
0
1
1
1
1
Timer mode selection
TQnMD1
0
0
1
1
0
0
1
1
TQnMD0
0
1
0
1
0
1
0
1
Enable operation with external event count input.
(Perform counting at the valid edge of the external event count input
signal.)
Cautions 1. External event count input is selected in the external event count mode
regardless of the value of the TQnEEE bit.
2. Set the TQnEEE and TQnMD2 to TQnMD0 bits when the TQnCTL0.TQnCE
bit = 0. (The same value can be written when the TQnCE bit = 1.) The
operation is not guaranteed when rewriting is performed with the TQnCE
bit = 1. If rewriting was mistakenly performed, clear the TQnCE bit to 0
and then set the bits again.
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(3) TMQn I/O control register 0 (TQnIOC0)
The TQnIOC0 register is an 8-bit register that controls the timer output (TOQn0 to TOQn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQnOL3
TQnOLm
0
1
TOQnm pin output level setting (m = 0 to 3)
TOQnm pin output inversion disabled
TOQnm pin output inversion enabled
TQnIOC0
(n = 0 to 2)
TQnOE3
TQnOL2 TQnOE2
TQnOL1 TQnOE1 TQnOL0
TQnOE0
6
5
4
3
2
1
After reset: 00H R/W Address:
TQ0IOC0 FFFFF542H, TQ1IOC0 FFFFF612H,
TQ2IOC0 FFFFF622H
TQnOEm
0
1
TOQnm pin output setting (m = 0 to 3)
Timer output disabled
When TQnOLm bit = 0: Low level is output from the TOQnm pin
When TQnOLm bit = 1: High level is output from the TOQnm pin
7
0
Timer output enabled (A square wave is output from the TOQnm pin).
Cautions 1.
Rewrite the TQnOLm and TQnOEm bits when the
TQnCTL0.TQnCE bit = 0. (The same value can be written
when the TQnCE bit = 1.) If rewriting was mistakenly
performed, clear the TQnCE bit to 0 and then set the bits
again.
2. Even if the TQnOLm bit is manipulated when the TQnCE and
TQnOEm bits are 0, the TOQnm pin output level varies.
Remark m = 0 to 3
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(4) TMQn I/O control register 1 (TQnIOC1)
The TQnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQn0
to TIQn3 pins).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQnIS7
TQnIS7
0
0
1
1
TQnIS6
0
1
0
1
Capture trigger input signal (TIQn3 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TQnIOC1
(n = 0 to 2)
TQnIS6
TQnIS5
TQnIS4
TQnIS3
TQnIS2
TQnIS1
TQnIS0
6
5
4
3
2
1
After reset: 00H R/W Address:
TQ0IOC1 FFFFF543H, TQ1IOC1 FFFFF613H,
TQ2IOC1 FFFFF623H
TQnIS5
0
0
1
1
TQnIS4
0
1
0
1
Capture trigger input signal (TIQn2 pin) valid edge detection
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7
0
TQnIS3
0
0
1
1
TQnIS2
0
1
0
1
Capture trigger input signal (TIQn1 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TQnIS1
0
0
1
1
TQnIS0
0
1
0
1
Capture trigger input signal (TIQn0 pin) valid edge setting
No edge detection (capture operation invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
Cautions
1.
Rewrite the TQnIS7 to TQnIS0 bits when the
TQnCTL0.TQnCE bit = 0. (The same value can be written
when the TQnCE bit = 1.) If rewriting was mistakenly
performed, clear the TQnCE bit to 0 and then set the bits
again.
2. The TQnIS7 to TQnIS0 bits are valid only in the free-
running timer mode and the pulse width measurement
mode. In all other modes, a capture operation is not
possible.
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(5) TMQn I/O control register 2 (TQnIOC2)
The TQnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIQn0 pin) and external trigger input signal (TIQn0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
TQnEES1
0
0
1
1
TQnEES0
0
1
0
1
External event count input signal (TIQn0 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
TQnIOC2
(n = 0 to 2)
0
0
0
TQnEES1 TQnEES0 TQnETS1 TQnETS0
6
5
4
3
2
1
After reset: 00H R/W Address:
TQ0IOC2 FFFFF544H, TQ1IOC2 FFFFF614H,
TQ2IOC2 FFFFF624H
TQnETS1
0
0
1
1
TQnETS0
0
1
0
1
External trigger input signal (TIQn0 pin) valid edge setting
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
7
0
Cautions 1. Rewrite the TQnEES1, TQnEES0, TQnETS1, and TQnETS0
bits when the TQnCTL0.TQnCE bit = 0. (The same value
can be written when the TQnCE bit = 1.) If rewriting was
mistakenly performed, clear the TQnCE bit to 0 and then
set the bits again.
2. The TQnEES1 and TQnEES0 bits are valid only when the
TQnCTL1.TQnEEE bit = 1 or when the external event
count mode (TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0
bits = 001) has been set.
3. The TQnETS1 and TQnETS0 bits are valid only when the
external trigger pulse output mode (TQnCTL1.TQnMD2 to
TQnCTL1.TQnMD0 bits = 010) or the one-shot pulse
output mode (TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0 =
011) is set.
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(6) TMQn option register 0 (TQnOPT0)
The TQnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TQnCCS3
TQnCCSm
0
1
TQnCCRm register capture/compare selection
The TQnCCSm bit setting is valid only in the free-running timer mode.
Compare register selected
Capture register selected
TQnOPT0
(n = 0 to 2)
TQnCCS2 TQnCCS1 TQnCCS0
0
0
0
TQnOVF
6
5
4
3
2
1
After reset: 00H R/W Address:
TQ0OPT0 FFFFF545H, TQ1OPT0 FFFFF615H,
TQ2OPT0 FFFFF625H
TQnOVF
Set (1)
Reset (0)
TMQn overflow detection
The TQnOVF bit is set to 1 when the 16-bit counter count value overflows from
FFFFH to 0000H in the free-running timer mode or the pulse width measurement
mode.
An interrupt request signal (INTTQnOV) is generated at the same time that the
TQnOVF bit is set to 1. The INTTQnOV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
The TQnOVF bit is not cleared even when the TQnOVF bit or the TQnOPT0
register are read when the TQnOVF bit = 1.
The TQnOVF bit can be both read and written, but the TQnOVF bit cannot be set
to 1 by software. Writing 1 has no influence on the operation of TMQn.
Overflow occurred
TQnOVF bit 0 written or TQnCTL0.TQnCE bit = 0
7
0
Cautions 1.
Rewrite the TQnCCS3 to TQnCCS0 bits when the
TQnCTL0.TQnCE bit = 0. (The same value can be written
when the TQnCE bit = 1.) If rewriting was mistakenly
performed, clear the TQnCE bit to 0 and then set the bits
again.
2. Be sure to clear bits 1 to 3 to "0".
Remark m = 0 to 3
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(7) TMQn capture/compare register 0 (TQnCCR0)
The TQnCCR0 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TQnOPT0.TQnCCS0 bit. In the pulse width measurement mode, the
TQnCCR0 register can be used only as a capture register. In any other mode, this register can be used only
as a compare register.
The TQnCCR0 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TQnCCR0 register is prohibited in the following statuses. For details, see
3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TQnCCR0
(n = 0 to 2)
12
10
8
6
4
2
After reset: 0000H R/W Address:
TQ0CCR0 FFFFF546H, TQ1CCR0 FFFFF616H,
TQ2CCR0 FFFFF626H
14
0
13
11
9
7
5
3
15
1
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(a) Function as compare register
The TQnCCR0 register can be rewritten even when the TQnCTL0.TQnCE bit = 1.
The set value of the TQnCCR0 register is transferred to the CCR0 buffer register. When the value of the
16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTQnCC0) is generated. If TOQn0 pin output is enabled at this time, the output of the TOQn0 pin is
inverted.
When the TQnCCR0 register is used as a cycle register in the interval timer mode, external event count
mode, external trigger pulse output mode, one-shot pulse output mode, PWM output mode, or triangular
wave PWM mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of
the CCR0 buffer register.
(b) Function as capture register
When the TQnCCR0 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQnCCR0 register if the valid edge of the capture trigger input pin
(TIQn0 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TQnCCR0 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQn0 pin) is detected.
Even if the capture operation and reading the TQnCCR0 register conflict, the correct value of the
TQnCCR0 register can be read.
Remark n = 0 to 2
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Table 8-2. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
-
Triangular wave PWM mode
Compare register
Batch write
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(8) TMQn capture/compare register 1 (TQnCCR1)
The TQnCCR1 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TQnOPT0.TQnCCS1 bit. In the pulse width measurement mode, the
TQnCCR1 register can be used only as a capture register. In any other mode, this register can be used only
as a compare register.
The TQnCCR1 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TQnCCR1 register is prohibited in the following statuses. For details, see
3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TQnCCR1
(n = 0 to 2)
12
10
8
6
4
2
After reset: 0000H R/W Address:
TQ0CCR1 FFFFF548H, TQ1CCR1 FFFFF618H,
TQ2CCR1 FFFFF628H
14
0
13
11
9
7
5
3
15
1
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(a) Function as compare register
The TQnCCR1 register can be rewritten even when the TQnCTL0.TQnCE bit = 1.
The set value of the TQnCCR1 register is transferred to the CCR1 buffer register. When the value of the
16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTQnCC1) is generated. If TOQn1 pin output is enabled at this time, the output of the TOQn1 pin is
inverted.
(b) Function as capture register
When the TQnCCR1 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQnCCR1 register if the valid edge of the capture trigger input pin
(TIQn1 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TQnCCR1 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQn1 pin) is detected.
Even if the capture operation and reading the TQnCCR1 register conflict, the correct value of the
TQnCCR1 register can be read.
Remark n = 0 to 2
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Table 8-3. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
-
Triangular wave PWM mode
Compare register
Batch write
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(9) TMQn capture/compare register 2 (TQnCCR2)
The TQnCCR2 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TQnOPT0.TQnCCS2 bit. In the pulse width measurement mode, the
TQnCCR2 register can be used only as a capture register. In any other mode, this register can be used only
as a compare register.
The TQnCCR2 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TQnCCR2 register is prohibited in the following statuses. For details, see
3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TQnCCR2
(n = 0 to 2)
12
10
8
6
4
2
After reset: 0000H R/W Address:
TQ0CCR2 FFFFF54AH, TQ1CCR2 FFFFF61AH,
TQ2CCR2 FFFFF62AH
14
0
13
11
9
7
5
3
15
1
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(a) Function as compare register
The TQnCCR2 register can be rewritten even when the TQnCTL0.TQnCE bit = 1.
The set value of the TQnCCR2 register is transferred to the CCR2 buffer register. When the value of the
16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal
(INTTQnCC2) is generated. If TOQn2 pin output is enabled at this time, the output of the TOQn2 pin is
inverted.
(b) Function as capture register
When the TQnCCR2 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQnCCR2 register if the valid edge of the capture trigger input pin
(TIQn2 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TQnCCR2 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQn2 pin) is detected.
Even if the capture operation and reading the TQnCCR2 register conflict, the correct value of the
TQnCCR2 register can be read.
Remark n = 0 to 2
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Table 8-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
-
Triangular wave PWM mode
Compare register
Batch write
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(10) TMQn capture/compare register 3 (TQnCCR3)
The TQnCCR3 register can be used as a capture register or a compare register depending on the mode.
This register can be used as a capture register or a compare register only in the free-running timer mode,
depending on the setting of the TQnOPT0.TQnCCS3 bit. In the pulse width measurement mode, the
TQnCCR3 register can be used only as a capture register. In any other mode, this register can be used only
as a compare register.
The TQnCCR3 register can be read or written during operation.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
Caution Accessing the TQnCCR3 register is prohibited in the following statuses. For details, see
3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TQnCCR3
(n = 0 to 2)
12
10
8
6
4
2
After reset: 0000H R/W Address:
TQ0CCR3 FFFFF54CH, TQ1CCR3 FFFFF61CH,
TQ2CCR3 FFFFF62CH
14
0
13
11
9
7
5
3
15
1
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(a) Function as compare register
The TQnCCR3 register can be rewritten even when the TQnCTL0.TQnCE bit = 1.
The set value of the TQnCCR3 register is transferred to the CCR3 buffer register. When the value of the
16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal
(INTTQnCC3) is generated. If TOQn3 pin output is enabled at this time, the output of the TOQn3 pin is
inverted.
(b) Function as capture register
When the TQnCCR3 register is used as a capture register in the free-running timer mode, the count value
of the 16-bit counter is stored in the TQnCCR3 register if the valid edge of the capture trigger input pin
(TIQn3 pin) is detected. In the pulse-width measurement mode, the count value of the 16-bit counter is
stored in the TQnCCR3 register and the 16-bit counter is cleared (0000H) if the valid edge of the capture
trigger input pin (TIQn3 pin) is detected.
Even if the capture operation and reading the TQnCCR3 register conflict, the correct value of the
TQnCCR3 register can be read.
Remark n = 0 to 2
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Table 8-5. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Operation Mode
Capture/Compare Register
How to Write Compare Register
Interval timer
Compare register
Anytime write
External event counter
Compare register
Anytime write
External trigger pulse output
Compare register
Batch write
One-shot pulse output
Compare register
Anytime write
PWM output
Compare register
Batch write
Free-running timer
Capture/compare register
Anytime write
Pulse width measurement
Capture register
-
Triangular wave PWM mode
Compare register
Batch write
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(11) TMQn counter read buffer register (TQnCNT)
The TQnCNT register is a read buffer register that can read the count value of the 16-bit counter.
If this register is read when the TQnCTL0.TQnCE bit = 1, the count value of the 16-bit timer can be read.
This register is read-only, in 16-bit units.
The value of the TQnCNT register is cleared to 0000H when the TQnCE bit = 0. If the TQnCNT register is read
at this time, the value of the 16-bit counter (FFFFH) is not read, but 0000H is read.
The value of the TQnCNT register is cleared to 0000H after reset, as the TQnCE bit is cleared to 0.
Caution Accessing the TQnCNT register is prohibited in the following statuses. For details, see 3.4.8
(2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
TQnCNT
(n = 0 to 2)
12
10
8
6
4
2
After reset: 0000H R Address:
TQ0CNT FFFFF54EH, TQ1CNT FFFFF61EH,
TQ2CNT FFFFF62EH
14
0
13
11
9
7
5
3
15
1
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(12) TIQnm pin noise elimination control register (QnmNFC)
The QnmNFC register is an 8-bit register that sets the digital noise filter of the timer Q input pin for noise
elimination.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: Q00NFC: FFFFFB50H (TIQ00 pin)
Q01NFC: FFFFFB54H (TIQ01 pin)
Q02NFC:
FFFFFB58H
(TIQ02 pin)
Q03NFC: FFFFFB5CH (TIQ03 pin)
Q10NFC: FFFFFB60H (TIQ10 pin)
Q11NFC: FFFFFB64H (TIQ11 pin)
Q12NFC: FFFFFB68H (TIQ12 pin)
Q13NFC: FFFFFB6CH (TIQ13 pin)
Q20NFC: FFFFFB70H (TIQ20 pin)
Q21NFC: FFFFFB74H (TIQ21 pin)
Q22NFC: FFFFFB78H (TIQ22 pin)
Q23NFC: FFFFFB7CH (TIQ23 pin)
7 6 5 4 3 2 1 0
QnmNFC
0 NFSTS 0
0
0 NFC2
NFC1
NFC0
(n = 0 to 2, m = 0 to 3)
NFSTS
Setting of number of times of sampling by digital noise filter
0
3
times
1
2
times
NFC2
NFC1
NFC0 Sampling
clock
0 0 0
f
XX
0 0 1
f
XX
/2
0 1 0
f
XX
/4
0 1 1
f
XX
/16
1 0 0
f
XX
/32
1 0 1
f
XX
/64
Other than above
Setting prohibited
Cautions 1. Be sure to clear bits 3 to 5 and 7 to "0".
2. A signal input to the timer input pin (TIQnm) before the QnmNFC
register is set is output with digital noise eliminated.
Therefore, set the sampling clock (NFC2 to NFC0) and the number of
times of sampling (NFSTS) by using the QnmNFC register, wait for
initialization time = (Sampling clock)
(Number of times of sampling),
and enable the timer operation.
Remark The width of the noise that can be accurately eliminated is (Sampling clock)
(Number of times of sampling 1). Even noise with a width narrower than this
may cause a miscount if it is synchronized with the sampling clock.
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8.5
Operation
TMQn can perform the following operations.
Operation
TQnCTL1.TQnEST Bit
(Software Trigger Bit)
TIQn0 Pin
(External Trigger Input)
Capture/Compare
Register Setting
Compare Register
Write
Interval timer mode
Invalid
Invalid
Compare only
Anytime write
External event count mode
Note 1
Invalid Invalid Compare
only
Anytime
write
External trigger pulse output mode
Note 2
Valid Valid Compare
only
Batch
write
One-shot pulse output mode
Note 2
Valid Valid Compare
only
Anytime
write
PWM output mode
Invalid
Invalid
Compare only
Batch write
Free-running timer mode
Invalid
Invalid
Switching enabled
Anytime write
Pulse width measurement mode
Note 2
Invalid Invalid Capture
only
Not
applicable
Triangular wave PWM mode
Invalid
Invalid
Compare only
Batch write
Notes 1. To use the external event count mode, specify that the valid edge of the TIQn0 pin capture trigger input
is not detected (by clearing the TQnIOC1.TQnIS1 and TQnIOC1.TQnIS0 bits to "00").
2. When using the external trigger pulse output mode, one-shot pulse output mode, and pulse width
measurement mode, select the internal clock as the count clock (by clearing the TQnCTL1.TQnEEE bit
to 0).
Remark n= 0 to 2
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8.5.1
Interval timer mode (TQnMD2 to TQnMD0 bits = 000)
In the interval timer mode, an interrupt request signal (INTTQnCC0) is generated at the specified interval if the
TQnCTL0.TQnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the
TOQn0 pin.
Usually, the TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode.
Figure 8-2. Configuration of Interval Timer
16-bit counter
Output
controller
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Count clock
selection
Clear
Match signal
TOQn0 pin
INTTQnCC0 signal
Remark n = 0 to 2
Figure 8-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
TOQn0 pin output
INTTQnCC0 signal
D
0
D
0
D
0
D
0
D
0
Interval (D
0
+ 1)
Interval (D
0
+ 1)
Interval (D
0
+ 1)
Interval (D
0
+ 1)
Remark n = 0 to 2
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When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting. At this time, the output of the TOQn0 pin is inverted. Additionally,
the set value of the TQnCCR0 register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
cleared to 0000H, the output of the TOQn0 pin is inverted, and a compare match interrupt request signal
(INTTQnCC0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TQnCCR0 register + 1)
Count clock cycle
Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
Select count clock
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
(b) TMQn control register 1 (TQnCTL1)
0
0
0/1
Note
0
0
TQnCTL1
0, 0, 0:
Interval timer mode
0
0
0
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
0: Operate on count
clock selected by bits
TQnCKS0 to TQnCKS2
1: Count with external
event count input signal
Note This bit can be set to 1 only when the interrupt request signals (INTTQnCC0 and INTTQnCCk) are
masked by the interrupt mask flags (TQnCCMK0 to TQnCCMKk) and the timer output (TOQnk) is
performed at the same time. However, the TQnCCR0 and TQnCCRk registers must be set to the same
value (see 8.5.1 (2) (d) Operation of TQnCCR1 to TQnCCR3 registers) (k = 1 to 3).
Remark n = 0 to 2
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Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2)
(c) TMQn I/O control register 0 (TQnIOC0)
0/1
0/1
0/1
0/1
0/1
TQnIOC0
0: Disable TOQn0 pin output
1: Enable TOQn0 pin output
Setting of output level with
operation of TOQn0 pin disabled
0: Low level
1: High level
0: Disable TOQn1 pin output
1: Enable TOQn1 pin output
Setting of output level with
operation of TOQn1 pin disabled
0: Low level
1: High level
0/1
0/1
0/1
TQnOE1 TQnOL0
TQnOE0
TQnOL1
0: Disable TOQn2 pin output
1: Enable TOQn2 pin output
Setting of output level with
operation of TOQn2 pin disabled
0: Low level
1: High level
0: Disable TOQn3 pin output
1: Enable TOQn3 pin output
Setting of output level with
operation of TOQn3 pin disabled
0: Low level
1: High level
TQnOE3 TQnOL2
TQnOE2
TQnOL3
(d) TMQn counter read buffer register (TQnCNT)
By reading the TQnCNT register, the count value of the 16-bit counter can be read.
(e) TMQn capture/compare register 0 (TQnCCR0)
If the TQnCCR0 register is set to D
0
, the interval is as follows.
Interval = (D
0
+ 1)
Count clock cycle
(f) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3)
Usually, the TQnCCR1 to TQnCCR3 registers are not used in the interval timer mode. However, the set
value of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer registers. The
compare match interrupt request signals (INTTQnCCR1 to INTTQnCCR3) is generated when the count
value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer registers.
Therefore, mask the interrupt request by using the corresponding interrupt mask flags (TQnCCMK1 to
TQnCCMK3).
Remarks 1. TMQn I/O control register 1 (TQnIOC1), TMQn I/O control register 2 (TQnIOC2), and
TMQn option register 0 (TQnOPT0) are not used in the interval timer mode.
2. n = 0 to 2
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(1) Interval timer mode operation flow
Figure 8-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
TOQn0 pin output
INTTQnCC0 signal
D
0
D
0
D
0
D
0
<1>
<2>
TQnCE bit = 1
TQnCE bit = 0
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC0 register,
TQnCCR0 register
Initial setting of these registers is performed
before setting the TQnCE bit to 1.
The TQnCKS0 to TQnCKS2 bits can be
set at the same time when counting has
been started (TQnCE bit = 1).
The counter is initialized and counting is
stopped by clearing the TQnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0 to 2
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(2) Interval timer mode operation timing
(a) Operation if TQnCCR0 register is set to 0000H
If the TQnCCR0 register is set to 0000H, the INTTQnCC0 signal is generated at each count clock
subsequent to the first count clock, and the output of the TOQn0 pin is inverted.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TQnCE bit
TQnCCR0 register
TOQn0 pin output
INTTQnCC0 signal
0000H
Interval time
Count clock cycle
Interval time
Count clock cycle
FFFFH
0000H
0000H
0000H
0000H
Remark n = 0 to 2
(b) Operation if TQnCCR0 register is set to FFFFH
If the TQnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to
0000H in synchronization with the next count-up timing. The INTTQnCC0 signal is generated and the
output of the TOQn0 pin is inverted. At this time, an overflow interrupt request signal (INTTQnOV) is not
generated, nor is the overflow flag (TQnOPT0.TQnOVF bit) set to 1.
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
TOQn0 pin output
INTTQnCC0 signal
FFFFH
Interval time
10000H
count clock cycle
Interval time
10000H
count clock cycle
Interval time
10000H
count clock cycle
Remark n = 0 to 2
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(c) Notes on rewriting TQnCCR0 register
To change the value of the TQnCCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
TQnOL0 bit
TOQn0 pin output
INTTQnCC0 signal
D
1
D
2
D
1
D
1
D
2
D
2
D
2
L
Interval time (1)
Interval time (NG)
Interval
time (2)
Remarks 1. Interval time (1):
(D
1
+ 1)
Count clock cycle
Interval time (NG): (10000H + D
2
+ 1)
Count clock cycle
Interval time (2):
(D
2
+ 1)
Count clock cycle
2. n = 0 to 2
If the value of the TQnCCR0 register is changed from D
1
to D
2
while the count value is greater than D
2
but
less than D
1
, the count value is transferred to the CCR0 buffer register as soon as the TQnCCR0 register
has been rewritten. Consequently, the value of the 16-bit counter that is compared is D
2
.
Because the count value has already exceeded D
2
, however, the 16-bit counter counts up to FFFFH,
overflows, and then counts up again from 0000H. When the count value matches D
2
, the INTTQnCC0
signal is generated and the output of the TOQn0 pin is inverted.
Therefore, the INTTQnCC0 signal may not be generated at the interval time "(D
1
+ 1)
Count clock cycle"
or "(D
2
+ 1)
Count clock cycle" originally expected, but may be generated at an interval of "(10000H + D
2
+ 1)
Count clock period".
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(d) Operation of TQnCCR1 to TQnCCR3 registers
Figure 8-6. Configuration of TQnCCR1 to TQnCCR3 Registers
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Clear
Match signal
INTTQnCC0 signal
TOQn3 pin
INTTQnCC3 signal
TOQn0 pin
TQnCCR1
register
CCR1 buffer
register
Match signal
TOQn1 pin
INTTQnCC1 signal
TQnCCR3
register
CCR3 buffer
register
Match signal
TOQn2 pin
INTTQnCC2 signal
TQnCCR2
register
CCR2 buffer
register
Match signal
Output
controller
Count
clock
selection
Output
controller
Output
controller
Output
controller
16-bit counter
Remark n = 0 to 2
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If the set value of the TQnCCRk register is less than the set value of the TQnCCR0 register, the
INTTQnCCk signal is generated once per cycle. At the same time, the output of the TOPQnk pin is
inverted.
The TOQnk pin outputs a square wave with the same cycle as that output by the TOQn0 pin.
Remark k = 1 to 3,
n = 0 to 2
Figure 8-7. Timing Chart When D
01
D
k1
D
01
D
11
D
21
D
31
D
21
D
11
D
31
D
01
D
01
D
21
D
11
D
31
D
01
D
21
D
11
D
31
D
01
D
21
D
11
D
31
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
TOQn0 pin output
INTTQnCC0 signal
TQnCCR1 register
TOQn1 pin output
INTTQnCC1 signal
TQnCCR2 register
TOQn2 pin output
INTTQnCC2 signal
TQnCCR3 register
TOQn3 pin output
INTTQnCC3 signal
Remark n = 0 to 2
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If the set value of the TQnCCRk register is greater than the set value of the TQnCCR0 register, the count
value of the 16-bit counter does not match the value of the TQnCCRk register. Consequently, the
INTTQnCCk signal is not generated, nor is the output of the TOQnk pin changed.
Remark k = 1 to 3,
n = 0 to 2
Figure 8-8. Timing Chart When D
01
< D
k1
D
01
D
11
D
21
L
L
L
D
31
D
01
D
01
D
01
D
01
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
TOQn0 pin output
INTTQnCC0 signal
TQnCCR1 register
TOQn1 pin output
INTTQnCC1 signal
TQnCCR2 register
TOQn2 pin output
INTTQnCC2 signal
TQnCCR3 register
TOQn3 pin output
INTTQnCC3 signal
Remark n = 0 to 2
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8.5.2
External event count mode (TQnMD2 to TQnMD0 bits = 001)
In the external event count mode, the valid edge of the external event count input is counted when the
TQnCTL0.TQnCE bit is set to 1, and an interrupt request signal (INTTQnCC0) is generated each time the specified
number of edges have been counted. The TOQn0 pin cannot be used.
Usually, the TQnCCR1 to TQnCCR3 registers are not used in the external event count mode.
Figure 8-9. Configuration in External Event Count Mode
16-bit counter
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Edge
detector
Clear
Match signal
INTTQnCC0 signal
TIQn0 pin
(external event
count input)
Remark n = 0 to 2
Figure 8-10. Basic Timing in External Event Count Mode
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
D
0
D
0
D
0
D
0
16-bit counter
TQnCCR0 register
NTTQnCC0 signal
External event
count input
(TIQn0 pin input)
D
0
External
event
count
interval
(D
0
+ 1)
D
0
- 1
D
0
0000
0001
External
event
count
interval
(D
0
+ 1)
External
event
count
interval
(D
0
+ 1)
Remarks 1. This figure shows the basic timing when the rising edge is specified as the valid edge of the
external event count input.
2. n = 0 to 2
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When the TQnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQnCCR0
register is transferred to the CCR0 buffer register.
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
cleared to 0000H, and a compare match interrupt request signal (INTTQnCC0) is generated.
The INTTQnCC0 signal is generated each time the valid edge of the external event count input has been detected
(set value of TQnCCR0 register + 1) times.
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
0: Stop counting
1: Enable counting
0
0
0
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
(b) TMQn control register 1 (TQnCTL1)
0
0
0
0
0
TQnCTL1
0, 0, 1:
External event count mode
0
0
1
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
(c) TMQn I/O control register 0 (TQnIOC0)
0
0
0
0
0
TQnIOC0
0: Disable TOQn0 pin output
0: Disable TOQn1 pin output
0
0
0
TQnOE1 TQnOL0
TQnOE0
TQnOL1
TQnOE3 TQnOL2
TQnOE2
TQnOL3
0: Disable TOQn2 pin output
0: Disable TOQn3 pin output
(d) TMQn I/O control register 2 (TQnIOC2)
0
0
0
0
0/1
TQnIOC2
Select valid edge
of external event
count input
0/1
0
0
TQnEES0 TQnETS1 TQnETS0
TQnEES1
Remark n = 0 to 2
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Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2)
(e) TMQn counter read buffer register (TQnCNT)
The count value of the 16-bit counter can be read by reading the TQnCNT register.
(f) TMQn capture/compare register 0 (TQnCCR0)
If D
0
is set to the TQnCCR0 register, the counter is cleared and a compare match interrupt request
signal (INTTQnCC0) is generated when the number of external event counts reaches (D
0
+ 1).
(g) TMQn capture/compare registers 1 to 3 (TQnCCR1 to TQnCCR3)
Usually, the TQnCCR1 to TQnCCR3 registers are not used in the external event count mode. However,
the set value of the TQnCCR1 to TQnCCR3 registers are transferred to the CCR1 to CCR3 buffer
registers. When the count value of the 16-bit counter matches the value of the CCR1 to CCR3 buffer
registers, compare match interrupt request signals (INTTQnCC1 to INTTQnCC3) are generated.
Therefore, mask the interrupt signal by using the interrupt mask flags (TQnCCMK1 to TQnCCMK3).
Remarks 1. The TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are
not used in the external event count mode.
2. n = 0 to 2
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(1) External event count mode operation flow
Figure 8-12. Flow of Software Processing in External Event Count Mode
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
D
0
D
0
D
0
D
0
<1>
<2>
TQnCE bit = 1
TQnCE bit = 0
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC0 register,
TQnIOC2 register,
TQnCCR0 register
Initial setting of these registers
is performed before setting the
TQnCE bit to 1.
The TQnCKS0 to TQnCKS2 bits can
be set at the same time when counting
has been started (TQnCE bit = 1).
The counter is initialized and counting
is stopped by clearing the TQnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
Remark n = 0 to 2
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(2) Operation timing in external event count mode
Cautions 1. In the external event count mode, do not set the TQnCCR0 register to 0000H.
2. In the external event count mode, use of the timer output is disabled. If performing timer
output using external event count input, set the interval timer mode, and select the
operation enabled by the external event count input for the count clock
(TQnCTL1.TQnMD2 to TQnCTL1.TQnMD0 bits = 000, TQnCTL1.TQnEEE bit = 1).
(a) Operation if TQnCCR0 register is set to FFFFH
If the TQnCCR0 register is set to FFFFH, the 16-bit counter counts to FFFFH each time the valid edge of
the external event count signal has been detected. The 16-bit counter is cleared to 0000H in
synchronization with the next count-up timing, and the INTTQnCC0 signal is generated. At this time, the
TQnOPT0.TQnOVF bit is not set.
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
FFFFH
External event
count signal
interval
External event
count signal
interval
External event
count signal
interval
Remark n = 0 to 2
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(b) Notes on rewriting the TQnCCR0 register
To change the value of the TQnCCR0 register to a smaller value, stop counting once and then change the
set value.
If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
D
1
D
2
D
1
D
1
D
2
D
2
D
2
External event
count signal
interval (1)
(D
1
+ 1)
External event count signal
interval (NG)
(10000H + D
2
+ 1)
External event
count signal
interval (2)
(D
2
+ 1)
Remark n = 0 to 2
If the value of the TQnCCR0 register is changed from D
1
to D
2
while the count value is greater than D
2
but
less than D
1
, the count value is transferred to the CCR0 buffer register as soon as the TQnCCR0 register
has been rewritten. Consequently, the value that is compared with the 16-bit counter is D
2
.
Because the count value has already exceeded D
2
, however, the 16-bit counter counts up to FFFFH,
overflows, and then counts up again from 0000H. When the count value matches D
2
, the INTTQnCC0
signal is generated.
Therefore, the INTTQnCC0 signal may not be generated at the valid edge count of "(D
1
+ 1) times" or "(D
2
+ 1) times" originally expected, but may be generated at the valid edge count of "(10000H + D
2
+ 1) times".
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(c) Operation of
TQnCCR1 to TQnCCR3 registers
Figure 8-13. Configuration of TQnCCR1 to TQnCCR3 Registers
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Clear
Match signal
INTTQnCC0 signal
INTTQnCC3 signal
TIQn0 pin
TQnCCR1
register
CCR1 buffer
register
Match signal
INTTQnCC1 signal
TQnCCR3
register
CCR3 buffer
register
Match signal
INTTQnCC2 signal
TQnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Edge
detector
Remark n = 0 to 2
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If the set value of the TQnCCRk register is smaller than the set value of the TQnCCR0 register, the
INTTQnCCk signal is generated once per cycle.
Remark k = 1 to 3,
n = 0 to 2
Figure 8-14. Timing Chart When D
01
D
k1
D
01
D
11
D
21
D
31
D
21
D
11
D
31
D
01
D
01
D
21
D
11
D
31
D
01
D
21
D
11
D
31
D
01
D
21
D
11
D
31
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
TQnCCR1 register
INTTQnCC1 signal
TQnCCR2 register
INTTQnCC2 signal
TQnCCR3 register
INTTQnCC3 signal
Remark n = 0 to 2
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If the set value of the TQnCCRk register is greater than the set value of the TQnCCR0 register, the
INTTQnCCk signal is not generated because the count value of the 16-bit counter and the value of the
TQnCCRk register do not match.
Remark k = 1 to 3,
n = 0 to 2
Figure 8-15. Timing Chart When D
01
< D
k1
D
01
D
11
D
21
L
L
L
D
31
D
01
D
01
D
01
D
01
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
TQnCCR1 register
INTTQnCC1 signal
TQnCCR2 register
INTTQnCC2 signal
TQnCCR3 register
INTTQnCC3 signal
Remark n = 0 to 2
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8.5.3
External trigger pulse output mode (TQnMD2 to TQnMD0 bits = 010)
In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the
TQnCTL0.TQnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event
counter Q starts counting, and outputs a PWM waveform from the TOQn1 to TOQn3 pins.
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a
software trigger, a square wave that has one cycle of the PWM waveform as half its cycle can also be output from the
TOQn0 pin.
Figure 8-16. Configuration in External Trigger Pulse Output Mode
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Clear
Match signal
INTTQnCC0 signal
TOQn3 pin
INTTQnCC3 signal
TOQn0 pin
TIQn0 pin
Transfer
S
R
TQnCCR1
register
CCR1 buffer
register
Match signal
TOQn1 pin
INTTQnCC1 signal
Transfer
Transfer
S
R
TQnCCR3
register
CCR3 buffer
register
Match signal
Transfer
TOQn2 pin
INTTQnCC2 signal
S
R
TQnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count
clock
selection
Count
start
control
Edge
detector
Software trigger
generation
Output
controller
(RS-FF)
Output
controller
Output
controller
(RS-FF)
Output
controller
Remark n = 0 to 2
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Figure 8-17. Basic Timing in External Trigger Pulse Output Mode
D
1
D
2
D
3
D
1
D
2
D
3
D
1
D
2
D
3
D
1
D
1
D
2
D
3
Active level
width (D
2
)
Active level
width (D
2
)
Active level
width (D
2
)
Active level
width (D
3
)
Active level
width (D
3
)
Cycle (D
0
+ 1)
Cycle (D
0
+ 1)
Wait
for trigger
Active level
width (D
3
)
Cycle (D
0
+ 1)
FFFFH
16-bit counter
0000H
TQnCE bit
External trigger input
(TIQn0 pin input)
TQnCCR0 register
INTTQnCC0 signal
TOQn0 pin output
(only when software
trigger is used)
TQnCCR1 register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
Active level
width
(D
1
)
Active level
width
(D
1
)
Active level
width
(D
1
)
Active level
width
(D
1
)
Active level
width
(D
1
)
D
0
D
1
D
3
D
2
D
0
D
0
D
0
D
0
Remark n = 0 to 2
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16-bit timer/event counter Q waits for a trigger when the TQnCE bit is set to 1. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOQnk pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOQn0 pin is inverted. The TOQnk pin outputs a high-level regardless of the status
(high/low) when a trigger is generated.)
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TQnCCRk register)
Count clock cycle
Cycle = (Set value of TQnCCR0 register + 1)
Count clock cycle
Duty factor = (Set value of TQnCCRk register)/(Set value of TQnCCR0 register + 1)
The compare match request signal (INTTQnCC0) is generated when the 16-bit counter counts next time after its
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal (INTTQnCCk) is generated when the count value of the 16-bit counter matches the
value of the CCRk buffer register.
The value set to the TQnCCRm register is transferred to the CCRm buffer register when the count value of the 16-
bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
The valid edge of an external trigger input signal, or setting the software trigger (TQnCTL1.TQnEST bit) to 1 is
used as the trigger.
Remark k = 1 to 3,
m = 0 to 3,
n = 0 to 2
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (1/3)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1.
Remark n = 0 to 2
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Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (2/3)
(b) TMQn control register 1 (TQnCTL1)
0
0/1
0/1
0
0
TQnCTL1
0: Operate on count
clock selected by
TQnCKS0 to TQnCKS2 bits
1: Count with external
event input signal
Generate software trigger
when 1 is written
0
1
0
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
0, 1, 0:
External trigger pulse
output mode
(c) TMQn I/O control register 0 (TQnIOC0)
0/1
0/1
0/1
0/1
0/1
TQnIOC0
0: Disable TOQn0 pin output
1: Enable TOQn0 pin output
Setting of output level while
operation of TOQn0 pin is disabled
0: Low level
1: High level
0: Disable TOQn1 pin output
1: Enable TOQn1 pin output
Specification of active level
of TOQn1 pin output
0: Active-high
1: Active-low
0/1
0/1
0/1
Note
TQnOE1 TQnOL0
TQnOE0
TQnOL1
TOQnk pin output
16-bit counter
When TQnOLk bit = 0
TOQnk pin output
16-bit counter
When TQnOLk bit = 1
TQnOE3 TQnOL2
TQnOE2
TQnOL3
Specification of active level
of TOQn3 pin output
0: Active-high
1: Active-low
0: Disable TOQn2 pin output
1: Enable TOQn2 pin output
Specification of active level
of TOQn2 pin output
0: Active-high
1: Active-low
0: Disable TOQn3 pin output
1: Enable TOQn3 pin output
Note Clear this bit to 0 when the TOQn0 pin is not used in the external trigger pulse output mode.
Remark n = 0 to 2
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Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3)
(d) TMQn I/O control register 2 (TQnIOC2)
0
0
0
0
0/1
TQnIOC2
Select valid edge of
external trigger input
Select valid edge of
external event count input
0/1
0/1
0/1
TQnEES0 TQnETS1 TQnETS0
TQnEES1
(e) TMQn counter read buffer register (TQnCNT)
The value of the 16-bit counter can be read by reading the TQnCNT register.
(f) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
If D
0
is set to the TQnCCR0 register, D
1
to the TQnCCR1 register, D
2
to the TQnCCR2 register, and D
3
,
to the TQnCCR3 register, the cycle and active level of the PWM waveform are as follows.
Cycle = (D
0
+ 1)
Count clock cycle
TOQn1 pin PWM waveform active level width = D
1
Count clock cycle
TOQn2 pin PWM waveform active level width = D
2
Count clock cycle
TOQn3 pin PWM waveform active level width = D
3
Count clock cycle
Remarks 1. TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not
used in the external trigger pulse output mode.
2. Updating TMQn capture/compare register 2 (TQnCCR2) and TMQn capture/compare
register 3 (TQnCCR3) is validated by writing TMQn capture/compare register 1 (TQnCCR1).
3. n = 0 to 2
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(1) Operation flow in external trigger pulse output mode
Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2)
D
10
D
10
D
10
D
20
D
30
D
00
D
11
D
21
D
01
D
31
D
11
D
21
D
00
D
31
D
20
D
30
D
00
D
21
D
00
D
31
D
11
D
21
D
00
D
31
FFFFH
16-bit counter
0000H
TQnCE bit
External trigger input
(TIQn0 pin input)
TQnCCR0 register
CCR0 buffer register
INTTQnCC0 signal
TOQn0 pin output
(only when software
trigger is used)
TQnCCR1 register
CCR1 buffer register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
CCR2 buffer register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
CCR3 buffer register
INTTQnCC3 signal
TOQn3 pin output
D
00
D
01
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
10
D
11
D
10
D
11
D
10
D
11
D
20
D
21
D
20
D
21
D
20
D
21
D
21
D
30
D
31
D
30
D
31
D
30
D
31
D
30
D
31
<1>
<2> <3>
<4>
<5>
<6>
<7>
D
11
D
11
D
20
D
10
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2)
START
<1> Count operation start flow
TQnCE bit = 1
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC0 register,
TQnIOC2 register,
TQnCCR0 to TQnCCR3
registers
Initial setting of these
registers is performed
before setting the
TQnCE bit to 1.
Writing of the TQnCCR1
register must be performed
when the set duty factor is only
changed after writing the
TQnCCR2 and TQnCCR3
registers.
When the counter is cleared
after setting, the value of the
TQnCCRm register is transferred
to the CCRm buffer register.
TQnCCR1 register writing of the
same value is necessary only
when the set duty factor of
TOQn2 and TOQn3 pin
outputs is changed.
When the counter is
cleared after setting,
the value of the TQnCCRm
register is transferred to
the CCRm buffer register.
Only writing of the TQnCCR1
register must be performed when
the set duty factor is only changed.
When counter is cleared after
setting, the value of the TQnCCRm
register is transferred to the CCRm
buffer register.
Counting is stopped.
The TQnCKS0 to
TQnCKS2 bits can be
set at the same time
when counting is
enabled (TQnCE bit = 1).
Trigger wait status
Writing of the TQnCCR1
register must be performed
after writing the TQnCCR0,
TQnCCR2, and TQnCCR3
registers.
When the counter is cleared
after setting, the value
of the TQnCCRm register is
transferred to the CCRm buffer
registers.
TQnCCR1 register writing
of the same value is
necessary only when the
set cycle is changed.
<2> TQnCCR0 to TQnCCR3 register
setting change flow
<3> TQnCCR0 register setting change flow
<4> TQnCCR1 to TQnCCR3 register
setting change flow
<5> TQnCCR2, TQnCCR3 register
setting change flow
<6> TQnCCR1 register setting change flow
<7> Count operation stop flow
TQnCE bit = 0
Setting of TQnCCR2,
TQnCCR3 registers
Setting of TQnCCR1 register
Setting of TQnCCR2,
TQnCCR3 registers
Setting of TQnCCR1 register
STOP
Setting of TQnCCR1 register
Setting of TQnCCR0 register
Setting of TQnCCR1 register
Setting of TQnCCR0, TQnCCR2,
and TQnCCR3 registers
TQnCCR1 register
When the counter is
cleared after setting,
the value of the TQnCCRm
register is transferred to
the CCRm buffer register.
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(2) External trigger pulse output mode operation timing
(a) Note on changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TQnCCR1 register last.
Rewrite the TQnCCRk register after writing the TQnCCR1 register after the INTTQnCC0 signal is detected.
FFFFH
16-bit counter
0000H
TQnCE bit
External trigger input
(TIQn0 pin input)
D
30
D
00
D
01
D
30
D
30
D
20
D
20
D
20
D
21
D
11
D
00
D
00
D
31
D
01
D
01
D
21
D
11
D
31
TQnCCR0 register
CCR0 buffer register
INTTQnCC0 signal
TQnCCR1 register
CCR1 buffer register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
CCR2 buffer register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
CCR3 buffer register
INTTQnCC3 signal
TOQn3 pin output
TOQn0 pin output
(only when software
trigger is used)
D
10
D
10
D
10
D
00
D
11
D
10
D
11
D
10
D
21
D
20
D
21
D
20
D
31
D
30
D
31
D
30
D
00
D
01
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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In order to transfer data from the TQnCCRm register to the CCRm buffer register, the TQnCCR1 register
must be written.
To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the
TQnCCR0 register, set the active level width to the TQnCCR2 and TQnCCR3 registers, and then set an
active level to the TQnCCR1 register.
To change only the cycle of the PWM waveform, first set the cycle to the TQnCCR0 register, and then write
the same value to the TQnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform, first set an active level to the
TQnCCR2 and TQnCCR3 registers and then set an active level to the TQnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform output by the TOQn1 pin, only the
TQnCCR1 register has to be set.
To change only the active level width (duty factor) of the PWM waveform output by the TOQn2 and TOQn3
pins, first set an active level width to the TQnCCR2 and TQnCCR3 registers, and then write the same
value to the TQnCCR1 register.
After data is written to the TQnCCR1 register, the value written to the TQnCCRm register is transferred to
the CCRm buffer register in synchronization with clearing of the 16-bit counter, and is used as the value
compared with the 16-bit counter.
To write the TQnCCR0 to TQnCCR3 registers again after writing the TQnCCR1 register once, do so after
the INTTQnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become
undefined because timing of transferring data from the TQnCCRm register to the CCRm buffer register
conflicts with writing the TQnCCRm register.
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TQnCCRk register to 0000H. If the set value of the TQnCCR0 register is
FFFFH, the INTTQnCCk signal is generated periodically.
Count clock
16-bit counter
TQnCE bit
TQnCCR0 register
TQnCCRk register
INTTQnCC0 signal
INTTQnCCk signal
TOQnk pin output
D
0
0000H
D
0
0000H
D
0
0000H
D
0
- 1
D
0
0000
FFFF
0000
D
0
- 1
D
0
0000
0001
L
Remark k = 1 to 3,
n = 0 to 2
To output a 100% waveform, set a value of (set value of TQnCCR0 register + 1) to the TQnCCRk register.
If the set value of the TQnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TQnCE bit
TQnCCR0 register
TQnCCRk register
INTTQnCC0 signal
INTTQnCCk signal
TOQnk pin output
D
0
D
0
+ 1
D
0
D
0
+ 1
D
0
D
0
+ 1
D
0
- 1
D
0
0000
FFFF
0000
D
0
- 1
D
0
0000
0001
Remark k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(c) Conflict between trigger detection and match with CCRk buffer register
If the trigger is detected immediately after the INTTQnCCk signal is generated, the 16-bit counter is
immediately cleared to 0000H, the output signal of the TOQnk pin is asserted, and the counter continues
counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
CCRk buffer register
INTTQnCCk signal
TOQnk pin output
External trigger input
(TIQn0 pin input)
D
k
D
k
- 1
0000
FFFF
0000
Shortened
D
k
Remark k = 1 to 3,
n = 0 to 2
If the trigger is detected immediately before the INTTQnCCk signal is generated, the INTTQnCCk signal is
not generated, and the 16-bit counter is cleared to 0000H and continues counting. The output signal of the
TOQnk pin remains active. Consequently, the active period of the PWM waveform is extended.
16-bit counter
CCRk buffer register
INTTQnCCk signal
TOQnk pin output
External trigger input
(TIQn0 pin input)
D
k
D
k
- 2
D
k
- 1
D
k
0000
FFFF
0000
0001
Extended
Remark k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(d) Conflict between trigger detection and match with CCR0 buffer register
If the trigger is detected immediately after the INTTQnCC0 signal is generated, the 16-bit counter is
cleared to 0000H and continues counting up. Therefore, the active period of the TOQnk pin is extended by
time from generation of the INTTQnCC0 signal to trigger detection.
16-bit counter
CCR0 buffer register
INTTQnCC0 signal
TOQnk pin output
External trigger input
(TIQn0 pin input)
D
0
D
0
- 1
D
0
0000
FFFF
0000
0000
Extended
Remark k = 1 to 3,
n = 0 to 2
If the trigger is detected immediately before the INTTQnCC0 signal is generated, the INTTQnCC0 signal is
not generated. The 16-bit counter is cleared to 0000H, the TOQnk pin is asserted, and the counter
continues counting. Consequently, the inactive period of the PWM waveform is shortened.
16-bit counter
CCR0 buffer register
INTTQnCC0 signal
TOQnk pin output
External trigger input
(TIQn0 pin input)
D
0
D
0
- 1
D
0
0000
FFFF
0000
0001
Shortened
Remark k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(e) Generation timing of compare match interrupt request signal (INTTQnCCk)
The timing of generation of the INTTQnCCk signal in the external trigger pulse output mode differs from
the timing of other INTTQnCCk signals; the INTTQnCCk signal is generated when the count value of the
16-bit counter matches the value of the CCRk buffer register.
Count clock
16-bit counter
CCRk buffer register
TOQnk pin output
INTTQnCCk signal
D
k
D
k
- 2
D
k
- 1
D
k
D
k
+ 1
D
k
+ 2
Remark k = 1 to 3,
n = 0 to 2
Usually, the INTTQnCCk signal is generated in synchronization with the next count up after the count value
of the 16-bit counter matches the value of the CCRk buffer register.
In the external trigger pulse output mode, however, it is generated one clock earlier. This is because the
timing is changed to match the timing of changing the output signal of the TOQnk pin.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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8.5.4
One-shot pulse output mode (TQnMD2 to TQnMD0 bits = 011)
In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQnCTL0.TQnCE bit is
set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and
outputs a one-shot pulse from the TOQn1 to TOQn3 pins.
Instead of the external trigger, a software trigger can also be generated to output the pulse. When the software
trigger is used, the TOQn0 pin outputs the active level while the 16-bit counter is counting, and the inactive level when
the counter is stopped (waiting for a trigger).
Figure 8-20. Configuration in One-Shot Pulse Output Mode
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Clear
Match signal
INTTQnCC0 signal
TOQn3 pin
INTTQnCC3 signal
TOQn0 pin
TIQn0 pin
Transfer
S
R
S
R
TQnCCR1
register
CCR1 buffer
register
Match signal
TOQn1 pin
INTTQnCC1 signal
Transfer
Transfer
S
R
TQnCCR3
register
CCR3 buffer
register
Match signal
Transfer
TOQn2 pin
INTTQnCC2 signal
S
R
TQnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count clock
selection
Count start
control
Edge
detector
Software trigger
generation
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-21. Basic Timing in One-Shot Pulse Output Mode
D
0
D
1
D
2
D
3
D
1
D
2
D
3
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
D
0
Delay
(D
1
)
Active
level width
(D
0
- D
1
+ 1)
Delay
(D
1
)
Active
level width
(D
0
- D
1
+ 1)
Delay
(D
1
)
Active
level width
(D
0
- D
1
+ 1)
Delay
(D
2
)
Active
level width
(D
0
- D
2
+ 1)
Delay
(D
2
)
Active
level width
(D
0
- D
2
+ 1)
Delay
(D
2
)
Active
level width
(D
0
- D
2
+ 1)
Delay
(D
3
)
Active
level width
(D
0
- D
3
+ 1)
Delay
(D
3
)
Active
level width
(D
0
- D
3
+ 1)
Delay
(D
3
)
Active
level width
(D
0
- D
3
+ 1)
FFFFH
16-bit counter
0000H
TQnCE bit
External trigger input
(TIQn0 pin input)
TQnCCR0 register
INTTQnCC0 signal
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
TQnCCR1 register
INTTQnCC1 signal
TOQn1 pin output
TOQn0 pin output
(only when software
trigger is used)
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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When the TQnCE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQnk pin.
After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a
trigger is generated again while the one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TQnCCRk register)
Count clock cycle
Active level width = (Set value of TQnCCR0 register
- Set value of TQnCCRk register + 1) Count clock cycle
The compare match interrupt request signal INTTQnCC0 is generated when the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTQnCCk)
is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
The valid edge of an external trigger input or setting the software trigger (TQnCTL1.TQnEST bit) to 1 is used as the
trigger.
Remark k = 1 to 3,
n = 0 to 2
Figure 8-22. Setting of Registers in One-Shot Pulse Output Mode (1/3)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
(b) TMQn control register 1 (TQnCTL1)
0
0/1
0/1
0
0
TQnCTL1
0: Operate on count clock
selected by TQnCKS0 to
TQnCKS2 bits
1: Count external event
input signal
Generate software trigger
when 1 is written
0
1
1
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
0, 1, 1:
One-shot pulse output mode
Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1.
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-22. Register Setting in One-Shot Pulse Output Mode (2/3)
(c) TMQn I/O control register 0 (TQnIOC0)
TOQnk pin output
16-bit counter
When TQnOLk bit = 0
TOQnk pin output
16-bit counter
When TQnOLk bit = 1
0/1
0/1
0/1
0/1
0/1
TQnIOC0
0: Disable TOQn0 pin output
1: Enable TOQn0 pin output
Setting of output level while
operation of TOQn0 pin is disabled
0: Low level
1: High level
0: Disable TOQn1 pin output
1: Enable TOQn1 pin output
Specification of active level
of TOQn1 pin output
0: Active-high
1: Active-low
0/1
0/1
0/1
Note
TQnOE1 TQnOL0
TQnOE0
TQnOL1
TQnOE3 TQnOL2
TQnOE2
TQnOL3
Specification of active level
of TOQn3 pin output
0: Active-high
1: Active-low
0: Disable TOQn2 pin output
1: Enable TOQn2 pin output
Specification of active level
of TOQn2 pin output
0: Active-high
1: Active-low
0: Disable TOQn3 pin output
1: Enable TOQn3 pin output
(d) TMQn I/O control register 2 (TQnIOC2)
0
0
0
0
0/1
TQnIOC2
Select valid edge of
external trigger input
Select valid edge of
external event count input
0/1
0/1
0/1
TQnEES0 TQnETS1 TQnETS0
TQnEES1
Note Clear this bit to 0 when the TOQn0 pin is not used in the one-shot pulse output mode.
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-22. Register Setting in One-Shot Pulse Output Mode (3/3)
(e) TMQn counter read buffer register (TQnCNT)
The value of the 16-bit counter can be read by reading the TQnCNT register.
(f) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
If D
0
is set to the TQnCCR0 register and D
k
to the TQnCCRk register, the active level width and output
delay period of the one-shot pulse are as follows.
Active level width = (D
k
- D
0
+ 1)
Count clock cycle
Output delay period = (D
k
)
Count clock cycle
Remarks 1. TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not
used in the one-shot pulse output mode.
2.
k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(1) Operation flow in one-shot pulse output mode
Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2)
FFFFH
16-bit counter
0000H
TQnCE bit
External trigger input
(TIQn0 pin input)
TQnCCR0 register
INTTQnCC0 signal
TOQn0 pin output
(only when software
trigger is used)
TQnCCR1 register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
D
00
D
01
D
11
D
10
D
21
D
20
D
31
D
30
D
10
D
20
D
30
D
11
D
21
D
31
D
00
D
01
<3>
<1>
<2>
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2)
TQnCE bit = 1
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC0 register,
TQnIOC2 register,
TQnCCR0 to TQnCCR3 registers
Initial setting of these
registers is performed
before setting the
TQnCE bit to 1.
The TQnCKS0 to
TQnCKS2 bits can be
set at the same time
when counting has been
started (TQnCE bit = 1).
Trigger wait status
START
<1> Count operation start flow
TQnCE bit = 0
Count operation is
stopped
STOP
<3> Count operation stop flow
Setting of TQnCCR0 to TQnCCR3
registers
As rewriting the
TQnCCRm register
immediately forwards
to the CCRm buffer
register, rewriting
immediately after
the generation of the
INTTQnCCR0 signal
is recommended.
<2> TQnCCR0 to TQnCCR3 register setting change flow
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(2) Operation timing in one-shot pulse output mode
(a) Note on rewriting TQnCCRm register
To change the set value of the TQnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TQnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
D
k0
D
k1
D
01
D
01
D
00
D
k1
D
01
D
k0
D
k0
D
k1
D
00
D
00
FFFFH
16-bit counter
0000H
TQnCE bit
External trigger input
(TIQn0 pin input)
TQnCCR0 register
INTTQnCC0 signal
TOQn0 pin output
(only when software
trigger is used)
TQnCCRk register
INTTQnCCk signal
TOQnk pin output
Delay
(D
k0
)
Active level width
(D
00
- D
k0
+ 1)
Active level width
(D
01
- D
k1
+ 1)
Active level width
(D
01
- D
k1
+ 1)
Delay
(D
k1
)
Delay
(10000H + D
k1
)
When the TQnCCR0 register is rewritten from D
00
to D
01
and the TQnCCRk register from D
k0
to D
k1
where
D
00
> D
01
and D
k0
> D
k1
, if the TQnCCRk register is rewritten when the count value of the 16-bit counter is
greater than D
k1
and less than D
k0
and if the TQnCCR0 register is rewritten when the count value is
greater than D
01
and less than D
00
, each set value is reflected as soon as the register has been rewritten
and compared with the count value. The counter counts up to FFFFH and then counts up again from
0000H. When the count value matches D
k1
, the counter generates the INTTQnCCk signal and asserts the
TOQnk pin. When the count value matches D
01
, the counter generates the INTTQnCC0 signal, deasserts
the TOQnk pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the
one-shot pulse that is originally expected.
Remark k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(b) Generation timing of compare match interrupt request signal (INTTQnCCk)
The generation timing of the INTTQnCCk signal in the one-shot pulse output mode is different from other
INTTQnCCk signals; the INTTQnCCk signal is generated when the count value of the 16-bit counter
matches the value of the TQnCCRk register.
Count clock
16-bit counter
TQnCCRk register
TOQnk pin output
INTTQnCCk signal
D
k
D
k
- 2
D
k
- 1
D
k
D
k
+ 1
D
k
+ 2
Usually, the INTTQnCCk signal is generated when the 16-bit counter counts up next time after its count
value matches the value of the TQnCCRk register.
In the one-shot pulse output mode, however, it is generated one clock earlier. This is because the timing is
changed to match the change timing of the TOQnk pin.
Remark k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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8.5.5
PWM output mode (TQnMD2 to TQnMD0 bits = 100)
In the PWM output mode, a PWM waveform is output from the TOQn1 to TOQn3 pins when the TQnCTL0.TQnCE
bit is set to 1.
In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOQn0 pin.
Figure 8-24. Configuration in PWM Output Mode
CCR0 buffer register
TQnCE bit
TQnCCR0 register
Clear
Match signal
INTTQnCC0 signal
TOQn3 pin
INTTQnCC3 signal
TOQn0 pin
Transfer
S
R
TQnCCR1
register
CCR1 buffer
register
Match signal
TOQn1 pin
INTTQnCC1 signal
Transfer
Transfer
S
R
TQnCCR3
register
CCR3 buffer
register
Match signal
Transfer
TOQn2 pin
INTTQnCC2 signal
S
R
TQnCCR2
register
CCR2 buffer
register
Match signal
16-bit counter
Count
clock
selection
Count
start
control
Output
controller
(RS-FF)
Output
controller
Output
controller
(RS-FF)
Output
controller
(RS-FF)
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-25. Basic Timing in PWM Output Mode
D
0
D
1
D
2
D
3
D
1
D
2
D
3
D
0
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
D
0
D
1
D
2
D
3
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
TOQn0 pin output
TQnCCR1 register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
Active level
width (D
3
)
Cycle (D
0
+ 1)
Cycle (D
0
+ 1)
Cycle (D
0
+ 1)
Cycle (D
0
+ 1)
Active level
width (D
3
)
Active level
width (D
3
)
Active level
width (D
3
)
Active
level width
(D
1
)
Active
level width
(D
1
)
Active
level width
(D
1
)
Active
level width
(D
1
)
Active
level width
(D
2
)
Active
level width
(D
2
)
Active
level width
(D
2
)
Active
level width
(D
2
)
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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When the TQnCE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs
PWM waveform from the TOQnk pin.
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
Active level width = (Set value of TQnCCRk register)
Count clock cycle
Cycle = (Set value of TQnCCR0 register + 1)
Count clock cycle
Duty factor = (Set value of TQnCCRk register)/(Set value of TQnCCR0 register + 1)
The PWM waveform can be changed by rewriting the TQnCCRm register while the counter is operating. The newly
written value is reflected when the count value of the 16-bit counter matches the value of the CCR0 buffer register and
the 16-bit counter is cleared to 0000H.
The compare match interrupt request signal (INTTQnCC0) is generated when the 16-bit counter counts next time
after its count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The
compare match interrupt request signal (INTTQnCCk) is generated when the count value of the 16-bit counter
matches the value of the CCRk buffer register.
Remark k = 1 to 3,
m = 0 to 3,
n = 0 to 2
Figure 8-26. Setting of Registers in PWM Output Mode (1/3)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
(b) TMQn control register 1 (TQnCTL1)
0
0
0/1
0
0
TQnCTL1
1
0
0
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
1, 0, 0:
PWM output mode
0: Operate on count clock
selected by TQnCKS0 to
TQnCKS2 bits
1: Count external event
input signal
Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1.
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-26. Setting of Registers in PWM Output Mode (2/3)
(c) TMQn I/O control register 0 (TQnIOC0)
TOQnk pin output
16-bit counter
When TQnOLk bit = 0
TOQnk pin output
16-bit counter
When TQnOLk bit = 1
0/1
0/1
0/1
0/1
0/1
TQnIOC0
0: Disable TOQn0 pin output
1: Enable TOQn0 pin output
Setting of output level while
operation of TOQn0 pin is disabled
0: Low level
1: High level
0: Disable TOQn1 pin output
1: Enable TOQn1 pin output
Specification of active level of
TOQn1 pin output
0: Active-high
1: Active-low
0/1
0/1
0/1
Note
TQnOE1 TQnOL0
TQnOE0
TQnOL1
TQnOE3 TQnOL2
TQnOE2
TQnOL3
Specification of active level
of TOQn3 pin output
0: Active-high
1: Active-low
0: Disable TOQn2 pin output
1: Enable TOQn2 pin output
Specification of active level
of TOQn2 pin output
0: Active-high
1: Active-low
0: Disable TOQn3 pin output
1: Enable TOQn3 pin output
(d) TMQn I/O control register 2 (TQnIOC2)
0
0
0
0
0/1
TQnIOC2
Select valid edge
of external event
count input.
0/1
0
0
TQnEES0 TQnETS1 TQnETS0
TQnEES1
(e) TMQn counter read buffer register (TQnCNT)
The value of the 16-bit counter can be read by reading the TQnCNT register.
Note Clear this bit to 0 when the TOQn0 pin is not used in the PWM output mode.
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-26. Register Setting in PWM Output Mode (3/3)
(f) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
If D
0
is set to the TQnCCR0 register and D
k
to the TQnCCRk register, the cycle and active level of the
PWM waveform are as follows.
Cycle = (D
0
+ 1)
Count clock cycle
Active level width = D
k
Count clock cycle
Remarks 1. TMQn I/O control register 1 (TQnIOC1) and TMQn option register 0 (TQnOPT0) are not
used in the PWM output mode.
2. Updating the TMQn capture/compare register 2 (TQnCCR2) and TMQn capture/compare
register 3 (TQnCCR3) is validated by writing the TMQn capture/compare register 1
(TQnCCR1).
3. n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(1) Operation flow in PWM output mode
Figure 8-27. Software Processing Flow in PWM Output Mode (1/2)
D
10
D
10
D
10
D
20
D
30
D
00
D
11
D
21
D
01
D
31
D
11
D
21
D
00
D
31
D
20
D
30
D
00
D
21
D
00
D
31
D
11
D
21
D
00
D
31
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
CCR0 buffer register
INTTQnCC0 signal
TOQn0 pin output
TQnCCR1 register
CCR1 buffer register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
CCR2 buffer register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
CCR3 buffer register
INTTQnCC3 signal
TOQn3 pin output
D
00
D
01
D
00
D
00
D
01
D
00
D
10
D
11
D
10
D
10
D
11
D
10
D
11
D
10
D
11
D
11
D
20
D
21
D
20
D
21
D
20
D
21
D
21
D
30
D
31
D
30
D
31
D
30
D
31
D
30
D
31
<1>
<2> <3>
<4>
<5>
<6>
<7>
D
11
D
10
D
20
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-27. Software Processing Flow in PWM Output Mode (2/2)
START
<1> Count operation start flow
TQnCE bit = 1
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC0 register,
TQnIOC2 register,
TQnCCR0 to TQnCCR3
registers
Initial setting of these
registers is performed
before setting the
TQnCE bit to 1.
Only writing of the TQnCCR1
register must be performed
when the set duty factor is only
changed after writing the
TQnCCR2 and TQnCCR3
registers.
When the counter is cleared after
setting, the value of the
TQnCCRm register is transferred
to the CCRm buffer register.
TQnCCR1 register writing of the
same value is necessary only
when the set duty factor of
TOQn2 and TOQn3 pin
outputs is changed.
When the counter is
cleared after setting,
the value of the TQnCCRm
register is transferred to
the CCRm buffer register.
Only writing of the TQnCCR1
register must be performed when
the set duty factor is only changed.
When counter is cleared after
setting, the value of the TQnCCRm
register is transferred to the CCRm
buffer register.
Counting is stopped.
The TQnCKS0 to
TQnCKS2 bits can be
set at the same time
when counting is
enabled (TQnCE bit = 1).
Writing of the TQnCCR1
register must be performed
after writing the TQnCCR0,
TQnCCR2, and TQnCCR3
registers.
When the counter is cleared
after setting, the value
of the TQnCCRm register is
transferred to the CCRm buffer
registers.
TQnCCR1 writing
of the same value is
necessary only when the
set cycle is changed.
<2> TQnCCR0 to TQnCCR3 register
setting change flow
<3> TQnCCR0 register setting change flow
<4> TQnCCR1 to TQnCCR3 register
setting change flow
<5> TQnCCR2, TQnCCR3 register
setting change flow
<6> TQnCCR1 register setting change flow
<7> Count operation stop flow
TQnCE bit = 0
Setting of TQnCCR2,
TQnCCR3 registers
Setting of TQnCCR1 register
Setting of TQnCCR2,
TQnCCR3 registers
Setting of TQnCCR1 register
STOP
Setting of TQnCCR1 register
Setting of TQnCCR0 register
Setting of TQnCCR1 register
Setting of TQnCCR0, TQnCCR2,
and TQnCCR3 registers
TQnCCR1 register
When the counter is
cleared after setting, the
value of the TQnCCRm
register is transferred to
the CCRm buffer register.
Remark k = 1 to 3,
m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(2) PWM output mode operation timing
(a) Changing pulse width during operation
To change the PWM waveform while the counter is operating, write the TQnCCR1 register last.
Rewrite the TQnCCRk register after writing the TQnCCR1 register after the INTTQnCC1 signal is detected.
FFFFH
16-bit counter
0000H
TQnCE bit
D
30
D
00
D
01
D
30
D
30
D
20
D
20
D
20
D
21
D
11
D
00
D
00
D
31
D
01
D
01
D
21
D
11
D
31
TQnCCR0 register
CCR0 buffer register
INTTQnCC0 signal
TQnCCR1 register
CCR1 buffer register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
CCR2 buffer register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
CCR3 buffer register
INTTQnCC3 signal
TOQn3 pin output
TOQn0 pin output
D
10
D
10
D
10
D
00
D
11
D
10
D
11
D
10
D
21
D
20
D
21
D
20
D
31
D
30
D
31
D
30
D
00
D
01
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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To transfer data from the TQnCCRm register to the CCRm buffer register, the TQnCCR1 register must be
written.
To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the
TQnCCR0 register, set the active level width to the TQnCCR2 and TQnCCR3 registers, and then set an
active level width to the TQnCCR1 register.
To change only the active level width (duty factor) of PWM wave, first set the active level to the TQnCCR2
and TQnCCR3 registers, and then set an active level to the TQnCCR1 register.
To change only the active level width (duty factor) of the PWM waveform output by the TOQn1 pin, only the
TQnCCR1 register has to be set.
To change only the active level width (duty factor) of the PWM waveform output by the TOQn2 and TOQn3
pins, first set an active level width to the TQnCCR2 and TQnCCR3 registers, and then write the same
value to the TQnCCR1 register.
After the TQnCCR1 register is written, the value written to the TQnCCRm register is transferred to the
CCRm buffer register in synchronization with the timing of clearing the 16-bit counter, and is used as a
value to be compared with the value of the 16-bit counter.
To change only the cycle of the PWM waveform, first set a cycle to the TQnCCR0 register, and then write
the same value to the TQnCCR1 register.
To write the TQnCCR0 to TQnCCR3 registers again after writing the TQnCCR1 register once, do so after
the INTTQnCC0 signal is generated. Otherwise, the value of the CCRm buffer register may become
undefined because the timing of transferring data from the TQnCCRm register to the CCRm buffer register
conflicts with writing the TQnCCRm register.
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(b) 0%/100% output of PWM waveform
To output a 0% waveform, set the TQnCCRk register to 0000H. If the set value of the TQnCCR0 register is
FFFFH, the INTTQnCCk signal is generated periodically.
Count clock
16-bit counter
TQnCE bit
TQnCCR0 register
TQnCCRk register
INTTQnCC0 signal
INTTQnCCk signal
TOQnk pin output
D
0
0000H
D
0
0000H
D
0
0000H
D
0
- 1
D
0
0000
FFFF
0000
D
0
- 1
D
0
0000
0001
Remark k = 1 to 3,
n = 0 to 2
To output a 100% waveform, set a value of (set value of TQnCCR0 register + 1) to the TQnCCRk register.
If the set value of the TQnCCR0 register is FFFFH, 100% output cannot be produced.
Count clock
16-bit counter
TQnCE bit
TQnCCR0 register
TQnCCRk register
INTTQnCC0 signal
INTTQnCCk signal
TOQnk pin output
D
0
D
0
+ 1
D
0
D
0
+ 1
D
0
D
0
+ 1
D
0
- 1
D
0
0000
FFFF
0000
D
0
- 1
D
0
0000
0001
Remark k = 1 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(c) Generation timing of compare match interrupt request signal (INTTQnCCk)
The timing of generation of the INTTQnCCk signal in the PWM output mode differs from the timing of other
INTTQnCCk signals; the INTTQnCCk signal is generated when the count value of the 16-bit counter
matches the value of the TQnCCRk register.
Count clock
16-bit counter
CCRk buffer register
TOQnk pin output
INTTQnCCk signal
D
k
D
k
- 2
D
k
- 1
D
k
D
k
+ 1
D
k
+ 2
Remark k = 1 to 3,
n = 0 to 2
Usually, the INTTQnCCk signal is generated in synchronization with the next counting up after the count
value of the 16-bit counter matches the value of the TQnCCRk register.
In the PWM output mode, however, it is generated one clock earlier. This is because the timing is changed
to match the change timing of the output signal of the TOQnk pin.
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8.5.6
Free-running timer mode (TQnMD2 to TQnMD0 bits = 101)
In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQnCTL0.TQnCE bit is set to
1. At this time, the TQnCCRm register can be used as a compare register or a capture register, depending on the
setting of the TQnOPT0.TQnCCS0 and TQnOPT0.TQnCCS1 bits.
Remark m = 0 to 3,
n = 0 to 2
Figure 8-28. Configuration in Free-Running Timer Mode
TOQn3 pin output
TOQn2 pin output
TOQn1 pin output
TOQn0 pin output
INTTQnOV signal
TQnCCS0,
TQnCCS1 bits
(capture/compare
selection)
INTTQnCC3 signal
INTTQnCC2 signal
INTTQnCC1 signal
INTTQnCC0 signal
TIQn3 pin
(capture
trigger input)
TQnCCR3
register
(capture)
TIQn0pin
(external event
count input/
capture
trigger input)
Internal count clock
TQnCE
bit
TIQn1 pin
(capture
trigger input)
TIQn2 pin
(capture
trigger input)
TQnCCR0
register
(capture)
TQnCCR1
register
(capture)
TQnCCR2
register
(capture)
TQnCCR3
register
(compare)
TQnCCR2
register
(compare)
TQnCCR1
register
(compare)
0
1
0
1
0
1
0
1
16-bit counter
TQnCCR0
register
(compare)
Output
controller
Output
controller
Output
controller
Output
controller
Count
clock
selection
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Edge
detector
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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When the TQnCE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQn0
to TOQn3 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQnCCRm
register, a compare match interrupt request signal (INTTQnCCm) is generated, and the output signal of the TOQnm
pin is inverted.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
The TQnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected
at that time, and compared with the count value.
Figure 8-29. Basic Timing in Free-Running Timer Mode (Compare Function)
D
10
D
20
D
30
D
00
D
20
D
31
D
31
D
30
D
00
D
11
D
11
D
21
D
01
D
11
D
21
D
01
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TOQn1 pin output
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
INTTQnOV signal
TQnOVF bit
TOQn0 pin output
TQnCCR1 register
INTTQnCC1 signal
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
D
00
D
01
D
11
D
10
D
21
D
20
D
31
D
30
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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When the TQnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQnm pin is
detected, the count value of the 16-bit counter is stored in the TQnCCRm register, and a capture interrupt request
signal (INTTQnCCm) is generated.
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
generates an overflow interrupt request signal (INTTQnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TQnOVF bit) is also set to 1. Clear the overflow flag to 0 by executing the
CLR instruction by software.
Figure 8-30. Basic Timing in Free-Running Timer Mode (Capture Function)
D
20
D
00
D
30
D
10
D
11
D
21
D
31
D
12
D
01
D
02
D
22
D
32
D
03
D
13
D
33
D
23
0000
D
00
D
01
D
02
D
03
0000
D
10
D
11
D
12
D
13
0000
D
20
D
21
D
23
D
22
0000
D
30
D
31
D
32
D
33
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TIQn2 pin input
TQnCCR2 register
INTTQnCC2 signal
TIQn3 pin input
TQnCCR3 register
INTTQnCC3 signal
INTTQnOV signal
TQnOVF bit
TIQn1 pin input
TQnCCR1 register
INTTQnCC1 signal
TQnCE bit
TIQn0 pin input
TQnCCR0 register
INTTQnCC0 signal
Remark n = 0 to 2
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Figure 8-31. Register Setting in Free-Running Timer Mode (1/3)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
Note The setting is invalid when the TQnCTL1.TQnEEE bit = 1
(b) TMQn control register 1 (TQnCTL1)
0
0
0/1
0
0
TQnCTL1
1
0
1
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
1, 0, 1:
Free-running mode
0: Operate with count
clock selected by
TQnCKS0 to TQnCKS2 bits
1: Count on external
event count input signal
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-31. Register Setting in Free-Running Timer Mode (2/3)
(c) TMQn I/O control register 0 (TQnIOC0)
0/1
0/1
0/1
0/1
0/1
TQnIOC0
0: Disable TOQn0 pin output
1: Enable TOQn0 pin output
0: Disable TOQn1 pin output
1: Enable TOQn1 pin output
Setting of output level with
operation of TOQn1 pin
disabled
0: Low level
1: High level
0/1
0/1
0/1
TQnOE1 TQnOL0
TQnOE0
TQnOL1
TQnOE3 TQnOL2
TQnOE2
TQnOL3
Setting of output level with
operation of TOQn3 pin
disabled
0: Low level
1: High level
0: Disable TOQn2 pin output
1: Enable TOQn2 pin output
Setting of output level with
operation of TOQn2 pin
disabled
0: Low level
1: High level
0: Disable TOQn3 pin output
1: Enable TOQn3 pin output
Setting of output level with
operation of TOQn0 pin disabled
0: Low level
1: High level
(d) TMQn I/O control register 1 (TQnIOC1)
0/1
0/1
0/1
0/1
0/1
TQnIOC1
Select valid edge
of TIQn0 pin input
Select valid edge
of TIQn1 pin input
0/1
0/1
0/1
TQnIS2
TQnIS1
TQnIS0
TQnIS3
TQnIS6
TQnIS5
TQnIS4
TQnIS7
Select valid edge
of TIQn2 pin input
Select valid edge
of TIQn3 pin input
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-31. Register Setting in Free-Running Timer Mode (3/3)
(e) TMQn I/O control register 2 (TQnIOC2)
0
0
0
0
0/1
TQnIOC2
Select valid edge of
external event count input
0/1
0
0
TQnEES0 TQnETS1 TQnETS0
TQnEES1
(f) TMQn option register 0 (TQnOPT0)
0/1
0/1
0/1
0/1
0
TQnOPT0
Overflow flag
Specifies if TQnCCR0
register functions as
capture or compare register
Specifies if TQnCCR1
register functions as
capture or compare register
0
0
0/1
TQnCCS0
TQnOVF
TQnCCS1
TQnCCS2
TQnCCS3
Specifies if TQnCCR2
register functions as
capture or compare register
Specifies if TQnCCR3
register functions as
capture or compare register
(g) TMQn counter read buffer register (TQnCNT)
The value of the 16-bit counter can be read by reading the TQnCNT register.
(h) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
These registers function as capture registers or compare registers depending on the setting of the
TQnOPT0.TQnCCSm bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIQnm pin is detected.
When the registers function as compare registers and when D
m
is set to the TQnCCRm register, the
INTTQnCCm signal is generated when the counter reaches (D
m
+ 1), and the output signal of the
TOQnm pin is inverted.
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(1) Operation flow in free-running timer mode
(a) When using capture/compare register as compare register
Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2)
D
10
D
20
D
30
D
00
D
10
D
20
D
30
D
00
D
11
D
31
D
01
D
21
D
21
D
11
D
11
D
31
D
01
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
TOQn0 pin output
TQnCCR1 register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
INTTQnOV signal
TQnOVF bit
D
00
D
10
D
20
D
30
D
01
D
11
D
21
D
31
Cleared to 0 by
CLR instruction
Set value changed
Set value changed
Set value changed
Set value changed
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<3>
<1>
<2>
<2>
<2>
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
TQnCE bit = 1
Read TQnOPT0 register
(check overflow flag).
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC0 register,
TQnIOC2 register,
TQnOPT0 register,
TQnCCR0 to TQnCCR3 registers
Initial setting of these registers
is performed before setting the
TQnCE bit to 1.
The TQnCKS0 to TQnCKS2 bits
can be set at the same time
when counting has been started
(TQnCE bit = 1).
START
Execute instruction to clear
TQnOVF bit (CLR TQnOVF).
<1> Count operation start flow
<2> Overflow flag clear flow
TQnCE bit = 0
Counter is initialized and
counting is stopped by
clearing TQnCE bit to 0.
STOP
<3> Count operation stop flow
TQnOVF bit = 1
NO
YES
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(b) When using capture/compare register as capture register
Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2)
D
20
D
00
D
30
D
10
D
11
D
21
D
31
D
12
D
01
D
02
D
22
D
32
D
03
D
13
D
33
D
23
0000
D
00
D
01
D
02
D
03
0000
0000
0000
0000
0000
D
10
D
11
D
12
D
13
0000
D
20
D
21
D
23
D
22
0000
D
30
D
31
D
32
D
33
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
<3>
<1>
<2>
<2>
<2>
FFFFH
16-bit counter
0000H
TQnCE bit
TIQn2 pin input
TQnCCR2 register
INTTQnCC2 signal
TIQn3 pin input
TQnCCR3 register
INTTQnCC3 signal
INTTQnOV signal
TQnOVF bit
TIQn1 pin input
TQnCCR1 register
INTTQnCC1 signal
TIQn0 pin input
TQnCCR0 register
INTTQnCC0 signal
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2)
TQnCE bit = 1
Read TQnOPT0 register
(check overflow flag).
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits)
TQnCTL1 register,
TQnIOC1 register,
TQnOPT0 register
Initial setting of these registers
is performed before setting the
TQnCE bit to 1.
The TQnCKS0 to TQnCKS2 bits can
be set at the same time when counting
has been started (TQnCE bit = 1).
START
Execute instruction to clear
TQnOVF bit (CLR TQnOVF).
<1> Count operation start flow
<2> Overflow flag clear flow
TQnCE bit = 0
Counter is initialized and
counting is stopped by
clearing TQnCE bit to 0.
STOP
<3> Count operation stop flow
TQnOVF bit = 1
NO
YES
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter Q is used as an interval timer with the TQnCCRm register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTQnCCm signal has been detected.
D
00
D
10
D
20
D
01
D
30
D
12
D
03
D
22
D
31
D
21
D
23
D
02
D
13
FFFFH
16-bit counter
0000H
TQnCE bit
TQnCCR0 register
INTTQnCC0 signal
TOQn0 pin output
TQnCCR1 register
INTTQnCC1 signal
TOQn1 pin output
TQnCCR2 register
INTTQnCC2 signal
TOQn2 pin output
TQnCCR3 register
INTTQnCC3 signal
TOQn3 pin output
Interval period
(D
00
+ 1)
Interval period
(10000H +
D
02
- D
01
)
Interval period
(D
01
- D
00
)
Interval period
(D
03
- D
02
)
Interval period
(D
04
- D
03
)
D
00
D
01
D
02
D
03
D
04
D
05
Interval period
(D
10
+ 1)
Interval period
(10000H + D
12
- D
11
)
Interval period
(D
11
- D
10
)
Interval period
(D
13
- D
12
)
D
10
D
11
D
12
D
13
D
14
Interval period
(D
20
+ 1)
Interval period
(10000H + D
21
- D
20
)
Interval period
(10000H + D
23
- D
22
)
Interval period
(D
22
- D
21
)
Interval period
(D
30
+ 1)
Interval period
(10000H + D
31
- D
30)
D
20
D
21
D
22
D
23
D
31
D
30
D
32
D
04
D
11
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TQnCCRm register must be re-set in the
interrupt servicing that is executed when the INTTQnCCm signal is detected.
The set value for re-setting the TQnCCRm register can be calculated by the following expression, where
"D
m
" is the interval period.
Compare register default value: D
m
- 1
Value set to compare register second and subsequent time: Previous set value + D
m
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(b) Pulse width measurement with capture register
When pulse width measurement is performed with the TQnCCRm register used as a capture register,
software processing is necessary for reading the capture register each time the INTTQnCCm signal has
been detected and for calculating an interval.
D
20
D
00
D
30
D
10
D
11
D
21
D
31
D
12
D
01
D
02
D
32
D
13
D
03
D
22
D
33
D
23
0000
Pulse interval
(10000H +
D
01
- D
00
)
Pulse interval
(10000H +
D
02
- D
01
)
Pulse interval
(10000H +
D
03
- D
02
)
D
00
D
01
D
02
D
03
Pulse interval
(D
00
+ 1)
0000
Pulse interval
(10000H +
D
11
- D
10
)
Pulse interval
(10000H +
D
12
- D
11
)
Pulse interval
(D
13
- D
12
)
D
10
D
11
D
12
D
13
Pulse interval
(D
10
+ 1)
0000
Pulse interval
(10000H +
D
21
- D
20
)
Pulse interval
(20000H +
D
22
- D
21
)
Pulse interval
(D
23
- D
22
)
D
20
D
21
D
23
D
22
Pulse interval
(D
20
+ 1)
0000
Pulse interval
(10000H +
D
31
- D
30
)
Pulse interval
(10000H +
D
32
- D
31
)
Pulse interval
(10000H +
D
33
- D
32
)
D
30
D
31
D
32
D
33
Pulse interval
(D
30
+ 1)
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
Cleared to 0 by
CLR instruction
FFFFH
16-bit counter
0000H
TQnCE bit
TIQn0 pin input
TQnCCR0 register
INTTQnCC0 signal
TIQn2 pin input
TQnCCR2 register
INTTQnCC2 signal
TIQn3 pin input
TQnCCR3 register
INTTQnCC3 signal
INTTQnOV signal
TQnOVF bit
TIQn1 pin input
TQnCCR1 register
INTTQnCC1 signal
Remark n = 0 to 2
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When executing pulse width measurement in the free-running timer mode, four pulse widths can be
measured with one channel.
To measure a pulse width, the pulse width can be calculated by reading the value of the TQnCCRm
register in synchronization with the INTTQnCCm signal, and calculating the difference between the read
value and the previously read value.
Remark m = 0 to 3,
n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(c) Processing of overflow when two or more capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an
example of incorrect processing is shown below.
Example of incorrect processing when two or more capture registers are used
FFFFH
16-bit counter
0000H
TQnCE bit
TIQn0 pin input
TQnCCR0 register
TIQn1 pin input
TQnCCR1 register
INTTQnOV signal
TQnOVF bit
D
00
D
01
D
10
D
11
D
10
<1>
<2>
<3>
<4>
D
00
D
11
D
01
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TQnCCR0 register (setting of the default value of the TIQn0 pin input).
<2> Read the TQnCCR1 register (setting of the default value of the TIQn1 pin input).
<3> Read the TQnCCR0 register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
01
- D
00
).
<4> Read the TQnCCR1 register.
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
11
- D
10
) (incorrect).
Remark n = 0 to 2
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the
other capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(1/2)
Example when two capture registers are used (using overflow interrupt)
FFFFH
16-bit counter
0000H
TQnCE bit
INTTQnOV signal
TQnOVF bit
TQnOVF0 flag
Note
TIQn0 pin input
TQnCCR0 register
TQnOVF1 flag
Note
TIQn1 pin input
TQnCCR1 register
D
10
D
11
D
00
D
01
D
10
<1>
<2>
<5> <6>
<3>
<4>
D
00
D
11
D
01
Note The TQnOVF0 and TQnOVF1 flags are set on the internal RAM by software.
<1> Read the TQnCCR0 register (setting of the default value of the TIQn0 pin input).
<2> Read the TQnCCR1 register (setting of the default value of the TIQn1 pin input).
<3> An overflow occurs. Set the TQnOVF0 and TQnOVF1 flags to 1 in the overflow interrupt servicing,
and clear the overflow flag to 0.
<4> Read the TQnCCR0 register.
Read the TQnOVF0 flag. If the TQnOVF0 flag is 1, clear it to 0.
Because the TQnOVF0 flag is 1, the pulse width can be calculated by (10000H + D
01
- D
00
).
<5> Read the TQnCCR1 register.
Read the TQnOVF1 flag. If the TQnOVF1 flag is 1, clear it to 0 (the TQnOVF0 flag is cleared in
<4>, and the TQnOVF1 flag remains 1).
Because the TQnOVF1 flag is 1, the pulse width can be calculated by (10000H + D
11
- D
10
)
(correct).
<6> Same as <3>
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(2/2)
Example when two capture registers are used (without using overflow interrupt)
FFFFH
16-bit counter
0000H
TQnCE bit
INTTQnOV signal
TQnOVF bit
TQnOVF0 flag
Note
TIQn0 pin input
TQnCCR0 register
TQnOVF1 flag
Note
TIQn1 pin input
TQnCCR1 register
D
10
D
11
D
00
D
01
D
10
<1>
<2>
<5> <6>
<3>
<4>
D
00
D
11
D
01
Note The TQnOVF0 and TQnOVF1 flags are set on the internal RAM by software.
<1> Read the TQnCCR0 register (setting of the default value of the TIQn0 pin input).
<2> Read the TQnCCR1 register (setting of the default value of the TIQn1 pin input).
<3> An overflow occurs. Nothing is done by software.
<4> Read the TQnCCR0 register.
Read the overflow flag. If the overflow flag is 1, set only the TQnOVF1 flag to 1, and clear the
overflow flag to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
01
- D
00
).
<5> Read the TQnCCR1 register.
Read the overflow flag. Because the overflow flag is cleared in <4>, 0 is read.
Read the TQnOVF1 flag. If the TQnOVF1 flag is 1, clear it to 0.
Because the TQnOVF1 flag is 1, the pulse width can be calculated by (10000H + D
11
- D
10
)
(correct).
<6> Same as <3>
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an
overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect
processing is shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH
16-bit counter
0000H
TQnCE bit
TIQnm pin input
TQnCCRm register
INTTQnOV signal
TQnOVF bit
D
m0
D
m1
D
m0
D
m1
<1> <2>
<3> <4>
1 cycle of 16-bit counter
Pulse width
The following problem may occur when a long pulse width in the free-running timer mode.
<1> Read the TQnCCRm register (setting of the default value of the TIQnm pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TQnCCRm register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
m1
- D
m0
)
(incorrect).
Actually, the pulse width must be (20000H + D
m1
- D
m0
) because an overflow occurs twice.
Remark n = 0 to 2
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may
not be obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or
use software. An example of how to use software is shown next.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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Example when capture trigger interval is long
FFFFH
16-bit counter
0000H
TQnCE bit
TIQnm pin input
TQnCCRm register
INTTQnOV signal
TQnOVF bit
Overflow
counter
Note
D
m0
D
m1
1H
0H
2H
0H
D
m0
D
m1
<1> <2>
<3> <4>
1 cycle of 16-bit counter
Pulse width
Note The overflow counter is set arbitrarily by software on the internal RAM.
<1> Read the TQnCCRm register (setting of the default value of the TIQnm pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
interrupt servicing.
<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag
to 0 in the overflow interrupt servicing.
<4> Read the TQnCCRm register.
Read the overflow counter.
When the overflow counter is "N", the pulse width can be calculated by (N 10000H + D
m1
D
m0
).
In this example, the pulse width is (20000H + D
m1
D
m0
) because an overflow occurs twice.
Clear the overflow counter (0H).
Remark n = 0 to 2
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ)
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(e) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TQnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TQnOPT0 register. To accurately detect an overflow, read the TQnOVF
bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
(iii) Operation to clear to 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TQnOVF bit)
Read
Write
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TQnOVF bit)
Read
Write
0 write signal
Overflow
set signal
0 write signal
Overflow
set signal
Overflow flag
(TQnOVF bit)
Overflow flag
(TQnOVF bit)
L
H
L
Remark n = 0 to 2
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear
instruction.
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8.5.7
Pulse width measurement mode (TQnMD2 to TQnMD0 bits = 110)
In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQnCTL0.TQnCE bit
is set to 1. Each time the valid edge input to the TIQnm pin has been detected, the count value of the 16-bit counter is
stored in the TQnCCRm register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TQnCCRm register after a capture interrupt request
signal (INTTQnCCm) occurs.
Select either of the TIQn0 to TIQn3 pins as the capture trigger input pin. Specify "No edge detected" by using the
TQnIOC1 register for the unused pins.
When an external clock is used as the count clock, measure the pulse width of the TIQnk pin because the external
clock is fixed to the TIQn0 pin. At this time, clear the TQnIOC1.TQnIS1 and TQnIOC1.TQnIS0 bits to 00 (capture
trigger input (TIQn0 pin): No edge detected).
Remark m = 0 to 3,
n = 0 to 2,
k = 1 to 3
Figure 8-34. Configuration in Pulse Width Measurement Mode
INTTQnOV signal
INTTQnCC0 signal
INTTQnCC1 signal
INTTQnCC2 signal
INTTQnCC3 signal
TIQn3 pin
(capture
trigger input)
TQnCCR3
register
(capture)
TIQn0 pin
(external
event count
input/capture
trigger input)
Internal count clock
TQnCE
bit
TIQn1 pin
(capture
trigger input)
TIQn2 pin
(capture
trigger input)
TQnCCR0
register
(capture)
TQnCCR1
register
(capture)
TQnCCR2
register
(capture)
16-bit counter
Clear
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Edge
detector
Count
clock
selection
Remark n = 0 to 2
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Figure 8-35. Basic Timing in Pulse Width Measurement Mode
FFFFH
16-bit counter
0000H
TQnCE bit
TIQnm pin input
TQnCCRm register
INTTQnCCm signal
INTTQnOV signal
TQnOVF bit
D
0
0000H
D
1
D
2
D
3
Cleared to 0 by
CLR instruction
Remark m = 0 to 3,
n = 0 to 2
When the TQnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQnm pin is
later detected, the count value of the 16-bit counter is stored in the TQnCCRm register, the 16-bit counter is cleared to
0000H, and a capture interrupt request signal (INTTQnCCm) is generated.
The pulse width is calculated as follows.
Pulse width = Captured value
Count clock cycle
If the valid edge is not input to the TIQnm pin even when the 16-bit counter counted up to FFFFH, an overflow
interrupt request signal (INTTQnOV) is generated at the next count clock, and the counter is cleared to 0000H and
continues counting. At this time, the overflow flag (TQnOPT0.TQnOVF bit) is also set to 1. Clear the overflow flag to 0
by executing the CLR instruction via software.
If the overflow flag is set to 1, the pulse width can be calculated as follows.
Pulse width = (10000H
TQnOVF bit set (1) count + Captured value) Count clock cycle
Remark m = 0 to 3,
n = 0 to 2
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Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2)
(a) TMQn control register 0 (TQnCTL0)
0/1
0
0
0
0
TQnCTL0
Select count clock
Note
0: Stop counting
1: Enable counting
0/1
0/1
0/1
TQnCKS2 TQnCKS1 TQnCKS0
TQnCE
Note Setting is invalid when the TQnEEE bit = 1.
(b) TMQn control register 1 (TQnCTL1)
0
0
0/1
0
0
TQnCTL1
1
1
0
TQnMD2 TQnMD1 TQnMD0
TQnEEE
TQnEST
TQnSYE
1, 1, 0:
Pulse width measurement mode
0: Operate with count
clock selected by
TQnCKS0 to TQnCKS2 bits
1: Count external event
count input signal
(c) TMQn I/O control register 1 (TQnIOC1)
0/1
0/1
0/1
0/1
0/1
TQnIOC1
Select valid edge
of TIQn0 pin input
Select valid edge
of TIQn1 pin input
0/1
0/1
0/1
TQnIS2
TQnIS1
TQnIS0
TQnIS3
TQnIS6
TQnIS5
TQnIS4
TQnIS7
Select valid edge
of TIQn2 pin input
Select valid edge
of TIQn3 pin input
(d) TMQn I/O control register 2 (TQnIOC2)
0
0
0
0
0/1
TQnIOC2
Select valid edge of
external event count input
0/1
0
0
TQnEES0 TQnETS1 TQnETS0
TQnEES1
Remark n = 0 to 2
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Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2)
(e) TMQn option register 0 (TQnOPT0)
0
0
0
0
0
TQnOPT0
Overflow flag
0
0
0/1
TQnOVF
TQnCCS1
TQnCCS2
TQnCCS3
TQnCCS0
(f) TMQn counter read buffer register (TQnCNT)
The value of the 16-bit counter can be read by reading the TQnCNT register.
(g) TMQn capture/compare registers 0 to 3 (TQnCCR0 to TQnCCR3)
These registers store the count value of the 16-bit counter when the valid edge input to the TIQnm pin
is detected.
Remarks 1. TMQn I/O control register 0 (TQnIOC0) is not used in the pulse width measurement mode.
2. m = 0 to 3,
n = 0 to 2
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(1) Operation flow in pulse width measurement mode
Figure 8-37. Software Processing Flow in Pulse Width Measurement Mode
<1>
<2>
Set TQnCTL0 register
(TQnCE bit = 1)
TQnCE bit = 0
Register initial setting
TQnCTL0 register
(TQnCKS0 to TQnCKS2 bits),
TQnCTL1 register,
TQnIOC1 register,
TQnIOC2 register,
TQnOPT0 register
Initial setting of these registers
is performed before setting the
TQnCE bit to 1.
The TQnCKS0 to TQnCKS2 bits can
be set at the same time when counting
has been started (TQnCE bit = 1).
The counter is initialized and counting
is stopped by clearing the TQnCE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
FFFFH
16-bit counter
0000H
TQnCE bit
TIQn0 pin input
TQnCCR0 register
INTTQnCC0 signal
D
0
0000H
0000H
D
1
D
2
Remark n = 0 to 2
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(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
The overflow flag can be cleared to 0 by clearing the TQnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TQnOPT0 register. To accurately detect an overflow, read the TQnOVF
bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
(i) Operation to write 0 (without conflict with setting)
(iii) Operation to clear to 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TQnOVF bit)
Read
Write
0 write signal
Overflow
set signal
Register
access signal
Overflow flag
(TQnOVF bit)
Read
Write
0 write signal
Overflow
set signal
0 write signal
Overflow
set signal
Overflow flag
(TQnOVF bit)
Overflow flag
(TQnOVF bit)
L
H
L
Remark n = 0 to 2
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear
instruction.
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8.5.8
Triangular wave PWM mode (TQnMD2 to TQnMD0 = 111)
In the triangular wave PWM mode, TMQn capture/compare register k (TQnCCRk) is used to set the duty factor,
and TMQn capture/compare register 0 (TQnCCR0) is used to set the cycle.
By using these four registers and operating the timer, triangular wave PWM with a variable cycle is output.
The value of the TQnCCRm register can be rewritten when TQnCE = 1.
To stop timer Q, clear TQnCE to 0. The waveform of PWM is output from the TOQnk pin. The TOQn0 pin produces
a toggle output when the value of the 16-bit counter matches the value of the TQnCCR0 register and when the
counter underflows.
Caution In the PWM mode, the capture function of the TQnCCRm register cannot be used because this
register can be used only as a compare register.
Remark n = 0 to 2, m = 0 to 3, k = 1 to 3
Figure 8-38. Timing of Basic Operation in Triangular Wave PWM Mode
(TQnOE0 = 1, TQnOE1 = 1, TQnOE2 = 1, TQnOE3 = 1,
TQnOL0 = 0, TQnOL1 = 0, TQnOL2 = 0, TQnOL3 = 0)
TQnCE = 1
FFFFH
16-bit
counter
TOQn0
TOQn1
INTTQnOV
INTTQnCC0
match interrupt
INTTQnCC1
match interrupt
TQnCCR0
TOQn2
TOQn3
INTTQnCC2
match interrupt
INTTQnCC3
match interrupt
0000H
D
00
D
00
D
30
D
30
D
20
D
20
D
10
D
10
TQnCCR1
0000H
D
10
TQnCCR2
0000H
D
20
TQnCCR3
0000H
D
30
D
00
D
30
D
30
D
20
D
20
D
10
D
00
D
30
D
30
D
20
D
20
Remark n = 0 to 2
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8.5.9 Timer
output
operations
The following table shows the operations and output levels of the TOQn0 to TOQn3 pins.
Table 8-6. Timer Output Control in Each Mode
Operation Mode
TOQn0 Pin
TOQn1 Pin
TOQn2 Pin
TOQn3 Pin
Interval timer mode
Square wave output
External event count mode
Square wave output
-
External trigger pulse output mode
External trigger pulse
output
External trigger pulse
output
External trigger pulse
output
One-shot pulse output mode
One-shot pulse
output
One-shot pulse
output
One-shot pulse
output
PWM output mode
Square wave output
PWM output
PWM output
PWM output
Free-running timer mode
Square wave output (only when compare function is used)
Pulse width measurement mode
-
Triangular wave PWM output mode Square wave output
Triangular PWM
output
Triangular PWM
output
Triangular PWM
output
Table 8-7. Truth Table of TOQn0 to TOQn3 Pins Under Control of Timer Output Control Bits
TQnIOC0.TQnOLm Bit
TQnIOC0.TQnOEm Bit
TQnCTL0.TQnCE Bit
Level of TOQnm Pin
0
Low-level output
0 Low-level
output
0
1
1
Low level immediately before counting, high
level after counting is started
0
High-level output
0 High-level
output
1
1
1
High level immediately before counting, low level
after counting is started
Remark m = 0 to 3,
n = 0 to 2
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8.6 Timer Tuned Operation Function
Timer P and timer Q have a timer tuned operation function.
The timers that can be synchronized are listed in Table 8-8.
Table 8-8. Tuned Operation Mode of Timers
Master Timer
Slave Timer
TMP0 TMP1
TMP2 TMP3 TMQ0
TMQ1 TMQ2
Cautions 1. The tuned operation mode is enabled or disabled by the TPmCTL1.TPmSYE and
TQnCTL1.TQnSYE bits. For TMQ2, either or both TMQ3 and TMQ0 can be specified as slaves.
2.
Set the tuned operation mode using the following procedure.
<1> Set the TPmCTL1.TPmSYE and TQnCTL1.TQnSYE bits of the slave timer to enable the
tuned operation.
Set the TPmCTL1.TPmMD2 to TPmCTL1.TPmMD0 and TQnCTL1.TPnMD2 to
TQnCTL1.TPnMD0 bits of the slave timer to the free-running mode
<2> Set the timer mode by using the TPnCTL1.TPnMD2 to TPnCTL1.TPnMD0 and
TQnCTL1.TPnMD2 to TQnCTL1.TPnMD0 bits.
At this time, do not set the TPnCTL1.TPnSYE and TQnCTL1.TQnSYE bits of the master
timer.
<3> Set the compare register value of the master and slave timers.
<4> Set the TPmCTL0.TPmCE and TQnCTL0.TQnCE bits of the slave timer to enable
operation on the internal operating clock.
<5> Set the TPnCTL0.TPnCE and TQnCTL0.TQnCE bits of the master timer to enable
operation on the internal operating clock.
Remark m = 1, 3
n = 0, 2
Tables 8-9 and 8-10 show the timer modes that can be used in the tuned operation mode (
: Settable, : Not
settable).
Table 8-9. Timer Modes Usable in Tuned Operation Mode
Master Timer
Free-Running Mode
PWM Mode
Triangular Wave PWM Mode
TMP0
TMP2
TMQ1
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Table 8-10. Timer Output Functions
Free-Running Mode
PWM Mode
Triangular Wave PWM
Mode
Tuned
Channel
Timer Pin
Tuning OFF
Tuning ON
Tuning OFF
Tuning ON
Tuning OFF
Tuning ON
TOP00 PPG
Toggle
N/A
TMP0
(master)
TOP01 PPG
PWM
N/A
TOP10 PPG
Toggle PWM N/A
Ch0
TMP1
(slave)
TOP11 PPG
PWM
N/A
TOP20 PPG
Toggle
N/A
TMP2
(master)
TOP21 PPG
PWM
N/A
TOP30 PPG
Toggle PWM N/A
TMP3
(slave)
TOP31 PPG
PWM
N/A
TOQ00 PPG
Toggle PWM Toggle N/A
Ch1
TMQ0
(slave)
TOQ01 to TOQ03
PPG
PWM
Triangular
wave PWM
N/A
TOQ10 PPG
Toggle
Toggle
TMQ1
(master)
TOQ11 to TOQ13
PPG
PWM
Triangular
wave PWM
TOQ20 PPG
Toggle PWM Toggle
Triangular
wave PWM
Ch2
TMQ2
(slave)
TOQ21 to TOQ23
PPG
PWM
Triangular
wave PWM
Remark The timing of transmitting data from the compare register of the master timer to the compare register of
the slave timer is as follows.
PPG:
CPU write timing
Toggle, PWM, triangular wave PWM: Timing at which timer counter and compare register match TOPn0
and TOQm0 (n = 0 to 3, m = 0 to 2)
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Figure 8-39. Tuned Operation Image (TMP2, TMP3, TMQ0)
TMP2
TOP21 (PWM output)
16-bit timer/counter
Unit operation
TMP2 (master ) + TMP3 (slave) + TMQ0 (slave)
Tuned operation
Five PWM outputs are available when
PWM is operated as a single unit.
16-bit capture/compare
16-bit capture/compare
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TMP3
TOP31 (PWM output)
TMQ0
TOQ01 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
TOP21 (PWM output)
16-bit timer/counter
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOP30 (PWM output)
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
16-bit capture/compare
TOP31 (PWM output)
TOQ01 (PWM output)
TOQ00 (PWM output)
TOQ02 (PWM output)
TOQ03 (PWM output)
Seven PWM outputs are available when
PWM is operated in tuned operation mode.
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Figure 8-40. Basic Operation Timing of Tuned PWM Function (TMP2, TMP3, TMQ0)
TOP20
TOP21
TOP30
TOQ00
TOQ01
TOQ02
TOQ03
TOP31
TP2CCR0
TP2CE
INTTP2CC0
match interrupt
INTTP2CC1
match interrupt
INTTP3CC0
match interrupt
INTTP3CC1
match interrupt
INTTQ0CC0
match interrupt
INTTQ0CC1
match interrupt
INTTQ0CC2
match interrupt
INTTQ0CC3
match interrupt
TP3CE
TQ0CE
FFFFH
0000H
TMP2
16-bit
counter
D
00
D
00
D
70
D
60
D
50
D
40
D
30
D
20
D
10
D
00
D
70
D
60
D
50
D
40
D
30
D
20
D
10
TP2CCR1
D
10
TP3CCR0
D
20
TP3CCR1
D
30
TQ0CCR0
D
40
TQ0CCR1
D
50
TQ0CCR2
D
60
TQ0CCR3
D
70
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8.7 Cautions
(1) Capture operation
When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may
be captured in the TQnCCR0, TQnCCR1, TQnCCR2, and TQnCCR3 registers if the capture trigger is input
immediately after the TQnCE bit is set to 1.
(a) Free-running timer mode
Count clock
0000H
FFFFH
TQnCE bit
TQnCCR0 register
FFFFH
0001H
0000H
TIQn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX
)
Capture
trigger input
(b) Pulse width measurement mode
0000H
FFFFH
FFFFH
0002H
0000H
Count clock
TQnCE bit
TQnCCR0 register
TIQn0 pin input
Capture
trigger input
16-bit counter
Sampling clock (f
XX
)
Capture
trigger input
Remark n = 0 to 2
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CHAPTER 9 16-BIT INTERVAL TIMER M (TMM)
9.1 Overview
Interval function
8 clocks selectable
16-bit counter 1
(The 16-bit counter cannot be read during timer count operation.)
Compare register 1
(The compare register cannot be written during timer counter operation.)
Compare match interrupt 1
Timer M supports only the clear & start mode. The free-running timer mode is not supported.
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9.2 Configuration
TMM0 includes the following hardware.
Table 9-1. Configuration of TMM0
Item Configuration
Timer register
16-bit counter
Register
TMM0 compare register 0 (TM0CMP0)
Control register
TMM0 control register 0 (TM0CTL0)
Figure 9-1. Block Diagram of TMM0
TM0CTL0
Internal bus
f
XX
f
XX
/2
f
XX
/4
f
XX
/64
f
XX
/512
INTWT
f
R
/8
f
XT
Controller
16-bit counter
Match
Clear
INTTM0EQ0
TM0CMP0
TM0CE TM0CKS2 TM0CKS1TM0CKS0
Selector
Remark f
XX
:
Main clock frequency
f
R
:
Internal oscillation clock frequency
f
XT
:
Subclock frequency
INTWT: Watch timer interrupt request signal
(1) 16-bit counter
This is a 16-bit counter that counts the internal clock.
The 16-bit counter cannot be read or written.
(2) TMM0 compare register 0 (TM0CMP0)
The TM0CMP0 register is a 16-bit compare register.
This register can be read or written in 16-bit units.
Reset sets this register to 0000H.
The same value can always be written to the TM0CMP0 register by software.
TM0CMP0 register rewrite is prohibited when the TM0CTL0.TM0CE bit = 1.
TM0CMP0
12
10
8
6
4
2
After reset: 0000H R/W Address: FFFFF694H
14
0
13
11
9
7
5
3
15
1
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9.3 Register
(1) TMM0 control register (TM0CTL0)
The TM0CTL0 register is an 8-bit register that controls the TMM0 operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
The same value can always be written to the TM0CTL0 register by software. Rewriting this register, except the
TM0CE bit, is prohibited while the timer is operating.
TM0CE
TMM0 operation disabled (16-bit counter reset asynchronously).
Operation clock application stopped.
TMM0 operation enabled. Operation clock application started. TMM0
operation started.
TM0CE
0
1
Internal clock operation enable/disable specification
TM0CTL0
0
0
0
0
TM0CKS2 TM0CKS1 TM0CKS0
6
5
4
3
2
1
After reset: 00H R/W Address: FFFFF690H
The internal clock control and internal circuit reset for TMM0 are performed
asynchronously with the TM0CE bit. When the TM0CE bit is cleared to 0, the
internal clock of TMM0 is disabled (fixed to low level) and 16-bit counter is reset
asynchronously.
7
0
f
XX
f
XX
/2
f
XX
/4
f
XX
/64
f
XX
/512
INTWT
f
R
/8
f
XT
TM0CKS2
0
0
0
0
1
1
1
1
Count clock selection
TM0CKS1
0
0
1
1
0
0
1
1
TM0CKS0
0
1
0
1
0
1
0
1
Cautions 1. Set the TM0CKS2 to TM0CKS0 bits when TM0CE bit = 0.
When changing the value of TM0CE from 0 to 1, it is not possible to set
the value of the TM0CKS2 to TM0CKS0 bits simultaneously.
2. Be sure to clear bits 3 to 6 to "0".
Remark f
XX
: Main clock frequency
f
R
: Internal oscillation clock frequency
f
XT
: Subclock frequency
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9.4 Operation
Caution Do not set the TM0CMP0 register to FFFFH.
9.4.1
Interval timer mode
In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the
TM0CTL0.TM0CE bit is set to 1.
Figure 9-2. Configuration of Interval Timer
16-bit counter
TM0CMP0 register
TM0CE bit
Count clock
selection
Clear
Match signal
INTTM0EQ0 signal
Figure 9-3. Basic Timing of Operation in Interval Timer Mode
FFFFH
16-bit counter
0000H
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
D
D
D
D
D
Interval (D + 1)
Interval (D + 1)
Interval (D + 1)
Interval (D + 1)
When the TM0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
with the count clock, and the counter starts counting.
When the count value of the 16-bit counter matches the value of the TM0CMP0 register, the 16-bit counter is
cleared to 0000H and a compare match interrupt request signal (INTTM0EQ0) is generated.
The interval can be calculated by the following expression.
Interval = (Set value of TM0CMP0 register + 1)
Count clock cycle
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Figure 9-4. Register Setting for Interval Timer Mode Operation
(a) TMM0 control register 0 (TM0CTL0)
0/1
0
0
0
0
TM0CTL0
0/1
0/1
0/1
TM0CKS2 TM0CKS1 TM0CKS0
TM0CE
0: Stop counting
1: Enable counting
Select count clock
(b) TMM0 compare register 0 (TM0CMP0)
If the TM0CMP0 register is set to D, the interval is as follows.
Interval = (D + 1)
Count clock cycle
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(1) Interval timer mode operation flow
Figure 9-5. Software Processing Flow in Interval Timer Mode
FFFFH
16-bit counter
0000H
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
D
D
D
D
<1>
<2>
TM0CE bit = 1
TM0CE bit = 0
Register initial setting
TM0CTL0 register
(TM0CKS0 to TM0CKS2 bits)
TM0CMP0 register
Initial setting of these registers is performed
before setting the TM0CE bit to 1.
The TM0CKS0 to TM0CKS2 bits can be
set at the same time when counting has
been started (TM0CE bit = 1).
The counter is initialized and counting is
stopped by clearing the TM0CE bit to 0.
START
STOP
<1> Count operation start flow
<2> Count operation stop flow
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(2) Interval timer mode operation timing
Caution Do not set the TM0CMP0 register to FFFFH.
(a) Operation if TM0CMP0 register is set to 0000H
If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock.
The value of the 16-bit counter is always 0000H.
Count clock
16-bit counter
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
0000H
Interval time
Count clock cycle
FFFFH
0000H
0000H
0000H
0000H
Interval time
Count clock cycle
(b) Operation if TM0CMP0 register is set to N
If the TM0CMP0 register is set to N, the 16-bit counter counts up to N. The counter is cleared to 0000H in
synchronization with the next count-up timing and the INTTM0EQ0 signal is generated.
FFFFH
16-bit counter
0000H
TM0CE bit
TM0CMP0 register
INTTM0EQ0 signal
N
Interval time
(N + 1)
count clock cycle
Interval time
(N + 1)
count clock cycle
Interval time
(N + 1)
count clock cycle
N
Remark 0000H < N < FFFFH
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9.4.2 Cautions
(1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1,
depending on the count clock selected.
Selected Count Clock
Maximum Time Before Counting Start
f
XX
2/f
XX
f
XX
/2 6/f
XX
f
XX
/4 24/f
XX
f
XX
/64 128/f
XX
f
XX
/512 1024/f
XX
INTWT
Second rising edge of INTWT signal
f
R
/8 16/f
R
f
XT
2/f
XT
(2) Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is operating.
If these registers are rewritten while the TM0CE bit is 1, the operation cannot be guaranteed.
If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set the registers.
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CHAPTER 10 WATCH TIMER FUNCTIONS
10.1 Functions
The watch timer has the following functions.
Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the
main clock or subclock.
Interval timer: An interrupt request signal (INTWTI) is generated at set intervals.
The watch timer and interval timer functions can be used at the same time.
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10.2 Configuration
The block diagram of the watch timer is shown below.
Figure 10-1. Block Diagram of Watch Timer
Internal bus
Watch timer operation mode register
(WTM)
f
BRG
f
W
/2
4
f
W
/2
5
f
W
/2
6
f
W
/2
7
f
W
/2
8
f
W
/2
10
f
W
/2
11
f
W
/2
9
f
XT
11-bit prescaler
Clear
Clear
INTWT
INTWTI
WTM0
WTM1
WTM2
WTM3
WTM4
WTM5
WTM6
WTM7
5-bit counter
f
W
3
f
X
f
X
/8
f
X
/4
f
X
/2
f
X
BGCS00
BGCS01
BGCE0
3-bit
prescaler
8-bit counter
Clear
Match
f
BGCS
PRSM0 register
PRSCM0 register
1/2
2
Internal bus
Clock
control
Selector
Selector
Selector
Selector
Selector
Remark f
X
:
Main clock oscillation frequency
f
BGCS
:
Watch timer source clock frequency
f
BRG
:
Watch timer count clock frequency
f
XT
: Subclock
frequency
f
W
:
Watch timer clock frequency
INTWT: Watch timer interrupt request signal
INTWTI: Interval timer interrupt request signal
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(1) Clock
control
This block controls supplying and stopping the operating clock (f
X
) when the watch timer operates on the main
clock.
(2) 3-bit
prescaler
This prescaler divides f
X
to generate f
X
/2, f
X
/4, or f
X
/8.
(3) 8-bit
counter
This 8-bit counter counts the source clock (f
BGCS
).
(4) 11-bit
prescaler
This prescaler divides f
W
to generate a clock of f
W
/2
4
to f
W
/2
11
.
(5) 5-bit
counter
This counter counts f
W
or f
W
/2
9
, and generates a watch timer interrupt request signal at intervals of 2
4
/f
W
, 2
5
/f
W
,
2
12
/f
W
, or 2
14
/f
W
.
(6) Selector
The watch timer has the following five selectors.
Selector that selects one of f
X
, f
X
/2, f
X
/4, or f
X
/8 as the source clock of the watch timer
Selector that selects the main clock (f
X
) or subclock (f
XT
) as the clock of the watch timer
Selector that selects f
W
or f
W
/2
9
as the count clock frequency of the 5-bit counter
Selector that selects 2
4
/f
W
, 2
13
/f
W
, 2
5
/f
W
, or 2
14
/f
W
as the INTWT signal generation time interval
Selector that selects 2
4
/f
W
to 2
11
/f
W
as the interval timer interrupt request signal (INTWTI) generation time
interval
(7) PRSCM
register
This is an 8-bit compare register that sets the interval time.
(8) PRSM
register
This register controls clock supply to the watch timer.
(9) WTM
register
This is an 8-bit register that controls the operation of the watch timer/interval timer, and sets the interrupt
request signal generation interval.
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10.3 Registers
The following registers are provided for the watch timer.
Prescaler mode register 0 (PRSM0)
Prescaler compare register 0 (PRSCM0)
Watch timer operation mode register (WTM)
(1) Prescaler mode register 0 (PRSM0)
The PRSM0 register controls the generation of the watch timer count clock.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
PRSM0
0
0
BGCE0
0
0
BGCS01 BGCS00
Disabled
Enabled
BGCE0
0
1
Main clock operation enable
f
X
f
X
/2
f
X
/4
f
X
/8
5 MHz
200 ns
400 ns
800 ns
1.6 s
4 MHz
250 ns
500 ns
1 s
2 s
BGCS01
0
0
1
1
BGCS00
0
1
0
1
Selection of watch timer source clock (f
BGCS
)
After reset: 00H R/W Address: FFFFF8B0H
Cautions 1. Do not change the values of the BGCS00 and BGCS01 bits during watch timer operation.
2. Set the PRSM0 register before setting the BGCE0 bit to 1.
3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used
so as to obtain an f
BRG
frequency of 32.768 kHz.
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(2) Prescaler compare register 0 (PRSCM0)
The PRSCM0 register is an 8-bit compare register.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
PRSCM07
PRSCM0
PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00
After reset: 00H R/W Address: FFFFF8B1H
Cautions 1. Do not rewrite the PRSCM0 register during watch timer operation.
2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1.
3. Set the PRSM0 and PRSCM0 registers according to the main clock frequency that is used
so as to obtain an f
BRG
frequency of 32.768 kHz.
The calculation for f
BRG
is shown below.
f
BRG
= f
BGCS
/2N
Remark f
BGCS
: Watch timer source clock set by the PRSM0 register
N:
Set value of PRSCM0 register = 1 to 256
However, N = 256 only when PRSCM0 register is set to 00H.
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(3) Watch timer operation mode register (WTM)
The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time
of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag.
Set the PRSM0 register before setting the WTM register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(1/2)
WTM7
2
4
/f
W
(488 s: f
W
= f
XT
)
2
5
/f
W
(977 s: f
W
= f
XT
)
2
6
/f
W
(1.95 ms: f
W
= f
XT
)
2
7
/f
W
(3.91 ms: f
W
= f
XT
)
2
8
/f
W
(7.81 ms: f
W
= f
XT
)
2
9
/f
W
(15.6 ms: f
W
= f
XT
)
2
10
/f
W
(31.3 ms: f
W
= f
XT
)
2
11
/f
W
(62.5 ms: f
W
= f
XT
)
2
4
/f
W
(488 s: f
W
= f
BRG
)
2
5
/f
W
(977 s: f
W
= f
BRG
)
2
6
/f
W
(1.95 ms: f
W
= f
BRG
)
2
7
/f
W
(3.90 ms: f
W
= f
BRG
)
2
8
/f
W
(7.81 ms: f
W
= f
BRG
)
2
9
/f
W
(15.6 ms: f
W
= f
BRG
)
2
10
/f
W
(31.2 ms: f
W
= f
BRG
)
2
11
/f
W
(62.5 ms: f
W
= f
BRG
)
WTM7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WTM6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Selection of interval time of prescaler
WTM
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
WTM5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WTM4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
After reset: 00H R/W Address: FFFFF680H
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(2/2)
2
14
/f
W
(0.5 s: f
W
= f
XT
)
2
13
/f
W
(0.25 s: f
W
= f
XT
)
2
5
/f
W
(977 s: f
W
= f
XT
)
2
4
/f
W
(488 s: f
W
= f
XT
)
2
14
/f
W
(0.5 s: f
W
= f
BRG
)
2
13
/f
W
(0.25 s: f
W
= f
BRG
)
2
5
/f
W
(977 s: f
W
= f
BRG
)
2
4
/f
W
(488 s: f
W
= f
BRG
)
WTM7
0
0
0
0
1
1
1
1
Selection of set time of watch flag
Clears after operation stops
Starts
WTM1
0
1
Control of 5-bit counter operation
WTM3
0
0
1
1
0
0
1
1
WTM2
0
1
0
1
0
1
0
1
Stops operation (clears both prescaler and 5-bit counter)
Enables operation
WTM0
0
1
Watch timer operation enable
Caution Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0.
Remarks 1. f
W
: Watch timer clock frequency
2. Values in parentheses apply to operation with f
W
= 32.768 kHz
3. f
XT
: Subclock frequency
4. f
BRG
: Watch timer count clock frequency
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10.4 Operation
10.4.1 Operation as watch timer
The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates
using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz) or main clock.
The count operation starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11. When the WTM0 bit is
cleared to 0, the 11-bit prescaler and 5-bit counter are cleared and the count operation stops.
The time of the watch timer can be adjusted by clearing the WTM1 bit to 0 and then the 5-bit counter when
operating at the same time as the interval timer. At this time, an error of up to 15.6 ms may occur for the watch timer,
but the interval timer is not affected.
If the main clock is used as the count clock of the watch timer, set the count clock using the PRSM0.BGCS01 and
BGCS00 bits, the 8-bit comparison value using the PRSCM0 register, and the count clock frequency (f
BRG
) of the
watch timer to 32.768 kHz.
When the PRSM0.BGCE0 bit is set (1), f
BRG
is supplied to the watch timer.
f
BRG
can be calculated by the following expression.
f
BRG
= f
X
/(2
m+1
N)
To set f
BRG
to 32.768 kHz, perform the following calculation and set the BGCS01 and BGCS00 bits and the
PRSCM0 register.
<1> Set N = f
X
/65,536. Set m = 0.
<2> When the value resulting from rounding up the first decimal place of N is even, set N before the roundup as
N/2 and m as m + 1.
<3> Repeat <2> until N is odd or m = 3.
<4> Set the value resulting from rounding up the first decimal place of N to the PRSCM0 register and m to the
BGCS01 and BGCS00 bits.
Example: When
f
X
= 4.00 MHz
<1> N = 4,000,000/65,536 = 61.03..., m = 0
<2>, <3> Because N (round up the first decimal place) is odd, N = 61, m = 0.
<4> Set value of PRSCM0 register: 3DH (61), set value of BGCS01 and BGCS00 bits: 00
At this time, the actual f
BRG
frequency is as follows.
f
BRG
= f
X
/(2
m+1
N) = 4,000,000/(2 61)
= 32.787 kHz
Remark m: Division value (set value of BGCS01 and BGCS00 bits) = 0 to 3
N: Set value of PRSCM0 register = 1 to 256
However, N = 256 only when PRSCM0 register is set to 00H.
f
X
: Main clock oscillation frequency
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10.4.2 Operation as interval timer
The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal
(INTWTI) at intervals specified by a preset count value.
The interval time can be selected by the WTM4 to WTM7 bits of the WTM register.
Table 10-1. Interval Time of Interval Timer
WTM7 WTM6 WTM5 WTM4
Interval
Time
0 0 0 0
2
4
1/fw
488
s (operating at f
W
= f
XT
= 32.768 kHz)
0 0 0 1
2
5
1/fw
977
s (operating at f
W
= f
XT
= 32.768 kHz)
0 0 1 0
2
6
1/fw
1.95 ms (operating at f
W
= f
XT
= 32.768 kHz)
0 0 1 1
2
7
1/fw
3.91 ms (operating at f
W
= f
XT
= 32.768 kHz)
0 1 0 0
2
8
1/fw
7.81 ms (operating at f
W
= f
XT
= 32.768 kHz)
0 1 0 1
2
9
1/fw
15.6 ms (operating at f
W
= f
XT
= 32.768 kHz)
0 1 1 0
2
10
1/fw
31.3 ms (operating at f
W
= f
XT
= 32.768 kHz)
0 1 1 1
2
11
1/fw
62.5 ms (operating at f
W
= f
XT
= 32.768 kHz)
1 0 0 0
2
4
1/fw
488
s (operating at f
W
= f
BRG
= 32.768 kHz)
1 0 0 1
2
5
1/fw
977
s (operating at f
W
= f
BRG
= 32.768 kHz)
1 0 1 0
2
6
1/fw
1.95 ms (operating at f
W
= f
BRG
= 32.768 kHz)
1 0 1 1
2
7
1/fw
3.91 ms (operating at f
W
= f
BRG
= 32.768 kHz)
1 1 0 0
2
8
1/fw
7.81 ms (operating at f
W
= f
BRG
= 32.768 kHz)
1 1 0 1
2
9
1/fw
15.6 ms (operating at f
W
= f
BRG
= 32.768 kHz)
1 1 1 0
2
10
1/fw
31.3 ms (operating at f
W
= f
BRG
= 32.768 kHz)
1 1 1 1
2
11
1/fw
62.5 ms (operating at f
W
= f
BRG
= 32.768 kHz)
Remark f
W
: Watch timer clock frequency
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Figure 10-2. Operation Timing of Watch Timer/Interval Timer
Start
Overflow
Overflow
0H
Interrupt time of watch timer (0.5 s)
Interrupt time of watch timer (0.5 s)
Interval time (T)
Interval time (T)
nT
nT
5-bit counter
Count clock
f
W
or f
W
/2
9
Watch timer interrupt
INTWT
Interval timer interrupt
INTWTI
Remarks 1. When 0.5 seconds of the watch timer interrupt time is set.
2. f
W
: Watch timer clock frequency
Values in parentheses apply to operation with f
W
= 32.768 kHz.
n: Number of interval timer operations
10.4.3 Cautions
Some time is required before the first watch timer interrupt request signal (INTWT) is generated after operation is
enabled (WTM.WTM1 and WTM.WTM0 bits = 1).
Figure 10-3. Example of Generation of Watch Timer Interrupt Request Signal (INTWT)
(When Interrupt Cycle = 0.5 s)
It takes 0.515625 seconds (max.) for the first INTWT signal to be generated (2
9
1/32768 = 0.015625 seconds
longer (max.)). The INTWT signal is then generated every 0.5 seconds.
0.5 s
0.5 s
0.515625 s
WTM0, WTM1
INTWT
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CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2
11.1 Functions
Watchdog timer 2 has the following functions.
Default-start watchdog timer
Note 1
Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal)
Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of
INTWDT2 signal)
Note 2
Input selectable from main clock and internal oscillation clock as the source clock
Notes 1. Watchdog timer 2 automatically starts in the reset mode following reset release.
When watchdog timer 2 is not used, either stop its operation before reset is executed via this
function, or clear watchdog timer 2 once and stop it within the next interval time.
Also, write to the WDTM2 register for verification purposes only once, even if the default settings
(reset mode, interval time: f
R
/2
19
) do not need to be changed.
2. For the non-maskable interrupt servicing due to a non-maskable interrupt request signal (INTWDT2),
see 16.2.2 (2) INTWDT2 signal.
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11.2 Configuration
The following shows the block diagram of watchdog timer 2.
Figure 11-1. Block Diagram of Watchdog Timer 2
f
XX
/2
9
Clock
input
controller
Output
controller
WDT2RES
(internal reset signal)
WDCS22
Internal bus
INTWDT2
WDCS21 WDCS20
WDCS23
WDCS24
0
WDM21 WDM20
Selector
16-bit
counter
f
XX
/2
16
to f
XX
/2
23
,
f
R
/2
12
to f
R
/2
19
Watchdog timer enable
register (WDTE)
Watchdog timer mode
register 2 (WDTM2)
3
3
2
Clear
f
R
/2
3
Remark f
XX
:
Main clock frequency
f
R
:
Internal oscillation clock frequency
INTWDT2:
Non-maskable interrupt request signal from watchdog timer 2
WDTRES2: Watchdog timer 2 reset signal
Watchdog timer 2 includes the following hardware.
Table 11-1. Configuration of Watchdog Timer 2
Item Configuration
Control registers
Watchdog timer mode register 2 (WDTM2)
Watchdog timer enable register (WDTE)
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11.3 Registers
(1) Watchdog timer mode register 2 (WDTM2)
The WDTM2 register sets the overflow time and operation clock of watchdog timer 2.
This register can be read or written in 8-bit units. This register can be read any number of times, but it can be
written only once following reset release.
Reset sets this register to 67H.
Caution Accessing the WDTM2 register is prohibited in the following statuses. For details, see 3.4.8
(2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
0
WDTM2
WDM21
WDM20 WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
After reset: 67H R/W Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
(generation of INTWDT2 signal)
Reset mode (generation of WDT2RES signal)
WDM21
0
0
1
WDM20
0
1
Selection of operation mode of watchdog timer 2
Note
Note If the OPB1 bit is set to 1 by using the option byte function (see CHAPTER 25), the reset mode is fixed.
Cautions 1. For details of the WDCS20 to WDCS24 bits, see Table 11-2 Watchdog Timer 2 Clock
Selection.
2. If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
generated and the counter is reset.
3. To intentionally generate an overflow signal, write to the WDTM2 register only twice or
write a value other than ACH to the WDTE register once.
4. To stop the operation of watchdog timer 2, write 1FH to the WDTM2 register. If the OPB1
bit is set to 1 by using the option byte function (see CHAPTER 25), however, watchdog
timer 2 cannot be stopped by any means other than reset.
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Table 11-2. Watchdog Timer 2 Clock Selection
WDCS24 WDCS23 WDCS22 WDCS21 WDCS20
Selected Clock
100 kHz (MIN.)
200 kHz (TYP.)
400 kHz (MAX.)
0 0 0 0 0
2
12
/f
R
41.0 ms
20.5 ms
10.2 ms
0 0 0 0 1
2
13
/f
R
81.9 ms
41.0 ms
20.5 ms
0 0 0 1 0
2
14
/f
R
163.8 ms
81.9 ms
41.0 ms
0 0 0 1 1
2
15
/f
R
327.7 ms
163.8 ms
81.9 ms
0 0 1 0 0
2
16
/f
R
655.4 ms
327.7 ms
163.8 ms
0 0 1 0 1
2
17
/f
R
1,310.7 ms
655.4 ms
327.7 ms
0 0 1 1 0
2
18
/f
R
2,621.4 ms
1,310.7 ms
655.4 ms
0 0 1 1 1
2
19
/f
R
5,242.9 ms
2,621.4 ms
1,310.7 ms
f
XX
= 4 MHz
f
XX
= 5 MHz
0 1 0 0 0
2
16
/f
XX
16.4 ms
13.1 ms
0 1 0 0 1
2
17
/f
XX
32.8 ms
26.2 ms
0 1 0 1 0
2
18
/f
XX
65.5 ms
52.4 ms
0 1 0 1 1
2
19
/f
XX
131.1 ms
104.9 ms
0 1 1 0 0
2
20
/f
XX
262.1 ms
209.7 ms
0 1 1 0 1
2
21
/f
XX
524.3 ms
419.4 ms
0 1 1 1 0
2
22
/f
XX
1,048.6 ms
838.9 ms
0 1 1 1 1
2
23
/f
XX
2,097.2 ms
1,677.7 ms
1 1 1 1 1
Operation
stopped
Caution If the OPB1 bit is set to 1 by using the option byte function, the clock is fixed to the internal
oscillation clock (f
R
) (2
12
/f
R
to 2
19
/f
R
can be selected). For details, see CHAPTER 25 OPTION
BYTE FUNCTION.
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(2) Watchdog timer enable register (WDTE)
The counter of watchdog timer 2 is cleared and counting restarted by writing "ACH" to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 9AH.
WDTE
After reset: 9AH R/W Address: FFFFF6D1H
Cautions 1. When a value other than "ACH" is written to the WDTE register, an overflow signal is
forcibly output.
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
overflow signal is forcibly output.
3. To intentionally generate an overflow signal, write to the WDTM2 register only twice or
write a value other than ACH to the WDTE register once.
4. The read value of the WDTE register is "9AH" (which differs from written value "ACH").
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11.4 Operation
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write
the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After
this, the operation of watchdog timer 2 cannot be stopped.
The WDCS24 to WDCS20 bits of the WDTM2 register are used to select the watchdog timer 2 loop detection time
interval.
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again.
After the count operation has started, write ACH to WDTE within the loop detection time interval.
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non-
maskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDM21 and
WDTM2.WDM20 bits.
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization
after a reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation
clock.
To not use watchdog timer 2, write 1FH to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 16.2.2 (2)
INTWDT2 signal.
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CHAPTER 12 A/D CONVERTER
12.1 Overview
The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 24
analog input signal channels (ANI0 to ANI23).
The A/D converter has the following features.
10-bit resolution
24 channels
Successive approximation method
Operating voltage: AV
REF0
= 4.0 to 5.5 V
Analog input voltage: 0 V to AV
REF0
The following functions are provided as operation modes.
Continuous select mode
Continuous scan mode
One-shot scan mode
The following functions are provided as trigger modes.
Software trigger mode
External trigger mode (external, 1)
Timer trigger mode
Power-fail monitor function (conversion result compare function)
12.2 Functions
(1) 10-bit resolution A/D conversion
An analog input channel is selected from ANI0 to ANI23, and an A/D conversion operation is repeated at a
resolution of 10 bits. Each time A/D conversion has been completed, an interrupt request signal (INTAD) is
generated.
(2) Power-fail detection function
This function is used to detect a drop in the battery voltage. The result of A/D conversion (the value of the
ADA0CRnH register) is compared with the value of the ADA0PFT register, and the INTAD signal is generated
only when a specified comparison condition is satisfied (n = 0 to 23).
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12.3 Configuration
The block diagram of the A/D converter is shown below.
Figure 12-1. Block Diagram of A/D Converter
ANI0
:
:
ANI1
ANI2
ANI21
ANI22
ANI23
ADA0M2
ADA0M1
ADA0M0
ADA0S
ADA0PFT
Controller
Voltage
comparator
ADA0PFM
ADA0CR0
ADA0CR1
:
:
ADA0CR2
ADA0CR22
ADA0CR23
Internal bus
AV
REF0
ADA0CE bit
AV
SS
INTAD
Edge
detection
ADTRG
Controller
Sample & hold circuit
ADA0ETS0 bit
INTTP2CC0
INTTP2CC1
ADA0ETS1 bit
ADA0CE bit
ADA0TMD1 bit
ADA0TMD0 bit
Selector
Selector
ADA0PFE bit
ADA0PFC bit
SAR
Voltage comparator
&
Compare voltage
generation DAC
The A/D converter includes the following hardware.
Table 12-1. Configuration of A/D Converter
Item Configuration
Analog inputs
24 channels (ANI0 to ANI23 pins)
Registers
Successive approximation register (SAR)
A/D conversion result registers 0 to 23 (ADA0CR0 to ADA0CR23)
A/D conversion result registers 0H to 23H (ADCR0H to ADCR23H): Only higher 8 bits
can be read
Control registers
A/D converter mode registers 0 to 2 (ADA0M0 to ADA0M2)
A/D converter channel specification register 0 (ADA0S)
Power fail compare mode register (ADA0PFM)
Power fail compare threshold value register (ADA0PFT)
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(1) Successive approximation register (SAR)
The SAR register compares the voltage value of the analog input signal with the output voltage of the compare
voltage generation DAC (compare voltage), and holds the comparison result starting from the most significant
bit (MSB).
When the comparison result has been held down to the least significant bit (LSB) (i.e., when A/D conversion is
complete), the contents of the SAR register are transferred to the ADA0CRn register.
Remark n = 0 to 23
(2) A/D conversion result register n (ADA0CRn), A/D conversion result register nH (ADA0CRnH)
The ADA0CRn register is a 16-bit register that stores the A/D conversion result. ADA0ARn consist of 24
registers and the A/D conversion result is stored in the 10 higher bits of the AD0CRn register corresponding to
analog input. (The lower 6 bits are fixed to 0.)
(3) A/D converter mode register 0 (ADA0M0)
This register specifies the operation mode and controls the conversion operation by the A/D converter.
(4) A/D converter mode register 1 (ADA0M1)
This register sets the conversion time of the analog input signal to be converted.
(5) A/D converter mode register 2 (ADA0M2)
This register sets the hardware trigger mode.
(6) A/D converter channel specification register (ADA0S)
This register sets the input port that inputs the analog voltage to be converted.
(7) Power-fail compare mode register (ADA0PFM)
This register sets the power-fail monitor mode.
(8) Power-fail compare threshold value register (ADA0PFT)
The ADA0PFT register sets a threshold value that is compared with the value of A/D conversion result register
nH (ADA0CRnH). The 8-bit data set to the ADA0PFT register is compared with the higher 8 bits of the A/D
conversion result register (ADA0CRnH).
(9) Controller
The controller compares the result of the A/D conversion (the value of the ADA0CRnH register) with the value
of the ADA0PFT register when A/D conversion is completed or when the power-fail detection function is used,
and generates the INTAD signal only when a specified comparison condition is satisfied.
(10) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals selected by the input circuit and sends the
sampled data to the voltage comparator. This circuit also holds the sampled analog input signal voltage
during A/D conversion.
(11) Voltage
comparator
The voltage comparator compares a voltage value that has been sampled and held with the voltage value of
the compare voltage generation DAC.
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(12) Compare voltage generation DAC
This compare voltage generation DAC is connected between AV
REF0
and AV
SS
and generates a voltage for
comparison with the analog input signal.
(13) ANI0 to ANI23 pins
These are analog input pins for the 24 A/D converter channels and are used to input analog signals to be
converted into digital signals. Pins other than the one selected as the analog input by the ADA0S register
can be used as input port pins.
Cautions 1. Make sure that the voltages input to the ANI0 to ANI23 pins do not exceed the rated
values. In particular if a voltage of AV
REF0
or higher is input to a channel, the conversion
value of that channel becomes undefined, and the conversion values of the other
channels may also be affected.
2. The analog input pins (ANI0 to ANI23) function alternately as input port pins (P70 to P715,
P120 to P127). If any of ANI0 to ANI23 is selected to execute A/D conversion, do not
execute an input instruction to ports 7 and 12 during conversion. If executed, the
conversion resolution may be degraded.
(14) AV
REF0
pin
This is the pin used to input the reference voltage of the A/D converter. Always make the potential at this pin
the same as that at the V
DD
pin even when the A/D converter is not used. The signals input to the ANI0 to
ANI23 pins are converted to digital signals based on the voltage applied between the AV
REF0
and AV
SS
pins.
(15) AV
SS
pin
This is the ground pin of the A/D converter. Always make the potential at this pin the same as that at the V
SS
pin even when the A/D converter is not used.
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12.4 Registers
The A/D converter is controlled by the following registers.
A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2)
A/D converter channel specification register 0 (ADA0S)
Power-fail compare mode register (ADA0PFM)
The following registers are also used.
A/D conversion result register n (ADA0CRn)
A/D conversion result register nH (ADA0CRnH)
Power-fail compare threshold value register (ADA0PFT)
(1) A/D converter mode register 0 (ADA0M0)
The ADA0M0 register is an 8-bit register that specifies the operation mode and controls conversion operations.
This register can be read or written in 8-bit or 1-bit units. However, ADA0EF bit is read-only.
Reset sets this register to 00H.
Caution Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.8
(2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
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ADA0CE
ADA0CE
0
1
Stops A/D conversion
Enables A/D conversion
A/D conversion control
ADA0M0
0
ADA0MD1 ADA0MD0 ADA0ETS1 ADA0ETS0 ADA0TMD
ADA0EF
ADA0TMD
0
1
Software trigger mode
External trigger mode/timer trigger mode
Trigger mode specification
ADA0EF
0
1
A/D conversion stopped
A/D conversion in progress
A/D converter status display
ADA0MD1
0
0
1
1
ADA0MD0
0
1
0
1
Continuous select mode
Continuous scan mode
Setting prohibited
One-shot scan mode
Specification of A/D converter operation mode
ADA0ETS1
0
0
1
1
ADA0ETS0
0
1
0
1
No edge detection
Falling edge detection
Rising edge detection
Detection of both rising and falling edges
Specification of external trigger (ADTRG pin) input valid edge
After reset: 00H R/W Address: FFFFF200H
Cautions 1. Write operations to bit 0 are ignored.
2. Changing the ADA0M1 register value is prohibited while A/D
conversion is enabled (ADA0CE bit = 1).
3. If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers
are written during A/D conversion (ADA0EF bit = 1), the following will
be performed according to the mode.
In software trigger mode
A/D conversion is stopped and started again from the beginning.
In hardware trigger mode
A/D conversion is stopped, and the trigger standby state is set.
4. When not using the A/D converter, stop the operation by setting the
ADA0CE bit to 0 to reduce the power consumption.
5. The resolution for the first conversion of the data of the input pin
immediately after the start of A/D conversion may be degraded. For
details, see 12.6 (7) AV
REF0
pin.
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(2) A/D converter mode register 1 (ADA0M1)
The ADA0M1 register is an 8-bit register that controls the conversion time specification.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF201H
7 6 5 4 3 2 1 0
ADA0M1
ADA0HS1
0 0 0
ADA0FR3 ADA0FR2 ADA0FR1
ADA0FR0
Cautions 1. Be sure to clear bits 6 to 4 to "0".
2. Be sure to set the ADA0HS1 bit to "1".
Remark For A/D conversion time setting examples, see Table 12-2.
Table 12-2. Conversion Mode Setting Example
ADA0FR3 to ADA0FR0
ADA0HS1
3 2 1 0
A/D Conversion
Time
f
XX
= 20 MHz
f
XX
= 16 MHz
f
XX
= 4 MHz
A/D Stabilization
Time
Note
0 0 0 0
31/f
XX
Setting prohibited Setting prohibited 7.75
s 16/f
XX
0 0 0 1
62/f
XX
3.10
s 3.88
s 15.50
s 31/f
XX
0 0 1 0
93/f
XX
4.65
s 5.81
s
Setting prohibited
47/f
XX
0 0 1 1
124/f
XX
6.20
s 7.75
s
Setting prohibited
50/f
XX
0 1 0 0
155/f
XX
7.75
s 9.69
s
Setting prohibited
50/f
XX
0 1 0 1
186/f
XX
9.30
s 11.63
s
Setting prohibited
50/f
XX
0 1 1 0
217/f
XX
10.85
s 13.56
s
Setting prohibited
50/f
XX
0 1 1 1
248/f
XX
12.40
s 15.50
s
Setting prohibited
50/f
XX
1 0 0 0
279/f
XX
13.95
s
Setting prohibited Setting prohibited
50/f
XX
1 0 0 1
310/f
XX
15.50
s
Setting prohibited Setting prohibited
50/f
XX
1 0 1 0
341/f
XX
Setting prohibited Setting prohibited Setting prohibited
50/f
XX
1 0 1 1
372/f
XX
Setting prohibited Setting prohibited Setting prohibited
50/f
XX
1 1 0 0
403/f
XX
Setting prohibited Setting prohibited Setting prohibited
50/f
XX
1 1 0 1
434/f
XX
Setting prohibited Setting prohibited Setting prohibited
50/f
XX
1 1 1 0
465/f
XX
Setting prohibited Setting prohibited Setting prohibited
50/f
XX
1
1 1 1 1
496/f
XX
Setting prohibited Setting prohibited Setting prohibited
50/f
XX
Note When the ADA0CE bit of the ADA0M0 register is changed from 0 to 1 to secure the A/D converter
stabilization time, the first A/D conversion starts after one of the above clock values is input.
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(3) A/D converter mode register 2 (ADA0M2)
The ADA0M2 register specifies the hardware trigger mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
ADA0M2
0
0
0
0
0
ADA0TMD1 ADA0TMD0
ADA0TMD1
0
0
1
1
ADA0TMD0
0
1
0
1
Specification of hardware trigger mode
External trigger mode (when ADTRG pin valid edge detected)
Timer trigger mode 0
(when INTTP2CC0 interrupt request generated)
Timer trigger mode 1
(when INTTP2CC1 interrupt request generated)
Setting prohibited
After reset: 00H R/W Address: FFFFF203H
6
5
4
3
2
1
0
7
Caution Be sure to clear bits 7 to 2 to "0".
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(4) A/D converter channel specification register 0 (ADA0S)
The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
R/W
Address: FFFFF202H
7 6 5 4 3 2 1 0
ADA0S 0
0
0
ADA0S4
ADA0S3
ADA0S2
ADA0S1
ADA0S0
ADA0S4 ADA0S3 ADA0S2 ADA0S1 ADA0S0
Select
mode
Scan
mode
0 0 0 0 0
ANI0
ANI0
0 0 0 0 1
ANI1
ANI0,
ANI1
0 0 0 1 0
ANI2
ANI0
to
ANI2
0 0 0 1 1
ANI3
ANI0
to
ANI3
0 0 1 0 0
ANI4
ANI0
to
ANI4
0 0 1 0 1
ANI5
ANI0
to
ANI5
0 0 1 1 0
ANI6
ANI0
to
ANI6
0 0 1 1 1
ANI7
ANI0
to
ANI7
0 1 0 0 0
ANI8
ANI0
to
ANI8
0 1 0 0 1
ANI9
ANI0
to
ANI9
0 1 0 1 0
ANI10
ANI0
to
ANI10
0 1 0 1 1
ANI11
ANI0
to
ANI11
0 1 1 0 0
ANI12
ANI0
to
ANI12
0 1 1 0 1
ANI13
ANI0
to
ANI13
0 1 1 1 0
ANI14
ANI0
to
ANI14
0 1 1 1 1
ANI15
ANI0
to
ANI15
1 0 0 0 0
ANI16
ANI0
to
ANI16
1 0 0 0 1
ANI17
ANI0
to
ANI17
1 0 0 1 0
ANI18
ANI0
to
ANI18
1 0 0 1 1
ANI19
ANI0
to
ANI19
1 0 1 0 0
ANI20
ANI0
to
ANI20
1 0 1 0 1
ANI21
ANI0
to
ANI21
1 0 1 1 0
ANI22
ANI0
to
ANI22
1 0 1 1 1
ANI23
ANI0
to
ANI23
Other than above
Setting prohibited
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(5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH)
The ADA0CRn and ADA0CRnH registers store the A/D conversion results.
These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access
and the ADA0CRnH register for 8-bit access. The 10 bits of the conversion result are read from the higher 10
bits of the ADA0CRn register, and 0 is read from the lower 6 bits. The higher 8 bits of the conversion result are
read from the ADA0CRnH register.
Caution Accessing the ADA0CRn and ADA0CRnH registers is prohibited in the following statuses.
For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
When the CPU operates with the subclock and the main clock oscillation is stopped
When the CPU operates with the internal oscillation clock
After reset: Undefined
R
Address: ADA0CR0 FFFFF210H, ADA0CR1 FFFFF212H,
ADA0CR2 FFFFF214H, ADA0CR3 FFFFF216H
ADA0CR4 FFFFF218H, ADA0CR5 FFFFF21AH
ADA0CR6 FFFFF21CH, ADA0CR7 FFFFF21EH
ADA0CR8 FFFFF220H, ADA0CR9 FFFFF222H
ADA0CR10 FFFFF224H, ADA0CR11 FFFFF226H
ADA0CR12 FFFFF228H, ADA0CR13 FFFFF22AH
ADA0CR14 FFFFF22CH, ADA0CR15 FFFFF22EH
ADA0CR16 FFFFF230H, ADA0CR17 FFFFF232H
ADA0CR18 FFFFF234H, ADA0CR19 FFFFF236H
ADA0CR20 FFFFF238H, ADA0CR21 FFFFF23AH
ADA0CR22 FFFFF23CH, ADA0CR23 FFFFF23EH
15
14
13
12
11
10 9 8 7 6 5 4 3 2 1 0
ADA0CRn AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
0
0 0 0 0
After reset: Undefined
R
Address: ADA0CR0H FFFFF211H, ADA0CR1H FFFFF213H,
ADA0CR2H FFFFF215H, ADA0CR3H FFFFF217H
ADA0CR4H FFFFF219H, ADA0CR5H FFFFF21BH
ADA0CR6H FFFFF21DH, ADA0CR7H FFFFF21FH
ADA0CR8H FFFFF221H, ADA0CR9H FFFFF223H
ADA0CR10H FFFFF225H, ADA0CR11H FFFFF227H
ADA0CR12H FFFFF229H, ADA0CR13H FFFFF22BH
ADA0CR14H FFFFF22DH, ADA0CR15H FFFFF22FH
ADA0CR16H FFFFF231H, ADA0CR17H FFFFF233H
ADA0CR18H FFFFF235H, ADA0CR19H FFFFF237H
ADA0CR20H FFFFF239H, ADA0CR21H FFFFF23BH
ADA0CR22H FFFFF23DH, ADA0CR23H FFFFF23FH
7 6 5 4 3 2 1 0
ADA0CRnH
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Remark n = 0 to 23
Caution A write operation to the ADA0M0 and ADA0S registers may cause the contents of the
ADA0CRn register to become undefined. After the conversion, read the conversion
result before writing to the ADA0M0 and ADA0S registers. Correct conversion results
may not be read if a sequence other than the above is used.
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The relationship between the analog voltage input to the analog input pins (ANI0 to ANI23) and the A/D conversion
result (ADA0CRn register) is as follows.
V
IN
SAR = INT (
AV
REF0
1,024 + 0.5)
ADA0CR
Note
= SAR
64
Or,
AV
REF0
AV
REF0
(SAR
- 0.5)
1,024
V
IN
< (SAR + 0.5)
1,024
INT( ):
Function that returns the integer of the value in ( )
V
IN
:
Analog input voltage
AV
REF0
:
AV
REF0
pin voltage
ADA0CR: Value of ADA0CRn register
Note The lower 6 bits of the ADA0CRn register are fixed to 0.
The following shows the relationship between the analog input voltage and the A/D conversion results.
Figure 12-2. Relationship Between Analog Input Voltage and A/D Conversion Results
1,023
1,022
1,021
3
2
1
0
Input voltage/AV
REF0
1
2,048
1
1,024
3
2,048
2
1,024
5
2,048
3
1,024
2,043
2,048
1,022
1,024
2,045
2,048
1,023
1,024
2,047
2,048
1
A/D conversion results
ADA0CRn
SAR
FFC0H
FF80H
FF40H
00C0H
0080H
0040H
0000H
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(6) Power-fail compare mode register (ADA0PFM)
The ADA0PFM register is an 8-bit register that sets the power-fail compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
ADA0PFE
Power-fail compare disabled
Power-fail compare enabled
ADA0PFE
0
1
Selection of power-fail compare enable/disable
ADA0PFM
ADA0PFC
0
0
0
0
0
0
Generates an interrupt request signal (INTAD) when ADA0CRnH
ADA0PFT
Generates an interrupt request signal (INTAD) when ADA0CRnH < ADA0PFT
ADA0PFC
0
1
Selection of power-fail compare mode
After reset: 00H R/W Address: FFFFF204H
7
6
5
4
3
2
1
0
Cautions 1. In the select mode, the 8-bit data set to the ADA0PFT register is compared with the
value of the ADA0CRnH register specified by the ADA0S register. If the result matches
the condition specified by the ADA0PFC bit, the conversion result is stored in the
ADA0CRn register and the INTAD signal is generated. If it does not match, however,
the interrupt signal is not generated.
2. In the scan mode, the 8-bit data set to the ADA0PFT register is compared with the
contents of the ADA0CR0H register. If the result matches the condition specified by
the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the
INTAD signal is generated. If it does not match, however, the INTAD signal is not
generated. Regardless of the comparison result, the scan operation is continued and
the conversion result is stored in the ADA0CRn register until the scan operation is
completed. However, the INTAD signal is not generated after the scan operation has
been completed.
(7) Power-fail compare threshold value register (ADA0PFT)
The ADA0PFT register sets the compare value in the power-fail compare mode.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
ADA0PFT
After reset: 00H R/W Address: FFFFF205H
7
6
5
4
3
2
1
0
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12.5 Operation
12.5.1 Basic operation
<1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the
ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set,
conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or
timer trigger mode.
<2> When A/D conversion is started, the voltage input to the selected analog input channel is sampled by the
sample & hold circuit.
<3> When the sample & hold circuit samples the input channel for a specific time, it enters the hold status, and
holds the input analog voltage until A/D conversion is complete.
<4> Set bit 9 of the successive approximation register (SAR) to set the compare voltage generation DAC to (1/2)
AV
REF0
.
<5> The voltage difference between the compare voltage generation DAC and the analog input voltage is
compared by the voltage comparator. If the analog input voltage is higher than (1/2) AV
REF0
, the MSB of the
SAR register remains set. If it is lower than (1/2) AV
REF0
, the MSB is reset.
<6> Next, bit 8 of the SAR register is automatically set and the next comparison is started. Depending on the
value of bit 9, to which a result has been already set, the compare voltage generation DAC is selected as
follows.
Bit 9 = 1: (3/4) AV
REF0
Bit 9 = 0: (1/4) AV
REF0
This compare voltage and the analog input voltage are compared and, depending on the result, bit 8 is
manipulated as follows.
Analog input voltage
Compare voltage: Bit 8 = 1
Analog input voltage
Compare voltage: Bit 8 = 0
<7> This comparison is continued to bit 0 of the SAR register.
<8> When comparison of the 10 bits is complete, the valid digital result is stored in the SAR register, which is then
transferred to and stored in the ADA0CRn register. After that, an A/D conversion end interrupt request signal
(INTAD) is generated.
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12.5.2 Trigger mode
The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a
software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1,
and external trigger mode. The ADA0M0.ADA0TMD bit is used to set the trigger mode. The hardware trigger modes
are set by the ADA0M2.ADA0TMD1 and ADA0M2.ADA0TMD0 bits.
(1) Software trigger mode
When the ADA0M0.ADA0CE bit is set to 1, the signal of the analog input pin (ANI0 to ANI23) specified by the
ADA0S register is converted. When conversion is complete, the result is stored in the ADA0CRn register. At
the same time, the A/D conversion end interrupt request signal (INTAD) is generated.
If the operation mode specified by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits is the continuous
select/scan mode, the next conversion is started, unless the ADA0CE bit is cleared to 0 after completion of the
first conversion. Conversion is performed once and ends if the operation mode is the one-shot select/scan
mode.
When conversion is started, the ADA0M0.ADA0EF bit is set to 1 (indicating that conversion is in progress).
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion
is aborted and started again from the beginning.
(2) External trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI23) specified by the ADA0S register is
started when an external trigger is input (to the ADTRG pin). Which edge of the external trigger is to be
detected (i.e., the rising edge, falling edge, or both rising and falling edges) can be specified by using the
ADA0M0.ADA0ETS1 and ADA0M0.ATA0ETS0 bits. When the ADA0CE bit is set to 1, the A/D converter waits
for the trigger, and starts conversion after the external trigger has been input.
When conversion is completed, the result of conversion is stored in the ADA0CRn register, regardless of
whether the continuous select, continuous scan, or one-shot scan mode is set as the operation mode by the
ADA0MD1 and ADA0MD0 bits. At the same time, the INTAD signal is generated, and the A/D converter waits
for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the
A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is
stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started
again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during the conversion operation,
the conversion is not aborted, and the A/D converter waits for the trigger again.
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(3) Timer trigger mode
In this mode, converting the signal of the analog input pin (ANI0 to ANI23) specified by the ADA0S register is
started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare
register connected to the timer. The INTTP2CC0 or INTTP2CC1 signal is selected by the ADA0TMD1 and
ADA0TMD0 bits, and conversion is started at the rising edge of the specified compare match interrupt request
signal. When the ADA0CE bit is set to 1, the A/D converter waits for a trigger, and starts conversion when the
compare match interrupt request signal of the timer is input.
When conversion is completed, regardless of whether the continuous select, continuous scan, or one-shot
scan mode is set as the operation mode by the ADA0MD1 and ADA0MD0 bits, the result of the conversion is
stored in the ADA0CRn register. At the same time, the INTAD signal is generated, and the A/D converter waits
for the trigger again.
When conversion is started, the ADA0EF bit is set to 1 (indicating that conversion is in progress). While the
A/D converter is waiting for the trigger, however, the ADA0EF bit is cleared to 0 (indicating that conversion is
stopped). If the valid trigger is input during the conversion operation, the conversion is aborted and started
again from the beginning.
If the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT register is written during conversion, the conversion
is stopped and the A/D converter waits for the trigger again.
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12.5.3 Operation mode
Three operation modes are available as the modes in which to set the ANI0 to ANI23 pins: continuous select mode,
continuous scan mode, and one-shot scan mode.
The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits.
(1) Continuous select mode
In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into
a digital value.
The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode,
an analog input pin corresponds to an ADA0CRn register on a one-to-one basis. Each time A/D conversion is
completed, the A/D conversion end interrupt request signal (INTAD) is generated. After completion of
conversion, the next conversion is started, unless the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 23).
Figure 12-3. Timing Example of Continuous Select Mode Operation (ADA0S Register = 01H)
ANI1
A/D conversion
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 5
(ANI1)
Data 6
(ANI1)
Data 7
(ANI1)
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 6
(ANI1)
ADA0CR1
INTAD
Conversion start
Set ADA0CE bit = 1
Conversion start
Set ADA0CE bit = 1
(2) Continuous scan mode
In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S
register, and their values are converted into digital values.
The result of each conversion is stored in the ADA0CRn register corresponding to the analog input pin. When
conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated,
and A/D conversion is started again from the ANI0 pin, unless the ADA0CE bit is cleared to 0 (n = 0 to 23).
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Figure 12-4. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H)
(a) Timing example
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
Data 7
(ANI2)
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
ADA0CRn
INTAD
Conversion start
Set ADA0CE bit = 1
ANI3
ANI0
ANI1
ANI2
Data 1
Data 2
Data 3
Data 4
Data 6
Data 5
Data 7
(b) Block diagram
A/D converter
ADA0CRn register
Analog input pin
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI21
ANI22
ANI23
.
.
.
.
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ADA0CR21
ADA0CR22
ADA0CR23
.
.
.
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(3) One-shot scan mode
In this mode, analog input pins are sequentially selected, from the ANI0 pin to the pin specified by the ADA0S
register, and their values are converted into digital values.
Each conversion result is stored in the ADA0CRn register corresponding to the analog input pin. When
conversion of the analog input pin specified by the ADA0S register is complete, the INTAD signal is generated.
A/D conversion is stopped after it has been completed (n = 0 to 23).
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Figure 12-5. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H)
(a) Timing example
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
ADA0CRn
INTAD
Conversion start
Set ADA0CE bit = 1
Conversion end
ANI3
ANI0
ANI1
ANI2
Data 1
Data 2
Data 3
Data 4
Data 6
Data 5
Data 7
(b) Block diagram
A/D converter
ADA0CRn register
Analog input pin
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI21
ANI22
ANI23
.
.
.
.
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ADA0CR21
ADA0CR22
ADA0CR23
.
.
.
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12.5.4 Power-fail compare mode
The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and
ADA0PFT registers.
When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed
(normal use of the A/D converter).
When the ADA0PFE bit = 1 and when the ADA0PFM.ADA0PFC bit = 0, the value of the ADA0CRnH register is
compared with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is
generated only if ADA0CRnH
ADA0PFT.
When the ADA0PFE bit = 1 and when the ADA0PFC bit = 1, the value of the ADA0CRnH register is compared
with the value of the ADA0PFT register when conversion is completed, and the INTAD signal is generated only if
ADA0CRnH < ADA0PFT.
Remark n = 0 to 23
In the power-fail compare mode, three modes are available as modes in which to set the ANI0 to ANI23 pins:
continuous select mode, continuous scan mode, and one-shot scan mode.
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(1) Continuous select mode
In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is
compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the
condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD
signal is generated. If it does not match, the conversion result is stored in the ADA0CRn register, and the
INTAD signal is not generated. After completion of the first conversion, the next conversion is started, unless
the ADA0M0.ADA0CE bit is cleared to 0 (n = 0 to 23).
Figure 12-6. Timing Example of Continuous Select Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 01H)
ANI1
A/D conversion
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 5
(ANI1)
Data 6
(ANI1)
Data 7
(ANI1)
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Data 1
(ANI1)
Data 2
(ANI1)
Data 3
(ANI1)
Data 4
(ANI1)
Data 6
(ANI1)
ADA0CR1
INTAD
Conversion start
Set ADA0CE bit = 1
ADA0PFT
unmatch
ADA0PFT
unmatch
ADA0PFT
match
ADA0PFT
match
ADA0PFT
match
Conversion start
Set ADA0CE bit = 1
(2) Continuous scan mode
In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0
pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of
channel 0 is compared with the value of the ADA0PFT register. If the result of power-fail comparison matches
the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register, and the INTAD
signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and the
INTAD signal is not generated.
After the result of the first conversion has been stored in the ADA0CR0 register, the results of sequentially
converting the voltages on the analog input pins up to the pin specified by the ADA0S register are continuously
stored. After completion of conversion, the next conversion is started from the ANI0 pin again, unless the
ADA0CE bit is cleared to 0.
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Figure 12-7. Timing Example of Continuous Scan Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 03H)
(a) Timing example
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
Data 7
(ANI2)
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 5
(ANI0)
Data 6
(ANI1)
ADA0CRn
INTAD
Conversion start
Set ADA0CE bit = 1
ADA0PFT
match
ADA0PFT
unmatch
ANI3
ANI0
ANI1
ANI2
Data 1
Data 2
Data 3
Data 4
Data 6
Data 5
Data 7
(b) Block diagram
A/D converter
ADA0CRn register
Analog input pin
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI21
ANI22
ANI23
.
.
.
.
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ADA0CR21
ADA0CR22
ADA0CR23
.
.
.
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(3) One-shot scan mode
In this mode, the results of converting the voltages of the analog input pins sequentially selected from the ANI0
pin to the pin specified by the ADA0S register are stored, and the set value of the ADA0CR0H register of
channel 0 is compared with the set value of the ADA0PFT register. If the result of power-fail comparison
matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CR0 register and the
INTAD signal is generated. If it does not match, the conversion result is stored in the ADA0CR0 register, and
the INTAD0 signal is not generated. After the result of the first conversion has been stored in the ADA0CR0
register, the results of converting the signals on the analog input pins specified by the ADA0S register are
sequentially stored. The conversion is stopped after it has been completed.
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Figure 12-8. Timing Example of One-Shot Scan Mode Operation
(When Power-Fail Comparison Is Made: ADA0S Register = 03H)
(a) Timing example
A/D conversion
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 1
(ANI0)
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
ADA0CRn
INTAD
Conversion start
Set ADA0CE bit = 1
Conversion end
ADA0PFT
match
ANI3
ANI0
ANI1
ANI2
Data 1
Data 2
Data 3
Data 4
Data 6
Data 5
Data 7
(b) Block diagram
A/D converter
ADA0CRn register
Analog input pin
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI21
ANI22
ANI23
.
.
.
.
ADA0CR0
ADA0CR1
ADA0CR2
ADA0CR3
ADA0CR4
ADA0CR5
ADA0CR21
ADA0CR22
ADA0CR23
.
.
.
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12.6 Cautions
(1) When A/D converter is not used
When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE
bit to 0.
(2) Input range of ANI0 to ANI23 pins
Input the voltage within the specified range to the ANI0 to ANI23 pins. If a voltage equal to or higher than
AV
REF0
or equal to or lower than AV
SS
(even within the range of the absolute maximum ratings) is input to any of
these pins, the conversion value of that channel is undefined, and the conversion value of the other channels
may also be affected.
(3) Countermeasures against noise
To maintain the 10-bit resolution, the ANI0 to ANI23 pins must be effectively protected from noise. The
influence of noise increases as the output impedance of the analog input source becomes higher. To lower the
noise, connecting an external capacitor as shown in Figure 12-9 is recommended.
Figure 12-9. Processing of Analog Input Pin
AV
REF0
V
DD
V
SS
AV
SS
Clamp with a diode with a low V
F
(0.3 V or less)
if noise equal to or higher than AV
REF0
or equal
to or lower than AV
SS
may be generated.
ANI0 to ANI23
(4) Alternate I/O
The analog input pins (ANI0 to ANI23) function alternately as port pins. When selecting one of the ANI0 to
ANI23 pins to execute A/D conversion, do not execute an instruction to read an input port or write to an output
port during conversion as the conversion resolution may drop.
Also the conversion resolution may drop at the pins set as output port pins during A/D conversion if the current
flows due to the effect of the external circuit connected to the port pins.
If a digital pulse is applied to a pin adjacent to the pin whose input signal is being converted, the A/D
conversion value may not be as expected due to the influence of coupling noise. Therefore, do not apply a
pulse to a pin adjacent to the pin undergoing A/D conversion.
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(5) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the
analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected
analog input signal may be stored and the conversion end interrupt request flag may be set immediately before
the ADA0S register is rewritten. If the ADIF flag is read immediately after the ADA0S register is rewritten, the
ADIF flag may be set even though the A/D conversion of the newly selected analog input pin has not been
completed. When A/D conversion is stopped, clear the ADIF flag before resuming conversion.
Figure 12-10. Generation Timing of A/D Conversion End Interrupt Request
ADA0S rewriting
(ANIn conversion start)
ADA0S rewriting
(ANIm conversion start)
ADIF is set, but ANIm
conversion does not end
A/D conversion
ADA0CRn
INTAD
ANIn
ANIn
ANIm
ANIm
ANIm
ANIn
ANIn
ANIm
Remark n = 0 to 23
m = 0 to 23
(6) Internal equivalent circuit
The following shows the equivalent circuit of the analog input block.
Figure 12-11. Internal Equivalent Circuit of ANIn Pin
ANIn
C
IN
R
IN
R
IN
C
IN
TBD TBD
Remark n = 0 to 23
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(7) AV
REF0
pin
(a) The AV
REF0
pin is used as the power supply pin of the A/D converter and also supplies power to the
alternate-function ports. In an application where a backup power supply is used, be sure to supply the
same voltage as V
DD
to the AV
REF0
pin as shown in Figure 12-12.
(b) The AV
REF0
pin is also used as the reference voltage pin of the A/D converter. If the source supplying
power to the AV
REF0
pin has a high impedance or if the power supply has a low current supply capability,
the reference voltage may fluctuate due to the current that flows during conversion (especially, immediately
after the conversion operation enable bit ADA0CE has been set to 1). As a result, the conversion accuracy
may drop. To avoid this, it is recommended to connect a capacitor across the AV
REF0
and AV
SS
pins to
suppress the reference voltage fluctuation as shown in Figure 12-12.
(c) If the source supplying power to the AV
REF0
pin has a high DC resistance (for example, because of
insertion of a diode), the voltage when conversion is enabled may be lower than the voltage when
conversion is stopped, because of a voltage drop caused by the A/D conversion current.
Figure 12-12. AV
REF0
Pin Processing Example
AV
REF0
Note
AV
SS
Main power supply
Note Parasitic
inductance
(8) Reading ADA0CRn result
When the ADA0M0 to ADA0M2 or ADA0S register is written, the contents of the ADA0CRn register may be
undefined. Read the conversion result after completion of conversion and before writing to the ADA0M0 to
ADA0M2 and ADA0S registers. The correct conversion result may not be read at a timing different from the
above.
(9) A/D conversion result
If there is noise at the analog input pins and at the reference voltage input pins, that noise may generate an
illegal conversion result. Software processing will be needed to avoid a negative effect on the system from this
illegal conversion result. An example of this software processing is shown below.
Take the average result of a number of A/D conversions and use that as the A/D conversion result.
Execute a number of A/D conversions consecutively and use those results, omitting any exceptional results
that may have been obtained.
If an A/D conversion result that is judged to have generated a system malfunction is obtained, be sure to
recheck the system malfunction before performing malfunction processing.
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(10) Variation of A/D conversion results
The results of the A/D conversion may vary depending on the fluctuation of the supply voltage, or may be
affected by noise. To reduce the variation, take counteractive measures with the program such as averaging
the A/D conversion results.
(11) A/D conversion result hysteresis characteristics
The successive comparison type A/D converter holds the analog input voltage in the internal sample & hold
capacitor and then performs A/D conversion. After the A/D conversion has finished, the analog input voltage
remains in the internal sample & hold capacitor. As a result, the following phenomena may occur.
When the same channel is used for A/D conversions, if the voltage is higher or lower than the previous A/D
conversion, then hysteresis characteristics may appear where the conversion result is affected by the
previous value. Thus, even if the conversion is performed at the same potential, the result may vary.
When switching the analog input channel, hysteresis characteristics may appear where the conversion
result is affected by the previous channel value. This is because one A/D converter is used for the A/D
conversions. Thus, even if the conversion is performed at the same potential, the result may vary.
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12.7 How to Read A/D Converter Characteristics Table
This section describes the terms related to the A/D converter.
(1) Resolution
The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of
digital output is called 1 LSB (least significant bit). The ratio of 1 LSB to the full scale is expressed as %FSR
(full-scale range). %FSR is the ratio of a range of convertible analog input voltages expressed as a percentage,
and can be expressed as follows, independently of the resolution.
1%FSR = (Maximum value of convertible analog input voltage Minimum value of convertible analog
input voltage)/100
=
(AV
REF0
- 0)/100
=
AV
REF0
/100
When the resolution is 10 bits, 1 LSB is as follows:
1 LSB = 1/2
10
= 1/1,024
=
0.098%FSR
The accuracy is determined by the overall error, independently of the resolution.
(2) Overall error
This is the maximum value of the difference between an actually measured value and a theoretical value.
It is a total of zero-scale error, full-scale error, linearity error, and a combination of these errors.
The overall error in the characteristics table does not include the quantization error.
Figure 12-13. Overall Error
Ideal line
Overall error
1......1
0......0
0
AV
REF0
Analog input
Digital output
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(3) Quantization error
This is an error of
1/2 LSB that inevitably occurs when an analog value is converted into a digital value.
Because the A/D converter converts analog input voltages in a range of
1/2 LSB into the same digital codes,
a quantization error is unavoidable.
This error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, or
differential linearity error in the characteristics table.
Figure 12-14. Quantization Error
Quantization error
1......1
0......0
0
AV
REF0
Analog input
Digital output
1/2 LSB
1/2 LSB
(4) Zero-scale error
This is the difference between the actually measured analog input voltage and its theoretical value when the
digital output changes from 0...000 to 0...001 (1/2 LSB).
Figure 12-15. Zero-Scale Error
AV
REF0
Analog input (LSB)
Digital output (lower 3 bits)
Ideal line
111
-1
0
1
2
3
100
011
010
001
000
Zero-scale error
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(5) Full-scale error
This is the difference between the actually measured analog input voltage and its theoretical value when the
digital output changes from 1...110 to 1...111 (full scale
- 3/2 LSB).
Figure 12-16. Full-Scale Error
AV
REF0
Analog input (LSB)
Digital output (lower 3 bits)
111
AV
REF0
-
3
0
AV
REF0
-
2 AV
REF0
-
1
100
011
010
000
Full-scale error
(6) Differential linearity error
Ideally, the width to output a specific code is 1 LSB. This error indicates the difference between the actually
measured value and its theoretical value when a specific code is output. This indicates the basic
characteristics of the A/D conversion when the voltage applied to the analog input pins of the same channel is
consistently increased bit by bit from AV
SS
to AV
REF0
. When the input voltage is increased or decreased, or
when two or more channels are used, see 12.7 (2) Overall error.
Figure 12-17. Differential Linearity Error
Ideal width of 1 LSB
Differential
linearity error
1......1
0......0
AV
REF0
Analog input
Digital output
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(7) Integral linearity error
This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It
indicates the maximum value of the difference between the actually measured value and its theoretical value
where the zero-scale error and full-scale error are 0.
Figure 12-18. Integral Linearity Error
1......1
0......0
0
AV
REF0
Analog input
Digital output
Ideal line
Integral
linearity error
(8) Conversion time
This is the time required to obtain a digital output after each trigger has been generated.
The conversion time in the characteristics table includes the sampling time.
(9) Sampling time
This is the time for which the analog switch is ON to load an analog voltage to the sample & hold circuit.
Figure 12-19. Sampling Time
Sampling time
Conversion time
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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
The V850ES/HJ2 includes asynchronous serial interface A (UARTA).
The number of channels differs depending on the product. Table 13-1 shows the number of channels of each
product.
Table 13-1. Number of Channels of Asynchronous Serial Interface A
Product (Part Number)
Number of Channels
PD70F3709, 70F3710
3 channels (UARTA0 to UARTA2)
PD70F3711, 70F3712
4 channels (UARTA0 to UARTA3)
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13.1 Features
Transfer rate: 300 bps to 312.5 kbps (using internal system clock of 20 MHz and dedicated baud rate generator)
Full-duplex communication: Internal UARTAn receive data register (UAnRX)
Internal UARTAn transmit data register (UAnTX)
2-pin configuration:
TXDAn: Transmit data output pin
RXDAn: Receive data input pin
Reception error output function
Parity error
Framing error
Overrun error
Interrupt sources: 2
Reception complete interrupt (INTUAnR):
An interrupt is generated in the reception enabled status by
ORing three types of reception errors. It is also generated
when receive data is transferred from the receive shift register
to the receive data register after completion of serial transfer.
Transmission enable interrupt (INTUAnT):
This interrupt occurs upon transfer of transmit data from the
transmit data register to the transmit shift register in the
transmission enabled status.
Character length: 7, 8 bits
Parity function: Odd, even, 0, none
Transmission stop bit: 1, 2 bits
On-chip dedicated baud rate generator
MSB-/LSB-first transfer selectable
Transmit/receive data inverted input/output possible
SBF (Sync Break Field) transmission/reception in the LIN (Local Interconnect Network) communication format
possible
13 to 20 bits selectable for SBF transmission
Recognition of 11 bits or more possible for SBF reception
SBF reception flag provided
Remark n = 0 to 3 (
PD70F3711, 70F3712)
n = 0 to 2 (
PD70F3709, 70F3710)
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13.2 Configuration
The block diagram of the UARTAn is shown below.
Figure 13-1. Block Diagram of Asynchronous Serial Interface An
Internal bus
Internal bus
UAnOTP0
UAnCTL0
UAnSTR
UAnCTL1
UAnCTL2
Receive
shift register
UAnRX
Filter
Selector
UAnTX
Transmit
shift register
Transmission
controller
Reception
controller
Selector
Baud rate
generator
Baud rate
generator
INTUAnR
INTUAnT
TXDAn
RXDAn
f
XX
to f
XX
/2
10
ASCKA0
Note
Reception unit
Transmission
unit
Clock
selector
Note UARTA0
only
Remarks 1. n = 0 to 3 (
PD70F3711, 70F3712)
n = 0 to 2 (
PD70F3709, 70F3710)
2. For the configuration of the baud rate generator, see Figure 13-13.
UARTAn includes the following hardware units.
Table 13-2. Configuration of UARTAn
Item Configuration
Registers
UARTAn control register 0 (UAnCTL0)
UARTAn control register 1 (UAnCTL1)
UARTAn control register 2 (UAnCTL2)
UARTAn option control register 0 (UAnOPT0)
UARTAn status register (UAnSTR)
UARTAn receive shift register
UARTAn receive data register (UAnRX)
UARTAn transmit shift register
UARTAn transmit data register (UAnTX)
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(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation.
(2) UARTAn control register 1 (UAnCTL1)
The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn.
(3) UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn.
(4) UARTAn option control register 0 (UAnOPT0)
The UAnOPT0 register is an 8-bit register used to control serial transfer for the UARTAn.
(5) UARTAn status register (UAnSTR)
The UAnSTRn register consists of flags indicating the error contents when a reception error occurs. Each one
of the reception error flags is set (to 1) upon occurrence of a reception error and is reset (to 0) by reading the
UAnSTR register.
(6) UARTAn receive shift register
This is a shift register used to convert the serial data input to the RXDAn pin into parallel data. Upon reception
of 1 byte of data and detection of the stop bit, the receive data is transferred to the UAnRX register.
This register cannot be manipulated directly.
(7) UARTAn receive data register (UAnRX)
The UAnRX register is an 8-bit register that holds receive data. When 7 characters are received, 0 is stored in
the highest bit (when data is received LSB first).
In the reception enabled status, receive data is transferred from the UARTAn receive shift register to the
UAnRX register in synchronization with the completion of shift-in processing of 1 frame.
Transfer to the UAnRX register also causes the reception complete interrupt request signal (INTUAnR) to be
output.
(8) UARTAn transmit shift register
The transmit shift register is a shift register used to convert the parallel data transferred from the UAnTX
register into serial data.
When 1 byte of data is transferred from the UAnTX register, the shift register data is output from the TXDAn pin.
This register cannot be manipulated directly.
(9) UARTAn transmit data register (UAnTX)
The UAnTX register is an 8-bit transmit data buffer. Transmission starts when transmit data is written to the
UAnTX register. When data can be written to the UAnTX register (when data of one frame is transferred from
the UAnTX register to the UARTAn transmit shift register), the transmission enable interrupt request signal
(INTUAnT) is generated.
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13.3 Registers
(1) UARTAn control register 0 (UAnCTL0)
The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
(1/2)
UAnPWR
Disable UARTAn operation (UARTAn reset asynchronously)
Enable UARTAn operation
UAnPWR
0
1
UARTAn operation control
UAnCTL0
UAnTXE UAnRXE UAnDIR
UAnPS1 UAnPS0
UAnCL
UAnSL
6
5
4
3
2
1
After reset: 10H R/W Address: UA0CTL0 FFFFFA00H, UA1CTL0 FFFFFA10H,
UA2CTL0 FFFFFA20H, UA3CTL0 FFFFFA30H
The UARTAn operation is controlled by the UAnPWR bit. The TXDAn pin output
is fixed to high level by clearing the UAnPWR bit to 0 (fixed to low level if
UAnOPT0.UAnTDL bit = 1).
Disable transmission operation
Enable transmission operation
UAnTXE
0
1
Transmission operation enable
To start transmission, set the UAnPWR bit to 1 and then set the UAnTXE bit to 1.
To stop, transmission clear the UAnTXE bit to 0 and then UAnPWR bit to 0.
To initialize the transmission unit, clear the UAnTXE bit to 0, wait for two cycles of
the base clock, and then set the UAnTXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 13.6 (1) (a) Base clock).
Disable reception operation
Enable reception operation
UAnRXE
0
1
Reception operation enable
To start reception, set the UAnPWR bit to 1 and then set the UAnRXE bit to 1.
To stop reception, clear the UAnRXE bit to 0 and then UAnPWR bit to 0.
To initialize the reception unit, clear the UAnRXE bit to 0, wait for two periods of
the base clock, and then set the UAnRXE bit to 1 again. Otherwise, initialization
may not be executed (for the base clock, see 13.6 (1) (a) Base clock).
7
0
Remark n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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(2/2)
7 bits
8 bits
UAnCL
0
1
Specification of data character length of 1 frame of transmit/receive data
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
1 bit
2 bits
UAnSL
0
1
Specification of length of stop bit for transmit data
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
This register is rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the
UAnRXE bit = 0.
If "Reception with 0 parity" is selected during reception, a parity check is not performed.
Therefore, the UAnSTR.UAnPE bit is not set.
When transmission and reception are performed in the LIN format, clear the
UAnPS1 and UAnPS0 bits to 00.
No parity output
0 parity output
Odd parity output
Even parity output
Reception with no parity
Reception with 0 parity
Odd parity check
Even parity check
UAnPS1
0
0
1
1
Parity selection during transmission Parity selection during reception
UAnPS0
0
1
0
1
MSB-first transfer
LSB-first transfer
UAnDIR
0
1
Transfer direction selection
This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit =
the UAnRXE bit = 0.
Remark For details of parity, see 13.5.9 Parity types and operations.
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(2) UARTAn control register 1 (UAnCTL1)
For details, see 13.6 (2) UARTAn control register 1 (UAnCTL1).
(3) UARTAn control register 2 (UAnCTL2)
For details, see 13.6 (3) UARTAn control register 2 (UAnCTL2).
(4) UARTAn option control register 0 (UAnOPT0)
The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(1/2)
UAnSRF
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnRXE bit = 0 are set.
Also upon normal end of SBF reception.
During SBF reception
UAnSRF
0
1
SBF reception flag
UAnOPT0
UAnSRT
UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL
UAnRDL
6
5
4
3
2
1
After reset: 14H R/W Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H,
UA2OPT0 FFFFFA23H, UA3OPT0 FFFFFA33H
SBF reception trigger
UAnSRT
0
1
SBF reception trigger
SBF (Sync Break Field) reception is judged during LIN communication.
The UAnSRF bit is held at 1 when an SBF reception error occurs, and then SBF
reception is started again.
This is the SBF reception trigger bit during LIN communication, and when read,
"0" is always read. For SBF reception, set the UAnSRT bit (to 1) to enable SBF
reception.
Set the UAnSRT bit after setting the UAnPWR bit = UAnRXE bit = 1.
This is the SBF transmission trigger bit during LIN communication, and when read,
"0" is always read.
Set the UAnSTT bit after setting the UAnPWR bit = UAnTXE bit = 1.
SBF transmission trigger
UAnSTT
0
1
SBF transmission trigger
7
0
-
-
Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception (UAnSRF bit = 1).
Remark n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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(2/2)
UAnSLS2
1
1
1
0
0
0
0
1
UAnSLS1
0
1
1
0
0
1
1
0
UAnSLS0
1
0
1
0
1
0
1
0
13-bit output (reset value)
14-bit output
15-bit output
16-bit output
17-bit output
18-bit output
19-bit output
20-bit output
SBF transmit length selection
The output level of the TXDAn pin can be inverted using the UAnTDL bit.
This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0.
Normal output of transfer data
Inverted output of transfer data
UAnTDL
0
1
Transmit data level bit
The input level of the RXDAn pin can be inverted using the UAnRDL bit.
This register can be set when the UAnPWR bit = 0 or the UAnRXE bit = 0.
Normal input of transfer data
Inverted input of transfer data
UAnRDL
0
1
Receive data level bit
(5) UARTAn status register (UAnSTR)
The UAnSTR register is an 8-bit register that displays the UARTAn transfer status and reception error contents.
This register can be read or written in 8-bit or 1-bit units, but the UAnTSF bit is a read-only bit, while the
UAnPE, UAnFE, and UAnOVE bits can both be read and written. However, these bits can only be cleared by
writing 0; they cannot be set by writing 1 (even if 1 is written to them, the value is retained).
The initialization conditions are shown below.
Register/Bit Initialization
Conditions
UAnSTR register
Reset
UAnCTL0.UAnPWR = 0
UAnTSF bit
UAnCTL0.UAnTXE = 0
UAnPE, UAnFE, UAnOVE bits
0 write
UAnCTL0.UAnRXE = 0
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UAnTSF
When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set.
When, following transfer completion, there was no next data transfer
from UAnTX register
Write to UAnTX register
UAnTSF
0
1
Transfer status flag
UAnSTR
0
0
0
0
UAnPE
UAnFE
UAnOVE
6
5
4
3
2
1
After reset: 00H R/W Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H,
UA2STR FFFFFA24H, UA3STR FFFFFA34H
The UAnTSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UAnTSF bit = 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UAnTSF bit = 1.
When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
When 0 has been written
When parity of data and parity bit do not match during reception.
UAnPE
0
1
Parity error flag
The operation of the UAnPE bit is controlled by the settings of the
UAnCTL0.UAnPS1 and UAnCTL0.UAnPS0 bits.
The UAnPE bit can be read and written, but it can only be cleared by writing 0 to it, and
it cannot be set by writing 1 to it. When 1 is written to this bit, the value is retained.
When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set
When 0 has been written
When no stop bit is detected during reception
UAnFE
0
1
Framing error flag
Only the first bit of the receive data stop bits is checked, regardless of the value
of the UAnCTL0.UAnSL bit.
The UAnFE bit can be both read and written, but it can only be cleared by
writing 0 to it, and it cannot be set by writing 1 to it. When 1 is written to this bit,
the value is retained.
When the UAnPWR bit = 0 or the UAnRXE bit = 0 has been set.
When 0 has been written
When receive data has been set to the UAnRX register and the next
receive operation is completed before that receive data has been read
UAnOVE
0
1
Overrun error flag
When an overrun error occurs, the data is discarded without the next receive data
being written to the receive buffer.
The UAnOVE bit can be both read and written, but it can only be cleared by writing
0 to it. When 1 is written to this bit, the value is retained.
7
0
Remark n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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(6) UARTAn receive data register (UAnRX)
The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register.
The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception
of 1 byte of data.
During LSB-first reception when the data length has been specified as 7 bits, the receive data is transferred to
bits 6 to 0 of the UAnRX register and the MSB always becomes 0. During MSB-first reception, the receive data
is transferred to bits 7 to 1 of the UAnRX register and the LSB always becomes 0.
When an overrun error (UAnOVE) occurs, the receive data at this time is not transferred to the UAnRX register
and is discarded.
This register is read-only, in 8-bit units.
In addition to reset input, the UAnRX register can be set to FFH by clearing the UAnCTL0.UAnPWR bit to 0.
UAnRX
6
5
4
3
2
1
After reset: FFH R Address: UA0RX FFFFFA06H, UA1RX FFFFFA16H,
UA2RX FFFFFA26H, UA3RX FFFFFA36H
7
0
Remark n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
(7) UARTAn transmit data register (UAnTX)
The UAnTX register is an 8-bit register used to set transmit data.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
UAnTX
6
5
4
3
2
1
After reset: FFH R/W Address: UA0TX FFFFFA07H, UA1TX FFFFFA17H,
UA2TX FFFFFA27H, UA3TX FFFFFA37H
7
0
Remark n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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13.4 Interrupt Request Signals
The following two interrupt request signals are generated from UARTAn.
Reception complete interrupt request signal (INTUAnR)
Transmission enable interrupt request signal (INTUAnT)
The default priority for these two interrupt request signals is reception complete interrupt request signal then
transmission enable interrupt request signal.
Table 13-3. Interrupts and Their Default Priorities
Interrupt Priority
Reception complete
High
Transmission enable
Low
(1) Reception complete interrupt request signal (INTUAnR)
A reception complete interrupt request signal is output when data is shifted into the receive shift register and
transferred to the UAnRX register in the reception enabled status.
When a reception complete interrupt request signal is received and the data is read, read the UAnSTR register
and check that the reception result is not an error.
No reception complete interrupt request signal is generated in the reception disabled status.
(2) Transmission enable interrupt request signal (INTUAnT)
If transmit data is transferred from the UAnTX register to the UARTAn transmit shift register with transmission
enabled, the transmission enable interrupt request signal is generated.
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13.5 Operation
13.5.1 Data format
Full-duplex serial data reception and transmission is performed.
As shown in Figure 13-2, one data frame of transmit/receive data consists of a start bit, character bits, parity bit,
and stop bit(s).
Specification of the character bit length within 1 data frame, parity selection, specification of the stop bit length, and
specification of MSB/LSB-first transfer are performed using the UAnCTL0 register.
Moreover, control of UART output/inverted output for the TXDAn bit is performed using the UAnOPT0.UAnTDL bit.
Start
bit.................. 1 bit
Character bits........7 bits/8 bits
Parity bit ................Even parity/odd parity/0 parity/no parity
Stop
bit .................. 1 bit/2 bits
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Figure 13-2. UARTA Transmit/Receive Data Format
(a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
(b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity
bit
Stop
bit
(c) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H, TXDAn inversion
1 data frame
Start
bit
D7
D6
D5
D4
D3
D2
D1
D0
Parity
bit
Stop
bit
(d) 7-bit data length, LSB first, odd parity, 2 stop bits, transfer data: 36H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
Parity
bit
Stop
bit
Stop
bit
(e) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop
bit
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13.5.2 SBF transmission/reception format
The V850ES/HJ2 has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN
function.
Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave
is
15% or less.
Figures 13-3 and 13-4 outline the transmission and reception manipulations of LIN.
Figure 13-3. LIN Transmission Manipulation Outline
LIN
bus
Wake-up
signal
frame
Sync
break
field
Sync
field
Identifier
field
DATA
field
DATA
field
Check
SUM
field
INTUAnT
interrupt
TXDAn (output)
Note 3
8 bits
Note 1
Note 2
13 bits
SBF transmission
Note 4
55H
transmission
Data
transmission
Data
transmission
Data
transmission
Data
transmission
Notes 1. The interval between each field is controlled by software.
2. SBF output is performed by hardware. The output width is the bit length set by the
UAnOPT0.UAnSBL2 to UAnOPT0.UAnSBL0 bits. If even finer output width adjustments are
required, such adjustments can be performed using the UAnCTLn.UAnBRS7 to UAnCTLn.UAnBRS0
bits.
3. 80H transfer in the 8-bit mode is substituted for the wakeup signal frame.
4. A transmission enable interrupt request signal (INTUAnT) is output at the start of each transmission.
The INTUAnT signal is also output at the start of each SBF transmission.
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Figure 13-4. LIN Reception Manipulation Outline
Reception interrupt (INTUAnR)
Edge detection
Capture timer
Disable
Disable
Enable
RXDAn (input)
Enable
Note 2
13 bits
SBF
reception
Note 3
Note 4
Note 1
SF reception
ID reception
Data
transmission
Data
transmission
Note 5
Data transmission
LIN
bus
Wake-up
signal
frame
Sync
break
field
Sync
field
Identifier
field
DATA
field
DATA
field
Check
SUM
field
Notes 1. The wakeup signal is sent by the pin edge detector, UARTAn is enabled, and the SBF reception
mode is set.
2. The receive operation is performed until detection of the stop bit. Upon detection of SBF reception
of 11 or more bits, normal SBF reception end is judged, and an interrupt signal is output. Upon
detection of SBF reception of less than 11 bits, an SBF reception error is judged, no interrupt signal
is output, and the mode returns to the SBF reception mode.
3. If SBF reception ends normally, an interrupt request signal is output. The timer is enabled by an SBF
reception complete interrupt. Moreover, error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE,
and UAnSTR.UAnFE bits is suppressed and UART communication error detection processing and
UARTAn receive shift register and data transfer of the UAnRX register are not performed. The
UARTAn receive shift register holds the initial value, FFH.
4. The RXDAn pin is connected to TI (capture input) of the timer, the transfer rate is calculated, and the
baud rate error is calculated. The value of the UAnCTL2 register obtained by correcting the baud
rate error after dropping UARTA enable is set again, causing the status to become the reception
status.
5. Check-sum field distinctions are made by software. UARTAn is initialized following CSF reception,
and the processing for setting the SBF reception mode again is performed by software.
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13.5.3 SBF transmission
When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and
SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit).
Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is
output. A transmission enable interrupt request signal (INTUAnT) is generated upon SBF transmission start.
Following the end of SBF transmission, the UAnSTT bit is automatically cleared. Thereafter, the UART transmission
mode is restored.
Transmission is suspended until the data to be transmitted next is written to the UAnTX register, or until the SBF
transmission trigger (UAnSTT bit) is set.
Figure 13-5. SBF Transmission
INTUAnT
interrupt
TXDAn
1
2
3
4
5
6
7
8
9
10
11
12
13
Stop
bit
Setting of UAnSTT bit
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13.5.4 SBF reception
The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the
UAnCTL0.UAnRXE bit to 1.
The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1.
In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start
bit detection is performed.
Following detection of the start bit, reception is started and the internal counter counts up according to the set baud
rate.
When a stop bit is received, if the SBF width is 11 or more bits, normal processing is judged and a reception
complete interrupt request signal (INTUAnR) is output. The UAnOPT0.UAnSRF bit is automatically cleared and SBF
reception ends. Error detection for the UAnSTR.UAnOVE, UAnSTR.UAnPE, and UAnSTR.UAnFE bits is suppressed
and UART communication error detection processing is not performed. Moreover, data transfer of the UARTAn receive
shift register and UAnRX register is not performed and FFH, the initial value, is held. If the SBF width is 10 or fewer
bits, reception is terminated as error processing without outputting an interrupt, and the SBF reception mode is
returned to. The UAnSRF bit is not cleared at this time.
Figure 13-6. SBF Reception
(a) Normal SBF reception (detection of stop bit in more than 10.5 bits)
UAnSRF
RXDAn
1
2
3
4
5
6
11.5
7
8
9
10
11
INTUAnR
interrupt
(b) SBF reception error (detection of stop bit in 10.5 or fewer bits)
UAnSRF
RXDAn
1
2
3
4
5
6
10.5
7
8
9
10
INTUAnR
interrupt
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13.5.5 UART transmission
A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1.
Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started
by writing transmit data to the UAnTX register. The start bit, parity bit, and stop bit are automatically added.
Since the CTS (transmit enable signal) input pin is not provided in UARTAn, use a port to check that reception is
enabled at the transmit destination.
The data in the UAnTX register is transferred to the UARTAn transmit shift register upon the start of the transmit
operation.
A transmission enable interrupt request signal (INTUAnT) is generated upon completion of transmission of the data
of the UAnTX register to the UARTAn transmit shift register, and thereafter the contents of the UARTAn transmit shift
register are output to the TXDAn pin.
Write of the next transmit data to the UAnTX register is enabled after the INTUAnT signal is generated.
Figure 13-7. UART Transmission
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
INTUAnT
TXDAn
Remarks 1. LSB first
2. n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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13.5.6 Continuous transmission procedure
UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the
shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable
interrupt request signal (INTUAnT).
An efficient communication rate is realized by writing the data to be transmitted next to the UAnTX register during
transfer.
During continuous transmission, do not write the next transmit data to the UAnTX register before a transmit request
interrupt signal (INTUAnT) is generated after transmit data is written to the UAnTX register and transferred to the
UARTAn transmit shift register. If a value is written to the UAnTX register before a transmit request interrupt signal is
generated, the previously set transmit data is overwritten by the latest transmit data.
Caution When initializing transmissions during the execution of continuous transmissions, make sure
that the UAnSTR.UAnTSF bit is 0, then perform the initialization. Transmit data that is initialized
when the UAnTSF bit is 1 cannot be guaranteed.
In the case of continuous transmission, the communication rate from the stop bit to the start bit
of the next data is extended by two operating clocks from the normal rate.
Figure 13-8. Continuous Transmission Processing Flow
Start
Register settings
UAnTX write
Yes
Yes
No
No
Occurrence of transmission
interrupt?
Required number of
writes performed?
End
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Figure 13-9. Continuous Transmission Operation Timing
(a) Transmission start
Start Data
(1)
Data (1)
TXDAn
UAnTX
Transmission
shift register
INTUAnT
UAnTSF
Data (2)
Data (2)
Data (1)
Data (3)
Parity
Stop
Start Data
(2)
Parity
Stop
Start
(b) Transmission end
Start
Data (n 1)
Data (n 1)
Data (n 1)
Data (n)
FF
Data (n)
TXDAn
UAnTX
Transmission
shift register
INTUAnT
UAnTSF
UAnPWR or UAnTXE bit
Parity
Stop
Stop
Start
Data (n)
Parity
Parity
Stop
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13.5.7 UART reception
The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE
bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Start bit detection is performed using a two-step detection routine.
First the rising edge of the RXDAn pin is detected and sampling is started at the falling edge. The start bit is
recognized if the RXDAn pin is low level at the start bit sampling point. After a start bit has been recognized, the
receive operation starts, and serial data is saved to the UARTAn receive shift register according to the set baud rate.
When the reception complete interrupt request signal (INTUAnR) is output upon reception of the stop bit, the data
of the UARTAn receive shift register is written to the UAnRX register. However, if an overrun error (UAnSTR.UAnOVE
bit) occurs, the receive data at this time is not written to the UAnRX register and is discarded.
Even if a parity error (UAnSTR.UAnPE bit) or a framing error (UAnSTR.UAnFE bit) occurs during reception,
reception continues until the reception position of the first stop bit, and INTUAnR is output following reception
completion.
Figure 13-10. UART Reception
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
INTUAnR
RXDAn
UAnRX
Cautions 1. Be sure to read the UAnRX register even when a reception error occurs. If the UAnRX register
is not read, an overrun error occurs during reception of the next data, and reception errors
continue occurring indefinitely.
2. The operation during reception is performed assuming that there is only one stop bit. A
second stop bit is ignored.
3. When reception is completed, read the UAnRX register after the reception complete interrupt
request signal (INTUAnR) has been generated, and clear the UAnPWR or UAnRXE bit to 0. If
the UAnPWR or UAnRXE bit is cleared to 0 before the INTUAnR signal is generated, the read
value of the UAnRX register cannot be guaranteed.
4. If receive completion processing (INTUAnR signal generation) of UARTAn and the UAnPWR
bit = 0 or UAnRXE bit = 0 conflict, the INTUAnR signal may be generated in spite of these
being no data stored in the UAnRX register.
To complete reception without waiting INTUAnR signal generation, be sure to clear (0) the
interrupt request flag (UAnRIF) of the UAnRIC register, after setting (1) the interrupt mask flag
(UAnRMK) of the interrupt control register (UAnRIC) and then set (1) the UAnPWR bit = 0 or
UAnRXE bit = 0.
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13.5.8 Reception errors
Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data
reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal
(INTUAnR) is output when an error occurs.
It is possible to ascertain which error occurred during reception by reading the contents of the UAnSTR register.
Clear the reception error flag by writing 0 to it after reading it.
Receive data read flow
START
No
INTUAnR signal
generated?
Error occurs?
END
Yes
No
Yes
Error processing
Read UAnRX register
Read UAnSTR register
Caution When an INTUAnR signal is generated, the UAnSTR register must be read to check for errors.
Reception error causes
Error Flag
Reception Error
Cause
UAnPE
Parity error
Received parity bit does not match the setting
UAnFE
Framing error
Stop bit not detected
UAnOVE
Overrun error
Reception of next data completed before data was read from receive buffer
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When reception errors occur, perform the following procedures depending upon the kind of error.
Parity error
If false data is received due to problems such as noise in the reception line, discard the received data and
retransmit.
Framing error
A baud rate error may have occurred between the reception side and transmission side or the start bit may have
been erroneously detected. Since this is a fatal error for the communication format, check the operation stop in
the transmission side, perform initialization processing each other, and then start the communication again.
Overrun error
Since the next reception is completed before reading receive data, 1 frame of data is discarded. If this data was
needed, do a retransmission.
Caution If a receive error interrupt occurs during continuous reception, read the contents of the UAnSTR
register must be read before the next reception is completed, then perform error processing.
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13.5.9 Parity types and operations
Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00.
The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the
transmission side and the reception side.
In the case of even parity and odd parity, it is possible to detect odd-count bit errors. In the case of 0 parity and no
parity, errors cannot be detected.
(a) Even parity
(i) During transmission
The number of bits whose value is "1" among the transmit data, including the parity bit, is controlled so as
to be an even number. The parity bit values are as follows.
Odd number of bits whose value is "1" among transmit data: 1
Even number of bits whose value is "1" among transmit data: 0
(ii) During reception
The number of bits whose value is "1" among the reception data, including the parity bit, is counted, and if
it is an odd number, a parity error is output.
(b) Odd parity
(i) During transmission
Opposite to even parity, the number of bits whose value is "1" among the transmit data, including the parity
bit, is controlled so that it is an odd number. The parity bit values are as follows.
Odd number of bits whose value is "1" among transmit data: 0
Even number of bits whose value is "1" among transmit data: 1
(ii) During reception
The number of bits whose value is "1" among the receive data, including the parity bit, is counted, and if it
is an even number, a parity error is output.
(c) 0 parity
During transmission, the parity bit is always made 0, regardless of the transmit data.
During reception, parity bit check is not performed. Therefore, no parity error occurs, regardless of whether the
parity bit is 0 or 1.
(d) No parity
No parity bit is added to the transmit data.
Reception is performed assuming that there is no parity bit. No parity error occurs since there is no parity bit.
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13.5.10 Receive data noise filter
This filter samples the RXDAn pin using the base clock of the prescaler output.
When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled
as the input data. Therefore, data not exceeding 2 clock width is judged to be noise and is not delivered to the internal
circuit (see Figure 13-12). See 13.6 (1) (a) Base clock regarding the base clock.
Moreover, since the circuit is as shown in Figure 13-11, the processing that goes on within the receive operation is
delayed by 3 clocks in relation to the external signal status.
Figure 13-11. Noise Filter Circuit
Match
detector
In
Base clock (f
UCLK
)
RXDAn
Q
In
LD_EN
Q
Internal signal C
Internal signal B
In
Q
Internal signal A
Figure 13-12. Timing of RXDAn Signal Judged as Noise
Internal signal B
Base clock
RXDAn (input)
Internal signal C
Mismatch
(judged as noise)
Internal signal A
Mismatch
(judged as noise)
Match
Match
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13.6 Dedicated Baud Rate Generator
The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter,
and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated
baud rate generator output can be selected for each channel.
There is an 8-bit counter for transmission and another one for reception.
(1) Baud rate generator configuration
Figure 13-13. Configuration of Baud Rate Generator
f
UCLK
Selector
UAnPWR
8-bit counter
Match detector
Baud rate
UAnCTL2:
UAnBRS7 to UAnBRS0
1/2
UAnPWR, UAnTXEn bits (or UAnRXE bit)
UAnCTL1:
UAnCKS3 to UAnCKS0
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
f
XX
/256
f
XX
/512
f
XX
/1024
ASCKA0
Note
Note Only UARTA0 is valid; setting UARTA1 to UARTA3 is prohibited.
Remarks 1. n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
2. f
XX
: Main clock frequency
3. f
UCLK
: Base clock frequency
(a) Base clock
When the UAnCTL0.UAnPWR bit is 1, the clock selected by the UAnCTL1.UAnCKS3 to
UAnCTL1.UAnCKS0 bits is supplied to the 8-bit counter. This clock is called the base clock (f
UCLK
).
(b) Serial clock generation
A serial clock can be generated by setting the UAnCTL1 register and the UAnCTL2 register (n = 0 to 3).
The base clock is selected by UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits.
The frequency division value for the 8-bit counter can be set using the UAnCTL2.UAnBRS7 to
UAnCTL2.UAnBRS0 bits.
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(2) UARTAn control register 1 (UAnCTL1)
The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
0
UAnCTL1
0
0
0
UAnCKS3 UAnCKS2 UAnCKS1 UAnCKS0
6
5
4
3
2
1
After reset: 00H R/W Address: UA0CTL1 FFFFFA01H, UA1CTL1 FFFFFA11H,
UA2CTL1 FFFFFA21H, UA3CTL1 FFFFFA31H
7
0
f
XX
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
XX
/128
f
XX
/256
f
XX
/512
f
XX
/1,024
External clock
Note
(ASCKA0 pin)
Setting prohibited
UAnCKS2
0
0
0
0
1
1
1
1
0
0
0
0
UAnCKS3
0
0
0
0
0
0
0
0
1
1
1
1
Base clock (f
UCLK
) selection
UAnCKS1
0
0
1
1
0
0
1
1
0
0
1
1
UAnCKS0
0
1
0
1
0
1
0
1
0
1
0
1
Other than above
Note Only UARTA0 is valid; setting UARTA1 to UARTA3 is prohibited.
Remarks 1. f
XX
: Main clock frequency
2. n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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(3) UARTAn control register 2 (UAnCTL2)
The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
Caution Clear the UAnCTL0.UAnPWR bit to 0 or clear the UAnTXE and UAnRXE bits to 00 before
rewriting the UAnCTL2 register.
UAnBRS7
UAnCTL2
UAnBRS6 UAnBRS5 UAnBRS4 UAnBRS3 UAnBRS2 UAnBRS1 UAnBRS0
6
5
4
3
2
1
After reset FFH R/W Address: UA0CTL2 FFFFFA02H, UA1CTL2 FFFFFA12H,
UA2CTL2 FFFFFA22H, UA3CTL2 FFFFFA32H
7
0
UAn
BRS7
0
0
0
0
:
1
1
1
1
UAn
BRS6
0
0
0
0
:
1
1
1
1
UAn
BRS5
0
0
0
0
:
1
1
1
1
UAn
BRS4
0
0
0
0
:
1
1
1
1
UAn
BRS3
0
0
0
0
:
1
1
1
1
UAn
BRS2
0
1
1
1
:
1
1
1
1
UAn
BRS1
0
0
1
:
0
0
1
1
UAn
BRS0
0
1
0
:
0
1
0
1
Default
(k)
4
5
6
:
252
253
254
255
Serial
clock
f
UCLK
/4
f
UCLK
/5
f
UCLK
/6
:
f
UCLK
/252
f
UCLK
/253
f
UCLK
/254
f
UCLK
/255
Setting
prohibited
Remarks 1. f
UCLK
: Clock frequency selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits
2. n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
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(4) Baud rate
The baud rate is obtained by the following equation.
Baud rate = [bps]
When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at
UARTA0, calculate using the above equation).
Baud rate = [bps]
Remark f
UCLK
= Frequency of base clock selected by the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits
f
XX
: Main clock frequency
m = Value set using the UAnCTL1.UAnCKS3 to UAnCTL1.UAnCKS0 bits (m = 0 to 10)
k = Value set using the UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (k = 4 to 255)
The baud rate error is obtained by the following equation.
Error (%) =
- 1 100 [%]
=
- 1 100 [%]
When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at
UARTA0, calculate the baud rate error using the above equation).
Error (%) =
- 1 100 [%]
Cautions 1. The baud rate error during transmission must be within the error tolerance on the
receiving side.
2. The baud rate error during reception must satisfy the range indicated in (5) Allowable
baud rate range during reception.
f
UCLK
2
k
Actual baud rate (baud rate with error)
Target baud rate (correct baud rate)
f
XX
2
m+1
k
f
UCLK
2
k Target baud rate
f
XX
2
m+1
k Target baud rate
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To set the baud rate, perform the following calculation and set the UAnCTL1 and UAnCTL2 registers (when
using internal clock).
<1> Set k = f
XX
/(2
Target baud rate). Set m = 0.
<2> Set k = k/2 and m = m + 1 where k
256.
<3> Repeat <2> until k < 256.
<4> Roundup the first decimal place of k.
If k = 256 by the roundup, perform <2> again (k will become 128).
<5> Set m to the UAnCTL1 register and k to the UAnCTL2 register.
Example: When
f
XX
= 20 MHz and target baud rate = 153,600 bps
<1> k = 20,000,000/(2
153,600) = 65.10..., m = 0
<2>, <3> k = 65.10... < 256, m = 0
<4> Set value of UAnCTL2 register: k = 65 = 41H, set value of UAnCTL1 register: m = 0
Actual baud rate = 20,000,000/(2
65)
= 153,846 [bps]
Baud rate error = {20,000,000/(2
65 153,600) - 1} 100
= 0.160 [%]
The representative examples of baud rate settings are shown below.
Table 13-4. Baud Rate Generator Setting Data
f
XX
= 20 MHz
f
XX
= 16 MHz
f
XX
= 10 MHz
Baud Rate
(bps)
UAnCTL1 UAnCTL2 ERR
(%) UAnCTL1
UAnCTL2
ERR
(%) UAnCTL1
UAnCTL2 ERR
(%)
300
08H 82H 0.16 0AH 1AH 0.16 07H 82H 0.16
600 07H
82H
0.16
0AH
0DH
0.16
06H
82H
0.16
1,200 06H
82H
0.16
09H
0DH
0.16
05H
82H
0.16
2,400 05H
82H
0.16
08H
0DH
0.16
04H
82H
0.16
4,800 04H
82H
0.16
07H
0DH
0.16
03H
82H
0.16
9,600 03H
82H
0.16
06H
0DH
0.16
02H
82H
0.16
19,200
02H 82H 0.16 05H 0DH 0.16 01H 82H 0.16
31,250
01H A0H 0.00 01H 80H 0.00 00H A0H 0.00
38,400
01H 82H 0.16 00H D0H 0.16 00H 82H 0.16
76,800
00H 82H 0.16 03H 0DH 0.16 00H 41H 0.16
153,600
00H 41H 0.16 02H 0DH 0.16 00H 21H
-1.36
312,500 00H
20H
0.00
00H
1AH
-1.54 00H 10H 0.00
Remark f
XX
:
Main clock frequency
ERR: Baud rate error (%)
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(5) Allowable baud rate range during reception
The baud rate error range at the destination that is allowable during reception is shown below.
Caution The baud rate error during reception must be set within the allowable error range using the
following equation.
Figure 13-14. Allowable Baud Rate Range During Reception
FL
1 data frame (11
FL)
FLmin
FLmax
UARTAn
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Minimum
allowable
transfer rate
Maximum
allowable
transfer rate
Stop bit
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Latch timing
Stop bit
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
Remark n = 0 to 3:
PD70F3711, 70F3712
n = 0 to 2:
PD70F3709, 70F3710
As shown in Figure 13-14, the receive data latch timing is determined by the counter set using the UAnCTL2
register following start bit detection. The transmit data can be normally received if up to the last data (stop bit)
can be received in time for this latch timing.
When this is applied to 11-bit reception, the following is the theoretical result.
FL = (Brate)
-
1
Brate: UARTAn baud rate (n = 0 to 3)
k:
Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 3)
FL:
1-bit data length
Latch timing margin: 2 clocks
Minimum allowable transfer rate: FLmin = 11
FL - FL = FL
k
- 2
2k
21k + 2
2k
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Therefore, the maximum baud rate that can be received by the destination is as follows.
BRmax = (FLmin/11)
-
1
= Brate
Similarly, obtaining the following maximum allowable transfer rate yields the following.
FLmax = 11 FL - FL = FL
FLmax = FL
11
Therefore, the minimum baud rate that can be received by the destination is as follows.
BRmin = (FLmax/11)
-
1
= Brate
Obtaining the allowable baud rate error for UARTAn and the destination from the above-described equations for
obtaining the minimum and maximum baud rate values yields the following.
Table 13-5. Maximum/Minimum Allowable Baud Rate Error
Division Ratio (k)
Maximum Allowable Baud Rate Error
Minimum Allowable Baud Rate Error
4 +2.32%
-2.43%
8 +3.52%
-3.61%
20 +4.26%
-4.30%
50 +4.56%
-4.58%
100 +4.66%
-4.67%
255 +4.72%
-4.72%
Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock
frequency, and the division ratio (k). The higher the input clock frequency
and the larger the division ratio (k), the higher the accuracy.
2. k: Setting value of UAnCTL2.UAnBRS7 to UAnCTL2.UAnBRS0 bits (n = 0 to 3)
10
11
k + 2
2
k
21k
- 2
2
k
21k
- 2
20 k
22k
21k + 2
20k
21k
- 2
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(6) Baud rate during continuous transmission
During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks
longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no
influence on the transfer result.
Figure 13-15. Transfer Rate During Continuous Transfer
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL
1 data frame
FL
FL
FL
FL
FL
FL
FLstp
Start bit of 2nd byte
Start bit
Bit 0
Assuming 1 bit data length: FL; stop bit length: FLstp; and base clock frequency: f
UCLK
, we obtain the following
equation.
FLstp = FL + 2/f
UCLK
Therefore, the transfer rate during continuous transmission is as follows.
Transfer rate = 11
FL + (2/f
UCLK
)
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13.7 Cautions
(1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation
stops with each register retaining the value it had immediately before the clock supply was stopped. The
TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped.
However, the operation is not guaranteed after the clock supply is resumed. Therefore, after the clock supply
is resumed, the circuits should be initialized by setting the UAnCTL0.UAnPWR, UAnCTL0.UAnRXEn, and
UAnCTL0.UAnTXEn bits to 000.
(2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin.
To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear
PFCE91 bit to 0).
(3) In UARTAn, the interrupt caused by a communication error does not occur. When performing the transfer of
transmit data and receive data using DMA transfer, error processing cannot be performed even if errors (parity,
overrun, framing) occur during transfer. Either read the UAnSTR register after DMA transfer has been
completed to make sure that there are no errors, or read the UAnSTR register during communication to check
for errors.
(4) Start up the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnPWR bit to 1.
<2> Set the ports.
<3> Set the UAnCTL0.UAnTXE bit to 1, UAnCTL0.UAnRXE bit to 1.
(5) Stop the UARTAn in the following sequence.
<1> Set the UAnCTL0.UAnTXE bit to 0, UAnCTL0.UAnRXE bit to 0.
<2> Set the ports and set the UAnCTL0.UAnPWR bit to 0 (it is not a problem if port setting is not changed).
(6) In transmit mode (UAnCTL0.UAnPWR bit = 1 and UAnCTL0.UAnTXE bit = 1), do not overwrite the same value
to the UAnTX register by software because transmission starts by writing to this register. To transmit the same
value continuously, overwrite the same value.
(7) In continuous transmission, the communication rate from the stop bit to the next start bit is extended 2 base
clocks more than usual. However, the reception side initializes the timing by detecting the start bit, so the
reception result is not affected.
(8) If the break command is executed in the on-chip debug (OCD) mode and if UART receives data, an overrun
error occurs.
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CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
The V850ES/HJ2 has three channels of 3-wire serial interface (CSIB).
14.1 Features
Transfer rate: 8 Mbps to 4.9 kbps (f
XX
= 20 MHz, using internal clock)
Master mode and slave mode selectable
8-bit to 16-bit transfer, 3-wire serial interface
Interrupt request signals (INTCBnT, INTCBnR)
3
Serial clock and data phase switchable
Transfer data length selectable in 1-bit units between 8 and 16 bits
Transfer data MSB-first/LSB-first switchable
3-wire transfer SOBn: Serial data output
SIBn:
Serial data input
SCKBn: Serial clock I/O
Transmission mode, reception mode, and transmission/reception mode specifiable
Remark n = 0 to 2
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14.2 Configuration
The following shows the block diagram of CSIBn.
Figure 14-1. Block Diagram of CSIBn
Internal bus
CBnCTL2
CBnCTL0
CBnSTR
Controller
INTCBnR
SOBn
INTCBnT
CBnTX
SO latch
Phase
control
Shift register
CBnRX
CBnCTL1
Phase control
SIBn
Note
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
SCKBn
Selector
Note n = 0: f
BRG
n = 1: TOP01
n = 2: f
XX
/128
Remark n = 0 to 2
CSIBn includes the following hardware.
Table 14-1. Configuration of CSIBn
Item Configuration
Registers
CSIBn receive data register (CBnRX)
CSIBn transmit data register (CBnTX)
Control registers
CSIBn control register 0 (CBnCTL0)
CSIBn control register 1 (CBnCTL1)
CSIBn control register 2 (CBnCTL2)
CSIBn status register (CBnSTR)
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(1) CSIBn receive data register (CBnRX)
The CBnRX register is a 16-bit buffer register that holds receive data.
This register is read-only, in 16-bit units.
The receive operation is started by reading the CBnRX register in the reception enabled status.
If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL
register.
Reset sets this register to 0000H.
In addition to reset input, the CBnRX register can be initialized by clearing (to 0) the CBnPWR bit of the
CBnCTL0 register.
After reset: 0000H R Address: CB0RX FFFFFD04H, CB1RX FFFFFD14H,
CB2RX FFFFFD24H
CBnRX
(n = 0 to 2)
(2) CSIB transmit data register (CBnTX)
The CBnTX register is a 16-bit buffer register used to write the CSIBn transfer data.
This register can be read or written in 16-bit units.
The transmit operation is started by writing data to the CBnTX register in the transmission enabled status.
If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnTXL
register.
Reset sets this register to 0000H.
After reset 0000H R/W Address: CB0TX FFFFFD06H, CB1TX FFFFFD16H,
CB2TX FFFFFD26H
CBnTX
(n = 0 to 2)
Remark The communication start conditions are shown below.
Transmission mode (CBnTXE bit = 1, CBnRXE bit = 0):
Write to CBnTX register
Transmission/reception mode (CBnTXE bit = 1, CBnRXE bit = 1): Write to CBnTX register
Reception mode (CBnTXE bit = 0, CBnRXE bit = 1):
Read from CBnRX register
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14.3 Registers
The following registers are used to control CSIBn.
CSIBn control register 0 (CBnCTL0)
CSIBn control register 1 (CBnCTL1)
CSIBn control register 2 (CBnCTL2)
CSIBn status register (CBnSTR)
(1) CSIBn control register 0 (CBnCTL0)
CBnCTL0 is a register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
(1/3)
CBnPWR
Disable CSIBn operation and reset the CBnSTR register
Enable CSIBn operation
CBnPWR
0
1
Specification of CSIBn operation disable/enable
CBnCTL0
(n = 0 to 2)
CBnTXE
Note
CBnRXE
Note
CBnDIR
Note
0
0
CBnTMS
Note
CBnSCE
After reset: 01H R/W Address: CB0CTL0 FFFFFD00H, CB1CTL0 FFFFFD10H,
CB2CTL0 FFFFFD20H
The CBnPWR bit controls the CSIBn operation and resets the internal circuit.
Disable transmit operation
Enable transmit operation
CBnTXE
Note
0
1
Specification of transmit operation disable/enable
The SOBn output is low level when the CBnTXE bit is 0.
When the CBnRXE bit is cleared to 0, no reception complete interrupt is output
even when the prescribed data is transferred in order to disable the receive
operation, and the receive data (CBnRX register) is not updated.
Disable receive operation
Enable receive operation
CBnRXE
Note
0
1
Specification of receive operation disable/enable
Note These bits can only be rewritten when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be
set at the same time as rewriting these bits.
Caution To forcibly suspend transmission/reception, clear the CBnPWR bit instead of the CBnRxE
bit to 0.
At this time, the clock output is stopped.
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(2/3)
Single transfer mode
Continuous transfer mode
CBnTMS
Note
0
1
Transfer mode specification
[In single transfer mode]
The reception complete interrupt request signal (INTCBnR) is generated.
Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt
request signal (INTCBnT) is not generated.
If the next transmit data is written during communication (CBnSTR.CBnTSF bit =
1), it is ignored and the next communication is not started. Also, if reception-only
communication is set (CBnTXE bit = 0, CBnRXE bit = 1), the next communication
is not started even if the receive data is read during communication (CBnSTR.
CBbTSF bit = 1).
[In continuous transfer mode]
The continuous transmission is enabled by writing the next transmit data during
communication (CBnSTR.CBnTSF bit = 1). Writing the next transmission data is
enabled after a transmission enable interrupt (INTCBnT) occurrence.
If reception-only communication is set (CBnTXE bit = 0, CBnRXE bit = 1) in the
continuous transfer mode, the next reception is started continuously after a
reception complete interrupt (INTCBnR) regardless of the read operation of the
CBnRX register.
Therefore, read immediately the receive data from the CBnRX register. If this read
operation is delayed, an overrun error (CBnOVE bit = 1) occurs.
CBnDIR
Note
0
1
Specification of transfer direction mode (MSB/LSB)
MSB-first transfer
LSB-first transfer
Note These bits can only be rewritten when the CBnPWR bit = 0. However, CBnPWR bit = 1 can also be
set at the same time as rewriting these bits.
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(3/3)
Communication start trigger invalid
Communication start trigger valid
CBnSCE
0
1
Specification of start transfer disable/enable
In master mode
This bit enables or disables the communication start trigger.
(a) In single transmission or transmission/reception mode, or continuous
transmission or continuous transmission/reception mode
The setting of the CBnSCE bit has no influence on communication operation.
(b) In single reception mode
Clear the CBnSCE bit to 0 before reading the last receive data because
reception is started by reading the receive data (CBnRX register) to disable
the reception startup
Note 1
.
(c) In continuous reception mode
Clear the CBnSCE bit to 0 one communication clock before reception of the
last data is completed to disable the reception startup after the last data is
received
Note 2
.
In slave mode
This bit enables or disables the communication start trigger.
Set the CBnSCE bit to 1.
[Usage of CBnSCE bit]
In single reception mode
<1>When reception of the last data is completed by INTCBnR interrupt
servicing, clear the CBnSCE bit to 0 before reading the CBnRX register.
<2>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to
disable reception.
To continue reception, set the CBnSCE bit to 1 to start up the next reception
by dummy-reading the CBnRX register.
In continuous reception mode
<1>Clear the CBnSCE bit to 0 during the reception of the last data by INTCBnR
interrupt servicing.
<2>Read the CBnRX register.
<3>Read the last reception data by reading the CBnRX register after
acknowledging the CBnTIR interrupt.
<4>After confirming the CBnSTR.CBnTSF bit = 0, clear the CBnRXE bit to 0 to
disable reception.
To continue reception, set the CBnSCE bit to 1 to wait for the next reception
by dummy-reading the CBnRX register.
Notes 1. If the CBnSCE bit is read while it is 1, the next communication operation is started.
2.
The CBnSCE bit is not cleared to 0 one communication clock before the completion of the last
data reception, the next communication operation is automatically started.
Caution Be sure to clear bits 3 and 2 to "0".
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(2) CSIBn control register 1 (CBnCTL1)
CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
0
CBnCKP
0
0
1
1
Specification of data transmission/
reception timing in relation to SCKBn
CBnCTL1
(n = 0 to 2)
0
CBnDAP
0
1
0
1
0
CBnCKP CBnDAP CBnCKS2 CBnCKS1 CBnCKS0
After reset 00H R/W Address: CB0CTL1 FFFFFD01H, CB1CTL1 FFFFFD11H,
CB2CTL1 FFFFFD21H
CBnCKS2
0
0
0
0
1
1
1
1
CBnCKS1
0
0
1
1
0
0
1
1
CBnCKS0
0
1
0
1
0
1
0
1
Communication clock
f
XX
/2
f
XX
/4
f
XX
/8
f
XX
/16
f
XX
/32
f
XX
/64
f
BRG
Note
External clock (SCKBn)
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
Mode
CBnCTL1
(n = 0 to 2)
D7
D6
D5
D4
D3
D2
D1
D0
SCKBn (I/O)
SIBn capture
SOBn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SCKBn (I/O)
SIBn capture
SOBn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SCKBn (I/O)
SIBn capture
SOBn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SCKBn (I/O)
SIBn capture
SOBn (output)
Communication
type 1
Communication
type 2
Communication
type 3
Communication
type 4
n = 0
n = 1
n = 2
TMP0 (TOP01)
f
XX
/128
Note For details, see 14.8 Baud Rate Generator.
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(3) CSIBn control register 2 (CBnCTL2)
CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when
both the CBnTXE and CBnRXE bits = 0.
After reset: 00H R/W Address: CB0CTL2 FFFFFD02H, CB1CTL2 FFFFFD12H,
CB2CTL2 FFFFFD22H
0
CBnCTL2
(n = 0 to 2)
0
0
0
CBnCL3
CBnCL2
CBnCL1
CBnCL0
8 bits
9 bits
10 bits
11 bits
12 bits
13 bits
14 bits
15 bits
16 bits
CBnCL3
0
0
0
0
0
0
0
0
1
CBnCL2
0
0
0
0
1
1
1
1
CBnCL1
0
0
1
1
0
0
1
1
CBnCL0
0
1
0
1
0
1
0
1
Serial register bit length
Remarks 1. If the number of transfer bits is other than 8 or 16, prepare and use data stuffed from the
LSB of the CBnTX and CBnRX registers.
2.
: don't care
CHAPTER 14 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB)
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(a) Transfer data length change function
The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the
CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits.
When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX
register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB. Any data can
be set for the higher bits that are not used, but the receive data becomes 0 following serial transfer.
(i) Transfer bit length = 10 bits, MSB first
15
10
9
0
SOBn
SIBn
Insertion of 0
(ii) Transfer bit length = 12 bits, LSB first
0
SOBn
11
12
15
SIBn
Insertion of 0
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(4) CSIBn status register (CBnSTR)
CBnSTR is an 8-bit register that displays the CSIBn status.
This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only.
Reset sets this register to 00H.
In addition to reset input, the CBnSTR register can be initialized by clearing (0) the CBnCTL0.CBnPWR bit.
CBnTSF
Communication stopped
Communicating
CBnTSF
0
1
Communication status flag
CBnSTR
(n = 0 to 2)
0
0
0
0
0
0
CBnOVE
After reset 00H R/W Address: CB0STR FFFFFD03H, CB1STR FFFFFD13H,
CB2STR FFFFFD23H
During transmission, this register is set when data is prepared in the CBnTX
register, and during reception, it is set when a dummy read of the CBnRX register
is performed.
When transfer ends, this flag is cleared to 0 at the last edge of the clock.
No overrun
Overrun
CBnOVE
0
1
Overrun error flag
An overrun error occurs when the next reception starts without reading the value of
the receive buffer by CPU, upon completion of the receive operation.
The CBnOVE flag displays the overrun error occurrence status in this case.
The CBnOVE bit is valid also in the single transfer mode. Therefore, when only
using transmission, note the following.
Do not check the CBnOVE flag.
Read this bit even if reading the reception data is not required.
The CBnOVE flag is cleared by writing 0 to it. It cannot be set even by writing 1 to it.
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14.4 Interrupt Request Signals
CSIBn can generate the following two types of interrupt request signals.
Reception complete interrupt request signal (INTCBnR)
Transmission enable interrupt request signal (INTCBnT)
Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by
default, and the priority of the transmission enable interrupt request signal is lower.
Table 14-2. Interrupts and Their Default Priority
Interrupt Priority
Reception complete
High
Transmission enable
Low
(1) Reception complete interrupt request signal (INTCBnR)
When receive data is transferred to the CBnRX register while reception is enabled, the reception complete
interrupt request signal is generated.
This interrupt request signal can also be generated if an overrun error occurs.
When the reception complete interrupt request signal is acknowledged and the data is read, read the CBnSTR
register to check that the result of reception is not an error.
In the single transfer mode, the INTCBnR interrupt request signal is generated upon completion of
transmission, even when only transmission is executed.
(2) Transmission enable interrupt request signal (INTCBnT)
In the continuous transmission or continuous transmission/reception mode, transmit data is transferred from
the CBnTX register and, as soon as writing to CBnTX has been enabled, the transmission enable interrupt
request signal is generated.
In the single transmission and single transmission/reception modes, the INTCBnT interrupt is not generated.
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14.5 Operation
14.5.1 Single transfer mode (master mode, transmission/reception mode)
This section shows a case of MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (see 14.3 (2) CSIBn
control register 1 (CBnCTL1), and transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0, 0,
0, 0).
CBnTX write (55H)
CBnRX read (AAH)
(AAH)
(55H)
1
0
1
1
0
1
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
55H (transmit data)
SCKBn pin
CBnTX register
AAH
00H
CBnRX register
Shift
register
INTCBnR signal
Note
SIBn pin
SOBn pin
0
0
0
1
0
0
1
0
1
1
CBnTSF bit
CBnSCE bit
(1)
(5)
(6)
(8)
(7)
(2)
(3)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Write transfer data to the CBnTX register (transmission start).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Read the CBnRX register before clearing the CBnPWR bit to 0.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop operation of CSIBn (end
of transmission/reception).
Note In single transmission or single transmission/reception mode, the INTCBnT signal is not generated.
When communication is complete, the INTCBnR signal is generated.
Remarks 1. The processing of steps (3) and (4) can be set simultaneously.
2. n = 0 to 2
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14.5.2 Single transfer mode (master mode, reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 1 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0,
0, 0, 0).
(AAH)
1
0
1
1
0
0
1
01H
02H
05H
0AH
15H
2AH
55H
AAH
00H
SCKBn pin
CBnRX register
CBnRX read (dummy read)
Shift
register
CBnSCE bit
CBnTSF bit
INTCBnR signal
SIBn pin
SOBn pin
0
L
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(9)
(8)
CBnRX read (AAH)
AAH
00H
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same time as specifying the
transfer mode using the CBnDIR bit, to set the reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) Set the CBnSCE bit to 0 to set the final receive data status.
(8) Read the CBnRX register.
(9) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the CSIBn operation
(end of reception).
Remarks 1. The processing of steps (3) and (4) can be set simultaneously.
2. n = 0 to 2
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14.5.3 Continuous mode (master mode, transmission/reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 3 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
(8)
(7)
(7)
(6)
(5)
(1)
(2)
(3)
(4)
96H
00H
CCH
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
55H
CBnTX register
SCKBn pin
SOBn pin
SIBn pin
INTCBnT signal
INTCBnR signal
CBnTSF bit
CBnSCE bit
Shift register
SO latch
CBnRX register
0
0
0
0
AAH
96H
CCH
1
1
1
0
0
0
1
0
1
0
0
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE, and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Write transfer data to the CBnTX register (transmission start).
(6) The transmission enable interrupt request signal (INTCBnT) is received and transfer data is written to
the CBnTX register.
(7) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to 0.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of transmission/reception).
To continue transfer, repeat steps (5) to (7) before (8).
In transmission mode or transmission/reception mode, the communication is not started by reading the
CBnRX register.
Remark n = 0 to 2
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14.5.4 Continuous mode (master mode, reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
(8)
(6)
(6)
(7)
(5)
(1)
(2)
(3)
(4)
1
0
0
0
0
0
0
0
1
1
1
1
1
55H
SCKBn pin
CBnSCE bit
SIBn pin
INTCnR signal
CBnTSF bit
Shift register
CBnRX register
1
1
0
55H
AAH
AAH
00H
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR
bit, to set the reception enabled status.
(4) Set the CBnPWR bit to 1 to enable the CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register before the next receive data arrives or before the CBnPWR bit is cleared to
0.
(7) Set the CBnCTL0.CBnSCE bit = 0 while the last data being received to set the final receive data status.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of reception).
To continue transfer, repeat steps (5) and (6) before (7).
Remark n = 0 to 2
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14.5.5 Continuous reception mode (error)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
(8) (9) (10)
(7)
(6)
(5)
AAH
00H
1
0
0
0
0
0
0
1
1
1
1
1
SCKBn pin
SIBn pin
INTCBnR signal
CBnTSF bit
Shift register
CBnRX register
CBnOVE bit
55H
55H
0
1
0
AAH
1
(1)
(2)
(3)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE bit to 1 at the same time as specifying the transfer mode using the CBnDIR
bit, to set the reception enabled status.
(4) Set the CBnPWR bit = 1 to enable CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
(7) If the data could not be read before the end of the next transfer, the CBnSTR.CBnOVE flag is set to 1
upon the end of reception and the INTCBnR signal is output.
(8) Overrun error processing is performed after checking that the CBnOVE bit = 1 in the INTCBnR interrupt
servicing.
(9) Clear CBnOVE bit to 0.
(10) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation CSIBn
(end of reception).
Remark n = 0 to 2
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14.5.6 Continuous mode (slave mode, transmission/reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 2 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CSnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
(8)
(7)
(7)
(6)
(5)
96H
00H
CCH
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
55H
CBnTX register
SCKBn pin
SOBn pin
SIBn pin
INTCBnT signal
INTCBnR signal
Shift register
SO latch
CBnRX register
0
0
0
0
0
0
AAH
96H
CCH
1
0
0
0
1
1
CBnTSF bit
CBnSCE bit
(1)
(2)
(3)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnTXE, CBnRXE and CBnSCE bits of the CBnCTL0 register to 1 at the same time as
specifying the transfer mode using the CBnDIR bit, to set the transmission/reception enabled status.
(4) Set the CBnPWR bit to 1 to enable supply of the CSIBn operation.
(5) Write the transfer data to the CBnTX register.
(6) The transmission enable interrupt request signal (INTCBnT) is received and the transfer data is written
to the CBnTX register.
(7) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register.
(8) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of transmission/reception).
To continue transfer, repeat steps (5) to (7) before (8).
Remark n = 0 to 2
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14.5.7 Continuous mode (slave mode, reception mode)
This section shows the case using MSB first (CBnCTL0.CBnDIR bit = 0) and communication type 1 (see 14.3 (2)
CSIBn control register 1 (CBnCTL1)), transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits =
0, 0, 0, 0).
(7)
(6)
(6)
(5)
1
0
0
0
0
0
0
0
1
1
1
1
1
55H
SCKBn pin
SIBn pin
INTCBnR signal
CBnTSF bit
CBnSCE bit
Shift register
CBnRX register
1
1
55H
AAH
00H
AAH
0
(1)
(2)
(3)
(4)
(1) Clear the CBnCTL0.CBnPWR bit to 0.
(2) Set the CBnCTL1 and CBnCTL2 registers to specify the transfer mode.
(3) Set the CBnCTL0.CBnRXE and CBnCTL0.CBnSCE bits to 1 at the same time as specifying the
transfer mode using the CBnDIR bit, to set the reception enabled status.
(4) Set the CBnPWR bit = 1 to enable CSIBn operation.
(5) Perform a dummy read of the CBnRX register (reception start trigger).
(6) The reception complete interrupt request signal (INTCBnR) is output.
Read the CBnRX register. When reading the last data, clear the CBnCTL0.CBnSCE bit to 0 before
reading the CBnRX register.
(7) Check that the CBnSTR.CBnTSF bit = 0 and set the CBnPWR bit to 0 to stop the operation of CSIBn
(end of reception).
To continue transfer, repeat steps (5) and (6) before (7).
Remark n = 0 to 2
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14.5.8 Clock timing
(1/2)
(1) Communication type 1 (CBnCKP = 0, CBnDAP = 0)
D6
D5
D4
D3
D2
D1
SCKBn pin
SIBn
capture
Reg-R/W
SOBn pin
INTCBnT
interrupt
Note 1
INTCBnR
interrupt
Note 2
CBnTSF bit
D0
D7
(2) Communication type 2 (CBnCKP = 0, CBnDAP = 1)
D6
D5
D4
D3
D2
D1
D0
D7
SCKBn pin
SIBn
capture
Reg-R/W
SOBn pin
INTCBnT
interrupt
Note 1
INTCBnR
interrupt
Note 2
CBnTSF bit
Notes 1. The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data
shift register in the continuous transmission or continuous transmission/reception mode. In the
single transmission or single transmission/reception mode, the INTCBnT interrupt request signal is
not generated, but the INTCBnR interrupt request signal is generated upon completion of
communication.
2. The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready in the
CBnRX register while reception is enabled, and if an overrun error occurs. In the single mode, the
INTCBnR interrupt request signal is generated even in the transmission mode, upon completion of
communication.
Caution In communication type 2, the CBnTSF bit is cleared half a SCKBn clock after generation of an
INTCBnR interrupt request signal.
Remark n = 0 to 2
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(2/2)
(3) Communication type 3 (CBnCKP = 1, CBnDAP = 0)
D6
D5
D4
D3
D2
D1
D0
D7
SCKBn pin
SIBn
capture
Reg-R/W
SOBn pin
INTCBnT
interrupt
Note 1
INTCBnR
interrupt
Note 2
CBnTSF bit
(4) Communication type 4 (CBnCKP = 1, CBnDAP = 1)
D6
D5
D4
D3
D2
D1
D0
D7
SCKBn pin
SIBn
capture
Reg-R/W
SOBn pin
INTCBnT
interrupt
Note 1
INTCBnR
interrupt
Note 2
CBnTSF bit
Notes 1. The INTCBnT interrupt is set when the data written to the transmit buffer is transferred to the data
shift register in the continuous transmission or continuous transmission/reception modes. In the
single transmission or single transmission/reception modes, the INTCBnT interrupt request signal is
not generated, but the INTCBnR interrupt request signal is generated upon completion of
communication.
2. The INTCBnR interrupt occurs if reception is correctly completed and receive data is ready in the
CBnRX register while reception is enabled, and if an overrun error occurs. In the single mode, the
INTCBnR interrupt request signal is generated even in the transmission mode, upon completion of
communication.
Caution In communication type 4, the CBnTSF bit is cleared half a SCKBn clock after generation of an
INTCBnR interrupt request signal.
Remark n = 0 to 2
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14.6 Output Pin Status with Operation Disabled
(1) SCKBn pin
When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows.
CBnCKS2 CBnCKS1 CBnCKS0 CBnCKP
SCKBn
Pin
Output
1 1 1
High impedance
0
Fixed to high level
Other than above
1
Fixed to low level
Remarks 1. The output level of the SCKBn pin changes if any of the CBnCTL1.CBnCKP and
CBnCKS2 to CBnCKS0 bits is rewritten.
2. n = 0 to 2
3.
: don't care
(2) SOBn pin
When CSIBn operation is disabled (CBnPWR bit = 0), the SOBn pin output status is as follows.
CBnTXE
CBnDAP
CBnDIR
SOBn Pin Output
0
Fixed to low level
0
SOBn latch value (low level)
0
CBnTX register value (MSB)
1
1
1
CBnTX register value (LSB)
Remarks 1. The SOBn pin output changes when any one of the
CBnCTL0.CBnTXE, CBnCTL0.CBnDIR bits, and
CBnCTL1.CBnDAP bit is rewritten.
2. n = 0 to 2
3.
: don't care
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14.7 Operation Flow
(1) Single transmission
START
No
Yes
INTCBnR signal is
generated?
Transfer data exists?
END
Yes
No
Initial setting (CBnCTL0
Note
,
CBnCTL1 registers, etc.)
Write CBnTX register
(start transfer).
CBnPWR bit = 0
(CBnCTL0)
Note Set the CBnSCE bit to 1 in the initial setting.
Caution In the slave mode, data cannot be correctly transmitted if the next transfer clock is input
earlier than the CBnTX register is written.
Remark n = 0 to 2
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(2) Single reception
START
No
INTCBnR signal is
generated?
Last data?
END
Yes
Yes
No
Initial setting (CBnCTL0
Note
,
CBnCTL1 registers, etc.)
CBnRX register dummy read
(start reception)
CBnSCE bit = 0
(CBnCTL0)
CBnPWR bit = 0
(CBnCTL0)
CBnRX register read
CBnRX register read
Note Set the CBnSCE bit to 1 in the initial setting.
Caution In the single mode, data cannot be correctly received if the next transfer clock is input
earlier than the CBnRX register is read.
Remark n = 0 to 2
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(3) Single transmission/reception
START
Initial setting (CBnCTL0
Note 1
,
CBnCTL1 registers, etc.)
Write CBnTX register
(start transfer).
END
CBnPWR bit = 0,
CBnTXE bit = CBnRXE bit = 0
(CBnCTL0)
No
Transmission/reception
Transmission
Reception
INTCBnR signal is
generated?
Yes
Transfer end?
Write CBnTX register
Note 2
.
Read CBnRX register.
Read CBnRX register.
No
Yes
Transfer end?
Write CBnTX register
Note 2
.
No
Yes
Transfer end?
Write CBnTX register
Note 2
.
No
Yes
B
B
A
A
Notes 1. Set the CBnSCE bit to 1 in the initial setting.
2. If the next transfer is reception only, dummy data is written to the CBnTX register.
Caution Even in the single mode, the CBnSTR.CBnOVE flag is set to 1. If only transmission is
used in the transmission/reception mode, therefore, checking the CBnOVE flag is not
required.
Remark n = 0 to 2
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(4) Continuous transmission
START
No
Yes
INTCBnT signal is
generated?
Data to be
transferred next exists?
END
Yes
No
Initial setting (CBnCTL0
Note
,
CBnCTL1 registers, etc.)
Write CBnTX register
(start transfer).
CBnPWR bit = 0
(CBnCTL0)
No
CBnTSF bit = 1?
(CBnSTR)
Yes
Note Set the CBnSCE bit to 1 in the initial setting.
Remark n = 0 to 2
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(5) Continuous reception
START
END
No
No
Yes
INTCBnR signal is
generated?
CBnOVE bit = 1?
(CBnSTR)
No
Yes
Initial setting (CBnCTL0
Note
,
CBnCTL1 registers, etc.)
CBnRX register dummy read
(start reception)
CBnRX register read
CBnRX register read
CBnRX register read
CBnRX register read
Yes
Is data being
received last data?
CBnSCE bit = 0
(CBnCTL0)
CBnSCE bit = 1
(CBnCTL0)
No
INTCBnR signal is
generated?
Yes
CBnOVE bit clear
(CBnSTR)
Note Set the CBnSCE bit to 1 in the initial setting
Caution In the master mode, the clock is output without limit when dummy data is read from the
CBnRX register. To stop the clock, execute the flow marked
in the above flowchart.
In the slave mode, malfunction due to noise during communication can be prevented by
executing the flow marked
in the above flowchart.
Before resuming communication, set the CBnCTL0.CBnSCE bit to 1, and read dummy
data from the CBnRX register.
Remark n = 0 to 2
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(6) Continuous transmission/reception
START
END
No
No
INTCBnR signal is
generated?
Yes
No
INTCBnT signal is
generated?
Yes
Initial setting (CBnCTL0
Note
,
CBnCTL1 registers, etc.)
Write CBnTX register.
CBnRX register read
Yes
Yes
Is data completely
received last data?
No
Write CBnTX register.
Yes
Is data being
transferred last data?
No
CBnOVE bit = 0?
(CBnSTR)
CBnOVE bit clear
(CBnSTR)
Note Set the CBnSCE bit to 1 in the initial setting.
Remark n = 0 to 2
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14.8 Baud Rate Generator
The clock generated by the baud rate generator (prescaler 3) is supplied to the watch timer and CSIB0.
(1) Prescaler mode register 0 (PRSM0)
The PRSM0 register controls generation of the baud rate signal for CSIB.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
PRSM0
0
0
BGCE0
0
0
BGCS01 BGCS00
Disabled
Enabled
BGCE0
0
1
Baud rate output
f
X
f
X
/2
f
X
/4
f
X
/8
4 MHz
250 ns
500 ns
1 s
2 s
BGCS01
0
0
1
1
BGCS00
0
1
0
1
Count clock selection (f
BGCS
)
After reset: 00H R/W Address: FFFFF8B0H
5 MHz
200 ns
400 ns
800 ns
1.6 s
Cautions 1. Do not rewrite the PRSM0 register while watch timer and CSIB0 are operating.
2. Set the PRSM0 register before setting the BGCE0 bit to 1.
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(2) Prescaler compare register 0 (PRSCM0)
The PRSCM0 register is an 8-bit compare registers.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
PRSCM07
PRSCM0
PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00
After reset: 00H R/W Address: FFFFF8B1H
Cautions 1. Do not rewrite the PRSCM0 register while watch timer and CSIB are operating.
2. Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1.
14.8.1 Baud rate generation
The transmission/reception clock is generated by dividing the main clock. The baud rate generated from the main
clock is obtained by the following equation.
f
BRG
=
Remark f
BRG
:
BRG count clock
f
XX
:
Main clock oscillation frequency
k:
PRSM0 register setting value = 0 to 3
N:
PRSCM0 register setting value = 1 to 256
However, N = 256 only when PRSCM0 register is set to 00H.
f
XX
2
k+1
N
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14.9 Cautions
(1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed
even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading
the CBnSTR.CBnOVE bit after DMA transfer has been completed.
(2) In regards to registers that are forbidden from being rewritten during operations (CBnCTL0.CBnPWR bit is 1),
if rewriting has been carried out by mistake during operations, set the CBnCTL0.CBnPWR bit to 0 once, then
initialize CSIBn.
Registers to which rewriting during operation are prohibited are shown below.
CBnCTL0 register: CBnTXE, CBnRXE, CBnDIR, CBnTMS bits
CBnCTL1 register: CBnCKP, CBnDAP, CBnCKS2 to CBnCKS0 bits
CBnCTL2 register: CBnCL3 to CBnCL0 bits
(3) In communication type 2 and 4 (CBnCTL1.CBnDAP bit = 1), the CBnSTR.CBnTSF bit is cleared half a SCKBn
clock after occurrence of a reception complete interrupt (INTCBnR).
In the single transfer mode, writing the next transmit data is ignored during communication (CBnTSF bit = 1),
and the next communication is not started. Also if reception-only communication (CBnCTL0.CBnTXE bit = 0,
CBnCTL0.CBnRXE bit = 1) is set, the next communication is not started even if the receive data is read during
communication (CBnTSF bit = 1).
Therefore, when using the single transfer mode with communication type 2 or 4 (CBnDAP bit = 1), pay
particular attention to the following.
To start the next transmission, confirm that CBnTSF bit = 0 and then write the transmit data to the CBnTX
register.
To perform the next reception continuously when reception-only communication (CBnTXE bit = 0, CBnRXE
bit = 1) is set, confirm that CBnTSF bit = 0 and then read the CBnRX register.
Or, use the continuous transfer mode instead of the single transfer mode. Use of the continuous transfer mode
is recommended especially for using DMA.
Remark n = 0 to 2
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CHAPTER 15 DMA FUNCTION (DMA CONTROLLER)
The V850ES/HJ2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA
transfer.
The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA
requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from
external input pins, or software triggers (memory refers to internal RAM or external memory).
15.1 Features
4 independent DMA channels
Transfer unit: 8/16 bits
Maximum transfer count: 65,536 (2
16
)
Transfer type: Two-cycle transfer
Transfer mode: Single transfer mode
Transfer requests
Request by interrupts from on-chip peripheral I/O (serial interface, timer/counter, A/D converter) or interrupts
from external input pin
Requests by software trigger
Transfer targets
Internal RAM Peripheral I/O
Peripheral I/O Peripheral I/O
Internal RAM External memory
External memory Peripheral I/O
External memory External memory
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15.2 Configuration
CPU
Internal RAM
On-chip
peripheral I/O
On-chip peripheral I/O bus
Internal bus
Data
control
Address
control
Count
control
Channel
control
DMAC
V850ES/HJ2
Bus interface
External bus
External
RAM
External
ROM
External I/O
DMA source address
register n (DSAnH/DSAnL)
DMA transfer count
register n (DBCn)
DMA channel control
register n (DCHCn)
DMA destination address
register n (DDAnH/DDAnL)
DMA addressing control
register n (DADCn)
DMA trigger factor
register n (DTFRn)
Remark n = 0 to 3
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15.3 Registers
(1) DMA source address registers 0 to 3 (DSA0 to DSA3)
The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3).
These registers are divided into two 16-bit registers, DSAnH and DSAnL.
These registers can be read or written in 16-bit units.
External memory or on-chip peripheral I/O
Internal RAM
IR
0
1
Specification of DMA transfer source
Set the address (A25 to A16) of the DMA transfer source
(default value is undefined).
During DMA transfer, the next DMA transfer source address is held.
When DMA transfer is completed, the DMA address set first is held.
SA25 to SA16
Set the address (A15 to A0) of the DMA transfer source
(default value is undefined).
During DMA transfer, the next DMA transfer source address is held.
When DMA transfer is completed, the DMA address set first is held.
SA15 to SA0
After reset: Undefined R/W Address: DSA0H FFFFF082H, DSA1H FFFFF08AH,
DSA2H FFFFF092H, DSA3H FFFFF09AH,
DSA0L FFFFF080H, DSA1L FFFFF088H,
DSA2L FFFFF090H, DSA3L FFFFF098H
DSAnL
(n = 0 to 3)
SA15 SA14 SA13 SA12
SA6 SA5 SA4 SA3 SA2 SA1 SA0
SA7
SA8
SA9
SA10
SA11
DSAnH
(n = 0 to 3)
IR
0
0
0
SA22 SA21 SA20 SA19 SA18 SA17 SA16
SA23
SA24
SA25
0
0
Cautions 1. Be sure to clear bits 14 to 10 of the DSAnH register to 0.
2. Set the DSAnH and DSAnL registers at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
Period from after reset to start of first DMA transfer
Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
3. When the value of the DSAn register is read, two 16-bit registers, DSAnH and DSAnL, are
read. If reading and updating conflict, the value being updated may be read (see 15.13
Cautions).
4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
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(2) DMA destination address registers 0 to 3 (DDA0 to DDA3)
The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3).
These registers are divided into two 16-bit registers, DDAnH and DDAnL.
These registers can be read or written in 16-bit units.
External memory or on-chip peripheral I/O
Internal RAM
IR
0
1
Specification of DMA transfer destination
Set an address (A25 to A16) of DMA transfer destination
(default value is undefined).
During DMA transfer, the next DMA transfer destination address is held.
When DMA transfer is completed, the DMA transfer source address set
first is held.
DA25 to DA16
Set an address (A15 to A0) of DMA transfer destination
(default value is undefined).
During DMA transfer, the next DMA transfer destination address is held.
When DMA transfer is completed, the DMA transfer source address set
first is held.
DA15 to DA0
After reset: Undefined R/W Address: DDA0H FFFFF086H, DDA1H FFFFF08EH,
DDA2H FFFFF096H, DDA3H FFFFF09EH,
DDA0L FFFFF084H, DDA1L FFFFF08CH,
DDA2L FFFFF094H, DDA3L FFFFF09CH
DDAnL
(n = 0 to 3)
DA15 DA14 DA13 DA12
DA6 DA5 DA4 DA3 DA2 DA1 DA0
DA7
DA8
DA9
DA10
DA11
DDAnH
(n = 0 to 3)
IR
0
0
0
DA22 DA21 DA20 DA19 DA18 DA17 DA16
DA23
DA24
DA25
0
0
Cautions 1. Be sure to clear bits 14 to 10 of the DDAnH register to 0.
2. Set the DDAnH and DDAnL registers at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
Period from after reset to start of first DMA transfer
Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
3. When the value of the DDAn register is read, two 16-bit registers, DDAnH and DDAnL, are
read. If reading and updating conflict, a value being updated may be read (see 15.13
Cautions).
4. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
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(3) DMA byte count registers 0 to 3 (DBC0 to DBC3)
The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3).
These registers hold the remaining transfer count during DMA transfer.
These registers are decremented by 1 per one transfer regardless of the transfer data unit (8/16 bits), and the
transfer is terminated if a borrow occurs.
These registers can be read or written in 16-bit units.
Byte transfer count 1 or remaining byte transfer count
Byte transfer count 2 or remaining byte transfer count
:
Byte transfer count 65,536 (2
16
) or remaining byte transfer count
BC15 to
BC0
0000H
0001H
:
FFFFH
Byte transfer count setting or remaining
byte transfer count during DMA transfer
After reset: Undefined R/W Address: DBC0 FFFFF0C0H, DBC1 FFFFF0C2H,
DBC2 FFFFF0C4H, DBC3 FFFFF0C6H
DBCn
(n = 0 to 3)
15
BC15
14
BC14
13
BC13
12
BC12
11
BC11
10
BC10
9
BC9
8
BC8
7
BC7
6
BC6
5
BC5
4
BC4
3
BC3
2
BC2
1
BC1
0
BC0
The number of transfer data set first is held when DMA transfer is complete.
Cautions 1. Set the DBCn register at the following timing when DMA transfer is disabled (DCHCn.Enn
bit = 0).
Period from after reset to start of first DMA transfer
Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
2. Following reset, set the DSAnH, DSAnL, DDAnH, DDAnL, and DBCn registers before
starting DMA transfer. If these registers are not set, the operation when DMA transfer is
started is not guaranteed.
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(4) DMA addressing control registers 0 to 3 (DADC0 to DADC3)
The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n
= 0 to 3).
These registers can be read or written in 16-bit units.
Reset sets these registers to 0000H.
DADCn
(n = 0 to 3)
8 bits
16 bits
DS0
0
1
Setting of transfer data size
Increment
Decrement
Fixed
Setting prohibited
SAD1
0
0
1
1
SAD0
0
1
0
1
Setting of count direction of the transfer source address
Increment
Decrement
Fixed
Setting prohibited
DAD1
0
0
1
1
DAD0
0
1
0
1
Setting of count direction of the destination address
After reset: 0000H R/W Address: DADC0 FFFFF0D0H, DADC1 FFFFF0D2H,
DADC2 FFFFF0D4H, DADC3 FFFFF0D6H
SAD1
SAD0
DAD1
DAD0
0
0
0
0
0
DS0
0
0
0
0
0
0
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
Cautions 1. Be sure to clear bits 15, 13 to 8, and 3 to 0 of the DADCn register to "0".
2. Set the DADCn register at the following timing when DMA transfer is disabled (DCHCn.Enn
bit = 0).
Period from after reset to start of first DMA transfer
Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
3. The DS0 bit specifies the size of the transfer data, and does not control bus sizing. If 8-bit
data (DS0 bit = 0) is set, therefore, the lower data bus is not always used.
4. If the transfer data size is set to 16 bits (DS0 bit = 1), transfer cannot be started from an
odd address. Transfer is always started from an address with the first bit of the lower
address aligned to 0.
5. If DMA transfer is executed on an on-chip peripheral I/O register (as the transfer source or
destination), be sure to specify the same transfer size as the register size. For example, to
execute DMA transfer on an 8-bit register, be sure to specify 8-bit transfer.
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(5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA
channel n.
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are
write-only. If bit 1 or 2 is read, the read value is always 0.)
Reset sets these registers to 00H.
DCHCn
(n = 0 to 3)
DMA transfer had not completed.
DMA transfer had completed.
It is set to 1 on the last DMA transfer and cleared to 0 when it is read.
TCn
Note 1
0
1
Status flag indicates whether DMA transfer
through DMA channel n has completed or not
DMA transfer disabled
DMA transfer enabled
DMA transfer is enabled when the Enn bit is set to 1.
When DMA transfer is completed (when a terminal count is generated), this bit is
automatically cleared to 0.
To abort DMA transfer, clear the Enn bit to 0 by software. To resume, set the Enn
bit to 1 again.
When aborting or resuming DMA transfer, however, be sure to observe the
procedure described in 15.13 Cautions.
Enn
0
1
Setting of whether DMA transfer through
DMA channel n is to be enabled or disabled
This is a software startup trigger of DMA transfer.
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn
bit = 1), DMA transfer is started.
STGn
Note 2
After reset: 00H R/W Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H,
DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H
TCn
Note 1
0
0
0
0
INITn
Note 2
STGn
Note 2
Enn
0
1
2
3
4
5
6
7
INITn
Note 2
If the INITn bit is set to 1 with DMA transfer disabled (Enn bit = 0), the
DMA transfer status can be initialized.
When re-setting the DMA transfer status (re-setting the DDAnH, DDAnL,
DSAnH, DSAnL, DBCn, and DADCn registers) before DMA transfer is
completed (before the TCn bit is set to 1), be sure to initialize the DMA
channel.
When initializing the DMA controller, however, be sure to observe the
procedure described in 15.13 Cautions.
Notes 1. The TCn bit is read-only.
2. The INITn and STGn bits are write-only.
Cautions 1. Be sure to clear bits 6 to 3 of the DCHCn register to "0".
2. When DMA transfer is completed (when a terminal count is generated), the Enn bit is
cleared to 0 and then the TCn bit is set to 1. If the DCHCn register is read while its bits are
being updated, a value indicating "transfer not completed and transfer is disabled" (TCn bit
= 0 and Enn bit = 0) may be read.
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(6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt
request signals from on-chip peripheral I/O.
The interrupt request signals set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units.
Reset sets these registers to 00H.
DTFRn
(n = 0 to 3)
No DMA transfer request
DMA transfer request
DFn
Note
0
1
DMA transfer request flag
After reset: 00H R/W Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H,
DTFR2 FFFFF814H, DTFR3 FFFFF816H
DFn
0
IFCn5
IFCn4
IFCn3
IFCn2
IFCn1
IFCn0
0
1
2
3
4
5
6
7
Note The DFn bit is a write-only bit. Write 0 to this bit to clear a DMA transfer request if an interrupt that is
specified as the cause of starting DMA transfer occurs while DMA transfer is disabled.
Cautions 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
Period from after reset to start of first DMA transfer
Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
2. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-
IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1).
3. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an
interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA
transfer is enabled or disabled. If DMA is enabled in this status, DMA transfer is
immediately started.
Remark For the IFCn5 to IFCn0 bits, see Table 15-1 DMA Start Factors.
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Table 15-1. DMA Start Factors (1/2)
IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0
Interrupt
Source
0
0
0
0
0
0
DMA request by interrupt disabled
0 0 0 0 0 1
INTLVI
0 0 0 0 1 0
INTP0
0 0 0 0 1 1
INTP1
0 0 0 1 0 0
INTP2
0 0 0 1 0 1
INTP3
0 0 0 1 1 0
INTP4
0 0 0 1 1 1
INTP5
0 0 1 0 0 0
INTP6
0 0 1 0 0 1
INTP7
0 0 1 0 1 0
INTTQ0OV
0 0 1 0 1 1
INTTQ0CC0
0 0 1 1 0 0
INTTQ0CC1
0 0 1 1 0 1
INTTQ0CC2
0 0 1 1 1 0
INTTQ0CC3
0 0 1 1 1 1
INTTP0OV
0 1 0 0 0 0
INTTP0CC0
0 1 0 0 0 1
INTTP0CC1
0 1 0 0 1 0
INTTP1OV
0 1 0 0 1 1
INTTP1CC0
0 1 0 1 0 0
INTTP1CC1
0 1 0 1 0 1
INTTP2OV
0 1 0 1 1 0
INTTP2CC0
0 1 0 1 1 1
INTTP2CC1
0 1 1 0 0 0
INTTP3OV
0 1 1 0 0 1
INTTP3CC0
0 1 1 0 1 0
INTTP3CC1
0 1 1 0 1 1
INTTM0EQ0
0 1 1 1 0 0
INTCB0R
0 1 1 1 0 1
INTCB0T
0 1 1 1 1 0
INTCB1R
0 1 1 1 1 1
INTCB1T
1 0 0 0 0 0
INTUA0R
1 0 0 0 0 1
INTUA0T
1 0 0 0 1 0
INTUA1R
1 0 0 0 1 1
INTUA1T
1 0 0 1 0 0
INTAD
1 0 1 0 0 1
INTKR
1 0 1 0 1 0
INTTQ1OV
Remark n = 0 to 3
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Table 15-1. DMA Start Factors (2/2)
IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0
Interrupt
Source
1 0 1 0 1 1
INTTQ1CC0
1 0 1 1 0 0
INTTQ1CC1
1 0 1 1 0 1
INTTQ1CC2
1 0 1 1 1 0
INTTQ1CC3
1 0 1 1 1 1
INTUA2R
1 1 0 0 0 0
INTUA2T
1 1 0 1 0 1
INTTQ2OV
1 1 0 1 1 0
INTTQ2CC0
1 1 0 1 1 1
INTTQ2CC1
1 1 1 0 0 0
INTTQ2CC2
1 1 1 0 0 1
INTTQ2CC3
1 1 1 0 1 0
INTCB2R
1 1 1 0 1 1
INTCB2T
Remark n = 0 to 3
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15.4 Transfer Targets
Table 15-2 shows the relationship between the transfer targets (
: Transfer enabled, : Transfer disabled).
Table 15-2. Relationship Between Transfer Targets
Transfer Destination
Internal ROM
On-Chip
Peripheral I/O
Internal RAM
External Memory
On-chip
peripheral I/O
Internal RAM
External memory
Source
Internal ROM
Caution The operation is not guaranteed for combinations of transfer destination and source marked with
"
" in Table 15-2.
15.5 Transfer Modes
Single transfer is supported as the transfer mode.
In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer
request, transfer is performed again once. This operation continues until a terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority
DMA request always takes precedence.
If a new transfer request of the same channel and a transfer request of another channel with a lower priority are
generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released
to the CPU (the new transfer request of the same channel is ignored in the transfer cycle).
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15.6 Transfer Types
As a transfer type, the 2-cycle transfer is supported.
In two-cycle transfer, data transfer is performed in two cycles, a read cycle and a write cycle.
In the read cycle, the transfer source address is output and reading is performed from the source to the DMAC. In
the write cycle, the transfer destination address is output and writing is performed from the DMAC to the destination.
An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs
between the transfer source and destination for DMA transfer of two cycles, the operation is performed as follows.
<16-bit data transfer>
<1> Transfer from 32-bit bus
16-bit bus
A read cycle (the higher 16 bits are in a high-impedance state) is generated, followed by generation of a
write cycle (16 bits).
<2> Transfer from 16-/32-bit bus to 8-bit bus
A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice.
<3> Transfer from 8-bit bus to 16-/32-bit bus
An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once.
<4> Transfer between 16-bit bus and 32-bit bus
A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once.
For DMA transfer executed to an on-chip peripheral I/O register (transfer source/destination), be sure to specify the
same transfer size as the register size. For example, for DMA transfer to an 8-bit register, be sure to specify byte (8-
bit) transfer.
Remark The bus width of each transfer target (transfer source/destination) is as follows.
On-chip peripheral I/O: 16-bit bus width
Internal RAM:
32-bit bus width
External memory:
8-bit or 16-bit bus width
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15.7 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
The priorities are checked for every transfer cycle.
15.8 Time Related to DMA Transfer
The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are
shown below.
Single transfer: DMA response time (<1>) + Transfer source memory access (<2>) + 1
Note 1
+ Transfer
destination memory access (<2>)
DMA Cycle
Minimum Number of Execution Clocks
<1> DMA request response time
4 clocks (MIN.) + Noise elimination time
Note 2
External memory access
Depends on connected memory.
Internal RAM access
2 clocks
Note 3
<2> Memory access
Peripheral I/O register access
3 clocks + Number of wait cycles specified by VSWC register
Note 4
Notes 1. One clock is always inserted between a read cycle and a write cycle in DMA transfer.
2. If an external interrupt (INTPn) is specified as the trigger to start DMA transfer, noise elimination time is
added (n = 0 to 14).
3. Two clocks are required for a DMA cycle.
4. More wait cycles are necessary for accessing a specific peripheral I/O register (for details, see 3.4.8 (2)).
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15.9 DMA Transfer Start Factors
There are two types of DMA transfer start factors, as shown below.
(1) Request by software
If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer
is started.
To request the next DMA transfer cycle immediately after that, confirm, by using the DBCn register, that the
preceding DMA transfer cycle has been completed, and set the STGn bit to 1 again (n = 0 to 3).
TCn bit = 0, Enn bit = 1
STGn bit = 1 ... Starts the first DMA transfer.
Confirm that the contents of the DBCn register have been updated.
STGn bit = 1 ... Starts the second DMA transfer.
:
Generation of terminal count ... Enn bit = 0, TCn bit = 1, and INTDMAn signal is generated.
(2) Request by on-chip peripheral I/O
If an interrupt request is generated from the on-chip peripheral I/O set by the DTFRn register when the
DCHCn.TCn bit = 0 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
Cautions 1. Two start factors (software trigger and hardware trigger) cannot be used for one DMA
channel. If two start factors are simultaneously generated for one DMA channel, only one
of them is valid. The start factor that is valid cannot be identified.
2. A new transfer request that is generated after the preceding DMA transfer request was
generated or in the preceding DMA transfer cycle is ignored (cleared).
3. The transfer request interval of the same DMA channel varies depending on the setting of
bus wait in the DMA transfer cycle, the start status of the other channels, or the external
bus hold request. In particular, as described in Caution 2, a new transfer request that is
generated for the same channel before the DMA transfer cycle or during the DMA transfer
cycle is ignored. Therefore, the transfer request intervals for the same DMA channel must
be sufficiently separated by the system. When the software trigger is used, completion of
the DMA transfer cycle that was generated before can be checked by updating the DBCn
register.
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15.10 DMA Abort Factors
DMA transfer is aborted if a bus hold occurs.
The same applies if transfer is executed between the internal memory/on-chip peripheral I/O and internal
memory/on-chip peripheral I/O.
When the bus hold is cleared, DMA transfer is resumed.
15.11 End of DMA Transfer
When DMA transfer has been completed the number of times set to the DBCn register and when the DCHCn.Enn
bit is cleared to 0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the
interrupt controller (INTC) (n = 0 to 3).
The V850ES/HJ2 does not output a terminal count signal to an external device. Therefore, confirm completion of
DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
15.12 Operation Timing
Figures 15-1 to 15-4 show DMA operation timing.
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Figure 15-1. Priority of DMA (1)
Preparation
for transfer
Read
Write
Idle
End
processing
DMA2
processing
CPU processing
DMA1 processing
CPU processing
CPU processing
DMA0 processing
DMA0 transfer request
System clock
DMA1 transfer request
DMA2 transfer request
DMA transfer
Mode of processing
DF0 bit
DF1 bit
DF2 bit
Preparation
for transfer
Read
Write
Idle
End
processing
Preparation
for transfer
Read
Remarks 1. Transfer in the order of DMA0
DMA1 DMA2
2. In the case of transfer between external memory spaces (multiplexed bus, no wait)
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Figure 15-2. Priority of DMA (2)
Preparation
for transfer
Read
Write
Idle
DMA0 transfer request
System clock
DMA1 transfer request
DMA2 transfer request
DMA transfer
Mode of processing
DF0 bit
DF1 bit
DF2 bit
CPU processing
DMA0 processing
CPU processing
DMA1 processing
CPU processing
DMA0
processing
Read
Write
Idle
End
processing
Read
Preparation
for transfer
Preparation
for transfer
End
processing
Remarks 1. Transfer in the order of DMA0
DMA1 DMA0 (DMA2 is held pending.)
2. In the case of transfer between external memory spaces (multiplexed bus, no wait)
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Figure 15-3. Period in Which DMA Transfer Request Is Ignored (1)
Preparation
for transfer
Read cycle
Write cycle
Idle
End
processing
DMA transfer
Mode of processing
DFn bit
System clock
Transfer request generated
after this can be acknowledged
DMA0 processing
CPU processing
CPU processing
Note 2
Note 2
DMAn transfer
request
Note 1
Note 2
Notes 1. Interrupt from on-chip peripheral I/O, or software trigger (STGn bit)
2. New DMA request of the same channel is ignored between when the first request is generated and
the end processing is complete.
Remark In the case of transfer between external memory spaces (multiplexed bus, no wait)
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Man
ual
U17717EJ
2
V0UD
571
Figure 15-4. Period in Which DMA Transfer Request Is Ignored (2)
Preparation
for transfer
Read
Write
Idle
<1>
<2>
<3>
<4>
CPU processing
DMA0 processing
CPU processing
DMA1 processing
CPU processing
DMA0
processing
DMA0 transfer request
System clock
DMA1 transfer request
DMA2 transfer request
DMA transfer
Mode of processing
DF0 bit
DF1 bit
DF2 bit
Preparation
for transfer
Read
Write
Idle
Preparation
for transfer
Read
End
processing
End
processing
<1> DMA0 transfer request
<2> New DMA0 transfer request is generated during DMA0 transfer.
A DMA transfer request of the same channel is ignored during DMA transfer.
<3> Requests for DMA0 and DMA1 are generated at the same time.
DMA0 request is ignored (a DMA transfer request of the same channel during transfer is ignored).
DMA1 request is acknowledged.
<4> Requests for DMA0, DMA1, and DMA2 are generated at the same time.
DMA1 request is ignored (a DMA transfer request of the same channel during transfer is ignored).
DMA0 request is acknowledged according to priority. DMA2 request is held pending (transfer of DMA2 occurs next).
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15.13 Cautions
(1) Caution for VSWC register
When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the
VSWC register.
When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC
register, the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System
wait control register (VSWC)).
(2) Caution for DMA transfer executed on internal RAM
When executing the following instructions located in the internal RAM, do not execute a DMA transfer that
transfers data to/from the internal RAM (transfer source/destination), because the CPU may not operate
correctly afterward.
Data access instruction to misaligned address located in internal RAM
Conversely, when executing a DMA transfer to transfer data to/from the internal RAM (transfer
source/destination), do not execute the above two instructions.
(3) Caution for reading DCHCn.TCn bit (n = 0 to 3)
The TCn bit is cleared to 0 when it is read, but it is not automatically cleared even if it is read at a specific
timing. To accurately clear the TCn bit, add the following processing.
(a) When waiting for completion of DMA transfer by polling TCn bit
Confirm that the TCn bit has been set to 1 (after TCn bit = 1 is read), and then read the TCn bit three more
times.
(b) When reading TCn bit in interrupt servicing routine
Execute reading the TCn bit three times.
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(4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1)
Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may
not be initialized. To accurately initialize the channel, execute either of the following two procedures.
(a) Temporarily stop transfer of all DMA channels
Initialize the channel executing DMA transfer using the procedure in <1> to <7> below.
Note, however, that TCn bit is cleared to 0 when step <5> is executed. Make sure that the other
processing programs do not expect that the TCn bit is 1.
<1> Disable interrupts (DI).
<2> Read the DCHCn.Enn bit of DMA channels other than the one to be forcibly terminated, and transfer
the value to a general-purpose register.
<3> Clear the Enn bit of the DMA channels used (including the channel to be forcibly terminated) to 0. To
clear the Enn bit of the last DMA channel, execute the clear instruction twice. If the target of DMA
transfer (transfer source/destination) is the internal RAM, execute the instruction three times.
Example: Execute instructions in the following order if channels 0, 1, and 2 are used (if the target of
transfer is not the internal RAM).
Clear DCHC0.E00 bit to 0.
Clear DCHC1.E11 bit to 0.
Clear DCHC2.E22 bit to 0.
Clear DCHC2.E22 bit to 0 again.
<4> Set the INITn bit of the channel to be forcibly terminated to 1.
<5> Read the TCn bit of each channel not to be forcibly terminated. If both the TCn bit and the Enn bit
read in <2> are 1 (logical product (AND) is 1), clear the saved Enn bit to 0.
<6> After the operation in <5>, write the Enn bit value to the DCHCn register.
<7> Enable interrupts (EI).
Caution Be sure to execute step <5> above to prevent illegal setting of the Enn bit of the channels
whose DMA transfer has been normally completed between <2> and <3>.
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(b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly
<1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop
operation of the on-chip peripheral I/O).
<2> Check that the DMA transfer request of the channel to be forcibly terminated is not held pending, by
using the DTFRn.DFn bit. If a DMA transfer request is held pending, wait until execution of the
pending request is completed.
<3> When it has been confirmed that the DMA request of the channel to be forcibly terminated is not held
pending, clear the Enn bit to 0.
<4> Again, clear the Enn bit of the channel to be forcibly terminated.
If the target of transfer for the channel to be forcibly terminated (transfer source/destination) is the
internal RAM, execute this operation once more.
<5> Copy the initial number of transfers of the channel to be forcibly terminated to a general-purpose
register.
<6> Set the INITn bit of the channel to be forcibly terminated to 1.
<7> Read the value of the DBCn register of the channel to be forcibly terminated, and compare it with the
value copied in <5>. If the two values do not match, repeat operations <6> and <7>.
Remarks 1. When the value of the DBCn register is read in <7>, the initial number of transfers is read if
forced termination has been correctly completed. If not, the remaining number of transfers
is read.
2. Note that method (b) may take a long time if the application frequently uses DMA transfer for
a channel other than the DMA channel to be forcibly terminated.
(5) Procedure of temporarily stopping DMA transfer (clearing Enn bit)
Stop and resume the DMA transfer under execution using the following procedure.
<1> Suppress a transfer request from the DMA request source (stop the operation of the on-chip peripheral
I/O).
<2> Check the DMA transfer request is not held pending, by using the DFn bit (check if the DFn bit = 0).
If a request is pending, wait until execution of the pending DMA transfer request is completed.
<3> If it has been confirmed that no DMA transfer request is held pending, clear the Enn bit to 0 (this
operation stops DMA transfer).
<4> Set the Enn bit to 1 to resume DMA transfer.
<5> Resume the operation of the DMA request source that has been stopped (start the operation of the on-
chip peripheral I/O).
(6) Memory boundary
The operation is not guaranteed if the address of the transfer source or destination exceeds the area of the
DMA target (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer.
(7) Transferring misaligned data
DMA transfer of misaligned data with a 16-bit bus width is not supported.
If an odd address is specified as the transfer source or destination, the least significant bit of the address is
forcibly assumed to be 0.
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(8) Bus arbitration for CPU
Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place
during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the
CPU.
However, the CPU can access the external memory, on-chip peripheral I/O, and internal RAM to/from which
DMA transfer is not being executed.
The CPU can access the internal RAM when DMA transfer is being executed between the external memory
and on-chip peripheral I/O.
The CPU can access the internal RAM and on-chip peripheral I/O when DMA transfer is being executed
between the external memory and external memory.
(9) Registers/bits that must not be rewritten during DMA operation
Set the following registers at the following timing when a DMA operation is not under execution.
[Registers]
DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers
DTFRn.IFCn5 to DTFRn.IFCn0 bits
[Timing of setting]
Period from after reset to start of the first DMA transfer
Time after channel initialization to start of DMA transfer
Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer
(10) Be sure to set the following register bits to 0.
Bits 14 to 10 of DSAnH register
Bits 14 to 10 of DDAnH register
Bits 15, 13 to 8, and 3 to 0 of DADCn register
Bits 6 to 3 of DCHCn register
(11) DMA start factor
Do not start two or more DMA channels with the same start factor. If two or more channels are started with
the same factor, a DMA channel with a lower priority may be acknowledged earlier than a DMA channel with a
higher priority.
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(12) Read values of DSAn and DDAn registers
Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0
to 3).
For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source
address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and
DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA
transfer is executed immediately after the DSAnH register is read.
(a) If DMA transfer does not occur while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Read value of DSAnL register: DSAnL = FFFFH
(b) If DMA transfer occurs while DSAn register is read
<1> Read value of DSAnH register: DSAnH = 0000H
<2> Occurrence of DMA transfer
<3> Incrementing DSAn register: DSAn = 00100000H
<4> Read value of DSAnL register: DSAnL = 0000H
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CHAPTER 16 INTERRUPT/EXCEPTION PROCESSING FUNCTION
The V850ES/HJ2 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a
total of 66/68 interrupt requests.
An interrupt is an event that occurs independently of program execution, and an exception is an event whose
occurrence is dependent on program execution.
The V850ES/HJ2 can process interrupt request signals from the on-chip peripheral hardware and external sources.
Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an
exception event (i.e. fetching of an illegal opcode) (exception trap).
16.1 Features
Interrupts
Non-maskable interrupts: 2 sources
Maskable interrupts:
External: 15, Internal: 49/51 sources (see Table 1-1)
8 levels of programmable priorities (maskable interrupts)
Multiple interrupt control according to priority
Masks can be specified for each maskable interrupt request.
Noise elimination, edge detection, and valid edge specification for external interrupt request signals.
Exceptions
Software exceptions: 32 sources
Exception trap:
2 sources (illegal opcode exception, debug trap)
Interrupt/exception sources are listed in Table 16-1.
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Table 16-1. Interrupt Source List (1/3)
Type Classification
Default
Priority
Name Trigger
Generating
Unit
Exception
Code
Handler
Address
Restored
PC
Interrupt
Control
Register
Reset Interrupt
-
RESET
RESET pin input
Reset input by internal source
RESET 0000H 00000000H
Undefined
-
-
NMI
NMI pin valid edge input
Pin
0010H
00000010H
nextPC
-
Non-
maskable
Interrupt
- INTWDT2
WDT2
overflow
WDT2 0020H 00000020H
Note 1
-
-
TRAP0n
Note 2
TRAP instruction
-
004nH
Note 2
00000040H nextPC
-
Software
exception
Exception
-
TRAP1n
Note 2
TRAP instruction
-
005nH
Note 2
00000050H nextPC
-
Exception
trap
Exception
- ILGOP/
DBG0
Illegal opcode/
DBTRAP instruction
- 0060H 00000060H
nextPC
-
0
INTLVI
Low voltage detection
POCLVI 0080H 00000080H
nextPC LVIIC
1
INTP0
External interrupt pin input
edge detection (INTP0)
Pin 0090H
00000090H
nextPC
PIC0
2
INTP1
External interrupt pin input
edge detection (INTP1)
Pin 00A0H
000000A0H
nextPC
PIC1
3
INTP2
External interrupt pin input
edge detection (INTP2)
Pin 00B0H
000000B0H
nextPC
PIC2
4
INTP3
External interrupt pin input
edge detection (INTP3)
Pin 00C0H
000000C0H
nextPC
PIC3
5
INTP4
External interrupt pin input
edge detection (INTP4)
Pin 00D0H
000000D0H
nextPC
PIC4
6
INTP5
External interrupt pin input
edge detection (INTP5)
Pin 00E0H
000000E0H
nextPC
PIC5
7
INTP6
External interrupt pin input
edge detection (INTP6)
Pin 00F0H
000000F0H
nextPC
PIC6
8
INTP7
External interrupt pin input
edge detection (INTP7)
Pin 0100H
00000100H
nextPC
PIC7
9 INTTQ0OV
TMQ0
overflow
TMQ0 0110H 00000110H
nextPC TQ0OVIC
10
INTTQ0CC0 TMQ0 capture 0/compare 0
match
TMQ0 0120H 00000120H
nextPC TQ0CCIC0
11
INTTQ0CC1 TMQ0 capture 1/compare 1
match
TMQ0 0130H 00000130H
nextPC TQ0CCIC1
12
INTTQ0CC2 TMQ0 capture 2/compare 2
match
TMQ0 0140H 00000140H
nextPC TQ0CCIC2
13
INTTQ0CC3 TMQ0 capture 3/compare 3
match
TMQ0 0150H 00000150H
nextPC TQ0CCIC3
14 INTTP0OV
TMP0
overflow
TMP0
0160H 00000160H nextPC TP0OVIC
15
INTTP0CC0 TMP0 capture 0/compare 0
match
TMP0 0170H
00000170H
nextPC
TP0CCIC0
16
INTTP0CC1 TMP0 capture 1/compare 1
match
TMP0 0180H
00000180H
nextPC
TP0CCIC1
17 INTTP1OV
TMP1
overflow
TMP1
0190H 00000190H nextPC TP1OVIC
18
INTTP1CC0 TMP1 capture 0/compare 0
match
TMP1 01A0H
000001AH
nextPC
TP1CCIC0
19
INTTP1CC1 TMP1 capture 1/compare 1
match
TMP1 01B0H
000001B0H
nextPC
TP1CCIC1
20 INTTP2OV
TMP2
overflow
TMP2 01C0H
000001C0H
nextPC
TP2OVIC
Maskable Interrupt
21
INTTP2CC0 TMP2 capture 0/compare 0
match
TMP2 01D0H
000001D0H
nextPC
TP2CCIC0
Notes 1. For the restoring in the case of INTWDT2, see 16.2.2 (2) From INTWDT2 signal.
2. n = 0H to FH
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Table 16-1. Interrupt Source List (2/3)
Type Classification
Default
Priority
Name Trigger
Generating
Unit
Exception
Code
Handler
Address
Restored
PC
Interrupt
Control
Register
22
INTTP2CC1 TMP2 capture 1/compare 1
match
TMP2 01E0H
000001E0H
nextPC
TP2CCIC1
23 INTTP3OV
TMP3
overflow
TMP3 01F0H
000001F0H
nextPC
TP3OVIC
24
INTTP3CC0 TMP3 capture 0/compare 0
match
TMP3 0200H
00000200H
nextPC
TP3CCIC0
25
INTTP3CC1 TMP3 capture 1/compare 1
match
TMP3 0210H
00000210H
nextPC
TP3CCIC1
26
INTTM0EQ0 TMM0 compare match
TMM0
0220H
00000220H
nextPC
TM0EQIC0
27 INTCB0R CSIB0
reception
completion CSIB0
0230H
00000230H nextPC
CB0RIC
28 INTCB0T CSIB0
consecutive
transmission write enable
CSIB0 0240H 00000240H
nextPC CB0TIC
29 INTCB1R CSIB1
reception
completion CSIB1
0250H
00000250H nextPC
CB1RIC
30 INTCB1T CSIB1
consecutive
transmission write enable
CSIB1 0260H 00000260H
nextPC CB1TIC
31 INTUA0R UARTA0
reception
completion
UARTA0 0270H 00000280H nextPC UA0RIC
32
INTUA0T
UARTA0 transmission enable UARTA0 0280H 00000280H nextPC UA0TIC
33 INTUA1R UARTA1
reception
completion/UARTA1
reception error
UARTA1 0290H 00000290H nextPC UA1RIC
34
INTUA1T
UARTA1 transmission enable UARTA1 02A0H 000002A0H nextPC UA1TIC
35 INTAD
A/D
conversion
completion A/D
02BH
000002B0H nextPC
ADIC
36 INTKR Key
return
interrupt
request KR
0300H
00000300H nextPC KRIC
37 INTWTI Watch
timer
interval WT 0310H
00000310H
nextPC
WTIIC
38 INTWT Watch
timer
reference
time WT
0320H
00000320H nextPC
WTIC
39
INTP8
External interrupt pin input
edge detection (INTP8)
Pin 0330H
00000330H
nextPC
PIC8
40
INTP9
External interrupt pin input
edge detection (INTP9)
Pin 0340H
00000340H
nextPC
PIC9
41
INTP10
External interrupt pin input
edge detection (INTP10)
Pin 0350H
00000350H
nextPC
PIC10
42 INTTQ1OV
TMQ1
overflow
TMQ1 0360H 00000360H
nextPC TQ1OVIC
43
INTTQ1CC0 TMQ1 capture 0/compare 0
match
TMQ1 0370H 00000370H
nextPC TQ1CCIC0
44
INTTQ1CC1 TMQ1 capture 1/compare 1
match
TMQ1 0380H 00000380H
nextPC TQ1CCIC1
45
INTTQ1CC2 TMQ1 capture 2/compare 2
match
TMQ1 0390H 00000390H
nextPC TQ1CCIC2
46
INTTQ1CC3 TMQ1 capture 3/compare 3
match
TMQ1 03A0H
000003A0H
nextPC TQ1CCIC3
47 INTUA2R UARTA2
reception
completion/error
UARTA2 03B0H 000003B0H nextPC UA2RIC
48 INTUA2T UARTA2
transmission
enable
UARTA2 03C0H 000003C0H nextPC
UA2TIC
49
INTDMA0
DMA0 transfer end
DMA 0410H
00000410H
nextPC
DMAIC0
50
INTDMA1
DMA1 transfer end
DMA 0420H
00000420H
nextPC
DMAIC1
51
INTDMA2
DMA2 transfer end
DMA 0430H
00000430H
nextPC
DMAIC2
Maskable Interrupt
52
INTDMA3
DMA3 transfer end
DMA 0440H
00000440H
nextPC
DMAIC3
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Table 16-1. Interrupt Source List (3/3)
Type Classification
Default
Priority
Name Trigger
Generating
Unit
Exception
Code
Handler
Address
Restored
PC
Interrupt
Control
Register
53
INTP11
External interrupt pin input
edge detection (INTP11)
Pin 0450H
00000450H
nextPC
PIC11
54
INTP12
External interrupt pin input
edge detection (INTP12)
Pin 0460H
00000460H
nextPC
PIC12
55
INTP13
External interrupt pin input
edge detection (INTP13)
Pin 0470H
00000470H
nextPC
PIC13
56
INTP14
External interrupt pin input
edge detection (INTP14)
Pin 0480H
00000480H
nextPC
PIC14
57 INTTQ2OV TMQ2
overflow
TMQ2 0490H 00000490H
nextPC TQ2OVIC
58
INTTQ2CC0 TMQ2 capture 0/compare 0
match
TMQ2 04A0H 000004A0H
nextPC TQ2CCIC0
59
INTTQ2CC1 TMQ2 capture 1/compare 1
match
TMQ2 04B0H 000004B0H
nextPC TQ2CCIC1
60
INTTQ2CC2 TMQ2 capture 2/compare 2
match
TMQ2 04C0H 000004C0H
nextPC TQ2CCIC2
61
INTTQ2CC3 TMQ2 capture 3/compare 3
match
TMQ2 04D0H 000004D0H
nextPC TQ2CCIC3
62 INTCB2R CSIB2
reception
completion/error
CSIB2 04E0H 000004E0H
nextPC CB2RIC
63 INTCB2T CSIB2
continuous
transmission write enable
CSIB2 04F0H 000004F0H
nextPC CB2TIC
64
INTUA3R
Note
UARTA3 reception
completion/error
UARTA3 0500H
00000500H nextPC
UA3RIC
Maskable Interrupt
65
INTUA3T
Note
UARTA3 transmission enable UARTA3 0510H
00000510H nextPC
UA3TIC
Note
PD70F3711, 70F3712 only
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the same
time. The highest priority is 0.
The priority order of non-maskable interrupt is INTWDT2 > NMI.
Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC when
interrupt servicing is started. Note, however, that the restored PC when a non-
maskable or maskable interrupt is acknowledged while one of the following
instructions is being executed does not become the nextPC (if an interrupt is
acknowledged during interrupt execution, execution stops, and then resumes after
the interrupt servicing has finished).
Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
Division instructions (DIV, DIVH, DIVU, DIVHU)
PREPARE, DISPOSE instructions (only if an interrupt is generated before the
stack pointer is updated)
nextPC:
The PC value that starts the processing following interrupt/exception processing.
2. The execution address of the illegal instruction when an illegal opcode exception occurs is calculated
by (Restored PC
- 4).
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16.2 Non-Maskable Interrupts
A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt
disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request
signals.
This product has the following two non-maskable interrupt request signals.
NMI pin input (NMI)
Non-maskable interrupt request signal generated by overflow of watchdog timer (INTWDT2)
The valid edge of the NMI pin can be selected from four types: "rising edge", "falling edge", "both edges", and "no
edge detection".
The function of the NMI pin is enabled by setting the PMC0.PMC02 bit to 1 and the INTF0.INTF02 bit and
INTR0.INTR02 bit to a desired value, and specifying a desired valid edge.
The non-maskable interrupt request signal generated by overflow of watchdog timer 2 (INTWDT2) functions when
the WDTM2.WDM21 and WDTM2.WDM20 bits are set to "01".
If two or more non-maskable interrupt request signals occur at the same time, the interrupt with the higher priority
is serviced, as follows (the interrupt request signal with the lower priority is ignored).
INTWDT2 > NMI
If a new NMI or INTWDT2 request signal is issued while an NMI is being serviced, it is serviced as follows.
(1) If new NMI request signal is issued while NMI is being serviced
The new NMI request signal is held pending, regardless of the value of the PSW.NP bit. The pending NMI
request signal is acknowledged after the NMI currently under execution has been serviced (after the RETI
instruction has been executed).
(2) If INTWDT2 request signal is issued while NMI is being serviced
The INTWDT2 request signal is held pending if the NP bit remains set (1) while the NMI is being serviced. The
pending INTWDT2 request signal is acknowledged after the NMI currently under execution has been serviced
(after the RETI instruction has been executed).
If the NP bit is cleared (0) while the NMI is being serviced, the newly generated INTWDT2 request signal is
executed (the NMI servicing is stopped).
Caution For the non-maskable interrupt servicing executed by the non-maskable interrupt request
signal (INTWDT2), see 16.2.2 (2) From INTWDT2 signal.
Figure 16-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (1/2)
(a) NMI and INTWDT2 request signals generated at the same time
Main routine
System reset
NMI and INTWDT2 requests
(generated simultaneously)
INTWDT2 servicing
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Figure 16-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2)
(b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing
Non-maskable
interrupt being
serviced
Non-maskable interrupt request signal generated during non-maskable interrupt servicing
NMI
INTWDT2
NMI
NMI request generated during NMI servicing
INTWDT2 request generated during NMI servicing
(NP bit = 1 retained before INTWDT2 request)
Main routine
NMI
request
NMI servicing
(Held pending)
Servicing of
pending NMI
NMI
request
Main routine
System reset
NMI
request
NMI servicing
(Held pending)
INTWDT2
servicing
INTWDT2
request
INTWDT2 request generated during NMI servicing
(NP bit = 0 set before INTWDT2 request)
Main routine
System reset
NMI
request
NMI
servicing
INTWDT2
servicing
INTWDT2
request
NP = 0
INTWDT2 request generated during NMI servicing
(NP = 0 set after INTWDT2 request)
Main routine
System reset
NMI
request
NMI
servicing
INTWDT2
servicing
NP = 0
INTWDT2 request generated during INTWDT2 servicing
Main routine
System reset
INTWDT2 request
INTWDT2 servicing
(Invalid)
NMI request generated during INTWDT2 servicing
INTWDT2
Main routine
System reset
INTWDT2 request
INTWDT2 servicing
(Invalid)
NMI
request
(Held pending)
INTWDT2
request
INTWDT2
request
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16.2.1 Operation
If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers
control to the handler routine.
<1> Saves the restored PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes exception code (0010H, 0020H) to the higher halfword (FECC) of ECR.
<4> Sets the PSW.NP and PSW.ID bits to 1 and clears the PSW.EP bit to 0.
<5> Sets the handler address (00000010H, 00000020H) corresponding to the non-maskable interrupt to the PC,
and transfers control.
The servicing configuration of a non-maskable interrupt is shown in Figure 16-2.
Figure 16-2. Servicing Configuration of Non-Maskable Interrupt
PSW.NP
FEPC
FEPSW
ECR.FECC
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
0010H, 0020H
1
0
1
00000010H,
00000020H
1
0
NMI input
Non-maskable interrupt request
Interrupt servicing
Interrupt request held pending
INTC
acknowledged
CPU processing
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16.2.2 Restore
(1) From NMI pin input
Execution is restored from the NMI servicing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Loads the restored PC and PSW from FEPC and FEPSW, respectively, because the PSW.EP bit is 0 and
the PSW.NP bit is 1.
<2> Transfers control back to the address of the restored PC and PSW.
Figure 16-3 illustrates how the RETI instruction is processed.
Figure 16-3. RETI Instruction Processing
PSW.EP
RETI instruction
PSW.NP
Original processing restored
1
1
0
0
PC
PSW
EIPC
EIPSW
PC
PSW
FEPC
FEPSW
Caution When the EP and NP bits are changed by the LDSR instruction during non-maskable interrupt
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 1 using the LDSR
instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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(2) From INTWDT2 signal
Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2)
by using the RETI instruction is disabled. Execute the following software reset processing.
Figure 16-4. Software Reset Processing
INTWDT2 occurs.
FEPC
Software reset processing address
FEPSW
Value that sets NP bit = 1, EP bit = 0
RETI
RETI 10 times (FEPC and FEPSW
Note
must be set.)
PSW
PSW default value setting
Initialization processing
INTWDT2 servicing routine
Software reset processing routine
Note FEPSW
Value that sets NP bit = 1, EP bit = 0
16.2.3 NP flag
The NP flag is a status flag that indicates that non-maskable interrupt servicing is under execution.
This flag is set when a non-maskable interrupt request signal has been acknowledged, and masks non-maskable
interrupt requests to prohibit multiple interrupts from being acknowledged.
0
NP
EP
ID SAT CY
OV
S
Z
PSW
No non-maskable interrupt servicing
Non-maskable interrupt currently being serviced
NP
0
1
Non-maskable interrupt servicing status
After reset: 00000020H
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16.3 Maskable Interrupts
Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/HJ2 has 64/66
maskable interrupt sources.
If two or more maskable interrupt request signals are generated at the same time, they are acknowledged
according to the default priority. In addition to the default priority, eight levels of priorities can be specified by using
the interrupt control registers (programmable priority control).
When an interrupt request signal has been acknowledged, the acknowledgment of other maskable interrupt
request signals is disabled and the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
enables servicing of interrupts having a higher priority than the interrupt request signal in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the
same priority level cannot be nested.
To enable multiple interrupts, however, save EIPC and EIPSW to memory or general-purpose registers before
executing the EI instruction, and execute the DI instruction before the RETI instruction to restore the original values of
EIPC and EIPSW.
16.3.1 Operation
If a maskable interrupt occurs, the CPU performs the following processing, and transfers control to a handler
routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the PSW. ID bit to 1 and clears the PSW. EP bit to 0.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The maskable interrupt request signal masked by INTC and the maskable interrupt request signal generated while
another interrupt is being serviced (while the PSW.NP bit = 1 or the PSW.ID bit = 1) are held pending inside INTC. In
this case, servicing a new maskable interrupt is started in accordance with the priority of the pending maskable
interrupt request signal if either the maskable interrupt is unmasked or the NP and ID bits are cleared to 0 by using the
RETI or LDSR instruction.
How maskable interrupts are serviced is illustrated below.
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Figure 16-5. Maskable Interrupt Servicing
INT input
xxIF = 1
No
xxMK = 0
No
Is the interrupt
mask released?
Yes
Yes
No
No
No
Maskable interrupt request
Interrupt request held pending
PSW.NP
PSW.ID
1
1
Interrupt request held pending
0
0
Interrupt servicing
CPU processing
INTC acknowledged
Yes
Yes
Yes
Priority higher than
that of interrupt currently
being serviced?
Priority higher
than that of other interrupt
request?
Highest default
priority of interrupt requests
with the same priority?
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
Corresponding
bit of ISPR
Note
PC
Restored PC
PSW
Exception code
0
1
1
Handler address
Interrupt requested?
Note For the ISPR register, see 16.3.6 In-service priority register (ISPR).
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16.3.2 Restore
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
of the restored PC.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is
0.
<2> Transfers control to the address of the restored PC and PSW.
Figure 16-6 illustrates the processing of the RETI instruction.
Figure 16-6. RETI Instruction Processing
PSW.EP
RETI instruction
PSW.NP
Restores original processing
1
1
0
0
PC
PSW
Corresponding
bit of ISPR
Note
EIPC
EIPSW
0
PC
PSW
FEPC
FEPSW
Note For the ISPR register, see 16.3.6 In-service priority register (ISPR).
Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR
instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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16.3.3 Priorities of maskable interrupts
The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is
being serviced. Multiple interrupts can be controlled by priority levels.
There are two types of priority level control: control based on the default priority levels, and control based on the
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are
generated at the same time, interrupt request signals are serviced in order depending on the priority level allocated to
each interrupt request type (default priority level) beforehand. For more information, see Table 16-1
Interrupt/Exception Source List. The programmable priority control customizes interrupt request signals into eight
levels by setting the priority level specification flag.
Note that when an interrupt request signal is acknowledged, the PSW.ID flag is automatically set to 1. Therefore,
when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in
the interrupt service program) to set the interrupt enable mode.
Remark xx: Identification name of each peripheral unit (see Table 16-2 Interrupt Control Register (xxICn))
n: Peripheral unit number (see Table 16-2 Interrupt Control Register (xxICn)).
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Figure 16-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
While an Interrupt Is Being Serviced (1/2)
Main routine
EI
EI
Interrupt request a
(level 3)
Servicing of a
Servicing of b
Servicing of c
Interrupt request c
(level 3)
Servicing of d
Servicing of e
EI
Interrupt request e
(level 2)
Servicing of f
EI
Servicing of g
Interrupt request g
(level 1)
Interrupt request h
(level 1)
Servicing of h
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.
Interrupt
request b
(level 2)
Interrupt request d
(level 2)
Interrupt request f
(level 3)
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Remarks 1. a to u in the figure are the temporary names of interrupt request signals shown for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt request
signals.
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Figure 16-7. Example of Processing in Which Another Interrupt Request Signal Is Issued
While an Interrupt Is Being Serviced (2/2)
Main routine
EI
Interrupt request i
(level 2)
Servicing of i
Servicing of k
Interrupt
request j
(level 3)
Servicing of j
Interrupt request l
(level 2)
EI
EI
EI
Interrupt request o
(level 3)
Interrupt request s
(level 1)
Interrupt request k
(level 1)
Servicing of l
Servicing of n
Servicing of m
Servicing of s
Servicing of u
Servicing of t
Interrupt
request m
(level 3)
Interrupt request n
(level 1)
Servicing of o
Interrupt
request p
(level 2)
Interrupt
request q
(level 1)
Interrupt
request r
(level 0)
Interrupt request u
(level 2)
Note 2
Interrupt
request t
(level 2)
Note 1
Servicing of p
Servicing of q
Servicing of r
EI
If levels 3 to 0 are acknowledged
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Notes 1. Lower default priority
2. Higher
default
priority
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Figure 16-8. Example of Servicing Interrupt Request Signals Simultaneously Generated
Default priority
a > b > c
Main routine
EI
Interrupt request a (level 2)
Interrupt request b (level 1)
Interrupt request c (level 1)
Servicing of interrupt request b
.
.
Servicing of interrupt request c
Servicing of interrupt request a
Interrupt request b and c are
acknowledged first according to
their priorities.
Because the priorities of b and c are
the same, b is acknowledged first
according to the default priority.
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Remarks 1. a to c in the figure are the temporary names of interrupt request signals shown for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt request
signals.
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16.3.4 Interrupt control register (xxICn)
The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions
for each maskable interrupt request.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 47H.
Caution Disable interrupts (DI) or mask the interrupt to read the xxICn.xxIFn bit. If the xxIFn bit is read
while interrupts are enabled (EI) or while the interrupt is unmasked, the correct value may not be
read when acknowledging an interrupt and reading the bit conflict.
xxIFn
Interrupt request not issued
Interrupt request issued
xxIFn
0
1
Interrupt request flag
Note
xxICn
xxMKn
0
0
0
xxPRn2
xxPRn1
xxPRn0
Interrupt servicing enabled
Interrupt servicing disabled (pending)
xxMKn
0
1
Interrupt mask flag
Specifies level 0 (highest).
Specifies level 1.
Specifies level 2.
Specifies level 3.
Specifies level 4.
Specifies level 5.
Specifies level 6.
Specifies level 7 (lowest).
xxPRn2
0
0
0
0
1
1
1
1
Interrupt priority specification bit
xxPRn1
0
0
1
1
0
0
1
1
xxPRn0
0
1
0
1
0
1
0
1
After reset: 47H R/W Address: FFFFF110H to FFFFF1A2H
6
7
Note The flag xxlFn is reset automatically by the hardware if an interrupt request signal is acknowledged.
Remark xx: Identification name of each peripheral unit (see Table 16-2 Interrupt Control Registers (xxICn))
n: Peripheral unit number (see Table 16-2 Interrupt Control Registers (xxICn)).
The addresses and bits of the interrupt control registers are as follows.
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Table 16-2. Interrupt Control Registers (xxICn) (1/2)
Bit
Address Register
7 6 5 4 3 2 1 0
FFFFF110H
LVIIC
LVIIF
LVIMK
0 0 0
LVIPR2
LVIPR1
LVIPR0
FFFFF112H
PIC0
PIF0
PMK0
0 0 0
PPR02
PPR01
PPR00
FFFFF114H
PIC1
PIF1
PMK1
0 0 0
PPR12
PPR11
PPR10
FFFFF116H
PIC2
PIF2
PMK2
0 0 0
PPR22
PPR21
PPR20
FFFFF118H
PIC3
PIF3
PMK3
0 0 0
PPR32
PPR31
PPR30
FFFFF11AH
PIC4
PIF4
PMK4
0 0 0
PPR42
PPR41
PPR40
FFFFF11CH
PIC5
PIF5
PMK5
0 0 0
PPR52
PPR51
PPR50
FFFFF11EH
PIC6
PIF6
PMK6
0 0 0
PPR62
PPR61
PPR60
FFFFF120H
PIC7
PIF7
PMK7
0 0 0
PPR72
PPR71
PPR70
FFFFF122H
TQ0OVIC
TQ0OVIF
TQ0OVMK
0 0 0
TQ0OVPR2
TQ0OVPR1
TQ0OVPR0
FFFFF124H TQ0CCIC0
TQ0CCIF0
TQ0CCMK0
0 0 0
TQ0CCPR02 TQ0CCPR01
TQ0CCPR00
FFFFF126H TQ0CCIC1
TQ0CCIF1
TQ0CCMK1
0 0 0
TQ0CCPR12 TQ0CCPR11
TQ0CCPR10
FFFFF128H TQ0CCIC2
TQ0CCIF2
TQ0CCMK2
0 0 0
TQ0CCPR22 TQ0CCPR21
TQ0CCPR20
FFFFF12AH TQ0CCIC3
TQ0CCIF3
TQ0CCMK3
0 0 0
TQ0CCPR32 TQ0CCPR31
TQ0CCPR30
FFFFF12CH
TP0OVIC
TP0OVIF
TP0OVMK
0 0 0
TP0OVPR2
TP0OVPR1
TP0OVPR0
FFFFF12EH TP0CCIC0
TP0CCIF0
TP0CCMK0
0 0 0
TP0CCPR02 TP0CCPR01
TP0CCPR00
FFFFF130H TP0CCIC1
TP0CCIF1
TP0CCMK1
0 0 0
TP0CCPR12 TP0CCPR11
TP0CCPR10
FFFFF132H
TP1OVIC
TP1OVIF
TP1OVMK
0 0 0
TP1OVPR2
TP1OVPR1
TP1OVPR0
FFFFF134H TP1CCIC0
TP1CCIF0
TP1CCMK0
0 0 0
TP1CCPR02 TP1CCPR01
TP1CCPR00
FFFFF136H TP1CCIC1
TP1CCIF1
TP1CCMK1
0 0 0
TP1CCPR12 TP1CCPR11
TP1CCPR10
FFFFF138H
TP2OVIC
TP2OVIF
TP2OVMK
0 0 0
TP2OVPR2
TP2OVPR1
TP2OVPR0
FFFFF13AH TP2CCIC0
TP2CCIF0
TP2CCMK0
0 0 0
TP2CCPR02 TP2CCPR01
TP2CCPR00
FFFFF13CH TP2CCIC1
TP2CCIF1
TP2CCMK1
0 0 0
TP2CCPR12 TP2CCPR11
TP2CCPR10
FFFFF13EH
TP3OVIC
TP3OVIF
TP3OVMK
0 0 0
TP3OVPR2
TP3OVPR1
TP3OVPR0
FFFFF140H TP3CCIC0
TP3CCIF0
TP3CCMK0
0 0 0
TP3CCPR02 TP3CCPR01
TP3CCPR00
FFFFF142H TP3CCIC1
TP3CCIF1
TP3CCMK1
0 0 0
TP3CCPR12 TP3CCPR11
TP3CCPR10
FFFFF144H TM0EQIC0
TM0EQIF0
TM0EQMK0
0 0 0
TM0EQPR02
TM0EQPR01
TM0EQPR00
FFFFF146H CB0RIC CB0RIF CB0RMK
0 0 0
CB0RPR2
CB0RPR1
CB0RPR0
FFFFF148H CB0TIC CB0TIF CB0TMK
0 0 0
CB0TPR2
CB0TPR1
CB0TPR0
FFFFF14AH CB1RIC CB1RIF CB1RMK
0 0 0
CB1RPR2
CB1RPR1
CB1RPR0
FFFFF14CH CB1TIC CB1TIF CB1TMK
0 0 0
CB1TPR2
CB1TPR1
CB1TPR0
FFFFF14EH UA0RIC UA0RIF UA0RMK
0 0 0
UA0RPR2
UA0RPR1
UA0RPR0
FFFFF150H UA0TIC UA0TIF UA0TMK
0 0 0
UA0TPR2
UA0TPR1
UA0TPR0
FFFFF152H UA1RIC UA1RIF UA1RMK
0 0 0
UA1RPR2
UA1RPR1
UA1RPR0
FFFFF154H UA1TIC UA1TIF UA1TMK
0 0 0
UA1TPR2
UA1TPR1
UA1TPR0
FFFFF156H ADIC ADIF ADMK
0 0 0
ADPR2
ADPR1
ADPR0
FFFFF160H KRIC KRIF KRMK
0 0 0
KRPR2
KRPR1
KRPR0
FFFFF162H
WTIIC
WTIIF
WTIMK
0 0 0
WTIPR2
WTIPR1
WTIPR0
FFFFF164H
WTIC
WTIF
WTMK
0 0 0
WTPR2
WTPR1
WTPR0
FFFFF166H
PIC8
PIF8
PMK8
0 0 0
PPR82
PPR81
PPR80
FFFFF168H
PIC9
PIF9
PMK9
0 0 0
PPR92
PPR91
PPR90
FFFFF16AH
PIC10
PIF10
PMK10
0 0 0
PPR102
PPR101
PPR100
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Table 16-2. Interrupt Control Registers (xxICn) (2/2)
Bit
Address Register
7 6 5 4 3 2 1 0
FFFFF16CH TQ1OVIC TQ1OVIF
TQ1OVMK
0
0
0
TQ1OVPR2
TQ1OVPR1
TQ1OVPR0
FFFFF16EH TQ1CCIC0
TQ1CCIF0
TQ1CCMK0
0 0 0
TQ1CCPR02
TQ1CCPR01 TQ1CCPR00
FFFFF170H TQ1CCIC1
TQ1CCIF1
TQ1CCMK1
0 0 0
TQ1CCPR12
TQ1CCPR11 TQ1CCPR10
FFFFF172H TQ1CCIC2
TQ1CCIF2
TQ1CCMK2
0 0 0
TQ1CCPR22
TQ1CCPR21 TQ1CCPR20
FFFFF174H TQ1CCIC3
TQ1CCIF3
TQ1CCMK3
0 0 0
TQ1CCPR32
TQ1CCPR31 TQ1CCPR30
FFFFF176H UA2RIC UA2RIF UA2RMK
0 0 0
UA2RPR2
UA2RPR1
UA2RPR0
FFFFF178H UA2TIC UA2TIF UA2TMK
0 0 0
UA2TPR2
UA2TPR1
UA2TPR0
FFFFF182H DMAIC0 DMAIF0 DMAMK0
0 0 0
DMAPR02
DMAPR01
DMAPR00
FFFFF184H DMAIC1 DMAIF1 DMAMK1
0 0 0
DMAPR12
DMAPR11
DMAPR10
FFFFF186H DMAIC2 DMAIF2 DMAMK2
0 0 0
DMAPR22
DMAPR21
DMAPR20
FFFFF188H DMAIC3 DMAIF3 DMAMK3
0 0 0
DMAPR32
DMAPR31
DMAPR30
FFFFF18AH PIC11 PIF11 PMK11
0
0
0
PPR112
PPR111
PPR110
FFFFF18CH PIC12 PIF12 PMK12
0
0
0
PPR122
PPR121
PPR120
FFFFF18EH PIC13 PIF13 PMK13
0
0
0
PPR132
PPR131
PPR130
FFFFF190H PIC14 PIF14 PMK14
0 0 0
PPR142
PPR141
PPR140
FFFFF192H TQ2OVIC
TQ2OVIF
TQ2OVMK
0
0
0 TQ2OVPR2
TQ2OVPR1
TQ2OVPR0
FFFFF194H TQ2CCIC0
TQ2CCIF0
TQ2CCMK0
0 0 0
TQ2CCPR02
TQ2CCPR01 TQ2CCPR00
FFFFF196H TQ2CCIC1
TQ2CCIF1
TQ2CCMK1
0 0 0
TQ2CCPR12
TQ2CCPR11 TQ2CCPR10
FFFFF198H TQ2CCIC2
TQ2CCIF2
TQ2CCMK2
0 0 0
TQ2CCPR22
TQ2CCPR21 TQ2CCPR20
FFFFF19AH TQ2CCIC3
TQ2CCIF3
TQ2CCMK3
0 0 0
TQ2CCPR32
TQ2CCPR31 TQ2CCPR30
FFFFF19CH CB2RIC CB2RIF CB2RMK
0 0 0
CB2RPR2
CB2RPR1
CB2RPR0
FFFFF19EH CB2TIC CB2TIF CB2TMK
0 0 0
CB2TPR2
CB2TPR1
CB2TPR0
FFFFF1A0H
UA3RIC
Note
UA3RIF UA3RMK
0
0
0
UA3RPR2 UA3RPR1 UA3RPR0
FFFFF1A2H
UA3TIC
Note
UA3TIF UA3TMK
0
0
0
UA3TPR2 UA3TPR1 UA3TPR0
Note
PD70F3711, 70F3712 only
16.3.5 Interrupt mask registers 0 to 4 (IMR0 to IMR4)
The IMR0 to IMR4 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to
IMR4 registers is equivalent to the xxICn.xxMKn bit.
The IMRm register can be read or written in 16-bit units (m = 0 to 4).
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,
these registers can be read or written in 8-bit or 1-bit units (m = 0 to 4).
Reset sets these registers to FFFFH.
Caution The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is manipulated using the
name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as
a result, the contents of the IMRm register are also rewritten).
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TP0CCMK0
PMK6
IMR0 (IMR0H
Note 1
)
IMR0L
TP0OVMK
PMK5
TQ0CCMK3
PMK4
TQ0CCMK2
PMK3
TQ0CCMK1
PMK2
TQ0CCMK0
PMK1
TQ0OVMK
PMK0
PMK7
LVIMK
After reset: FFFFH R/W Address: IMR0 FFFFF100H,
IMR0L FFFFF100H, IMR0H FFFFF101H
After reset: FFFFH R/W Address: IMR1 FFFFF102H,
IMR1L FFFFF102H, IMR1H FFFFF103H
After reset: FFFFH R/W Address: IMR2 FFFFF104H,
IMR2L FFFFF104H, IMR2H FFFFF105H
UA0RMK
TP3OVMK
IMR1 (IMR1H
Note 1
)
IMR1L
CB1TMK
TP2CCMK1
CB1RMK
TP2CCMK0
CB0TMK
TP2OVMK
CB0RMK
TP1CCMK1
TM0EQMK0
TP1CCMK0
TP3CCMK1
TP1OVMK
TP3CCMK0
TP0CCMK1
TQ1CCMK0
1
KRMK
UA0TMK
xxMKn
0
1
Interrupt servicing enabled
Interrupt servicing disabled
IMR2 (IMR2H
Note 1
)
IMR2L
TQ1OVMK
1
1
PMK9
1
ADMK
UA1TMK
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
0
PMK13
IMR3 (IMR3H
Note 1
)
IMR3L
PMK12
1
PMK11
1
DMAMK3
UA2TMK
DMAMK2
UA2RMK TQ1CCMK3 TQ1CCMK2 TQ1CCMK1
After reset: FFFFH R/W Address: IMR3 FFFFF106H,
IMR3L FFFFF106H, IMR3H FFFFF107H
8
1
9
DMAMK0
10
DMAMK1
11
12
13
14
15
1
2
3
4
5
6
7
1
0
8
9
10
11
12
13
14
15
1
2
3
4
5
6
7
0
8
9
WTIMK
10
WTMK
11
PMK8
12
13
PMK10
Setting of interrupt mask flag
14
15
1
UA1RMK
2
3
4
5
6
7
0
1
IMR4 (IMR4H
Note 1
)
IMR4L
1
CB2RMK
1
TQ2CCMK3
1
4
TQ2CCMK2
1
TQ2CCMK1 TQ2CCMK0 TQ2OVMK
PMK14
After reset: FFFFH R/W Address: IMR4 FFFFF108H,
IMR4L FFFFF108H, IMR4H FFFFF109H
8
UA3RMK
Note 2
9
UA3TMK
Note 2
10
1
11
12
13
14
15
1
2
3
4
5
6
7
CB2TMK
0
Notes 1. To read bits 8 to 15 of the IMR0 to IMR4 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of
IMR0H to IMR4H registers.
2.
PD70F3711, 70F3712 only
Caution Set bits 15 to 10 of the IMR4 register, bits 8 to 5 of the IMR3 register, and bits 7 to 4 of the IMR2
register to 1. If the setting of these bits is changed, the operation is not guaranteed.
Remark xx: Identification
name
of each peripheral unit (see Table 16-2 Interrupt Control Registers
(xxICn)).
n: Peripheral unit number (see Table 16-2 Interrupt Control Registers (xxICn))
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16.3.6 In-service priority register (ISPR)
The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt
request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal
is set to 1 and remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request signal having the highest
priority is automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-
maskable interrupt servicing or exception processing.
This register is read-only, in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution If an interrupt is acknowledged while the ISPR register is being read in the interrupt enabled (EI)
status, the value of the ISPR register after the bits of the register have been set by
acknowledging the interrupt may be read. To accurately read the value of the ISPR register
before an interrupt is acknowledged, read the register while interrupts are disabled (DI).
ISPR7
Interrupt request signal with priority n not acknowledged
Interrupt request signal with priority n acknowledged
ISPRn
0
1
Priority of interrupt currently acknowledged
ISPR
ISPR6
ISPR5
ISPR4
ISPR3
ISPR2
ISPR1
ISPR0
After reset: 00H R Address: FFFFF1FAH
7
6
5
4
3
2
1
0
Remark n = 0 to 7 (priority level)
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16.3.7 ID flag
This flag controls the maskable interrupt's operating state, and stores control information regarding enabling or
disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW.
Reset sets this flag to 00000020H.
0
NP
EP
ID SAT CY
OV
S
Z
PSW
Maskable interrupt request signal acknowledgment enabled
Maskable interrupt request signal acknowledgment disabled (pending)
ID
0
1
Specification of maskable interrupt servicing
Note
After reset: 00000020H
Note Interrupt disable flag (ID) function
This bit is set to 1 by the DI instruction and cleared to 0 by the EI instruction. Its value is also modified by
the RETI instruction or LDSR instruction when referencing the PSW.
Non-maskable interrupt request signals and exceptions are acknowledged regardless of this flag. When
a maskable interrupt request signal is acknowledged, the ID flag is automatically set to 1 by hardware.
The interrupt request signal generated during the acknowledgment disabled period (ID flag = 1) is
acknowledged when the xxICn.xxIFn bit is set to 1, and the ID flag is cleared to 0.
16.3.8 Watchdog timer mode register 2 (WDTM2)
This register can be read or written in 8-bit units (for details, see CHAPTER 11 FUNCTIONS OF WATCHDOG
TIMER 2).
Reset sets this register to 67H.
0
WDTM2
WDM21
WDM20
0
0
0
0
0
After reset: 67H R/W Address: FFFFF6D0H
Stops operation
Non-maskable interrupt request mode
Reset mode (initial-value)
WDM21
0
0
1
WDM20
0
1
Selection of watchdog timer operation mode
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16.4 Software Exception
A software exception is generated when the CPU executes the TRAP instruction, and can always be
acknowledged.
16.4.1 Operation
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the PSW.EP and PSW.ID bits to 1.
<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC,
and transfers control.
Figure 16-9 illustrates the processing of a software exception.
Figure 16-9. Software Exception Processing
TRAP instruction
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Restored PC
PSW
Exception code
1
1
Handler address
CPU processing
Exception processing
Note
Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.)
The handler address is determined by the TRAP instruction's operand (vector). If the vector is 00H to 0FH, it
becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.
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16.4.2 Restore
Recovery from software exception processing is carried out by the RETI instruction.
By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored
PC's address.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1.
<2> Transfers control to the address of the restored PC and PSW.
Figure 16-10 illustrates the processing of the RETI instruction.
Figure 16-10. RETI Instruction Processing
PSW.EP
RETI instruction
PC
PSW
EIPC
EIPSW
PSW.NP
Original processing restored
PC
PSW
FEPC
FEPSW
1
1
0
0
Caution When the EP and NP bits are changed by the LDSR instruction during the software exception
processing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 1 and the NP bit back to 0 using the LDSR
instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.
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16.4.3 EP flag
The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception
occurs.
0
NP
EP
ID SAT CY
OV
S
Z
PSW
Exception processing not in progress.
Exception processing in progress.
EP
0
1
Exception processing status
After reset: 00000020H
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16.5 Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850ES/HJ2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
16.5.1 Illegal opcode definition
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
15
16
23 22
x x x x x x 0
x
x
x
x
x
x
x
x
x
x
1
1
1
1
1
1
x
x
x
x
x
27 26
31
0
4
5
10
11
1
1
1
1
1
1
0
1
to
x: Arbitrary
Caution Since it is possible to assign this instruction to an illegal opcode in the future, it is recommended
that it not be used.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
control.
Figure 16-11 illustrates the processing of the exception trap.
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Figure 16-11. Exception Trap Processing
Exception trap (ILGOP) occurs
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
1
1
1
00000060H
Exception processing
CPU processing
(2) Restore
Recovery from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction,
the CPU carries out the following processing and controls the address of the restored PC.
<1> Loads the restored PC and PSW from DBPC and DBPSW.
<2> Transfers control to the address indicated by the restored PC and PSW.
Caution DBPC and DBPSW can be accessed only during the interval between the execution of the
DBTRAP instruction and the DBRET instruction.
Figure 16-12 illustrates the restore processing from an exception trap.
Figure 16-12. Restore Processing from Exception Trap
DBRET instruction
PC
PSW
DBPC
DBPSW
Jump to address of restored PC
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16.5.2 Debug trap
A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always
acknowledged.
(1) Operation
Upon occurrence of a debug trap, the CPU performs the following processing.
<1> Saves restored PC to DBPC.
<2> Saves current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets handler address (00000060H) for debug trap to PC and transfers control.
Figure 16-13 shows the debug trap processing format.
Figure 16-13. Debug Trap Processing Format
DBTRAP instruction
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
1
1
1
00000060H
Exception processing
CPU processing
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(2) Restoration
Restoration from a debug trap is executed with the DBRET instruction.
With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the
restored PC.
<1> The restored PC and PSW are read from DBPC and DBPSW.
<2> Control is transferred to the fetched address of the restored PC and PSW.
Caution DBPC and DBPSW can be accessed only during the interval between the execution of the
DBTRAP instruction and the DBRET instruction.
Figure 16-14 shows the processing format for restoration from a debug trap.
Figure 16-14. Processing Format of Restoration from Debug Trap
DBRET instruction
PC
PSW
DBPC
DBPSW
Jump to address of restored PC
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16.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP14)
16.6.1 Noise elimination
(1) Eliminating noise on NMI pin
The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the
NMI pin is not detected as an edge unless it is maintained for a specific time or longer. Therefore, an edge is
detected after specific time.
The NMI pin can be used to release the STOP mode. In the STOP mode, noise is not eliminated by using the
system clock because the internal system clock is stopped.
(2) Eliminating noise on INTP0 to INTP14 pins
The INTP0 to INTP14 pins have an internal noise elimination circuit that uses analog delay. Therefore, the
input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer.
Therefore, an edge is detected after specific time.
16.6.2 Edge detection
The valid edge of each of the NMI and INTP0 to INTP14 pins can be selected from the following four.
Rising edge
Falling edge
Both rising and falling edges
No edge detected
The edge of the NMI pin is not detected after reset. Therefore, the interrupt request signal is not acknowledged
unless a valid edge is enabled by using the INTF0 and INTR0 register (the NMI pin functions as a normal port pin).
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(1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0)
The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the
NMI pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF0n and INTR0n bits to 00,
and then set the port mode.
0
INTF0
INTF06
INTP3
INTF05
INTF04
INTF03
INTF02
0
0
After reset: 00H R/W Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H
0
INTR0
INTR06
INTR05
INTR04
INTR03
INTR02
0
0
INTP2
INTP1
INTP0
NMI
INTP3
INTP2
INTP1
INTP0
NMI
Remark For the valid edge specification combinations, see Table 16-3.
Table 16-3. Valid Edge Specification
INTF0n
INTR0n
Valid Edge Specification (n = 2 to 6)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1
1
Both rising and falling edges
Caution Be sure to clear the INTF0n and INTR0n bits to 00 if the corresponding pin is not used as the
NMI or INTP0 to INTP3 pins.
Remark n = 2:
Control of NMI pin
n = 3 to 6: Control of INTP0 to INTP3 pins
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(2) External interrupt rising, falling edge specification register 1 (INTR1, INTF1)
The INTR1 and INTF1 registers are 8-bit registers that specify detection of the rising and falling edges of the
INTP9 and INTP10 pins.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF1n and INTR1n bits to 00,
and then set the port mode.
INTR1
After reset: 00H R/W Address: INTR1 FFFFFC22H, INTF1 FFFFFC02H
0
0
0
0
0
0
INTR11
INTR10
INTF1
0
0
0
0
0
0
INTF11
INTF10
INTP10
INTP10
INTP9
INTP9
Remark For the valid edge specification combinations, see Table 16-4.
Table 16-4. Valid Edge Specification
INTF1n
INTR1n
Valid Edge Specification (n = 0, 1)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1
1
Both rising and falling edges
Caution Be sure to clear the INTF1n and INTR1n bits to 00 if the corresponding pin is not used as the
INTP9 and INTP10 pins.
Remark n = 0: Control of INTP9 pin
n = 1: Control of INTP10 pin
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(3) External interrupt rising, falling edge specification register 3 (INTR3, INTF3)
The INTR3 and INTF3 registers are 8-bit registers that specify detection of the rising and falling edges of the
INTP7 and INTP8 pins.
These registers can be read or written in 16-bit units.
However, when the higher 8 bits of INTF3 register are used as the INTF3H register and the lower 8 bits as the
INTF3L register, they can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF3n and INTR3n bits to 00,
and then set the port mode.
INTF3 (INTF3H
Note
)
After reset: 0000H R/W Address: INTF3 FFFFFC06H,
INTF3L FFFFFC06H, INTF3H FFFFFC07H
0
0
0
0
0
0
INTF39
0
(INTF3L)
0
0
0
0
0
0
INTF31
0
INTP8
INTP7
INTR3 (INTR3H
Note
)
After reset: 0000H R/W Address: INTR3 FFFFFC26H,
INTR3L FFFFFC26H, INTR3H FFFFFC27H
0
0
0
0
0
0
INTR39
0
(INTR3L)
0
0
0
0
0
0
INTR31
0
INTP8
INTP7
Caution When bits 8 to 15 of the INTF3 and INTR3 registers are read or written in 8-bit or 1-bit units,
specify them as bits 0 to 7 of the INTF3H and INTR3H registers.
Remark For the valid edge specification combinations, see Table 16-5.
Table 16-5. Valid Edge Specification
INTF3n
INTR3n
Valid Edge Specification (n = 1, 9)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1
1
Both rising and falling edges
Caution Be sure to clear the INTF3n and INTR3n bits to 00 if the corresponding pin is not used as the
INTP7 and INTP8 pins.
Remark n = 1: Control of INTP7 pin
n = 9: Control of INTP8 pin
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(4) External interrupt rising, falling edge specification register 6L (INTR6L, INTF6L)
The INTR6L and INTF6L registers are 8-bit registers that specify detection of the rising and falling edges of the
INTP11 to INTP13 pins.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF6n and INTR6n bits to 00,
and then set the port mode.
INTR6L
After reset: 00H R/W Address: INTR6 FFFFFC0CH, INTF6 FFFFFC2CH
0
0
0
0
0
INTR62
INTR61
INTR60
INTF6L
0
0
0
0
0
INTF62
INTT61
INTF60
INTP12
INTP12
INTP13
INTP13
INTP11
INTP11
Remark For the valid edge specification combinations, see Table 16-6.
Table 16-6. Valid Edge Specification
INTF6n
INTR6n
Valid Edge Specification (n = 0 to 2)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1
1
Both rising and falling edges
Caution Be sure to clear the INTF6n and INTR6n bits to 00 if the corresponding pin is not used as the
NMI or INTP11 to INTP13 pins.
Remark n = 0: Control of INTP11 pin
n = 1: Control of INTP12 pin
n = 2: Control of INTP13 pin
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(5) External interrupt falling, rising edge specification register 8 (INTF8, INTR8)
The INTF8 and INTR8 registers are 8-bit registers that specify detection of the falling and rising edges of the
external interrupt pin (INTP14).
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Cautions 1. When the function is changed from the external interrupt function (alternate function) to
the port function, an edge may be detected. Therefore, clear the INTF80 and INTR80 bits
to 00, and then set the port mode.
2. The INTP14 pin and RXDA3 pin are alternate-function pins. When using the pin as the
RXDA3 pin, disable edge detection for the INTP14 alternate-function pin (clear the
INTF8.INTF80 bit and the INTR8.INTR80 bit to 0). When using the pin as the INTP14 pin,
stop UARTA3 reception (clear the UA3CTL0.UA3RXE bit to 0).
INTF8
After reset: 00H R/W Address: INTF8 FFFFFC10H, INTR8 FFFFFC30H
0
0
0
0
0
0
0
INTF80
INTR8
0
0
0
0
0
0
0
INTR80
INTP14
INTP14
Remark For the valid edge specification combinations, see Table 16-7.
Table 16-7. Valid Edge Specification
INTF80
INTR80
Valid Edge Specification
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1
1
Both rising and falling edges
Caution Be sure to clear the INTF80 and INTR80 bits to 00 if the corresponding pin is not used as
INTP14 pin.
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(6) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H)
The INTF9H and INTR9H registers are 8-bit registers that specify detection of the falling and rising edges of
the external interrupt pins (INTP4 to INTP6).
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the
port function, an edge may be detected. Therefore, clear the INTF9n and INTR9n bits to 0,
and then set the port mode.
INTF9H
After reset: 00H R/W Address: INTF9H FFFFFC13H, INTR9H FFFFFC33H
INTF915 INTF914
INTF913
0
0
0
0
0
8
9
10
11
12
13
14
15
INTR9H
INTR915 INTR914 INTR913
0
0
0
0
0
8
9
10
11
12
13
14
15
INTP6
INTP5
INTP4
INTP6
INTP5
INTP4
Remark For the valid edge specification combinations, see Table 16-8.
Table 16-8. Valid Edge Specification
INTF9n
INTR9n
Valid Edge Specification (n = 13 to 15)
0
0
No edge detected
0 1
Rising
edge
1 0
Falling
edge
1
1
Both rising and falling edges
Caution Be sure to clear the INTF9n and INTR9n bits to 00 if the corresponding pin is not used as
INTP4 to INTP6 pins.
Remark n = 13 to 15: Control of INTP4 to INTP6 pins
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(7) Noise elimination control register (NFC)
Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using
the NFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
XX
/64, f
XX
/128, f
XX
/256, f
XX
/512, f
XX
/1,024, and f
XT
. Sampling is performed three times.
When digital noise elimination is selected, if the clock that performs sampling in the standby mode is stopped,
then the INTP3 interrupt request signal cannot be used for releasing the standby mode. When f
XT
is used as
the sampling clock, the INTP3 interrupt request signal can be used for releasing either the subclock operating
mode or the IDLE1/IDLE2/STOP/sub-IDLE mode.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock
the number of times set by the NFSTS bit is required until
the digital noise eliminator is initialized after the sampling clock has been changed. If the
valid edge of INTP3 is input after the sampling clock has been changed and before the time
of the sampling clock
the number of times set by the NFSTS bit passes, therefore, the
interrupt request signal may be generated. Therefore, note the following points when using
the interrupt and DMA functions.
When using the interrupt function, after the sampling clock the number of times set by
the NFSTS bit have elapsed, enable interrupts after the interrupt request flag (PIC3.PIF3
bit) has been cleared.
When using the DMA function (started by INTP3), enable DMA after the sampling clock
the number of times set by the NFSTS bit have elapsed.
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NFEN
NFC
NFSTS
0
0
0
NFC2
NFC1
NFC0
f
XX
/64
f
XX
/128
f
XX
/256
f
XX
/512
f
XX
/1,024
f
XT
(subclock)
NFC2
0
0
0
0
1
1
Digital sampling clock
Setting prohibited
NFC1
0
0
1
1
0
0
NFC0
0
1
0
1
0
1
After reset: 00H R/W Address: FFFFF318H
Analog noise elimination (60 ns (TYP.))
Digital noise elimination
NFEN
0
1
Settings of INTP3 pin noise elimination
Number of times of sampling
3 times
Number of times of sampling
twice
NFSTS
0
1
Setting of number of times of sampling of digital noise elimination
Other than above
Remarks 1. Since sampling is performed three times, the reliably eliminated noise width is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is
generated if noise synchronized with the sampling clock is input.
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16.7 Interrupt Acknowledge Time of CPU
Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt
request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt.
In IDLE1/IDLE2/STOP mode
When the external bus is accessed
When interrupt request non-sampling instructions are successively executed (see 16.8 Periods in Which
Interrupts Are Not Acknowledged by CPU.)
When the interrupt control register is accessed
Figure 16-15. Pipeline Operation at Interrupt Request Signal Acknowledgment (Outline)
(1) Minimum interrupt response time
IF
ID
EX
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (first instruction of interrupt servicing routine)
Interrupt request
IF
ID
EX MEM WB
IFX
IDX
INT1 INT2 INT3 INT4
4 system clocks
(2) Maximum interrupt response time
IF
ID
EX
Internal clock
Instruction 1
Instruction 2
Interrupt acknowledgment operation
Instruction (first instruction of interrupt servicing routine)
Interrupt request
IF
ID
EX MEM MEM MEM WB
IFX
IDX
INT1 INT2 INT3 INT3 INT3 INT4
6 system clocks
Remark INT1 to INT4: Interrupt acknowledgment processing
IFX:
Invalid instruction fetch
IDX:
Invalid instruction decode
Interrupt acknowledge time (internal system clock)
Internal interrupt
External interrupt
Condition
Minimum
4
4 +
Analog delay time
Maximum
6
6 +
Analog delay time
The following cases are exceptions.
In IDLE1/IDLE2/STOP mode
External bus access
Two or more interrupt request non-sample instructions are
executed in succession
Access to peripheral I/O register
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16.8 Periods in Which Interrupts Are Not Acknowledged by CPU
An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be
acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending).
The interrupt request non-sample instructions are as follows.
EI instruction
DI instruction
LDSR reg2, 0x5 instruction (for PSW)
The store instruction for the PRCMD register
The store, SET1, NOT1, or CLR1 instructions for the following registers.
Interrupt-related registers:
Interrupt control register (xxICn), interrupt mask registers 0 to 4 (IMR0 to IMR4)
In-service priority register (ISPR):
Command register (PRCMD):
Power save control register (PSC)
On-chip debug mode register (OCDM)
Peripheral emulation register 1 (PEMU1):
Remark xx: Identification name of each peripheral unit (see Table 16-2 Interrupt Control Registers
(xxICn))
n: Peripheral unit number (see Table 16-2 Interrupt Control Registers (xxICn)).
16.9 Cautions
The NMI pin alternately functions as the P02 pin. It functions as a normal port pin after reset. To enable the NMI
pin, validate the NMI pin with the PMC0 register. The initial setting of the NMI pin is "No edge detected". Select the
NMI pin valid edge using the INTF0 and INTR0 registers.
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CHAPTER 17 KEY INTERRUPT FUNCTION
17.1 Function
A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0
to KR7) by setting the KRM register.
Table 17-1. Assignment of Key Return Detection Pins
Flag Pin
Description
KRM0
Controls KR0 signal in 1-bit units
KRM1
Controls KR1 signal in 1-bit units
KRM2
Controls KR2 signal in 1-bit units
KRM3
Controls KR3 signal in 1-bit units
KRM4
Controls KR4 signal in 1-bit units
KRM5
Controls KR5 signal in 1-bit units
KRM6
Controls KR6 signal in 1-bit units
KRM7
Controls KR7 signal in 1-bit units
Figure 17-1. Key Return Block Diagram
INTKR
Key return mode register (KRM)
KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
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17.2 Register
(1) Key return mode register (KRM)
The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
KRM7
Does not detect key return signal
Detects key return signal
KRMn
0
1
Control of key return mode
KRM
KRM6
KRM5
KRM4
KRM3
KRM2
KRM1
KRM0
After reset: 00H R/W Address: FFFFF300H
Caution Rewrite the KRM register after once clearing the KRM register to 00H.
Remark For the alternate-function pin settings, see Table 4-25 Using Port Pin as Alternate
Function Pin.
17.3 Cautions
(1) If a low level is input to any of the KR0 to KR7 pins, the INTKR signal is not generated even if the falling edge
of another pin is input.
(2) The RXDA1 and KR7 pins must not be used at the same time. To use the RXDA1 pin, do not use the KR7 pin.
To use the KR7 pin, do not use the RXDA1 pin (it is recommended to set the PFC91 bit to 1 and clear
PFCE91 bit to 0).
(3) If the KRM register is changed, an interrupt request signal (INTKR) may be generated. To prevent this,
change the KRM register after disabling interrupts (DI) or masking, then clear the interrupt request flag
(KRIC.KRIF bit) to 0, and enable interrupts (EI) or clear the mask.
(4) To use the key interrupt function, be sure to set the port pin to the key return pin and then enable the operation
with the KRM register. To switch from the key return pin to the port pin, disable the operation with the KRM
register and then set the port pin.
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CHAPTER 18 STANDBY FUNCTION
18.1 Overview
The power consumption of the system can be effectively reduced by using the standby modes in combination and
selecting the appropriate mode for the application. The available standby modes are listed in Table 18-1.
Table 18-1. Standby Modes
Mode Functional
Outline
HALT mode
Mode in which only the operating clock of the CPU is stopped
IDLE1 mode
Mode in which all the operations of the internal circuits except the oscillator, PLL
Note
, and flash
memory are stopped
IDLE2 mode
Mode in which all the internal operations of the chip except the oscillator are stopped
STOP mode
Mode in which all the internal operations of the chip except the subclock oscillator are stopped
Subclock operation mode
Mode in which the subclock is used as the internal system clock
Sub-IDLE mode
Mode in which all the internal operations of the chip except the oscillator are stopped, in the
subclock operation mode
Note The PLL holds the previous operating status.
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Figure 18-1. Status Transition
Reset
Subclock operation mode
(fx operates, PLL operates)
Subclock operation mode
(fx stops, PLL stops)
Sub-IDLE mode
(fx operates, PLL operates)
Sub-IDLE mode
(fx stops, PLL stops)
STOP mode
(fx stops, PLL stops)
IDLE2 mode
(fx operates, PLL stops)
IDLE1 mode
(fx operates, PLL operates)
IDLE1 mode
(fx operates, PLL stops)
HALT mode
(fx operates, PLL stops)
HALT mode
(fx operates, PLL operates)
Normal operation mode
Oscillation
stabilization wait
Clock through mode
(PLL operates)
Clock through mode
(PLL stops)
PLL mode
(PLL operates)
Internal oscillation
clock operation
WDT overflow
Oscillation
stabilization wait
Note
PLL lockup
time wait
Oscillation
stabilization wait
Note
Oscillation
stabilization wait
Note
Note If a WDT overflow occurs during an oscillation stabilization time, the CPU operates on the internal
oscillation clock.
Remark f
X
: Main clock oscillation frequency
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18.2 Registers
(1) Power save control register (PSC)
The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to
specify the STOP mode. This register is a special register that can be written only by the special sequence
combinations (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
PSC
NMI1M
NMI0M
INTM
0
0
STP
0
7
6
5
4
3
2
1
0
After reset: 00H R/W Address: FFFFF1FEH
Standby mode release by INTWDT2 signal enabled
Standby mode release by INTWDT2 signal disabled
NMI1M
0
1
Standby mode release control upon occurrence of INTWDT2 signal
Standby mode release by NMI pin input enabled
Standby mode release by NMI pin input disabled
NMI0M
0
1
Standby mode release control by NMI pin input
Standby mode release by maskable interrupt request signal enabled
Standby mode release by maskable interrupt request signal disabled
INTM
0
1
Standby mode release control via maskable interrupt request signal
Normal mode
Standby mode
STP
0
1
Standby mode
Note
setting
Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode
Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1
and PSMR.PSM0 bits and then set the STP bit.
2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is
released.
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(2) Power save mode register (PSMR)
The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock
operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
0
IDLE1, sub-IDLE modes
STOP, sub-IDLE modes
IDLE2, sub-IDLE modes
STOP mode
PSM1
0
0
1
1
Specification of operation in software standby mode
PSMR
0
0
0
0
0
PSM1
PSM0
After reset: 00H R/W Address: FFFFF820H
PSM0
0
1
0
1
Cautions 1. Be sure to clear bits 2 to 7 to "0".
2. The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1.
Remark IDLE1:
In this mode, all operations except the oscillator operation and some other circuits (flash
memory and PLL) are stopped.
After the IDLE1 mode is released, the normal operation mode is restored without needing
to secure the oscillation stabilization time, like the HALT mode.
IDLE2:
In this mode, all operations except the oscillator operation are stopped.
After the IDLE2 mode is released, the normal operation mode is restored following the
lapse of the setup time specified by the OSTS register (flash memory and PLL).
STOP:
In this mode, all operations except the subclock oscillator operation are stopped.
After the STOP mode is released, the normal operation mode is restored following the
lapse of the oscillation stabilization time specified by the OSTS register.
Sub-IDLE: In this mode, all other operations are halted except for the oscillator. After the IDLE mode
has been released by the interrupt request signal, the subclock operation mode will be
restored after 12 cycles of the subclock have been secured.
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(3) Oscillation stabilization time select register (OSTS)
The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip
flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
The OSTS register can be read or written 8-bit units.
Reset sets this register to 06H.
0
OSTS
0
0
0
0
OSTS2
OSTS1
OSTS0
OSTS2
0
0
0
0
1
1
1
1
Selection of oscillation stabilization time/setup time
Note
OSTS1
0
0
1
1
0
0
1
1
OSTS0
0
1
0
1
0
1
0
1
After reset: 06H R/W Address: FFFFF6C0H
2
10
/f
X
2
11
/f
X
2
12
/f
X
2
13
/f
X
2
14
/f
X
2
15
/f
X
2
16
/f
X
4 MHz
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
8.192 ms
16.38 ms
5 MHz
0.205 ms
0.410 ms
0.819 ms
1.638 ms
3.277 ms
6.554 ms
13.107 ms
f
X
Setting prohibited
Note The oscillation stabilization time and setup time are required when the STOP mode and
IDLE2 mode are released, respectively.
Cautions 1. The wait time following release of the STOP mode does not include the time
until the clock oscillation starts ("a" in the figure below) following release of
the STOP mode, regardless of whether the STOP mode is released by reset or
the occurrence of an interrupt request signal.
a
STOP mode release
Voltage waveform of X1 pin
V
SS
2. Be sure to clear bits 3 to 7 to "0".
3. The oscillation stabilization time following reset release is 2
16
/f
X
(because the
initial value of the OSTS register = 06H).
Remark
f
X
= Main clock oscillation frequency
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18.3 HALT Mode
18.3.1 Setting and operation status
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply
to the other on-chip peripheral functions continues.
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was
set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
Table 18-3 shows the operating status in the HALT mode.
The average current consumption of the system can be reduced by using the HALT mode in combination with the
normal operation mode for intermittent operation.
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
2. If the HALT instruction is executed while an unmasked interrupt request signal is being held
pending, the status shifts to HALT mode, but the HALT mode is then released immediately by
the pending interrupt request.
18.3.2 Releasing HALT mode
The HALT mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP14 pin input), unmasked internal interrupt request signal
from a peripheral function operable in the HALT mode, or reset signal (reset by RESET pin input, WDT2RES signal,
power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)).
After the HALT mode has been released, the normal operation mode is restored.
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The HALT mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the HALT mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, the HALT mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced
is issued (including a non-maskable interrupt request signal), the HALT mode is released and that
interrupt request signal is acknowledged.
Table 18-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Release Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler address
or the next instruction is executed.
The next instruction is executed.
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(2) Releasing HALT mode by reset
The same operation as the normal reset operation is performed.
Table 18-3. Operating Status in HALT Mode
Setting of HALT Mode
Operating Status
Item
When Subclock Is Not Used
When Subclock Is Used
Main clock oscillator
Oscillation enabled
Subclock oscillator
-
Oscillation enabled
Internal oscillator
Oscillation enabled
PLL Operable
CPU Stops
operation
DMA Operable
Interrupt controller
Operable
Timer P (TMP0 to TMP3)
Operable
Timer Q (TMQ0 to TMQ2)
Operable
Timer M (TMM0)
Operable when a clock other than f
XT
is
selected as the count clock
Operable
Watch timer
Operable when f
X
(divided BRG) is
selected as the count clock
Operable
Watchdog timer 2
Operable
CSIB0 to CSIB2
Operable
Serial interface
UARTA0 to UARTA3
Operable
A/D converter
Operable
Key interrupt function (KR)
Operable
External bus interface
See 2.2 Pin States.
Port function
Retains status before HALT mode was set
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the HALT mode was set.
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18.4 IDLE1 Mode
18.4.1 Setting and operation status
The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1
in the normal operation mode.
In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and
other on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was set are
retained. The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions
that can operate with the subclock or an external clock continue operating.
Table 18-5 shows the operating status in the IDLE1 mode.
The IDLE1 mode can reduce the power consumption more than the HALT mode because it stops the operation of
the on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be
restored without waiting for the oscillation stabilization time after the IDLE1 mode has been released, in the same
manner as when the HALT mode is released.
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register
to set the IDLE1 mode.
2. If the IDLE1 mode is set while an unmasked interrupt request signal is being held pending,
the IDLE1 mode is released immediately by the pending interrupt request.
18.4.2 Releasing IDLE1 mode
The IDLE1 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP14 pin input), unmasked internal interrupt request signal
from a peripheral function operable in the IDLE1 mode, or reset signal (reset by RESET pin input, WDT2RES signal,
power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)).
After the IDLE1 mode has been released, the normal operation mode is restored.
(1) Releasing IDLE1 mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The IDLE1 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE1 mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is processed as follows.
Cautions 1. An interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and IDLE1 mode is not released.
2. If eliminating digital noise is selected by using the NFC register and if the sampling clock
is selected from f
XX
/64, f
XX
/128, f
XX
/256, f
XX
/512, and f
XX
/1024, the IDLE1 mode cannot be
released by the interrupt request signal of the INTP3 pin. For details, see 16.6.2 (7) Noise
elimination control register (NFC).
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, the IDLE1 mode is released, but that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the IDLE1 mode is released and
that interrupt request signal is acknowledged.
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Table 18-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal
Release Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler address
or the next instruction is executed.
The next instruction is executed.
(2) Releasing IDLE1 mode by reset
The same operation as the normal reset operation is performed.
Table 18-5. Operating Status in IDLE1 Mode
Setting of IDLE1 Mode
Operating Status
Item
When Subclock Is Not Used
When Subclock Is Used
Main clock oscillator
Oscillation enabled
Subclock oscillator
-
Oscillation enabled
Internal oscillator
Oscillation enabled
PLL Operable
CPU Stops
operation
DMA Stops
operation
Interrupt controller
Stops operation (but standby mode release is possible)
Timer P (TMP0 to TMP3)
Stops operation
Timer Q (TMQ0 to TMQ2)
Stops operation
Timer M (TMM0)
Operable when f
R
/8 is selected as the
count clock
Operable when f
R
/8 or f
XT
is selected as
the count clock
Watch timer
Operable when f
X
(divided BRG) is
selected as the count clock
Operable
Watchdog timer 2
Operable
CSIB0 to CSIB2
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 2)
Serial interface
UARTA0 to UARTA3
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
A/D converter
Holds operation (conversion result held)
Note
Key interrupt function (KR)
Operable
External bus interface
See 2.2 Pin States.
Port function
Retains status before IDLE1 mode was set
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the IDLE1 mode was set.
Note To realize low power consumption, stop the A/D converter before shifting to the IDLE1 mode.
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18.5 IDLE2 Mode
18.5.1 Setting and operation status
The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in
the normal operation mode.
In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and
other on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are
retained. The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral
functions that can operate with the subclock or an external clock continue operating.
Table 18-7 shows the operating status in the IDLE2 mode.
The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of
the on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped,
a setup time for the PLL and flash memory is required when IDLE2 mode is released.
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register
to set the IDLE2 mode.
2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending,
the IDLE2 mode is released immediately by the pending interrupt request.
18.5.2 Releasing IDLE2 mode
The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP14 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES
signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the
operating status it was in before the IDLE2 mode was set.
After the IDLE2 mode has been released, the normal operation mode is restored.
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is processed as follows.
Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released.
2. If eliminating digital noise is selected by using the NFC register and if the sampling clock
is selected from f
XX
/64, f
XX
/128, f
XX
/256, f
XX
/512, and f
XX
/1024, the IDLE2 mode cannot be
released by the interrupt request signal of the INTP3 pin. For details, see 16.6.2 (7) Noise
elimination control register (NFC).
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, the IDLE2 mode is released, but that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being
serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and
that interrupt request signal is acknowledged.
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Table 18-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal
Release Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address after securing the prescribed setup time.
Maskable interrupt request signal
Execution branches to the handler address
or the next instruction is executed after
securing the prescribed setup time.
The next instruction is executed after
securing the prescribed setup time.
(2) Releasing IDLE2 mode by reset
The same operation as the normal reset operation is performed.
Table 18-7. Operating Status in IDLE2 Mode
Setting of IDLE2 Mode
Operating Status
Item
When Subclock Is Not Used
When Subclock Is Used
Main clock oscillator
Oscillation enabled
Subclock oscillator
-
Oscillation enabled
Internal oscillator
Oscillation enabled
PLL Stops
operation
CPU Stops
operation
DMA Stops
operation
Interrupt controller
Stops operation (but standby mode release is possible)
Timer P (TMP0 to TMP3)
Stops operation
Timer Q (TMQ0 to TMQ2)
Stops operation
Timer M (TMM0)
Operable when f
R
/8 is selected as the
count clock
Operable when f
R
/8 or f
XT
is selected as
the count clock
Watch timer
Operable when f
X
(divided BRG) is
selected as the count clock
Operable
Watchdog timer 2
Operable
CSIB0 to CSIB2
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 2)
Serial interface
UARTA0 to UARTA3
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
A/D converter
Holds operation (conversion result held)
Note
Key interrupt function (KR)
Operable
External bus interface
See 2.2 Pin States.
Port function
Retains status before IDLE2 mode was set
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the IDLE2 mode was set.
Note To realize low power consumption, stop the A/D converter before shifting to the IDLE2 mode.
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18.5.3 Securing setup time when releasing IDLE2 mode
Secure the setup time for the ROM (flash memory) after releasing the IDLE2 mode because the operation of the
blocks other than the main clock oscillator stops after the IDLE2 mode is set.
(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
Secure the specified setup time by setting the OSTS register.
When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS
register setting. When it overflows, the normal operation mode is restored.
Oscillated waveform
ROM circuit stopped
Setup time count
Main clock
IDLE mode status
Interrupt request
(2) Release by reset (RESET pin input, WDT2RES generation)
This operation is the same as that of a normal reset.
The oscillation stabilization time is the initial value of the OSTS register, 2
16
/f
X
.
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18.6 STOP Mode
18.6.1 Setting and operation status
The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit
to 1 in the normal operation mode.
In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops. Clock supply to
the CPU and the on-chip peripheral functions is stopped.
As a result, program execution stops, and the contents of the internal RAM before the STOP mode was set are
retained. The on-chip peripheral functions that operate with the clock oscillated by the subclock oscillator or an
external clock continue operating.
Table 18-9 shows the operating status in the STOP mode.
Because the STOP mode stops operation of the main clock oscillator, it reduces the power consumption to a level
lower than the IDLE2 mode. If the subclock oscillator, internal oscillator, and external clock are not used, the power
consumption can be minimized with only leakage current flowing.
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register
to set the STOP mode.
2. If the STOP mode is set while an unmasked interrupt request signal is being held pending, the
STOP mode is released immediately by the pending interrupt request.
18.6.2 Releasing STOP mode
The STOP mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP14 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the STOP mode, or reset signal (reset by RESET pin input, WDT2RES
signal, power-on clear circuit (POC), or low-voltage detector (LVI)).
After the STOP mode has been released, the normal operation mode is restored after the oscillation stabilization
time has been secured.
Cautions 1. The interrupt request that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and PSC.INTM
bits to 1 becomes invalid and STOP mode is not released.
2. If eliminating digital noise is selected by using the NFC register and if the sampling clock is
selected from f
XX
/64, f
XX
/128, f
XX
/256, f
XX
/512, and f
XX
/1024, the STOP mode cannot be released
by the interrupt request signal of the INTP3 pin. For details, see 16.6.2 (7) Noise elimination
control register (NFC).
(1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The STOP mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt
request signal, regardless of the priority of the interrupt request signal. If the STOP mode is set in an interrupt
servicing routine, however, an interrupt request signal that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, the STOP mode is released, but that interrupt request signal is not acknowledged. The interrupt
request signal itself is retained.
(b)
If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced
is issued (including a non-maskable interrupt request signal), the STOP mode is released and that
interrupt request signal is acknowledged.
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Table 18-8. Operation After Releasing STOP Mode by Interrupt Request Signal
Release Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address after securing the oscillation stabilization time.
Maskable interrupt request signal
Execution branches to the handler address
or the next instruction is executed after
securing the oscillation stabilization time.
The next instruction is executed after
securing the oscillation stabilization time.
(2)
Releasing STOP mode by reset
The same operation as the normal reset operation is performed.
Table 18-9. Operating Status in STOP Mode
Setting of STOP Mode
Operating Status
Item
When Subclock Is Not Used
When Subclock Is Used
Main clock oscillator
Stops oscillation
Subclock oscillator
-
Oscillation enabled
Internal oscillator
Oscillation enabled
PLL Stops
operation
CPU Stops
operation
DMA Stops
operation
Interrupt controller
Stops operation (but standby mode release is possible)
Timer P (TMP0 to TMP3)
Stops operation
Timer Q (TMQ0 to TMQ2)
Stops operation
Timer M (TMM0)
Operable when f
R
/8 is selected as the
count clock
Operable when f
R
/8 or f
XT
is selected as
the count clock
Watch timer
Stops operation
Operable when f
XT
is selected as the
count clock
Watchdog timer 2
Operable when f
R
is selected as the count clock
CSIB0 to CSIB2
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 2)
Serial interface
UARTA0 to UARTA3
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
A/D converter
Stops operation (conversion result undefined)
Notes 1, 2
Key interrupt function (KR)
Operable
External bus interface
See 2.2 Pin States.
Port function
Retains status before STOP mode was set
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
Notes 1. If the STOP mode is set while the A/D converter is operating, the A/D converter is automatically stopped
and starts operating again after the STOP mode is released. However, in that case, the A/D conversion
results after the STOP mode is released are invalid. All the A/D conversion results before the STOP
mode is set are invalid.
2.
Even if the STOP mode is set while the A/D converter is operating, the power consumption is reduced
equivalently to when the A/D converter is stopped before the STOP mode is set.
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18.6.3 Securing oscillation stabilization time when releasing STOP mode
Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the
operation of the main clock oscillator stops after STOP mode is set.
(1)
Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
Secure the oscillation stabilization time by setting the OSTS register.
When the releasing source is generated, the dedicated internal timer starts counting according to the OSTS
register setting. When it overflows, the normal operation mode is restored.
Oscillated waveform
ROM circuit stopped
Setup time count
Main clock
STOP status
Interrupt request
(2)
Release by reset
This operation is the same as that of a normal reset.
The oscillation stabilization time is the initial value of the OSTS register, 2
16
/f
X
.
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18.7 Subclock Operation Mode
18.7.1
Setting and operation status
The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode.
When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock.
Check whether the clock has been switched by using the PCC.CLS bit.
When the PCC.MCK bit is set to 1, the operation of the main clock oscillator is stopped. As a result, the system
operates only on the subclock.
In the subclock operation mode, the power consumption can be reduced to a level lower than in the normal
operation mode because the subclock is used as the internal system clock. In addition, the power consumption can
be further reduced to the level of the STOP mode by stopping the operation of the main clock oscillator.
Table 18-10 shows the operating status in subclock operation mode.
Cautions 1. When manipulating the CK3 bit, do not change the set values of the PCC.CK2 to PCC.CK0 bits
(using a bit manipulation instruction to manipulate the bit is recommended). For details of
the PCC register, see 6.3 (1) Processor clock control register (PCC).
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the conditions
are satisfied and set the subclock operation mode.
Internal system clock (f
CLK
) > Subclock (f
XT
= 32.768 kHz)
4
Remark Internal system clock (f
CLK
): Clock generated from main clock (f
XX
) in accordance with the settings of the
CK2 to CK0 bits
18.7.2
Releasing subclock operation mode
The subclock operation mode is released by a reset signal (reset by RESET pin input, WDT2RES signal, power-on
clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)) when the CK3 bit is cleared to 0.
If the main clock is stopped (MCK bit = 1), set the MCK bit to 1, secure the oscillation stabilization time of the main
clock by software, and clear the CK3 bit to 0.
The normal operation mode is restored when the subclock operation mode is released.
Caution When manipulating the CK3 bit, do not change the set values of the CK2 to CK0 bits (using a bit
manipulation instruction to manipulate the bit is recommended).
For details of the PCC register, see 6.3 (1) Processor clock control register (PCC).
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Table 18-10. Operating Status in Subclock Operation Mode
Operating Status
Setting of Subclock Operation Mode
Item
When Main Clock Is Oscillating
When Main Clock Is Stopped
Subclock oscillator
Oscillation enabled
Internal oscillator
Oscillation enabled
PLL Operable
Stops
operation
Note
CPU Operable
DMA Operable
Interrupt controller
Operable
Timer P (TMP0 to TMP3)
Operable
Stops operation
Timer Q (TMQ0 to TMQ2)
Operable
Stops operation
Timer M (TMM0)
Operable
Operable when f
R
/8 or f
XT
is selected as
the count clock
Watch timer
Operable
Operable when f
XT
is selected as the
count clock
Watchdog timer 2
Operable
Operable when f
R
is selected as the
count clock
CSIB0 to CSIB2
Operable
Operable when the SCKBn input clock is
selected as the count clock (n = 0 to 2)
Serial interface
UARTA0 to UARTA3
Operable
Stops operation (but UARTA0 is
operable when the ASCKA0 input clock
is selected)
A/D converter
Operable
Stops operation
Key interrupt function (KR)
Operable
External bus interface
See 2.2 Pin States.
Port function
Settable
Internal data
Settable
Note Be sure to stop the PLL (PLLCTL.PLLON = 0) before stopping the main clock.
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, accessing a
register in which a wait occurs is disabled. If a wait is generated, it can be released only by reset
(see 3.4.8 (2)).
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18.8 Sub-IDLE Mode
18.8.1 Setting and operation status
The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP
bit to 1 in the subclock operation mode.
In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on-
chip peripheral functions is stopped.
As a result, program execution stops and the contents of the internal RAM before the sub-IDLE mode was set are
retained. The CPU and the other on-chip peripheral functions are stopped. However, the on-chip peripheral functions
that can operate with the subclock or an external clock continue operating.
Because the sub-IDLE mode stops operation of the CPU, flash memory, and other on-chip peripheral functions, it
can reduce the power consumption more than the subclock operation mode. If the sub-IDLE mode is set after the
main clock has been stopped, the current consumption can be reduced to a level as low as that in the STOP mode.
Table 18-12 shows the operating status in the sub-IDLE mode.
Cautions 1. Following the store instruction to set the PSC register to the sub-IDLE mode, insert five or
more NOP instructions.
2. If the sub-IDLE mode is set while an unmasked interrupt request signal is being held pending,
the sub-IDLE mode is then released immediately by the pending interrupt request.
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18.8.2 Releasing sub-IDLE mode
The sub-IDLE mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),
unmasked external interrupt request signal (INTP0 to INTP14 pin input), unmasked internal interrupt request signal
from the peripheral functions operable in the sub-IDLE mode, or reset signal (reset by RESET pin input, WDT2RES
signal, power-on clear circuit (POC), low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the
operating status it was in before the sub-IDLE mode was set.
When the sub-IDLE mode is released by an interrupt request signal, the subclock operation mode is set.
(1) Releasing sub-IDLE mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The sub-IDLE mode is released by a non-maskable interrupt request signal or an unmasked maskable
interrupt request signal, regardless of the priority of the interrupt request signal.
If the sub-IDLE mode is set in an interrupt servicing routine, however, an interrupt request signal that is issued
later is serviced as follows.
Cautions 1. The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and
PSC.INTM bits to 1 becomes invalid and sub-IDLE mode is not released.
2. When the sub-IDLE mode is released, 12 cycles of the subclock (about 366
s) elapse
from when the interrupt request signal that releases the sub-IDLE mode is generated to
when the mode is released.
3. If eliminating digital noise is selected by using the NFC register and if the sampling clock
is selected from f
XX
/64, f
XX
/128, f
XX
/256, f
XX
/512, and f
XX
/1024, the sub-IDLE mode cannot be
released by the interrupt request signal of the INTP3 pin. For details, see 16.6.2 (7) Noise
elimination control register (NFC).
(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced
is issued, the sub-IDLE mode is released, but that interrupt request signal is not acknowledged. The
interrupt request signal itself is retained.
(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being serviced
is issued (including a non-maskable interrupt request signal), the sub-IDLE mode is released and that
interrupt request signal is acknowledged.
Table 18-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal
Release Source
Interrupt Enabled (EI) Status
Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler address
or the next instruction is executed.
The next instruction is executed.
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(2) Releasing sub-IDLE mode by reset
The same operation as the normal reset operation is performed.
Table 18-12. Operating Status in Sub-IDLE Mode
Setting of Sub-IDLE Mode
Operating Status
Item
When Main Clock Is Oscillating
When Main Clock Is Stopped
Subclock oscillator
Oscillation enabled
Internal oscillator
Oscillation enabled
PLL Operable
Stops
operation
Note 1
CPU Stops
operation
DMA Stops
operation
Interrupt controller
Stops operation (but standby mode release is possible)
Timer P (TMP0 to TMP3)
Stops operation
Timer Q (TMQ0 to TMQ2)
Stops operation
Timer M (TMM0)
Operable when f
R
/8 or f
XT
is selected as the count clock
Watch timer
Stops operation
Operable when f
XT
is selected as the
count clock
Watchdog timer 2
Operable when f
R
is selected as the count clock
CSIB0 to CSIB2
Operable when the SCKBn input clock is selected as the count clock (n = 0 to 2)
Serial interface
UARTA0 to UARTA3
Stops operation (but UARTA0 is operable when the ASCKA0 input clock is selected)
A/D converter
Holds operation (conversion result held)
Note 2
Key interrupt function (KR)
Operable
External bus interface
See 2.2 Pin States (same operation status as IDLE1, IDLE2 mode).
Port function
Retains status before sub-IDLE mode was set
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the sub-IDLE mode was set.
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
2. To realize low power consumption, stop the A/D converter before shifting to the sub-IDLE mode.
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CHAPTER 19 RESET FUNCTIONS
19.1 Overview
The following reset functions are available.
(1) Four kinds of reset sources
External reset input via the RESET pin
Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES)
System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage
System reset via the detecting clock monitor (CLM) oscillation stop
System reset via the power-on clear circuit
After a reset is released, the source of the reset can be confirmed with the reset source flag register (RESF).
(2) Emergency operation mode
If the WDT2 overflows during the main clock oscillation stabilization time inserted after reset, a main clock
oscillation anomaly is judged and the CPU starts operating on the internal oscillation clock.
Caution When the CPU is being operated with the internal oscillation clock, access to the register in
which a wait state is generated is prohibited. For the register in which a wait state is
generated, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
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19.2 Registers to Check Reset Source
The V850ES/HJ2 has four kinds of reset sources. After a reset has been released, the source of the reset that
occurred can be checked with the reset source flag register (RESF).
(1) Reset source flag register (RESF)
The RESF register is a special register that can be written only by a combination of specific sequences (see
3.4.7 Special registers).
The RESF register indicates the source from which a reset signal is generated.
This register is read or written in 8-bit or 1-bit units.
RESET pin input or POC reset sets this register to 00H. The default value differs if the source of reset is other
than the RESET pin signal.
0
WDT2RF
0
1
Not generated
Generated
RESF
0
0
WDT2RF
0
0
CLMRF
LVIRF
After reset: 00H
Note
R/W Address: FFFFF888H
Reset signal from WDT2
LVIRF
0
1
Not generated
Generated
Reset signal from LVI
CLMRF
0
1
Not generated
Generated
Reset signal from CLM
Note The value of the RESF register is cleared to 00H when a reset is executed via the RESET pin. When a
reset is executed by watchdog timer 2 (WDT2), low-voltage detector (LVI), or clock monitor (CLM), the
reset flags of this register (WDT2RF bit, CLMRF bit, and LVIRF bit) are set. However, other sources are
retained.
Caution Only "0" can be written to each bit of this register. If writing "0" conflicts with setting the flag
(occurrence of reset), setting the flag takes precedence.
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19.3 Operation
19.3.1 Reset operation via RESET pin
When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized.
When the level of the RESET pin is changed from low to high, the reset status is released.
Table 19-1. Hardware Status on RESET Pin Input
Item
During Reset
After Reset
Main clock oscillator (f
X
)
Oscillation stops
Oscillation starts
Crystal oscillation
Oscillation continues
Subclock oscillator (f
XT
)
RC oscillation
Oscillation stops
Oscillation starts
Internal oscillator
Oscillation stops
Oscillation starts
Peripheral clock (f
X
to f
X
/1,024)
Operation stops
Operation starts after securing
oscillation stabilization time
Internal system clock (f
CLK
),
CPU clock (f
CPU
)
Operation stops
Operation starts after securing
oscillation stabilization time (initialized
to f
XX
/8)
CPU
Initialized
Program execution starts after securing
oscillation stabilization time
Watchdog timer 2
Operation stops (initialized to 0)
Operation starts
Internal RAM
Undefined if power-on reset or CPU access and reset input conflict (data is
damaged).
Otherwise value immediately after reset input is retained
Note 1
.
I/O lines (ports/alternate-function pins)
High impedance
Note 2
On-chip peripheral I/O registers
Initialized to specified status, OCDM register is set (01H).
Other on-chip peripheral functions
Operation stops
Operation can be started after securing
oscillation stabilization time
Notes 1. The firmware of the V850ES/HJ2 uses a part of the internal RAM after the internal system reset status
has been released because it supports a boot swap function. Therefore, the contents of some RAM
areas (RAM size: 20 KB (3FFA000H to 3FFA095H), RAM size: 12 KB (3FFC000H to 3FFC095H)) are
not retained after power-on reset.
2. When the power is turned on, the following pin may output an undefined level temporarily even during
reset.
P53/KR3/TIQ00/TOQ00/DDO pin
Caution The OCDM register is initialized by the RESET pin input. Therefore, note with caution that, if a
high level is input to the P05/DRST pin after a reset release before the OCDM.OCDM0 bit is
cleared, the on-chip debug mode is entered. For details, see CHAPTER 4 PORT FUNCTIONS.
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Figure 19-1. Timing of Reset Operation by RESET Pin Input
Counting of oscillation
stabilization time
Initialized to f
XX
/8 operation
Oscillation stabilization timer overflows
Internal system
reset signal
Analog delay
(eliminated as noise)
Analog delay
Analog delay
(eliminated as noise)
RESET
f
X
f
CLK
Analog delay
Figure 19-2. Timing of Power-on Reset Operation
Oscillation stabilization
time count
Must be on-chip
regulator stabilization
time (1 ms (max.))
or longer.
Initialized to f
XX
/8 operation
Overflow of timer for oscillation stabilization
Internal system
reset signal
RESET
f
X
V
DD
f
CLK
Analog delay
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19.3.2 Reset operation by watchdog timer 2
When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow
(WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status.
Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay),
and the reset status is then automatically released.
The main clock oscillator is stopped during the reset period.
Table 19-2. Hardware Status During Watchdog Timer 2 Reset Operation
Item
During Reset
After Reset
Main clock oscillator (f
X
)
Oscillation stops
Oscillation starts
Crystal oscillation
Oscillation continues
Subclock oscillator (f
XT
)
RC oscillation
Oscillation stops
Oscillation starts
Internal oscillator
Oscillation stops
Oscillation starts
Peripheral clock (f
XX
to f
XX
/1,024)
Operation stops
Operation starts after securing
oscillation stabilization time
Internal system clock (f
XX
),
CPU clock (f
CPU
)
Operation stops
Operation starts after securing
oscillation stabilization time (initialized
to f
XX
/8)
CPU
Initialized
Program execution after securing
oscillation stabilization time
Watchdog timer 2
Operation stops (initialized to 0)
Operation starts
Internal RAM
Undefined if power-on reset or CPU access and reset input conflict (data is
damaged).
Otherwise value immediately after reset input is retained
Note
.
I/O lines (ports/alternate-function pins)
High impedance
On-chip peripheral I/O register
Initialized to specified status, OCDM register retains its value.
On-chip peripheral functions other than
above
Operation stops
Operation can be started after securing
oscillation stabilization time.
Note The firmware of the V850ES/HJ2 uses a part of the internal RAM after the internal system reset status has
been released because it supports a boot swap function. Therefore, the contents of some RAM areas (RAM
size: 20 KB (3FFA000H to 3FFA095H), RAM size: 12 KB (3FFC000H to 3FFC095H)) are not retained after
power-on reset.
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19.3.3 Reset operation by power-on clear circuit
The supply voltage and detection voltage are compared when the power-on clear operation is enabled. If the
supply voltage drops below the detection voltage (including when power is applied), the system is reset and each
hardware unit is initialized to the default status.
The reset status lasts since the voltage drop has been detected until the supply voltage rises above the detection
voltage, and then is automatically cleared. After the reset status is cleared, time to stabilize oscillation of the main
clock oscillator (default value of OSTS register: 2
16
/f
X
) elapses, and then the CPU starts program execution. For
details, see CHAPTER 21 POWER-ON CLEAR CIRCUIT.
19.3.4 Reset operation by low-voltage detector
When LVI operation is enabled and when the LVIM.LVIMD bit is set to "1", the supply voltage and detection voltage
are compared. If the supply voltage drops below the detection voltage, the system is reset and each hardware unit is
initialized to the default status.
The reset status lasts from detection of the voltage drop until the supply voltage rises above the detection voltage,
and then is automatically cleared. After the reset status is cleared, time to stabilize oscillation of the main clock
oscillator (default value of OSTS register: 2
16
/f
X
) elapses, and then the CPU starts program execution.
For details, see CHAPTER 22 LOW-VOLTAGE DETECTOR.
19.3.5 Reset operation by clock monitor
When the clock monitor operation is enabled, the main clock is monitored by using the sampling clock (internal
oscillator). If stoppage of the main clock is detected, the system is reset and each hardware unit is initialized to the
default status.
For details, see CHAPTER 20 CLOCK MONITOR.
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CHAPTER 20 CLOCK MONITOR
20.1 Functions
The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request
signal when oscillation of the main clock is stopped.
Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by
any means other than reset.
When a reset by the clock monitor occurs, the RESF.CLMRF bit is set. For details on the RESF register, see 19.2
Registers to Check Reset Source.
The clock monitor automatically stops under the following conditions.
During oscillation stabilization time after STOP mode is released
When the main clock is stopped (from when the PCC.MCK bit = 1 during subclock operation, until the PCC.CLS
bit = 0 during main clock operation)
When the sampling clock (internal oscillation clock) is stopped
When the CPU operates with the internal oscillation clock
20.2 Configuration
The clock monitor includes the following hardware.
Table 20-1. Configuration of Clock Monitor
Item Configuration
Control register
Clock monitor mode register (CLM)
Figure 20-1. Block Diagram of Clock Monitor
Main clock
Internal oscillation
clock
Internal reset signal
Enable/disable
CLME
Clock monitor mode
register (CLM)
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20.3 Register
The clock monitor is controlled by the clock monitor mode register (CLM).
(1) Clock monitor mode register (CLM)
The CLM register is a special register. This can be written only in a special combination of sequences (see
3.4.7 Special register).
This register is used to set the operation mode of the clock monitor.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After
reset:
00H
R/W
Address:
FFFFF870H
7 6 5 4 3 2 1 0
CLM
0 0 0 0 0 0 0
CLME
CLME
Clock monitor operation enable or disable
0
Disable clock monitor operation.
1
Enable clock monitor operation.
Cautions 1. Once the CLME bit has been set to 1, it cannot be cleared to 0 by any means other
than reset.
2. When a reset by the clock monitor occurs, the CLME bit is cleared to 0 and the
RESF.CLMRF bit is set to 1.
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20.4 Operation
This section explains the functions of the clock monitor. The start and stop conditions are as follows.
<Start condition>
Enabling operation by setting the CLM.CLME bit to 1
<Stop conditions>
While oscillation stabilization time is being counted after STOP mode is released
When the main clock is stopped (from when PCC.MCK bit = 1 during subclock operation to when PCC.CLS
bit = 0 during main clock operation)
When the sampling clock (internal oscillation clock) is stopped
When the CPU operates using the internal oscillation clock
Table 20-2. Operation Status of Clock Monitor
(When CLM.CLME Bit = 1, During Internal Oscillation Clock Operation)
CPU Operating Clock
Operation Mode
Status of Main Clock
Status of Internal
Oscillation Clock
Status of Clock
Monitor
HALT mode
Oscillates
Oscillates
Note 1
Operates
Note 2
IDLE1, IDLE2 modes
Oscillates
Oscillates
Note 1
Operates
Note 2
Main clock
STOP mode
Stops
Oscillates
Note 1
Stops
Subclock (MCK bit of
PCC register = 0)
Sub-IDLE mode
Oscillates
Oscillates
Note 1
Operates
Note 2
Subclock (MCK bit of
PCC register = 1)
Sub-IDLE mode
Stops
Oscillates
Note 1
Stops
Internal oscillation
clock
Stops
Oscillates
Note 1
Stops
During reset
Stops
Stops
Stops
Notes 1. The internal oscillator can be stopped by using the option byte function (see CHAPTER 25) to enable
the internal oscillator to stop, and setting the RCM.RSTOP bit to 1.
2. The clock monitor is stopped while the internal oscillator is stopped.
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(1) Operation when main clock oscillation is stopped (CLME bit = 1)
If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as
shown in Figure 20-2.
Figure 20-2. Reset Period Due to That Oscillation of Main Clock Is Stopped
Four internal oscillation clocks
Main clock
Internal oscillation
clock
Internal reset
signal
CLM.CLME bit
RESF.CLMRF bit
(2) Clock monitor status after RESET input
RESET input clears the CLM.CLME bit to 0 and stops the clock monitor operation. When CLME bit is set to 1
by software at the end of the oscillation stabilization time of the main clock, monitoring is started.
Figure 20-3. Clock Monitor Status After RESET Input
(CLM.CLME bit = 1 is set after RESET input and at the end of main clock oscillation stabilization time)
CPU operation
Clock monitor status
CLME
RESET
Internal oscillation
clock
Main clock
Reset
Oscillation
stabilization time
Normal
operation
Clock supply
stopped
Normal operation
Monitoring
Monitoring stopped
Monitoring
Set to 1 by software
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(3) Operation in STOP mode or after STOP mode is released
If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and
while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor
operation is automatically started.
Figure 20-4. Operation in STOP Mode or After STOP Mode Is Released
Clock monitor
status
During
monitor
Monitor stops
During monitor
CLME
Internal oscillation
clock
Main clock
CPU
operation
Normal
operation
STOP
Oscillation stabilization time
Normal operation
Oscillation stops
Oscillation stabilization time
(set by OSTS register)
(4) Operation when main clock is stopped (arbitrary)
During subclock operation (PCC.CLS bit = 1) or when the main clock is stopped by setting the PCC.MCK bit to
1, the monitor operation is stopped until the main clock operation is started (PCC.CLS bit = 0). The monitor
operation is automatically started when the main clock operation is started.
Figure 20-5. Operation When Main Clock Is Stopped (Arbitrary)
Clock monitor
status
During
monitor
Monitor stops
Monitor stops
During monitor
CLME
Internal oscillation
clock
Main clock
CPU
operation
Oscillation stops
Subclock operation
Main clock operation
Oscillation stabilization time
(set by OSTS register)
Oscillation stabilization
time count by software
PCC.MCK bit = 1
(5) Operation while CPU is operating on internal oscillation clock (CCLS.CCLSF bit = 1)
The monitor operation is not stopped when the CCLSF bit is 1, even if the CLME bit is set to 1.
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CHAPTER 21 POWER-ON CLEAR CIRCUIT
21.1 Function
Functions of the power-on-clear (POC) circuit are shown below.
Generates a reset signal upon power application.
Compares the supply voltage (V
DD
) and detection voltage (V
POC0
), and generates a reset signal when V
DD
< V
POC0
(detection voltage (V
POC0
): 3.7 V
0.2 V).
Remarks 1. The V850ES/HJ2 has plural internal hardware units that generate an internal reset signal. When the
system is reset by watchdog timer 2 (WDT2RES), low-voltage detector (LVI), or clock monitor (CLM),
a flag corresponding to the reset source is allocated to the reset source flag register (RESF).
The RESF register is not cleared when an internal reset signal is generated by WDT2RES, LVI, or
clock monitor, and its flag corresponding to the reset source is set to 1. For details of the RESF
register, see CHAPTER 19 RESET FUNCTIONS.
2. The time from power application to starting program execution is "Time from power application to
releasing reset + 16 ms" if the operating frequency of a resonator externally connected is 5 MHz.
However, it varies depending on the external cause (such as a status of supply voltage to the
microcontroller and the stabilization time of the resonator).
21.2 Configuration
The block diagram is shown below.
Figure 21-1. Block Diagram of Power-on-Clear Circuit
-
+
Detection
voltage source
(V
POC0
)
Internal reset
signal
V
DD
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21.3 Operation
When the supply voltage and detection voltage are compared and if the supply voltage is lower than the detection
voltage (including at power application), the system is reset and each hardware is returned to the specific status.
Figure 21-2. Timing of Reset Signal Generation by Power-on-Clear Circuit
Delay
Time
Reset period
(excluding oscillation stabilization time)
Reset period
(excluding oscillation stabilization time)
Reset period
(excluding oscillation stabilization time)
Internal reset signal
POC detection signal
Supply voltage
(V
DD
)
POC detection voltage
(V
POC0
)
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CHAPTER 22 LOW-VOLTAGE DETECTOR
22.1 Functions
The low-voltage detector (LVI) has the following functions.
Compares the supply voltage (V
DD
) and detection voltage (V
LVI
) and generates an interrupt request signal or
internal reset signal when V
DD
< V
LVI
.
The level of the supply voltage to be detected can be changed by software (in two steps).
An interrupt request signal or internal reset signal can be selected.
Can operate in STOP mode.
Operation can be stopped by software.
If the low-voltage detector is used to generate a reset signal, the RESF.LVIRF bit is set to 1 when the reset signal is
generated. For details of RESF register, see CHAPTER 19 RESET FUNCTIONS.
22.2 Configuration
The block diagram is shown below.
Figure 22-1. Block Diagram of Low-Voltage Detector
LVIS0
LVION
Detection voltage
source (V
LVI
)
V
DD
V
DD
INTLVI
Internal bus
N-ch
Low-voltage detection level
select register (LVIS)
Low-voltage detection
register (LVIM)
LVIMD
LVIF
Internal reset signal
Selector
Low-
voltage
detection
level
selector
-
+
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22.3 Registers
(1) Low-voltage detection register (LVIM)
The LVIM register is used to enable or disable low voltage detection, and to set the operation mode of the low-
voltage detector. The LVIM register is a special register. It can be written only by a combination of specific
sequences (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units. However, bit 0 is read-only.
After
reset:
00H
R/W
Address:
FFFFF890H
7 6 5 4 3 2 1 0
LVIM
LVION
0 0 0 0 0
LVIMD
LVIF
LVION
Low voltage detection operation enable or disable
0
Disable
operation.
1
Enable
operation.
LVIMD
Selection of operation mode of low voltage detection
0
Generate interrupt request signal INTLVI when supply voltage < detection voltage.
1
Generate internal reset signal LVIRES when supply voltage < detection voltage.
LVIF
Low voltage detection flag
0
When supply voltage > detection voltage, or when operation is disabled
1
Supply voltage < detection voltage
Cautions 1. After setting the LVION bit to 1, wait for 0.2 ms (TYP.) (target value) before checking
the voltage using the LVIF bit.
2. The value of the LVIF flag is output as the output signal INTLVI when the LVION bit
= 1 and LVIMD bit = 0.
3. Be sure to clear bits 2 to 6 to "0".
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(2) Low-voltage detection level select register (LVIS)
The LVIS register is used to select the level of low voltage to be detected.
This register can be read or written in 8-bit units.
After
reset:
00H
R/W
Address:
FFFFF891H
7 6 5 4 3 2 1 0
LVIS
0 0 0 0 0 0 0
LVIS0
LVIS0
Detection
level
0
4.4
V
0.2 V
1
4.2
V
0.2 V
Cautions 1. This register cannot be written until a reset request due to something other than
low-voltage detection is generated after the LVIM.LVION and LVIM.LVIMD bits are
set to 1.
2. Be sure to clear bits 1 to 7 to "0".
(3) Internal RAM data status register (RAMS)
The RAMS register is a flag register that indicates whether the internal RAM is valid or not. The RAMS
register is a special register. It can be written only by a combination of specific sequences (see 3.4.7 Special
registers).
For the RAMS register, see 22.5 RAM Retention Voltage Detection Operation.
This register can be read or written in 8-bit or 1-bit units.
Caution The following shows the specific sequence after reset.
Setting conditions: Detection of voltage lower than detection level
Set by instruction
Generation of reset signal by watchdog timer overflow
Generation of reset signal while RAM is being accessed
Generation
of
reset
signal by clock monitor
Clearing condition: Writing of 0 in specific sequence
After
reset:
01H
R/W
Address:
FFFFF892H
7 6 5 4 3 2 1 0
RAMS
0 0 0 0 0 0 0
RAMF
RAMF
Internal RAM data valid/invalid
0
Valid
1
Invalid
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22.4 Operation
Depending on the setting of the LVIM.LVIMD bit, an interrupt request signal (INTLVI) or an internal reset signal is
generated.
22.4.1 To use for internal reset signal
<To start operation>
<1> Mask the interrupt of LVI.
<2> Select the voltage to be detected by using the LVIS.LVIS0 bit.
<3> Set the LVIM. LVION bit to 1 (to enable operation).
<4> Insert a wait cycle of 0.2 ms MAX. by software.
<5> By using the LVIM.LVIF bit, check if the supply voltage > detection voltage.
<6> Set the LVIM.LVIMD bit to 1 (to generate an internal reset signal).
Caution If the LVIMD bit is set to 1, the contents of the LVIM and LVIS registers cannot be changed until a
reset request other than LVI is generated.
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Figure 22-2. Operation Timing of Low-Voltage Detector (LVIMD Bit = 1)
Set (by instruction, refer to <3> above)
LVI reset request signal
LVIRF bit
Note 1
POC detection voltage
Supply voltage (V
DD
)
LVI detection voltage
LVION bit
LVI detection signal
POC reset request signal
Internal reset signal
(active low)
Clear
(by POC reset request signal)
Time
Delay
Delay
Delay
Note 2
Delay
Delay
Delay
Delay
Delay
Cleared by
instruction
Notes 1. The LVIRF bit is bit 0 of the reset source flag register (RESF). For details of RESF, see CHAPTER
19 RESET FUNCTIONS.
2. During the period in which the supply voltage is the set voltage or lower, the internal reset signal is
retained (internal reset state).
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22.4.2 To use for interrupt
<To start operation>
<1> Mask the interrupt of LVI.
<2> Select the voltage to be detected by using the LVIS.LVIS0 bit.
<3> Set the LVIM.LVION bit to 1 (to enable operation).
<4> Insert a wait cycle of 0.2 ms MAX, by software.
<5> By using the LVIM.LVIF bit, check if the supply voltage > detection voltage.
<6> Clear the interrupt request flag of LVI.
<7> Unmask the interrupt of LVI.
<To stop operation>
Clear the LVION bit to 0.
Figure 22-3. Operation Timing of Low-Voltage Detector (LVIM Bit = 0)
Supply voltage
(V
DD
)
LVI detection
voltage
POC detection
voltage
LVION bit
LVI detection
signal
Internal reset signal
(active low)
INTLVI signal
POC reset
request signal
Delay
Delay
Clear
(by POC reset request signal)
Delay
Time
Delay
Delay
Delay
Delay
Delay
Set (by instruction, refer to <3> above.)
LVIF bit
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22.5 RAM Retention Voltage Detection Operation
The supply voltage and detection voltage are compared. When the supply voltage drops below the detection
voltage (including on power application), the RAMS.RAMF bit is set (1).
When the POC function is not used and when the RAM retention voltage detection function is used, be sure to
input an external reset signal if the detected voltage falls below the operating voltage.
Figure 22-4. Operation Timing of RAM Retention Voltage Detection Function
Supply voltage
(V
DD
)
POC detection
voltage
RAM retention
detection voltage
POC detection
voltage
Set condition
detection signal
RAM retention voltage
detection signal
RAM retention flag
(RAMF bit)
Delay
Delay
Delay
Time
Note
Delay
Set
Set
Cleared by
instruction
Cleared by
instruction
Note A reset signal (WDTRES) is generated due to an overflow of the watchdog timer or RESET pin input
during RAM access.
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22.6 Emulation Function
When an in-circuit emulator is used, the operation of the RAM retention flag (RAMS.RAMF bit) can be pseudo-
controlled and emulated by manipulating the PEMU1 register on the debugger.
This register is valid only in the emulation mode. It is invalid in the normal mode.
(1) Peripheral emulation register 1 (PEMU1)
After
reset:
00H
R/W
Address:
FFFFF9FEH
7 6 5 4 3 2 1 0
PEMU1
0 0 0 0 0
EVARAMIN
0 0
EVARAMIN
Pseudo specification of RAM retention voltage detection signal
0
Do not detect voltage lower than RAM retention voltage.
1
Detect voltage lower than RAM retention voltage (set RAMF flag).
Caution This bit is not automatically cleared.
[Usage]
When an in-circuit emulator is used, pseudo emulation of RAMF is realized by rewriting this register on the
debugger.
<1> CPU break (CPU operation stops.)
<2> Set the EVARAMIN bit to 1 by using a register write command.
By setting the EVARAMIN bit to 1, the RAMF bit is set to 1 on hardware (the internal RAM data is invalid).
<3> Clear the EVARAMIN bit to 0 by using a register write command again.
Unless this operation is performed (clearing the EVARAMIN bit to 0), the RAMF bit cannot be cleared to 0 by
a CPU operation instruction.
<4> Run the CPU and resume emulation.
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CHAPTER 23 REGULATOR
23.1 Overview
The V850ES/HJ2 includes a regulator to reduce power consumption and noise.
This regulator supplies a stepped-down V
DD
power supply voltage to the oscillator block and internal logic circuits
(except the A/D converter and output buffers). The regulator output voltage is set to 2.5 V (TYP.).
Figure 23-1. Regulator
BV
DD
AV
REF0
FLMD0
V
DD
EV
DD
REGC
EV
DD
I/O buffer
Bidirectional level shifter
BV
DD
I/O buffer
Regulator
A/D converter
Flash
memory
Main/sub
oscillator
Internal digital circuits
2.5 V (TYP.)
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23.2 Operation
The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE1 mode,
IDLE2 mode, STOP mode, or during reset).
Be sure to connect a capacitor (4.7
F (preliminary value)) to the REGC pin to stabilize the regulator output.
A diagram of the regulator pin connection method is shown below.
Figure 23-2. REGC Pin Connection
REG
V
DD
V
SS
REGC
Input voltage = 3.5 to 5.5 V
Voltage supply to main oscillator/internal logic = 2.5 V (TYP.)
4.7 F
(preliminary value)
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CHAPTER 24 FLASH MEMORY
The following can be considered as the development environment and mass production applications using flash
memory versions.
For altering software after the V850ES/HJ2 is soldered onto the target system.
For data adjustment when starting mass production.
For differentiating software according to the specification in small scale production of various models.
For facilitating inventory management.
For updating software after shipment.
24.1 Features
4-byte/1-clock access (when instruction is fetched)
Capacity: 512/376/256/128 KB
Write voltage: Erase/write with a single power supply
Rewriting method
Rewriting by communication with dedicated flash programmer via serial interface (on-board/off-board
programming)
Rewriting flash memory by user program (self programming)
Flash memory write prohibit function supported (security function)
Safe rewriting of entire flash memory area by self programming using boot swap function
Interrupts can be acknowledged during self programming.
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24.1.1 Erasure unit
The units in which the 512, 376, 256, or 128 KB flash memory can be erased are as follows.
(1) All-area erasure
The flash memory areas can be erased at the same time.
(2) Block erasure
The flash memory can be erased in block units
Note
.
Block 0: 56 KB
Block 1: 8 KB
Block 2: 56 KB
Block 3: 8 KB
Block 4: 56 KB
Block 5: 56 KB
Block 6: 8 KB
Block 7: 8 KB
Block 8: 60 KB
Block 9: 60 KB
Block 10: 60 KB
Block 11: 60 KB
Block 12: 4 KB
Block 13: 4 KB
Block 14: 4 KB
Block 15: 4 KB
Note 4 blocks, blocks 0 to 3, for the 128 KB version (
PD70F3709).
8 blocks, blocks 0 to 7, for the 256 KB version (
PD70F3710).
10 blocks, blocks 0 to 9, for the 376 KB version (
PD70F3711).
16 blocks, blocks 0 to 15, for the 512 KB version (
PD70F3712).
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24.2 Rewriting by Dedicated Flash Programmer
The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/HJ2 is mounted on
the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on
the target system (off-board programming) by using a dedicated program adapter (FA series).
24.2.1 Programming environment
The following shows the environment required for writing programs to the flash memory of the V850ES/HJ2.
Figure 24-1. Environment Required for Writing Programs to Flash Memory
Host machine
RS-232C
Dedicated flash
programmer
V850ES/HJ2
FLMD1
V
DD
V
SS
RESET
UARTA0/CSIB0
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXXX YYYY
STATVE
FLMD0
USB
A host machine is required for controlling the dedicated flash programmer.
UARTA0 or CSIB0 is used for the interface between the dedicated flash programmer and the V850ES/HJ2 to
perform writing, erasing, etc. A dedicated program adapter (FA series) required for off-board writing.
Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
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24.2.2 Communication mode
Communication between the dedicated flash programmer and the V850ES/HJ2 is performed by serial
communication using the UARTA0 or CSIB0 interfaces of the V850ES/HJ2.
(1) UARTA0
Transfer rate: 9,600 to 153,600 bps
Figure 24-2. Communication with Dedicated Flash Programmer (UARTA0)
Dedicated flash
programmer
V850ES/HJ2
V
DD
V
SS
RESET
TXDA0
RXDA0
FLMD1
FLMD1
V
DD
GND
RESET
RxD
TxD
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXXX YYYY
STATVE
FLMD0
FLMD0
Cautions 1. Process the pins not shown in compliance with the processing of unused pins (see 2.4
Pin I/O Circuit Types and Recommended Connection of Unused Pins). Connect a resistor
of 1 k
to 10 k as necessary.
2. Do not input a high level to the DRST pin.
(2) CSIB0
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
Figure 24-3. Communication with Dedicated Flash Programmer (CSIB0)
Dedicated flash
programmer
V850ES/HJ2
FLMD1
V
DD
V
SS
RESET
SOB0
SIB0
SCKB0
FLMD1
V
DD
GND
RESET
SI
SO
SCK
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
X
XX YY
Y
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXX
X Y
YYY
STATVE
FLMD0
FLMD0
Cautions 1. Process the pins not shown in compliance with the processing of unused pins (see 2.4
Pin I/O Circuit Types and Recommended Connection of Unused Pins). Connect a resistor
of 1 k
to 10 k as necessary.
2. Do not input a high level to the DRST pin.
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(3) CSIB0 + HS
Serial clock: 2.4 kHz to 2.5 MHz (MSB first)
Figure 24-4. Communication with Dedicated Flash Programmer (CSIB0 + HS)
Dedicated flash
programmer
V850ES/HJ2
V
DD
V
SS
RESET
SOB0
SIB0
SCKB0
PCM0
V
DD
FLMD1
FLMD1
GND
RESET
SI
SO
SCK
HS
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXXX YYYY
STATVE
FLMD0
FLMD0
Cautions 1. Process the pins not shown in compliance with the processing of unused pins (see 2.4 Pin
I/O Circuit Types and Recommended Connection of Unused Pins). Connect a resistor of 1
k
to 10 k as necessary.
2. Do not input a high level to the DRST pin.
The dedicated flash programmer outputs the transfer clock, and the V850ES/HJ2 operates as a slave.
When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the
V850ES/HJ2. For details, refer to the PG-FP4 User's Manual (U15260E).
Table 24-1. Signal Connections of Dedicated Flash Programmer (PG-FP4)
PG-FP4
V850ES/HJ2
Processing for Connection
Signal Name
I/O
Pin Function
Pin Name
UARTA0
CSIB0
CSIB0 + HS
FLMD0 Output
Write
enable/disable
FLMD0
FLMD1 Output
Write
enable/disable
FLMD1
Note 1
Note 1
Note 1
VDD
-
V
DD
voltage generation/voltage monitor
V
DD
GND
-
Ground V
SS
CLK
Output
Clock output to V850ES/HJ2
X1, X2
Note 2
Note 2
Note 2
RESET Output
Reset
signal
RESET
SI/RxD Input
Receive
signal
SOB0,
TXDA0
SO/TxD
Output
Transmit signal
SIB0, RXDA0
SCK Output
Transfer
clock
SCKB0
HS Input
Handshake signal for CSIB0 + HS
communication
PCM0
Notes 1. Wire these pins as shown in Figure 24-5, or connect then to GND via pull-down resistor on board.
2. Clock cannot be supplied via the CLK pin of the flash programmer. Create an oscillator on board and
supply the clock.
Remark
: Must be connected.
: Does not have to be connected.
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Table 24-2. Wiring of Flash Writing Adapter for V850ES/HJ2 (FA-144GJ-UEN)
Flash Programmer (PG-FP4)
Connection Pins
When CSIB0 + HS Is
Used
When CSIB0 Is Used
When UARTA0 Is Used
Signal
Name
I/O Pin
Function
Pin Name
on FA
Board
Pin Name
Pin
No.
Pin Name
Pin
No.
Pin Name
Pin
No.
SI/RxD Input
Receive
signal SI
P41/SOB0
23 P41/SOB0
23 P30/TXDA0
25
SO/TxD Output Transmit
signal SO
P40/SIB0
22
P40/SIB0
22 P31/RXDA0/INTP7 26
SCK Output
Transfer
clock
SCK
P42/SCKB0
24
P42/SCKB0
24
Not
necessary
-
X1 Not
necessary
-
Not necessary
- Not necessary
-
CLK Output
Clock
to
V850ES/HJ2
X2 Not
necessary
-
Not necessary
- Not necessary
-
/RESET Output Reset signal
/RESET
RESET
14
RESET
14 RESET
14
FLMD0 Input Write
voltage FLMD0 FLMD0
8 FLMD0
8 FLMD0
8
FLMD1 Input Write
voltage FLMD1 PDL5/AD5/FLMD1 110 PDL5/AD5/FLMD1 110 PDL5/AD5/FLMD1 110
HS Input
Handshake
signal of CSI0
+ HS
communication
RESERVE/
HS
PCM0/WAIT 85
Not
necessary
- Not necessary
-
V
DD
9
V
DD
9
V
DD
9
BV
DD
104
BV
DD
104
BV
DD
104
EV
DD
5, 34 EV
DD
5,
34
EV
DD
5,
34
VDD
-
VDD voltage
generation/
voltage monitor
VDD
AV
REF0
1
AV
REF0
1
AV
REF0
1
V
SS
11
V
SS
11
V
SS
11
AV
SS
2
AV
SS
2
AV
SS
2
BV
SS
103
BV
SS
103
BV
SS
103
GND
-
Ground GND
EV
SS
33
EV
SS
33
EV
SS
33
Cautions 1. Be sure to connect the REGC pin to GND via a 4.7
F (preliminary value) capacitor.
2. A clock cannot be supplied from the CLK pin of the flash programmer. Create an oscillator on
the board and supply the clock from that oscillator.
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Figure 24-5. Example of Wiring of V850ES/HJ2 Flash Writing Adapter (FA-144GJ-UEN)
(in CSIB0 + HS Mode) (1/2)
V850ES/HJ2
VDD
GND
GND
VDD
GND
VDD
VDD
GND
Connect to VDD
Connect to GND
25
30
20
15
75
80
85
90
95
100
105
35
40
45
50
55
60
65
70
110
115
120
125
130
135
140
1
5
10
RFU-3
RFU-2
VDE
FLMD1 FLMD0
RFU-1
SI
SO
SCK
/RESET
V
PP
RESERVE/HS
X1
X2
Note 2
Note 1
Note 3
4.7 F (preliminary value)
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Figure 24-5. Example of Wiring of V850ES/HJ2 Flash Writing Adapter (FA-144GJ-UEN)
(in CSIB0 + HS Mode) (2/2)
Notes 1. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor.
2. Pins used when UARTA0 is used
3. Supply a clock by creating an oscillator on the flash writing adapter (enclosed by the broken lines).
Here is an example of the oscillator.
Example
X1
X2
Caution Do not input a high level to the DRST pin.
Remarks 1. Process the pins not shown in accordance with processing of unused pins (see 2.4 Pin I/O
Circuit Types and Recommended Connection of Unused Pins).
2. This adapter is used for the 144-pin plastic LQFP package.
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24.2.3 Flash memory control
The following shows the procedure for manipulating the flash memory.
Figure 24-6. Procedure for Manipulating Flash Memory
Start
Select communication system
Manipulate flash memory
End?
Yes
Supplies FLMD0 pulse
No
End
Switch to flash memory
programming mode
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24.2.4 Selection of communication mode
In the V850ES/HJ2, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin
after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash
programmer.
The following shows the relationship between the number of pulses and the communication mode.
Figure 24-7. Selection of Communication Mode
V
DD
V
DD
RESET (input)
FLMD1 (input)
FLMD0 (input)
RXDA0 (input)
TXDA0 (output)
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
(Note)
Power on
Oscillation
stabilized
Communication
mode selected
Flash control command communication
(erasure, write, etc.)
Reset
released
Note The number of clocks is as follows depending on the communication mode.
FLMD0 Pulse
Communication Mode
Remarks
0
UARTA0
Communication rate: 9,600 bps (after reset), LSB first
8
CSIB0
V850ES/HJ2 performs slave operation, MSB first
11 CSIB0
+ HS
V850ES/HJ2 performs slave operation, MSB first
Other RFU
Setting
prohibited
Caution
When UARTA0 is selected, the receive clock is calculated based on the reset command sent
from the dedicated flash programmer after receiving the FLMD0 pulse.
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24.2.5 Communication commands
The V850ES/HJ2 communicates with the dedicated flash programmer by means of commands. The signals sent
from the dedicated flash programmer to the V850ES/HJ2 are called "commands". The response signals sent from the
V850ES/HJ2 to the dedicated flash programmer are called "response commands".
Figure 24-8. Communication Commands
Dedicated flash programmer
V850ES/HJ2
Command
Response command
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XXXX YYYY
STATVE
The following shows the commands for flash memory control in the V850ES/HJ2. All of these commands are
issued from the dedicated flash programmer, and the V850ES/HJ2 performs the processing corresponding to the
commands.
Table 24-3. Flash Memory Control Commands
Support
Classification Command
Name
CSIB0
CSIB0 + HS
UARTA0
Function
Blank check
Block blank check
command
Checks if the contents of the memory in the
specified block have been correctly erased.
Chip erase command
Erases the contents of the entire memory.
Erase
Block erase command
Erases the contents of the memory of the
specified block.
Write Write
command
Writes the specified address range, and
executes a contents verify check.
Verify command
Compares the contents of memory in the
specified address range with data
transferred from the flash programmer.
Verify
Checksum command
Reads the checksum in the specified
address range.
Silicon signature
command
Reads silicon signature information.
System setting,
control
Security setting
command
Disables the block erase, chip erase,
program, read commands, and rewriting of
the boot area.
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24.2.6 Pin connection
When performing on-board writing, mount a connector on the target system to connect to the dedicated flash
programmer. Also, incorporate a function on-board to switch from the normal operation mode to the flash memory
programming mode.
In the flash memory programming mode, all the pins not used for flash memory programming become the same
status as that immediately after reset. Therefore, pin handling is required when the external device does not
acknowledge the status immediately after a reset.
(1) FLMD0 pin
In the normal operation mode, input a voltage of V
SS
level to the FLMD0 pin. In the flash memory
programming mode, supply a write voltage of V
DD
level to the FLMD0 pin.
Because the FLMD0 pin serves as a write protection pin in the self programming mode, a voltage of V
DD
level
must be supplied to the FLMD0 pin via port control, etc., before writing to the flash memory. For details, see
24.3.5 (1) FLMD0 pin.
Figure 24-9. FLMD0 Pin Connection Example
V850ES/HJ2
FLMD0
Dedicated flash programmer connection pin
Pull-down resistor (R
FLMD0
)
(2) FLMD1 pin
When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When V
DD
is supplied to the FLMD0
pin, the flash memory programming mode is entered, so 0 V must be input to the FLMD1 pin. The following
shows an example of the connection of the FLMD1 pin.
Figure 24-10. FLMD1 Pin Connection Example
FLMD1
Pull-down resistor (R
FLMD1
)
Other device
V850ES/HJ2
Caution If the V
DD
signal is input to the FLMD1 pin from another device during on-board writing and
immediately after reset, isolate this signal.
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Table 24-4. Relationship Between FLMD0 and FLMD1 Pins and Operation Mode When Reset Is Released
FLMD0 FLMD1
Operation
Mode
0
Don't care
Normal operation mode
V
DD
0
Flash memory programming mode
V
DD
V
DD
Setting
prohibited
(3) Serial interface pin
The following shows the pins used by each serial interface.
Table 24-5. Pins Used by Serial Interfaces
Serial Interface
Pins Used
UARTA0 TXDA0,
RXDA0
CSIB0
SOB0, SIB0, SCKB0
CSIB0
+ HS
SOB0, SIB0, SCKB0, PCM0
When connecting a dedicated flash programmer to a serial interface pin that is connected to another device
on-board, care should be taken to avoid conflict of signals and malfunction of the other device.
(a) Conflict of signals
When the dedicated flash programmer (output) is connected to a serial interface pin (input) that is
connected to another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate
the connection to the other device or set the other device to the output high-impedance status.
Figure 24-11. Conflict of Signals (Serial Interface Input Pin)
V850ES/HJ2
Input pin
Conflict of signals
Dedicated flash programmer
connection pins
Other device
Output pin
In the flash memory programming mode, the signal that the dedicated flash
programmer sends out conflicts with signals another device outputs.
Therefore, isolate the signals on the other device side.
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(b) Malfunction of other device
When the dedicated flash programmer (output or input) is connected to a serial interface pin (input or
output) that is connected to another device (input), the signal is output to the other device, causing the
device to malfunction. To avoid this, isolate the connection to the other device.
Figure 24-12. Malfunction of Other Device
V850ES/HJ2
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
In the flash memory programming mode, if the signal the V850ES/HJ2
outputs affects the other device, isolate the signal on the other device side.
V850ES/HJ2
Pin
Dedicated flash programmer
connection pin
Other device
Input pin
In the flash memory programming mode, if the signal the dedicated flash
programmer outputs affects the other device, isolate the signal on the other
device side.
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(4) RESET pin
When the reset signals of the dedicated flash programmer are connected to the RESET pin that is connected
to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the
connection to the reset signal generator.
When a reset signal is input from the user system in the flash memory programming mode, the programming
operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the
dedicated flash programmer.
Figure 24-13. Conflict of Signals (RESET Pin)
V850ES/HJ2
RESET
Dedicated flash programmer
connection pin
Reset signal generator
Conflict of signals
Output pin
In the flash memory programming mode, the signal the reset signal generator
outputs conflicts with the signal the dedicated flash programmer outputs.
Therefore, isolate the signals on the reset signal generator side.
(5) Port pins (including NMI)
When the system shifts to the flash memory programming mode, all the pins that are not used for flash
memory programming are in the same status as that immediately after reset. If the external device connected
to each port does not recognize the status of the port immediately after reset, pins require appropriate
processing, such as connecting to V
DD
via a resistor or connecting to V
SS
via a resistor.
(6) Other signal pins
Connect X1, X2, XT1, and XT2 in the same status as that in the normal operation mode.
During flash memory programming, input a low level to the DRST pin or leave it open. Do not input a high
level.
(7) Power supply
Supply the same power (V
DD
, V
SS
, EV
DD
, EV
SS
, BV
DD
, BV
SS
, AV
REF0
, AV
SS
, REGC) as in normal operation
mode.
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24.2.7 Recommended circuit example for writing
Figure 24-14 shows the recommended circuit example for writing.
Figure 24-14. Procedure for Manipulating Flash Memory
V
DD
V
SS
RESET
SOB0/TXDA0
SIB0/RXDA0
SCKB0
FLMD0
FLMD1
REGC
V
DD
V
SS
RESET
SIB0/RXDA0
SOB0/TXDA0
SCKB0
FLMD0
FLMD1
V850ES/HJ2
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XX
X
Y
Y
Y
XXX
XX
XXXXXX
XXXX
XX
X
X
Y
YY
Y
STATVE
Flashpro IV
Pull-down resistor (R
FLMD1
)
5 V
Capacitor (capacitance = 4.7 pF)
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24.3 Rewriting by Self Programming
24.3.1 Overview
The V850ES/HJ2 supports a flash macro service that allows the user program to rewrite the internal flash memory
by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user
application program, the flash memory can be rewritten by a user application transferred in advance to the internal
RAM or external memory. Consequently, the user program can be upgraded and constant data can be rewritten in the
field.
Figure 24-15. Concept of Self Programming
Application program
Self programming library
Flash macro service
Flash memory
Flash function execution
Flash information
Erase, write
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24.3.2 Features
(1) Secure self programming (boot swap function)
The V850ES/HJ2 supports a boot swap function that can exchange the physical memory of blocks 0 and 1
with the physical memory of blocks 2 and 3. By writing the start program to be rewritten to blocks 2 and 3 in
advance and then swapping the physical memory, the entire area can be safely rewritten even if a power
failure occurs during rewriting because the correct user program always exists in blocks 0 and 1.
Figure 24-16. Rewriting Entire Memory Area (Boot Swap)
Block 0
Block 1
Block 2
Block 3
Block 4
:
Last block
Block 0
Block 1
Block 2
Block 3
Block 4
:
Last block
Block 0
Block 1
Block 2
Block 3
Block 4
:
Last block
Boot swap
Rewriting blocks
2 and 3
(2) Interrupt support
Instructions cannot be fetched from the flash memory during self programming. Conventionally, a user handler
written to the flash memory could not be used even if an interrupt occurred.
Therefore, in the V850ES/HJ2, to use an interrupt during self programming, processing transits to the specific
address
Note
in the internal RAM. Allocate the jump instruction that transits processing to the user interrupt
servicing at the specific address
Note
in the internal RAM.
Note NMI interrupt:
Start address of internal RAM
Maskable interrupt: Start address of internal RAM + 4 addresses
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24.3.3 Standard self programming flow
The entire processing to rewrite the flash memory by flash self programming is illustrated below.
Figure 24-17. Standard Self Programming Flow
Flash environment initialization processing
Erase processing
Write processing
Flash information setting processing
Note 1
Internal verify processing
Boot area swap processing
Note 2
Flash environment end processing
Flash memory manipulation
End of processing
All blocks end?
Disable accessing flash area
Disable setting of STOP mode
Disable stopping clock
Yes
No
Notes 1. If a security setting is not performed, flash information setting processing does not have to be
executed.
2. If boot swap is not used, flash information setting processing and boot swap processing do not have
to be executed.
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24.3.4 Flash functions
Table 24-6. Flash Function List
Function Name
Outline
Support
FlashEnv Initialization
of flash control macro
FlashBlockErase
Erasure of specified one block
FlashWordWrite
Writing from specified address
FlashBlockIVerify
Internal verification of specified one block
FlashBlockBlankCheck
Blank check of specified one block
FlashFLMDCheck
Check of FLMD pin
FlashStatusCheck
Status check of operation specified immediately before
FlashGetInfo
Reading of flash information
FlashSetInfo
Setting of flash information
FlashBootSwap
Swapping of boot area
FlashWordRead
Data read from specified address
FlashSetUserHandler User
interrupt handler registration function
24.3.5 Pin processing
(1) FLMD0 pin
The FLMD0 pin is used to set the operation mode when reset is released and to protect the flash memory from
being written during self rewriting. It is therefore necessary to keep the voltage applied to the FLMD0 pin at 0
V when reset is released and a normal operation is executed. It is also necessary to apply a voltage of V
DD
level to the FLMD0 pin during the self programming mode period via port control before the memory is
rewritten.
When self programming has been completed, the voltage on the FLMD0 pin must be returned to 0 V.
Figure 24-18. Mode Change Timing
RESET signal
FLMD0 pin
V
DD
0 V
V
DD
0 V
Self programming mode
Normal
operation mode
Normal
operation mode
Caution Make sure that the FLMD0 pin is at 0 V when reset is released.
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24.3.6 Internal resources used
The following table lists the internal resources used for self programming. These internal resources can also be
used freely for purposes other than self programming.
Table 24-7. Internal Resources Used
Resource Name
Description
Stack area (user stack + (TBD)
bytes)
An extension of the stack used by the user is used by the library (can be used in both the
internal RAM and external RAM).
Library code ((TBD) bytes)
Program entity of library (can be used anywhere other than the flash memory block to be
manipulated).
Application program
Executed as a user application.
Calls flash functions.
Maskable interrupt
Can be used in user application execution status or self programming status. To use this
interrupt in the self-programming status, since the processing transits to the address of
the internal RAM start address + 4 addresses, allocate the jump instruction that transits
the processing to the user interrupt servicing at the address of the internal RAM start
address + 4 addresses in advance.
NMI interrupt
Can be used in user application execution status or self programming status. To use this
interrupt in the self-programming status, since the processing transits to the address of
the internal RAM start address, allocate the jump instruction that transits the processing
to the user interrupt servicing at the internal RAM start address in advance.
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CHAPTER 25 OPTION BYTE FUNCTION
The option byte is stored in address 000007AH of the internal flash memory (internal ROM area) as 8-bit data.
When writing a program to the V850ES/HJ2, be sure to set the option data corresponding to the following option in
the program at address 000007AH as default data.
The data in this area cannot be rewritten during program execution.
OPB7
OPB7
0
1
Crystal resonator mode
RC oscillator mode
OPB6
OPB6
0
1
-
-
-
-
OPB1
OPB0
Address: 0000007AH
Subclock operation mode setting
OPB0
0
1
Stopping enabled
Stopping disabled
Stopping internal oscillator enable/disable
OPB1
0
1
Operating clock (f
X
/f
R
) selectable
INTWDT2 mode/WDTRES mode selectable
Fixed to internal oscillation clock (f
R
)
Fixed to WDTRES mode
Watchdog timer 2 mode setting
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CHAPTER 26 ON-CHIP DEBUG FUNCTION
The V850ES/HJ2 has an on-chip debug function that uses the JTAG (Joint Test Action Group) interface (DRST,
DCK, DMS, DDI, and DDO pins) and that can be used via an on-chip debug emulator (MINICUBE
).
26.1 Features
Hardware break function: 2 points
Software break function: 4 points
Real-time RAM monitor function: Memory contents can be read during program execution.
Dynamic memory modification function (DMM function): RAM contents can be rewritten during program execution.
Mask function: RESET, NMI, HLDRQ, WAIT
ROM security function: 10-byte ID code authentication
Caution The
following
functions are not supported.
Trace function
Event function
Debug interrupt interface function (DBINT)
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26.2 Connection Circuit Example
MINICUBE
V850ES/HJ2
VDD
DCK
DMS
DDI
DDO
DRST
RESET
FLMD0
GND
EV
DD
DCK
DMS
DDI
DDO
DRST
Note 2
RESET
FLMD0
Note 3
FLMD1/PDL5
EV
SS
Note 1
ST
A
TUS
T
ARGET
PO
WER
Notes 1. Example of pin connection when MINICUBE is not connected
2. A pull-down resistor is provided on chip.
3. For flash memory rewriting
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26.3 Interface Signals
The interface signals are described below.
(1) DRST
This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously
initializes the debug control unit.
MINICUBE raises the DRST signal when it detects V
DD
of the target system after the integrated debugger is
started, and starts the on-chip debug unit of the device.
When the DRST signal goes high, a reset signal is also generated in the CPU.
When starting debugging by starting the integrated debugger, a CPU reset is always generated.
(2) DCK
This is a clock input signal. It supplies a 20 MHz clock from MINICUBE. In the on-chip debug unit, the DMS
and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling
edge.
(3) DMS
This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of
the DMS signal.
(4) DDI
This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK.
(5) DDO
This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal.
(6) EV
DD
This signal is used to detect VDD of the target system. If VDD from the target system is not detected, the
signals output from MINICUBE (DRST, DCK, DMS, DDI, FLMD0, and RESET) go into a high-impedance state.
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(7) FLMD0
The flash self programming function is used for the function to download data to the flash memory via the
integrated debugger. During flash self programming, the FLMD0 pin must be kept high. In addition, connect a
pull-down resistor to the FLMD0 pin.
The FLMD0 pin can be controlled in either of the following two ways.
<1> To control from MINICUBE
Connect the FLMD0 signal of MINICUBE to the FLMD0 pin.
In the normal mode, nothing is driven by MINICUBE (high impedance).
During a break, MINICUBE raises the FLMD0 pin to the high level when the download function of the
integrated debugger is executed.
<2> To control from port
Connect any port of the device to the FLMD0 pin.
The same port as the one used by the user program to realize the flash self programming function may
be used.
On the console of the integrated debugger, make a setting to raise the port pin to high level before
executing the download function, or lower the port pin after executing the download function.
For details, refer to the ID850QB Ver. 3.10 Integrated Debugger Operation User's Manual
(U17435E).
(8) RESET
This is a system reset input pin. If the DRST pin is made invalid by the value of the OCDM.OCDM0 bit set by
the user program, on-chip debugging cannot be executed. Therefore, reset is effected by MINICUBE, using
the RESET pin, to make the DRST pin valid (initialization).
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26.4 Register
(1) On-chip debug mode register (OCDM)
The OCDM register is used to select the normal operation mode or on-chip debug mode. This register is a
special register and can be written only in a combination of specific sequences (see 3.4.7 Special registers).
This register is also used to specify whether a pin provided with an on-chip debug function is used as an on-
chip debug pin or as an ordinary port/peripheral function pin. It also is used to disconnect the internal pull-
down resistor of the P05 pin.
The OCDM register can be written only while a low level is input to the P05 pin.
This register can be read or written in 8-bit or 1-bit units.
0
OCDM0
0
1
Operation mode
OCDM
0
0
0
0
0
0
OCDM0
After reset: 01H
Note
R/W Address: FFFFF9FCH
When P05 pin is low:
Normal operation mode (in which a pin that functions alternately as an
on-chip debug function pin is used as a port/peripheral function pin)
When P05 pin is high:
On-chip debug mode (in which a pin that functions alternately as an
on-chip debug function pin is used as an on-chip debug mode pin)
Selects normal operation mode (in which a pin that functions alternately
as on-chip debug function pin is used as a port/peripheral function pin) and
disconnects the on-chip pull-down resistor of the P05 pin.
Note The value of this register is 01H after reset by the RESET pin and is 00H after reset by power-on-clear
circuit (POC). After reset by the WDTRES2 signal, clock monitor (CLM), or low-voltage detector (LVI),
however, the value of the OCDM register is retained.
Cautions 1. When using the DDI, DDO, DCK, and DMS pins not as on-chip debug pins but as port pins
after external reset, the following actions must be taken.
Input a low level to the P05 pin.
Set the ODCM0 bit. In this case, take the following actions.
<1> Clear the OCDM0 bit to 0.
<2> Fix the P05 pin to the low level until <1> is completed.
2. The P05 pin has an on-chip pull-down resistor. This resistor is disconnected when the
OCDM0 flag is cleared to 0.
OCDM0 flag
(1: Pull-down ON, 0: Pull-down OFF)
10 to 100 k
(30 k
(TYP.))
P05
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26.5 Operation
The on-chip debug function is made invalid under the conditions shown in the table below.
When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0.
OCDM0 Flag
DRST Pin
0 1
L Invalid
Invalid
H Invalid
Valid
Remark L: Low-level input
H: High-level input
Figure 26-1. Timing When On-Chip Debug Function Is Not Used
Low-level input
After OCDM0 bit is cleared,
high level can be input/output.
Clearing OCDM0 bit
Releasing reset
RESET
OCDM0
P05/INTP2/DRST
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26.6 ROM Security Function
26.6.1 Security ID
The flash memory versions of the V850ES/HJ2 perform authentication using a 10-byte ID code to prevent the
contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip
debug emulator.
Set the ID code in the 10-byte on-chip flash memory area from 0000070H to 0000079H to allow the debugger
perform ID authentication.
If the IDs match, the security is released and reading flash memory and using the on-chip debug emulator are
enabled.
Set the 10-byte ID code to 0000070H to 0000079H.
Bit 7 of 0000079H is the on-chip debug emulator enable flag.
(0: Disable, 1: Enable)
When the on-chip debug emulator is started, the debugger requests ID input. When the ID code input on the
debugger and the ID code set in 0000070H to 0000079H match, the debugger starts.
Debugging cannot be performed if the on-chip debug emulator enable flag is 0, even if the ID codes match.
0 0 0 0 0 7 9 H
0 0 0 0 0 7 0 H
0 0 0 0 0 0 0 H
Security ID
(10 bytes)
Caution When the data in the flash memory has been deleted, all the bits are set to 1.
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26.6.2 Setting
The following shows how to set the ID code as shown in Table 26-1.
When the ID code is set as shown in Table 26-1, the ID code input in the configuration dialog box of the ID850QB
is "123456789ABCDEF123D4" (not case-sensitive).
Table 26-1. ID Code
Address Value
0x70 0x12
0x71 0x34
0x72 0x56
0x73 0x78
0x74 0x9A
0x75 0xBC
0x76 0xDE
0x77 0XF1
0x78 0x23
0x79 0xD4
The ID code can be specified for the device file that supports the CA850 Ver. 2.60 or later and the security ID by
the PM+ linker option setting.
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[Program example (when using CA850 Ver. 2.60 or later)]
#--------------------------------------
#
SECURITYID (continue ILGOP handler)
#--------------------------------------
.section
"SECURITY_ID"
--Interrupt handler address 0x70
.word
0x78563412
--0-3 byte code
.word
0xF1DEBC9A
--4-7 byte code
.hword
0xD423
--8-9 byte code
Remark Add the above program example to the startup files.
26.7 Cautions
(1) If a reset signal is input (from the target system or a reset signal from an internal reset source) during RUN
(program execution), the break function may malfunction.
(2) Even if the reset signal is masked by the mask function, the I/O buffer (port pin) may be reset if a reset signal
is input from a pin.
(3) Because a software breakpoint set in the internal flash memory is realized by the ROM correction function, it is
made temporarily invalid by target reset or internal reset generated by watchdog timer 2. The breakpoint
becomes valid again when a hardware break or forced break occurs, but a software break does not occur until
then.
(4) Pin reset during a break is masked and the CPU and peripheral I/O are not reset. If pin reset or internal reset
is generated as soon as the flash memory is rewritten by DMA or read by the RAM monitor function while the
user program is being executed, the CPU and peripheral I/O may not be correctly reset.
(5) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output.
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CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
27.1 Electrical Specifications
Absolute Maximum Ratings (T
A
= 25
C) (1/2)
Parameter Symbol
Conditions
Ratings
Unit
V
DD
V
DD
= EV
DD
= BV
DD
-0.5 to +6.5
V
BV
DD
V
DD
= EV
DD
= BV
DD
-0.5 to +6.5
V
EV
DD
V
DD
= EV
DD
= BV
DD
-0.5 to +6.5
V
AV
REF0
-0.5 to +6.5
V
V
SS
V
SS
= EV
SS
= BV
SS
= AV
SS
-0.5 to +0.5
V
AV
SS
V
SS
= EV
SS
= BV
SS
= AV
SS
-0.5 to +0.5
V
BV
SS
V
SS
= EV
SS
= BV
SS
= AV
SS
-0.5 to +0.5
V
Supply voltage
EV
SS
V
SS
= EV
SS
= BV
SS
= AV
SS
-0.5 to +0.5
V
V
I1
P00 to P06, P10, P11, P30 to P39, P40 to P42, P50 to P55,
P60 to P615, P80, P81, P90 to P915, RESET, FLMD0
-0.5 to EV
DD
+ 0.5
Note
V
V
I2
PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7,
PCT0 to PCT7, PDL0 to PDL15
-0.5 to BV
DD
+ 0.5
Note
V
Input voltage
V
I3
X1, X2, XT1, XT2
-0.5 to V
RO
+ 0.5
Note
V
Analog input voltage
V
IAN
P70 to P715, P120 to P127
-0.5 to AV
REF0
+ 0.5
Note
V
Note Be sure not to exceed the absolute maximum ratings (MAX. value) of each supply voltage.
Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between V
DD
or V
CC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
3. When directly connecting to the external circuit the pin that becomes high impedance state,
the timing must be designed such that the output conflict is avoided on the external circuit.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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Absolute Maximum Ratings (T
A
= 25
C) (2/2)
Parameter Symbol
Conditions
Ratings
Unit
Per pin
4
mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P60 to P615,
P80, P81, P90 to P915
Total of all pins
50
mA
Per pin
4
mA
P70 to P715, P120 to P127
Total of all pins
20
mA
Per pin
4
mA
Output current, low
I
OL
PCD0 to PCD3, PCM0 to PCM5,
PCS0 to PCS7, PCT0 to PCT7,
PDL0 to PDL15
Total of all pins
50
mA
Per pin
-4 mA
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55, P60 to P615,
P80, P81, P90 to P915
Total of all pins
-50 mA
Per pin
-4 mA
P70 to P715, P120 to P127
Total of all pins
-20 mA
Per pin
-4 mA
Output current, high
I
OH
PCD0 to PCD3, PCM0 to PCM5,
PCS0 to PCS7, PCT0 to PCT7,
PDL0 to PDL15
Total of all pins
-50 mA
Normal operation mode
Operating ambient
temperature
T
A
Flash memory programming mode
-40 to +85
C
Storage temperature
T
stg
-40 to +125
C
Cautions 1. Do not directly connect the output (or I/O) pins of IC products to each other, or to V
DD
, V
CC
and GND.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.
3. When directly connecting to the external circuit the pin that becomes high impedance state,
the timing must be designed such that the output conflict is avoided on the external circuit.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port
pins.
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27.2 Capacitance
(T
A
= 25
C, V
DD
= EV
DD
= AV
REF0
= BV
DD
= V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
I/O capacitance
C
IO
f
X
= 1 MHz,
Unmeasured pins returned to 0 V.
10
pF
27.3 Operating Conditions
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
REGC = 4.7
F,
at operation with main clock
4 20
MHz
REGC = 4.7
F,
at operation with subclock (crystal resonator)
32 35
kHz
Internal system clock
frequency
f
CLK
REGC = 4.7
F,
at operation with subclock (RC resonator)
12.5
Note 2
27.5
Note 2
kHz
Note The internal system clock frequency is half the oscillation frequency.
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27.4 Oscillator Characteristics
27.4.1 Main clock oscillator characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Resonator
Recommended
Circuit Parameter
Conditions MIN.
TYP.
MAX.
Unit
Oscillation frequency
(f
X
)
Note 1
4 5
MHz
After reset release
2
16
/f
X
s
After STOP mode
release
0.5
Note 3
Note 4 ms
Ceramic
resonator
Oscillation
stabilization time
Note 2
After IDLE2 mode
release
0.35
Note 3
Note 4
ms
Oscillation frequency
(f
X
)
Note 1
4 5
MHz
After reset release
2
16
/f
X
s
After STOP mode
release
0.5
Note 3
Note 4 ms
Crystal
resonator
X2
X1
Oscillation
stabilization time
Note 2
After IDLE2 mode
release
0.35
Note 3
Note 4
ms
Notes 1. Indicates only oscillator characteristics.
2. Time required to stabilize the crystal resonator after reset or STOP mode is released.
3. Time required to stabilize access to the internal flash memory.
4. The value differs depending on the OSTS register settings.
Cautions 1. When using the main clock oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. When the main clock is stopped and the subclock is operating, wait until the oscillation
stabilization time has been secured by the program before switching back to the main clock.
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27.4.2 Subclock oscillator characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Resonator Recommended
Circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
Oscillation frequency
(f
XT
)
Note 1
32
32.768
35
kHz
Crystal
resonator
XT2
XT1
Oscillation
stabilization time
Note 2
10
s
Oscillation frequency
(f
XT
)
Notes 1, 4
R = 390 k
5%
Note 3
C = 47 pF
10%
Note 3
25 40 55 kHz
RC
resonator
XT2
XT1
Oscillation
stabilization time
Note 2
100
s
Notes 1. Indicates only oscillator characteristics. For the CPU operation clock, see 27.8 AC Characteristics.
2. Time required from when V
DD
reaches oscillation voltage range (MIN.: 3.5 V) to when the crystal resonator
stabilizes.
3. To avoid an adverse effect from wiring capacitance, keep the wiring length as short as possible.
4. RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2. In the case of the RC
resonator, the internal system clock frequency is half the oscillation frequency: MIN. = 12.5 kHz, TYP. = 20
kHz, MAX. = 27.5 kHz.
Cautions 1. When using the subclock oscillator, wire as follows in the area enclosed by the broken lines in
the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
2. The subclock oscillator is designed as a low-amplitude circuit for reducing current consumption,
and is more prone to malfunction due to noise than the main clock oscillator. Particular care is
therefore required with the wiring method when the subclock is used.
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27.4.3 PLL characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input frequency
f
X
4 5
MHz
Output frequency
f
XX
16 20
MHz
Lock time
t
PLL
After
V
DD
reaches MIN.: 3.5 V
800
s
27.4.4 Internal oscillator characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output frequency
f
R
100 200 400 kHz
27.5 Voltage Regulator Characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input frequency
V
DD
3.5 5.5 V
Output frequency
V
RO
2.5
V
Lock time
t
REG
After V
DD
reaches MIN.: 3.5 V,
C = 4.7
F
20% connected to REGC pin
1
ms
V
DD
3.5 V
V
RO
RESET
t
REG
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27.6 DC Characteristics
27.6.1 I/O level
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
(1/2)
Parameter Symbol
Conditions
MIN. TYP. MAX.
Unit
V
IH1
P30, P34, P36 to P38, P41, P63 to P69,
P614, P615, P81, P98, P911
0.7EV
DD
EV
DD
V
V
IH2
P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P60 to P62, P610 to P613,
P80, P90 to P97, P99, P910, P912 to P915
0.8EV
DD
EV
DD
V
V
IH3
PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7,
PCT0 to PCT7, PDL0 to PDL15
0.7BV
DD
BV
DD
V
V
IH4
P70 to P715, P120 to P127
0.7AV
REF0
AV
REF0
V
Input voltage, high
V
IH5
RESET,
FLMD0
0.8EV
DD
EV
DD
V
V
IL1
P30, P34, P36 to P38, P41, P63 to P69,
P614, P615, P81, P98, P911
EV
SS
0.3EV
DD
V
V
IL2
P00 to P06, P10, P11, P31 to P33, P35, P39,
P40, P42, P50 to P55, P60 to P62, P610 to P613,
P80, P90 to P97, P99, P910, P912 to P915
EV
SS
0.2EV
DD
V
V
IL3
PCD0 to PCD3, PCM0 to PCM5, PCS0 to PCS7,
PCT0 to PCT7, PDL0 to PDL15
BV
SS
0.3BV
DD
V
V
IL4
P70 to P715, P120 to P127
AV
SS
0.3AV
REF0
V
Input voltage, low
V
IL5
RESET,
FLMD0
EV
SS
0.2EV
DD
V
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
(2/2)
Parameter Symbol
Conditions
MIN. TYP. MAX.
Unit
I
OH
=
-1.0 mA
EV
DD
- 1.0
EV
DD
V
V
OH1
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55,
P60 to P615, P80 to P81,
P90 to P915
I
OH
=
-0.1 mA
EV
DD
- 0.5
EV
DD
V
I
OH
=
-1.0 mA
BV
DD
- 1.0
BV
DD
V
V
OH2
PCD0 to PCD3, PCM0 to PCM5,
PCS0 to PCS7, PCT0 to PCT7,
PDL0 to PDL15
I
OH
=
-0.1 mA
BV
DD
- 0.5
BV
DD
V
I
OH
=
-1.0 mA
AV
REF0
- 1.0
AV
REF0
V
Output voltage,
high
Note 1
V
OH3
P70 to P715, P120 to P127
I
OH
=
-0.1 mA
AV
REF0
- 0.5
AV
REF0
V
V
OL1
P00 to P06, P10, P11, P30 to P39,
P40 to P42, P50 to P55,
P60 to P615, P80, P81,
P90 to P915
I
OL
= 10 mA
0
0.4
V
V
OL2
PCD0 to PCD3, PCM0 to PCM5,
PCS0 to PCS7, PCT0 to PCT7,
PDL0 to PDL15
I
OL
= 1.0 mA
0
0.4
V
Output voltage,
low
Note 1
V
OL3
P70 to P715, P120 to P127
I
OL
= 1.0 mA
0
0.4
V
Pull-up resistor
R
1
V
I
= 0 V
10
30
100
k
Pull-down
resistor
Note 2
R
2
V
I
= V
DD
10
30
100
k
Notes 1. The maximum value of the total of I
OH
/I
OL
is 20 mA/
-20 mA for each power supply (EV
DD
, BV
DD
, AV
REF0
).
2. DRST pin only
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
27.6.2 Pin leakage current
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Analog pin
+2.0
Input leakage current, high
I
LIH1
V
IN
= V
DD
Other than analog pin
+5.0
A
Analog pin
-2.0
Input leakage current, low
I
LIL1
V
IN
= 0 V
Other than analog pin
-0.5
A
Analog pin
+0.2
Output leakage current, high
I
LOH1
V
O
= V
DD
Other than analog pin
+5.0
A
Analog pin
-0.2
Output leakage current, low
I
LOL1
V
O
= 0 V
Other than analog pin
-5.0
A
Caution The value of the FMLD0 pin is as follows.
Input leakage current, high: 2
A (MAX)
Input leakage current, low: -2
A (MAX)
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27.6.3 Supply current
(1)
PD70F3711, 70F3712
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
All peripheral function
operating
40
55
mA
I
DD1
Normal
operation
mode
f
XX
= 20 MHz
(f
X
= 5 MHz)
All peripheral function
stopped
27
mA
All peripheral function
operating
25
35
mA
I
DD2
HALT
mode
f
XX
= 20 MHz
(f
X
= 5 MHz)
All peripheral function
stopped
14
mA
I
DD3
IDLE1
mode
f
XX
= 5 MHz (f
X
= 5 MHz), PLL off
0.6
0.9
mA
I
DD4
IDLE2
mode
f
XX
= 5 MHz (f
X
= 5 MHz), PLL off
0.25
0.7
mA
Crystal resonator (f
XT
= 32.768 kHz)
200
400
A
I
DD5
Subclock
operation
mode
Notes 2, 3
RC oscillator (f
XT
= 40 kHz
Note 4
)
200
400
A
Crystal resonator (f
XT
= 32.768 kHz)
20
120
A
I
DD6
Sub-IDLE
mode
Notes 2, 3
RC oscillator (f
XT
= 40 kHz
Note 4
)
35
140
A
POC stopped, internal oscillator stopped
7
50
A
POC operating, internal oscillator stopped
10
55
A
POC stopped, internal oscillator operating
15
65
A
Supply current
Note 1
I
DD7
Stop
mode
Notes 2, 5
POC operating, internal oscillator operating
18
70
A
Notes 1. Total current of V
DD
, EV
DD
, and BV
DD
(all ports stopped). The current of AV
REF0
and the port buffer current
including the current flowing through the on-chip pull-up/pull-down resistors are not included.
2. When the main clock oscillation is stopped.
3. POC operating, internal oscillator operating.
4. The RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2.
5. When the subclock oscillation is not used.
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
702
(2)
PD70F3709, 70F3710
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
All peripheral function
operating
30
45
mA
I
DD1
Normal
operation
mode
f
XX
= 20 MHz
(f
X
= 5 MHz)
All peripheral function
stopped
22
mA
All peripheral function
operating
18
28
mA
I
DD2
HALT
mode
f
XX
= 20 MHz
(f
X
= 5 MHz)
All peripheral function
stopped
11
mA
I
DD3
IDLE1
mode
f
XX
= 5 MHz (f
X
= 5 MHz), PLL off
0.6
0.9
mA
I
DD4
IDLE2
mode
f
XX
= 5 MHz (f
X
= 5 MHz), PLL off
0.25
0.7
mA
Crystal resonator (f
XT
= 32.768 kHz)
200
400
A
I
DD5
Subclock
operation
mode
Notes 2, 3
RC resonator (f
XT
= 40 kHz
Note 4
)
200
400
A
Crystal resonator (f
XT
= 32.768 kHz)
20
120
A
I
DD6
Sub-IDLE
mode
Notes 2, 3
RC resonator (f
XT
= 40 kHz
Note 4
)
35
140
A
POC stopped, internal oscillator stopped
7
50
A
POC operating, internal oscillator stopped
10
55
A
POC stopped, internal oscillator operating
15
65
A
Supply current
Note 1
I
DD7
Stop
mode
Notes 2, 5
POC operating, internal oscillator operating
18
70
A
Notes 1. Total current of V
DD
, EV
DD
, and BV
DD
(all ports stopped). The current of AV
REF0
and the port buffer current
including the current flowing through the on-chip pull-up/pull-down resistors are not included.
2. When the main clock oscillation is stopped.
3. POC operating, internal oscillator operating.
4. The RC oscillation frequency is 40 kHz (TYP.). This clock is internally divided by 2.
5. When the subclock oscillation is not used.
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
703
27.7 Data Retention Characteristics
STOP Mode (T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 1.9 V to 5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V)
Parameter Symbol Conditions MIN.
TYP.
MAX.
Unit
Data retention voltage
V
DDDR
In STOP mode
1.9
5.5
V
Data retention current
I
DDDR
V
DDDR
= 2.0 V
6
45
A
Supply voltage rise time
t
RVD
1
s
Supply voltage fall time
t
FVD
1
s
Supply voltage retention time
t
HVD
After STOP mode release
0
ms
STOP release signal input time
t
DREL
After V
DD
reaches MIN.: 3.5 V
0
s
Data retention input voltage, high
V
IHDR
All input ports
0.9V
DDDR
V
DDDR
V
Data retention input voltage, low
V
ILDR
All input ports
0
0.1V
DDDR
V
Caution Shifting to STOP mode and restoring from STOP mode must be performed within the rated
operating range.
t
DREL
t
HVD
t
FVD
t
RVD
STOP release signal input
STOP mode setting
V
DDDR
V
IHDR
V
IHDR
V
ILDR
V
DD
/EV
DD
/BV
DD
RESET (input)
STOP mode release interrupt (NMI, etc.)
(Released by falling edge)
STOP mode release interrupt (NMI, etc.)
(Released by rising edge)
Operating voltage lower limit (Min.)
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
704
27.8 AC Characteristics
(1) AC test input measurement points (V
DD
, AV
REF0
, EV
DD
, BV
DD
)
V
DD
V
SS
V
IH (MIN.)
V
IL (MAX.)
V
IH (MIN.)
V
IL (MAX.)
Measurement points
(2) AC test output measurement points
V
OH (MIN.)
V
OL (MAX.)
V
OH (MIN.)
V
OL (MAX.)
Measurement points
(3) Load conditions
DUT
(Device under
measurement)
C
L
= 50 pF
Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load
capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
705
27.8.1 CLKOUT Output
Timing
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions MIN.
MAX.
Unit
Output cycle
t
CYK
50 ns
80
s
High-level width
t
WKH
t
CYK
/2
- 15
ns
Low-level width
t
WKL
t
CYK
/2
- 15
ns
Rise time
t
KR
15
ns
Fall time
t
KF
15 ns
Clock Timing
CLKOUT (output)
t
CYK
t
WKH
t
WKL
t
KR
t
KF
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
706
27.8.2 Bus
Timing
(1) CLKOUT asynchronous
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
Address setup time (to ASTB
) t
SAST
(0.5 + t
ASW
)
- 20
ns
Address hold time (from ASTB
) t
HSTA
(0.5 + t
AHW
)
- 15
ns
Delay time from RD
to address float
t
FRDA
16
ns
Data input setup time from address
t
SAID
(2
+
n + t
ASW
+ t
AHW
)T
- 40
ns
Data input setup time from RD
t
SRDID
(1
+
n)T
- 30
ns
Delay time from ASTB
to RD, WRm
t
DSTRDWR
(0.5 + t
AHW
)T
- 15
ns
Data input hold time (from RD
) t
HRDID
0
ns
Address output time from RD
t
DRDA
(1
+
i )T
- 15
ns
Delay time from RD, WRm
to ASTB
t
DRDWRST
0.5T
- 15
ns
Delay time from RD
to ASTB
t
DRDST
(1.5
+
i + t
ASW
)T
- 15
ns
RD, WRm low-level width
t
WRDWRL
(1 + n)T
- 20
ns
ASTB high-level width
t
WSTH
(1
+
i + t
ASW
)T
- 15
ns
Data output time from WRm
t
DWROD
15
ns
Data output setup time (to WRm
) t
SODWR
(1 + n)T
- 25
ns
Data output hold time (from WRm
) t
HWROD
T
- 15
ns
t
SAWT1
(1.5 + t
ASW
+ t
AHW
)T
- 45
ns
WAIT setup time (to address)
t
SAWT2
n
1
(1.5 + n + t
ASW
+ t
AHW
)T
- 45
ns
t
HAWT1
(0.5 + n + t
ASW
+ t
AHW
)T
ns
WAIT hold time (from address)
t
HAWT2
n
1
(1.5 + n + t
ASW
+ t
AHW
)T
ns
t
SSTWT1
(1 + t
AHW
)T
- 35
ns
WAIT setup time (to ASTB
)
t
SSTWT2
n
1
(1 + n + t
AHW
)T
- 35
ns
t
HSTWT1
(n + t
AHW
)T
ns
WAIT hold time (from ASTB
)
t
HSTWT2
n
1
(1 + n + t
AHW
)T
ns
HLDRQ high-level width
t
WHQH
T + 10
ns
HLDAK low-level width
t
WHAL
T
- 20
ns
Delay time from HLDAK
to bus output
t
DHAC
3
ns
Delay time from HLDRQ
to HLDAK
t
DHQHA1
(2n + 7.5)T + 25
ns
Delay time from HLDRQ
to HLDAK
t
DHQHA2
0.5T
1.5T + 35
ns
Remarks 1. T = 1/f
CPU
(f
CPU
: CPU operating clock frequency)
2. n: Number of wait clocks inserted in the bus cycle.
The sampling timing changes when a programmable wait is inserted.
3. m = 0, 1
4. i: Number of idle states inserted after a read cycle (0 or 1).
5. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from
X1.
6. t
ASW
: Number of address setup wait clocks (0 or 1)
t
AHW
: Number of address hold wait clocks (0 or 1)
CHAPTER
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ELECTRICAL
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Preliminary User's Manual U17717EJ2V0UD
707
(2) CLKOUT synchronous
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
Delay time from CLKOUT
to address
t
DKA
0
24
ns
Delay time from CLKOUT
to address float t
FKA
0
24
ns
Delay time from CLKOUT
to ASTB
t
DKST
-12 +12
ns
Delay time from CLKOUT
to RD, WRm
t
DKRDWR
-5 14
ns
Data input setup time (to CLKOUT
) t
SIDK
20
ns
Data input hold time (from CLKOUT
) t
HKID
5
ns
Data output delay time from CLKOUT
t
DKOD
22
ns
WAIT setup time (to CLKOUT
) t
SWTK
30
ns
WAIT hold time (from CLKOUT
) t
HKWT
5
ns
HLDRQ setup time (to CLKOUT
) t
SHQK
30
ns
HLDRQ hold time (from CLKOUT
) t
HKHQ
5
ns
Delay time from CLKOUT
to HLDAK
t
DKHA
24
ns
Delay time from CLKOUT
to bus float
t
DKF
25
ns
Remarks 1. m = 0, 1
2. The values in the above specifications are values for when clocks with a 1:1 duty ratio are input from X1.
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
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Preliminary User's Manual U17717EJ2V0UD
708
Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
CLKOUT (output)
AD0 to AD15 (I/O)
ASTB (output)
RD (output)
WAIT (input)
T1
T2
TW
T3
Address
Hi-Z
t
DKA
t
DKST
t
SAST
t
HSTA
t
WSTH
t
FKA
t
SAID
t
DKST
t
HRDID
t
DRDWRST
t
DKRDWR
t
SRDID
t
DSTRDWR
t
SSTWT1
t
SWTK
t
HSTWT1
t
SSTWT2
t
HSTWT2
t
SAWT1
t
HAWT1
t
SAWT2
t
HAWT2
t
SWTK
t
HKWT
t
HKWT
t
WRDWRL
t
DRDA
t
DRDST
t
SIDK
t
HKID
t
DKRDWR
t
FRDA
Data
Remark WR0 and WR1 are high level.
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
709
Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)
CLKOUT (output)
AD0 to AD15 (I/O)
ASTB (output)
WR0 (output),
WR1 (output)
WAIT (input)
T1
T2
TW
T3
Data
Address
t
DKA
t
DKST
t
DKRDWR
t
DKRDWR
t
HKWT
t
HKWT
t
SWTK
t
SSTWT1
t
HSTWT1
t
SSTWT2
t
HSTWT2
t
SAWT1
t
HAWT1
t
SAWT2
t
HAWT2
t
SAST
t
WSTH
t
DRDWRST
t
HWROD
t
SODER
t
WRDWRL
t
DSTRDWR
t
DWROD
t
DKST
t
DKOD
t
HSTA
t
SWTK
Remark RD is high level.
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
710
Bus Hold
CLKOUT (output)
HLDRQ (input)
HLDAK (output)
AD0 to AD15 (I/O)
ASTB (output)
RD (output),
WR0 (output), WR1 (output)
TH
TH
TH
TI
Hi-Z
Hi-Z
Data
Hi-Z
t
SHQK
t
SHQK
t
DKF
t
DKF
t
HKHQ
t
WHQH
t
DHQHA2
t
WHAL
t
DHAC
t
DHQHA1
t
DKHA
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
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Preliminary User's Manual U17717EJ2V0UD
711
27.9 Basic Operation
(1) Reset, interrupt timing
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX. Unit
RESET low-level width
t
WRSL
500
ns
NMI high-level width
t
WNIH
Analog noise elimination
500
ns
NMI low-level width
t
WNIL
Analog noise elimination
500
ns
Analog noise elimination (n = 0 to 14)
500
ns
INTPn
Note 1
high-level width t
WITH
Digital noise elimination (n = 3)
Note 2
ns
Analog noise elimination (n = 0 to 14)
500
ns
INTPn
Note 1
low-level width
t
WITL
Digital noise elimination (n = 3)
Note 2
ns
Notes 1. The same value as the INTP0/P03 pin applies in the case of the ADTRG pin. The same value as the
INTP2/P05 pin applies in the case of the DRST pin.
2. 2T
samp
+ 20 or 3T
samp
+ 20
T
samp
: Sampling clock for noise elimination
Reset/Interrupt
t
REG
t
WNIH
t
WRSL
V
DD
RESET (input)
NMI (input)
INTPn (input)
t
WNIL
t
WITH
t
WITL
Remark n = 0 to 14
CHAPTER
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ELECTRICAL
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Preliminary User's Manual U17717EJ2V0UD
712
(2) Key interrupt timing
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
KRn input high-level width
t
WKRH
500
ns
KRn input low-level width
t
WKRL
Analog noise elimination (n = 0 to 7)
500
ns
t
WKRH
KRn (input)
t
WKRL
Remark n = 0 to 7
(3) Timer input timing
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
TIn high-level width
t
TIH
Note 2
ns
TIn low-level width
t
TIL
TIP00, TIP01, TIP10, TIP11, TIP20,
TIP21, TIP30, TIP31,
TIQ00 to TIQ03, TIQ10 to TIQ13,
TIQ20 to TIQ23
Note 1
Note 2
ns
Notes 1. Noise on the TIP00, TIP10, TIP20, TIP30, TIQ00, TIQ10, and TIQ20 pins can be eliminated only when a
capture signal is input.
The noise cannot be eliminated when an external trigger signal or an external event counter signal is input.
2. 2T
samp
+ 20 or 3T
samp
+ 20
T
samp
: Sampling clock for noise elimination
t
TIH
TIn (input)
t
TIL
Remark TIn: TIP00, TIP01, TIP10 TIP11, TIP20, TIP21, TIP30, TIP31, TIQ00 to TIQ03, TIQ10 to TIQ13,
TIQ20 to TIQ23
CHAPTER
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713
(4) CSIB timing
(a) Master mode
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
SCKBn cycle time
t
KCYn
125
ns
SCKBn high-level width
t
KHn
t
KCYn
/2
- 15
ns
SCKBn low-level width
t
KLn
t
KCYn
/2
- 15
ns
SIBn setup time (to SCKBn
) t
SIKn
30
ns
SIBn hold time (from SCKBn
) t
KSIn
25
ns
Output delay time from SCKBn
to SOBn
t
KSOn
25
ns
Remark n = 0 to 2
(b) Slave mode
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
MAX.
Unit
SCKBn cycle time
t
KCYn
200
ns
SCKBn high-level width
t
KHn
90
ns
SCKBn low-level width
t
KLn
90
ns
SIBn setup time (to SCKBn
) t
SIKn
50
ns
SIBn hold time (from SCKBn
) t
KSIn
50
ns
Output delay time from SCKBn
to SOBn
t
KSOn
50
ns
Remark n = 0 to 2
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
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Preliminary User's Manual U17717EJ2V0UD
714
t
KLn
t
SIKn
t
KSIn
t
KSOn
t
KCYn
t
KHn
SOBn (output)
Input data
Output data
SIBn (input)
SCKBn (I/O)
Hi-Z
Remark n = 0 to 2
(5) UARTA timing
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol Conditions MIN.
MAX.
Unit
Communication rate
312.5
kbps
ASCK0 cycle time
10
MHz
(6) A/D converter
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
bit
Overall error
Note
4.0
AV
REF0
5.5 V
0.15
0.3 %FSR
Conversion time
t
CONV
3.1
16
s
Analog input voltage
V
IAN
AV
SS
AV
REF0
V
When using A/D converter
5
10
mA
AV
REF0
current
I
AREF0
When not using A/D converter
1
10
A
Note Excluding quantization error (
0.05 %FSR). Indicates the ratio to the full-scale value (%FSR).
Remark FSR: Full Scale Range
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
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Preliminary User's Manual U17717EJ2V0UD
715
(7) POC circuit characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Detection voltage
V
POC0
3.5
3.7
3.9
V
Power supply startup time
t
PTH
V
DD
= 0 V
3.5 V
0.002
ms
Response delay time 1
Note 1
t
PTHD
After V
DD
reaches 3.9 V on power
application
3.0
ms
Response delay time 2
Note 2
t
PD
After V
DD
drops below 3.5 V on
power drop
1
ms
Minimum V
DD
width
t
PW
0.2
ms
Notes 1. The time required to release a reset after the detection voltage is detected.
2. The time required to output a reset after the detection voltage is detected.
t
PTH
t
PTHD
V
DD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
t
PW
t
PD
t
PTHD
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
716
(8) LVI circuit characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol Conditions MIN.
TYP.
MAX.
Unit
V
LVI0
4.2 4.4 4.6
V
Detection voltage
V
LVI1
4.0 4.2 4.4
V
Response time
Note 1
t
LD
After V
DD
reaches V
LVI0
/V
LVI1
(MAX.) or drops below V
LVI0
/V
LVI1
(MIN.)
0.2 2 ms
Minimum V
DD
width
t
LW
0.2
ms
Reference voltage stabilization
wait time
Note 2
t
LWAIT
After V
DD
reaches 3.5 V or
LVION bit (LVIM.bit7) changes
from 0 to 1
0.1
0.2
ms
Notes 1. The time required to output an interrupt/reset after the detection voltage is detected.
2. Unnecessary when the POC function is used.
t
LWAIT
LVION bit = 0
1
V
DD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Time
t
LW
t
LD
t
LD
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
717
(9) RAM retention flag characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol Conditions
MIN.
TYP.
MAX.
Unit
Detection voltage
V
RAMH
1.9
2.0
2.1
V
Supply voltage rise time
t
RAMHTH
V
DD
= 0 V
3.5 V
0.002
1800
ms
Response time
Note
t
RAMHD
After the supply voltage reaches
the detection voltage (MAX.)
0.2
2.0
ms
Minimum V
DD
width
t
RAMHW
0.2
ms
Note Time required to set the RAMF bit after the detection voltage is detected.
t
RAMHD
V
DD
Detection voltage (MAX.)
Detection voltage (TYP.)
Detection voltage (MIN.)
Operating voltage (MIN.)
Time
t
RAMHW
t
RAMHTH
t
RAMHD
CHAPTER
27
ELECTRICAL
SPECIFICATIONS
(TARGET)
Preliminary User's Manual U17717EJ2V0UD
718
27.10 Flash Memory Programming Characteristics
(1) Basic characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions MIN.
TYP.
MAX.
Unit
Operating frequency
f
CPU
4
20 MHz
Supply voltage
V
DD
3.5
5.5 V
Number of writes
C
WRT
Note
100
Times
Input voltage, high
V
IH
FLMD0
0.8EV
DD
EV
DD
V
Input voltage, low
V
IL
FLMD0
EV
SS
0.2EV
SS
V
Write time + erase time
t
IWRT
+
t
ERASE
TBD
s
Programming temperature
t
PRG
-40 +85 C
Note When writing initially to shipped products, it is counted as one rewrite for both "erase to write" and "write only".
Example (P: Write, E: Erase)
Shipped
product
P E P E P: 3 rewrites
Shipped
product
E P E P E P: 3 rewrites
(2) Serial write operation characteristics
(T
A
=
-40 to +85C, V
DD
= EV
DD
= BV
DD
= 3.5 V to 5.5 V, 4.0 V
AV
REF0
5.5 V, V
SS
= EV
SS
= BV
SS
= AV
SS
= 0 V, C
L
= 50 pF)
Parameter Symbol
Conditions MIN.
TYP.
MAX.
Unit
FLMD0 setup time from RESET
t
RFCF
70536/f
X
s
Count execution time
t
COUNT
3
ms
FLMD0 high-level width
t
CH
10
100
s
FLMD0 low-level width
t
CL
10 100
s
FLMD0 rise time
t
R
50 ns
FLMD0 fall time
t
F
50 ns
L
V
SS
V
DD
RESET
FLMD0
FLMD1
V
SS
V
DD
V
SS
V
DD
t
COUNT
t
RFCF
t
CL
t
F
t
R
t
CH
Preliminary User's Manual U17717EJ2V0UD
719
CHAPTER 28 PACKAGE DRAWING
108
73
1
36
109
144
72
37
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
ITEM
MILLIMETERS
NOTE
A
22.0
0.2
B
20.0
0.2
C
20.0
0.2
D
F
1.25
22.0
0.2
S144GJ-50-UEN
S
1.5
0.1
K
1.0
0.2
L
0.5
0.2
R
3
+4
-3
G
1.25
H
0.22
0.05
I
0.08
J
0.5 (T.P.)
M
0.17
N
0.08
P
1.4
Q
0.10
0.05
+0.03
-0.07
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
S
S
M
detail of lead end
I
J
F
G
H
Q
R
P
K
M
L
N
C
D
S
A
B
Preliminary User's Manual U17717EJ2V0UD
720
APPENDIX A REGISTER INDEX
(1/11)
Symbol Name Unit
Page
ADA0CR0
A/D conversion result register 0
ADC
466
ADA0CR0H
A/D conversion result register 0H
ADC
466
ADA0CR1
A/D conversion result register 1
ADC
466
ADA0CR1H
A/D conversion result register 1H
ADC
466
ADA0CR10
A/D conversion result register 10
ADC
466
ADA0CR10H
A/D conversion result register 10H
ADC
466
ADA0CR11
A/D conversion result register 11
ADC
466
ADA0CR11H
A/D conversion result register 11H
ADC
466
ADA0CR12
A/D conversion result register 12
ADC
466
ADA0CR12H
A/D conversion result register 12H
ADC
466
ADA0CR13
A/D conversion result register 13
ADC
466
ADA0CR13H
A/D conversion result register 13H
ADC
466
ADA0CR14
A/D conversion result register 14
ADC
466
ADA0CR14H
A/D conversion result register 14H
ADC
466
ADA0CR15
A/D conversion result register 15
ADC
466
ADA0CR15H
A/D conversion result register 15H
ADC
466
ADA0CR16
A/D conversion result register 16
ADC
466
ADA0CR16H
A/D conversion result register 16H
ADC
466
ADA0CR17
A/D conversion result register 17
ADC
466
ADA0CR17H
A/D conversion result register 17H
ADC
466
ADA0CR18
A/D conversion result register 18
ADC
466
ADA0CR18H
A/D conversion result register 18H
ADC
466
ADA0CR19
A/D conversion result register 19
ADC
466
ADA0CR19H
A/D conversion result register 19H
ADC
466
ADA0CR2
A/D conversion result register 2
ADC
466
ADA0CR2H
A/D conversion result register 2H
ADC
466
ADA0CR20
A/D conversion result register 20
ADC
466
ADA0CR20H
A/D conversion result register 20H
ADC
466
ADA0CR21
A/D conversion result register 21
ADC
466
ADA0CR21H
A/D conversion result register 21H
ADC
466
ADA0CR22
A/D conversion result register 22
ADC
466
ADA0CR22H
A/D conversion result register 22H
ADC
466
ADA0CR23
A/D conversion result register 23
ADC
466
ADA0CR23H
A/D conversion result register 23H
ADC
466
ADA0CR3
A/D conversion result register 3
ADC
466
ADA0CR3H
A/D conversion result register 3H
ADC
466
ADA0CR4
A/D conversion result register 4
ADC
466
ADA0CR4H
A/D conversion result register 4H
ADC
466
ADA0CR5
A/D conversion result register 5
ADC
466
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
721
(2/11)
Symbol Name Unit
Page
ADA0CR5H
A/D conversion result register 5H
ADC
466
ADA0CR6
A/D conversion result register 6
ADC
466
ADA0CR6H
A/D conversion result register 6H
ADC
466
ADA0CR7
A/D conversion result register 7
ADC
466
ADA0CR7H
A/D conversion result register 7H
ADC
466
ADA0CR8
A/D conversion result register 8
ADC
466
ADA0CR8H
A/D conversion result register 8H
ADC
466
ADA0CR9
A/D conversion result register 9
ADC
466
ADA0CR9H
A/D conversion result register 9H
ADC
466
ADA0M0
A/D converter mode register 0
ADC
461
ADA0M1
A/D converter mode register 1
ADC
463
ADA0M2
A/D converter mode register 2
ADC
464
ADA0PFM
Power-fail compare mode register
ADC
468
ADA0PFT
Power-fail compare threshold value register
ADC
468
ADA0S
A/D converter channel specification register 0
ADC
465
ADIC
Interrupt control register
INTC
594
AWC
Address wait control register
BCU
209
BCC
Bus cycle control register
BCU
210
BSC
Bus size configuration register bus
BCU
199
CB0CTL0
CSIB0 control register 0
CSI
526
CB0CTL1
CSIB0 control register 1
CSI
529
CB0CTL2
CSIB0 control register 2
CSI
530
CB0RIC
Interrupt control register
INTC
594
CB0RX
CSIB0 receive data register
CSI
525
CB0RXL
CSIB0 receive data register L
CSI
525
CB0STR
CSIB0 status register
CSI
532
CB0TIC
Interrupt control register
INTC
594
CB0TX
CSIB0 transmit data register
CSI
525
CB0TXL
CSIB0 transmit data register L
CSI
525
CB1CTL0
CSIB1 control register 0
CSI
526
CB1CTL1
CSIB1 control register 1
CSI
529
CB1CTL2
CSIB1 control register 2
CSI
530
CB1RIC
Interrupt control register
INTC
594
CB1RX
CSIB1 receive data register
CSI
525
CB1RXL
CSIB1 receive data register L
CSI
525
CB1STR
CSIB1 status register
CSI
532
CB1TIC
Interrupt control register
INTC
594
CB1TX
CSIB1 transmit data register
CSI
525
CB1TXL
CSIB1 transmit data register L
CSI
525
CB2CTL0
CSIB2 control register 0
CSI
526
CB2CTL1
CSIB2 control register 1
CSI
529
CB2CTL2
CSIB2 control register 2
CSI
530
CB2RIC
Interrupt control register
INTC
595
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
722
(3/11)
Symbol Name Unit
Page
CB2RX
CSIB2 receive data register
CSI
525
CB2RXL
CSIB2 receive data register L
CSI
525
CB2STR
CSIB2 status register
CSI
532
CB2TIC
Interrupt control register
INTC
595
CB2TX
CSIB2 transmit data register
CSI
525
CB2TXL
CSIB2 transmit data register L
CSI
525
CCLS
CPU operation clock status register
CG
224
CLM
Clock monitor mode register
CLM
646
CTBP
CALL base pointer
CPU
56
CTPC
CALLT execution status saving register
CPU
55
CTPSW
CALLT execution status saving register
CPU
55
DADC0
DMA addressing control register 0
DMA
558
DADC1
DMA addressing control register 1
DMA
558
DADC2
DMA addressing control register 2
DMA
558
DADC3
DMA addressing control register 3
DMA
558
DBC0
DMA transfer count register 0
DMA
557
DBC1
DMA transfer count register 1
DMA
557
DBC2
DMA transfer count register 2
DMA
557
DBC3
DMA transfer count register 3
DMA
557
DBPC
Exception/debug trap status saving register
CPU
56
DBPSW
Exception/debug trap status saving register
CPU
56
DCHC0
DMA channel control register 0
DMA
559
DCHC1
DMA channel control register 1
DMA
559
DCHC2
DMA channel control register 2
DMA
559
DCHC3
DMA channel control register 3
DMA
559
DDA0H
DMA destination address register 0H
DMA
556
DDA0L
DMA destination address register 0L
DMA
556
DDA1H
DMA destination address register 1H
DMA
556
DDA1L
DMA destination address register 1L
DMA
556
DDA2H
DMA destination address register 2H
DMA
556
DDA2L
DMA destination address register 2L
DMA
556
DDA3H
DMA destination address register 3H
DMA
556
DDA3L
DMA destination address register 3L
DMA
556
DMAIC0
Interrupt control register
INTC
595
DMAIC1
Interrupt control register
INTC
595
DMAIC2
Interrupt control register
INTC
595
DMAIC3
Interrupt control register
INTC
595
DSA0H
DMA source address register 0H
DMA
555
DSA0L
DMA source address register 0L
DMA
555
DSA1H
DMA source address register 1H
DMA
555
DSA1L
DMA source address register 1L
DMA
555
DSA2H
DMA source address register 2H
DMA
555
DSA2L
DMA source address register 2L
DMA
555
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
723
(4/11)
Symbol Name Unit
Page
DSA3H
DMA source address register 3H
DMA
555
DSA3L
DMA source address register 3L
DMA
555
DTFR0
DMA trigger factor register 0
DMA
560
DTFR1
DMA trigger factor register 1
DMA
560
DTFR2
DMA trigger factor register 2
DMA
560
DTFR3
DMA trigger factor register 3
DMA
560
DWC0
Data wait control register 0
BCU
207
ECR
Interrupt source register
CPU
53
EIPC
Interrupt status saving register
CPU
52
EIPSW
Interrupt status saving register
CPU
52
FEPC
NMI status saving register
CPU
53
FEPSW
NMI status saving register
CPU
53
IMR0
Interrupt mask register 0
INTC
595
IMR0H
Interrupt mask register 0H
INTC
595
IMR0L
Interrupt mask register 0L
INTC
595
IMR1
Interrupt mask register 1
INTC
595
IMR1H
Interrupt mask register 1H
INTC
595
IMR1L
Interrupt mask register 1L
INTC
595
IMR2
Interrupt mask register 2
INTC
595
IMR2H
Interrupt mask register 2H
INTC
595
IMR2L
Interrupt mask register 2L
INTC
595
IMR3
Interrupt mask register 3
INTC
595
IMR3H
Interrupt mask register 3H
INTC
595
IMR3L
Interrupt mask register 3L
INTC
595
IMR4
Interrupt mask register 4
INTC
595
IMR4H
Interrupt mask register 4H
INTC
595
IMR4L
Interrupt mask register 4L
INTC
595
INTF0
External interrupt falling edge specification register 0
INTC
95, 607
INTF1
External interrupt falling edge specification register 1
INTC
100, 608
INTF3
External interrupt falling edge specification register 3
INTC
106, 609
INTF3H
External interrupt falling edge specification register 3H
INTC
106, 609
INTF3L
External interrupt falling edge specification register 3L
INTC
106, 609
INTF6L
External interrupt falling edge specification register 6L
INTC
123, 610
INTF8
External interrupt falling edge specification register 8
INTC
130, 611
INTF9H
External interrupt falling edge specification register 9H
INTC
140, 612
INTR0
External interrupt rising edge specification register 0
INTC
95, 607
INTR1
External interrupt rising edge specification register 1
INTC
100, 608
INTR3
External interrupt rising edge specification register 3
INTC
107, 609
INTR3H
External interrupt rising edge specification register 3H
INTC
107, 609
INTR3L
External interrupt rising edge specification register 3L
INTC
107, 609
INTR6L
External interrupt rising edge specification register 6L
INTC
124, 610
INTR8
External interrupt rising edge specification register 8
INTC
130, 611
INTR9H
External interrupt rising edge specification register 9H
INTC
140, 612
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
724
(5/11)
Symbol Name Unit
Page
ISPR
In-service priority register
INTC
597
KRIC
Interrupt control register
INTC
594
KRM
Key return mode register
KR
618
LOCKR Lock
register
CG 227
LVIIC
Interrupt control register
INTC
594
LVIM Low-voltage
detection
register
LVI
653
LVIS
Low-voltage detection level select register
LVI
654
NFC
Noise elimination control register
INTC
613
OCDM
On-chip debug mode register
Debug
688
OSTS
Oscillation stabilization time select register
WDT
623
P0 Port
0
Port
92
P00NFC
TIP00 pin noise elimination control register
Timer
247
P01NFC
TIP01 pin noise elimination control register
Timer
247
P1 Port
1
Port
98
P10NFC
TIP10 pin noise elimination control register
Timer
247
P11NFC
TIP11 pin noise elimination control register
Timer
247
P12 Port
12
Port
143
P20NFC
TIP20 pin noise elimination control register
Timer
247
P21NFC
TIP21 pin noise elimination control register
Timer
247
P3 Port
3
Port
102
P30NFC
TIP30 pin noise elimination control register
Timer
247
P31NFC
TIP31 pin noise elimination control register
Timer
247
P3H Port
3H
Port
102
P3L Port
3L
Port
102
P4 Port
4
Port
109
P5 Port
5
Port
112
P6 Port
6
Port
118
P6H Port
6H
Port
118
P6L Port
6L
Port
118
P7H Port
7H
Port
126
P7L Port
7L
Port
126
P8 Port
8
Port
128
P9 Port
9
Port
132
P9H Port
9H
Port
132
P9L Port
9L
Port
132
PC Program
counter
CPU
50
PCC
Processor clock control register
CG
220
PCD Port
CD
Port
145
PCLM
Programmable clock mode register
CG
229
PCM Port
CM
Port
147
PCS Port
CS
Port
150
PCT Port
CT
Port
153
PDL Port
DL
Port
156
PDLH Port
DLH
Port
156
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
725
(6/11)
Symbol Name Unit
Page
PDLL Port
DLL
Port
156
PEMU1
Peripheral emulation register 1
LVI
659
PFC0
Port function control register 0
Port
94
PFC3L
Port function control register 3L
Port
104
PFC5
Port function control register 5
Port
114
PFC6
Port function control register 6
Port
121
PFC6H
Port function control register 6H
Port
121
PFC6L
Port function control register 6L
Port
121
PFC9
Port function control register 9
Port
135
PFC9H
Port function control register 9H
Port
135
PFC9L
Port function control register 9L
Port
135
PFCE3L
Port function control expansion register 3L
Port
105
PFCE5
Port function control expansion register 5
Port
114
PFCE9
Port function control expansion register 9
Port
136
PFCE9H
Port function control expansion register 9H
Port
136
PFCE9L
Port function control expansion register 9L
Port
136
PIC0
Interrupt control register
INTC
594
PIC1
Interrupt control register
INTC
594
PIC10
Interrupt control register
INTC
594
PIC11
Interrupt control register
INTC
595
PIC12
Interrupt control register
INTC
595
PIC13
Interrupt control register
INTC
595
PIC14
Interrupt control register
INTC
595
PIC2
Interrupt control register
INTC
594
PIC3
Interrupt control register
INTC
594
PIC4
Interrupt control register
INTC
594
PIC5
Interrupt control register
INTC
594
PIC6
Interrupt control register
INTC
594
PIC7
Interrupt control register
INTC
594
PIC8
Interrupt control register
INTC
594
PIC9
Interrupt control register
INTC
594
PLLCTL
PLL control register
CG
226
PLLS
PLL lockup time specification register
CG
228
PM0
Port mode register 0
Port
92
PM1
Port mode register 1
Port
98
PM12
Port mode register 12
Port
143
PM3
Port mode register 3
Port
102
PM3H
Port mode register 3H
Port
102
PM3L
Port mode register 3L
Port
102
PM4
Port mode register 4
Port
109
PM5
Port mode register 5
Port
112
PM6
Port mode register 6
Port
118
PM6H
Port mode register 6H
Port
118
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
726
(7/11)
Symbol Name Unit
Page
PM6L
Port mode register 6L
Port
118
PM7H
Port mode register 7H
Port
126
PM7L
Port mode register 7L
Port
126
PM8
Port mode register 8
Port
128
PM9
Port mode register 9
Port
132
PM9H
Port mode register 9H
Port
132
PM9L
Port mode register 9L
Port
132
PMC0
Port mode control register 0
Port
93
PMC1
Port mode control register 1
Port
99
PMC3
Port mode control register 3
Port
103
PMC3H
Port mode control register 3H
Port
103
PMC3L
Port mode control register 3L
Port
103
PMC4
Port mode control register 4
Port
110
PMC5
Port mode control register 5
Port
113
PMC6
Port mode control register 6
Port
119
PMC6H
Port mode control register 6H
Port
119
PMC6L
Port mode control register 6L
Port
119
PMC8
Port mode control register 8
Port
129
PMC9
Port mode control register 9
Port
133
PMC9H
Port mode control register 9H
Port
133
PMC9L
Port mode control register 9L
Port
133
PMCCM
Port mode control register CM
Port
148
PMCCS
Port mode control register CS
Port
151
PMCCT
Port mode control register CT
Port
154
PMCD
Port mode register CD
Port
145
PMCDL
Port mode control register DL
Port
157
PMCDLH
Port mode control register DLH
Port
157
PMCDLL
Port mode control register DLL
Port
157
PMCM
Port mode register CM
Port
147
PMCS
Port mode register CS
Port
150
PMCT
Port mode register CT
Port
153
PMDL
Port mode register DL
Port
156
PMDLH
Port mode register DLH
Port
156
PMDLL
Port mode register DLL
Port
156
PRCMD Command
register
CPU
82
PRSCM0
Prescaler compare register 0
WT
445, 551
PRSM0
Prescaler mode register 0
WT
444, 550
PSC
Power save control register
CG
621
PSMR
Power save mode register
CG
622
PSW Program
status
word
CPU
54
PU0
Pull-up resistor option register 0
Port
94
PU1
Pull-up resistor option register 1
Port
99
PU3
Pull-up resistor option register 3
Port
106
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
727
(8/11)
Symbol Name Unit
Page
PU3H
Pull-up resistor option register 3H
Port
106
PU3L
Pull-up resistor option register 3L
Port
106
PU4
Pull-up resistor option register 4
Port
110
PU5
Pull-up resistor option register 5
Port
116
PU6
Pull-up resistor option register 6
Port
123
PU6H
Pull-up resistor option register 6H
Port
123
PU6L
Pull-up resistor option register 6L
Port
123
PU8
Pull-up resistor option register 8
Port
129
PU9
Pull-up resistor option register 9
Port
140
PU9H
Pull-up resistor option register 9H
Port
140
PU9L
Pull-up resistor option register 9L
Port
140
Q00NFC
TIQ00 pin noise elimination control register
Timer
347
Q01NFC
TIQ01 pin noise elimination control register
Timer
347
Q02NFC
TIQ02 pin noise elimination control register
Timer
347
Q03NFC
TIQ03 pin noise elimination control register
Timer
347
Q10NFC
TIQ10 pin noise elimination control register
Timer
347
Q11NFC
TIQ11 pin noise elimination control register
Timer
347
Q12NFC
TIQ12 pin noise elimination control register
Timer
347
Q13NFC
TIQ13 pin noise elimination control register
Timer
347
Q20NFC
TIQ20 pin noise elimination control register
Timer
347
Q21NFC
TIQ21 pin noise elimination control register
Timer
347
Q22NFC
TIQ22 pin noise elimination control register
Timer
347
Q23NFC
TIQ23 pin noise elimination control register
Timer
347
r0 to r31
General-purpose register
CPU
50
RAMS
Internal RAM data status register
CG
654
RCM
Internal oscillation mode register
CG
224
RESF
Reset source flag register
CG
640
SELCNT0
Selector operation control register 0
Timer
324
SYS System
status
register
CPU
83
TM0CMP0
TMM0 compare register 0
Timer
434
TM0CTL0
TMM0 control register 0
Timer
435
TM0EQIC0
Interrupt control register
INTC
594
TP0CCIC0
Interrupt control register
INTC
594
TP0CCIC1
Interrupt control register
INTC
594
TP0CCR0
TMP0 capture/compare register 0
Timer
242
TP0CCR1
TMP0 capture/compare register 1
Timer
244
TP0CNT
TMP0 counter read buffer register
Timer
246
TP0CTL0
TMP0 control register 0
Timer
235
TP0CTL1
TMP0 control register 1
Timer
236
TP0IOC0
TMP0 I/O control register 0
Timer
238
TP0IOC1
TMP0 I/O control register 1
Timer
239
TP0IOC2
TMP0 I/O control register 2
Timer
240
TP0OPT0
TMP0 option register 0
Timer
241
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
728
(9/11)
Symbol Name Unit
Page
TP0OVIC
Interrupt control register
INTC
594
TP1CCIC0
Interrupt control register
INTC
594
TP1CCIC1
Interrupt control register
INTC
594
TP1CCR0
TMP1 capture/compare register 0
Timer
242
TP1CCR1
TMP1 capture/compare register 1
Timer
244
TP1CNT
TMP1 counter read buffer register
Timer
246
TP1CTL0
TMP1 control register 0
Timer
235
TP1CTL1
TMP1 control register 1
Timer
236
TP1IOC0
TMP1 I/O control register 0
Timer
238
TP1IOC1
TMP1 I/O control register 1
Timer
239
TP1IOC2
TMP1 I/O control register 2
Timer
240
TP1OPT0
TMP1 option register 0
Timer
241
TP1OVIC
Interrupt control register
INTC
594
TP2CCIC0
Interrupt control register
INTC
594
TP2CCIC1
Interrupt control register
INTC
594
TP2CCR0
TMP2 capture/compare register 0
Timer
242
TP2CCR1
TMP2 capture/compare register 1
Timer
244
TP2CNT
TMP2 counter read buffer register
Timer
246
TP2CTL0
TMP2 control register 0
Timer
235
TP2CTL1
TMP2 control register 1
Timer
236
TP2IOC0
TMP2 I/O control register 0
Timer
238
TP2IOC1
TMP2 I/O control register 1
Timer
239
TP2IOC2
TMP2 I/O control register 2
Timer
240
TP2OPT0
TMP2 option register 0
Timer
241
TP2OVIC
Interrupt control register
INTC
594
TP3CCIC0
Interrupt control register
INTC
594
TP3CCIC1
Interrupt control register
INTC
594
TP3CCR0
TMP3 capture/compare register 0
Timer
242
TP3CCR1
TMP3 capture/compare register 1
Timer
244
TP3CNT
TMP3 counter read buffer register
Timer
246
TP3CTL0
TMP3 control register 0
Timer
235
TP3CTL1
TMP3 control register 1
Timer
236
TP3IOC0
TMP3 I/O control register 0
Timer
238
TP3IOC1
TMP3 I/O control register 1
Timer
239
TP3IOC2
TMP3 I/O control register 2
Timer
240
TP3OPT0
TMP3 option register 0
Timer
241
TP3OVIC
Interrupt control register
INTC
594
TQ0CCIC0
Interrupt control register
INTC
594
TQ0CCIC1
Interrupt control register
INTC
594
TQ0CCIC2
Interrupt control register
INTC
594
TQ0CCIC3
Interrupt control register
INTC
594
TQ0CCR0
TMQ0 capture/compare register 0
Timer
338
TQ0CCR1
TMQ0 capture/compare register 1
Timer
340
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
729
(10/11)
Symbol Name Unit
Page
TQ0CCR2
TMQ0 capture/compare register 2
Timer
342
TQ0CCR3
TMQ0 capture/compare register 3
Timer
344
TQ0CNT
TMQ0 counter read buffer register
Timer
346
TQ0CTL0
TMQ0 control register 0
Timer
331
TQ0CTL1
TMQ0 control register 1
Timer
332
TQ0IOC0
TMQ0 I/O control register 0
Timer
334
TQ0IOC1
TMQ0 I/O control register 1
Timer
335
TQ0IOC2
TMQ0 I/O control register 2
Timer
336
TQ0OPT0
TMQ0 option register 0
Timer
337
TQ0OVIC
Interrupt control register
INTC
594
TQ1CCIC0
Interrupt control register
INTC
595
TQ1CCIC1
Interrupt control register
INTC
595
TQ1CCIC2
Interrupt control register
INTC
595
TQ1CCIC3
Interrupt control register
INTC
595
TQ1CCR0
TMQ1 capture/compare register 0
Timer
338
TQ1CCR1
TMQ1 capture/compare register 1
Timer
340
TQ1CCR2
TMQ1 capture/compare register 2
Timer
342
TQ1CCR3
TMQ1 capture/compare register 3
Timer
344
TQ1CNT
TMQ1 counter read buffer register
Timer
346
TQ1CTL0
TMQ1 control register 0
Timer
331
TQ1CTL1
TMQ1 control register 1
Timer
332
TQ1IOC0
TMQ1 I/O control register 0
Timer
334
TQ1IOC1
TMQ1 I/O control register 1
Timer
335
TQ1IOC2
TMQ1 I/O control register 2
Timer
336
TQ1OPT0
TMQ1 timer option register 0
Timer
337
TQ1OVIC
Interrupt control register
INTC
595
TQ2CCIC0
Interrupt control register
INTC
595
TQ2CCIC1
Interrupt control register
INTC
595
TQ2CCIC2
Interrupt control register
INTC
595
TQ2CCIC3
Interrupt control register
INTC
595
TQ2CCR0
TMQ2 capture/compare register 0
Timer
338
TQ2CCR1
TMQ2 capture/compare register 1
Timer
340
TQ2CCR2
TMQ2 capture/compare register 2
Timer
342
TQ2CCR3
TMQ2 capture/compare register 3
Timer
344
TQ2CNT
TMQ2 counter read buffer register
Timer
346
TQ2CTL0
TMQ2 I/O control register 0
Timer
331
TQ2CTL1
TMQ2 I/O control register 1
Timer
332
TQ2IOC0
TMQ2 I/O control register 0
Timer
334
TQ2IOC1
TMQ2 I/O control register 1
Timer
335
TQ2IOC2
TMQ2 I/O control register 2
Timer
336
TQ2OPT0
TMQ2 option register 0
Timer
337
TQ2OVIC
Interrupt control register
INTC
595
UA0CTL0
UARTA0 control register 0
UART
493
APPENDIX A REGISTER INDEX
Preliminary User's Manual U17717EJ2V0UD
730
(11/11)
Symbol Name Unit
Page
UA0CTL1
UARTA0 control register 1
UART
515
UA0CTL2
UARTA0 control register 2
UART
516
UA0OPT0
UARTA0 option control register 0
UART
495
UA0RIC
Interrupt control register
INTC
594
UA0RX
UARTA0 receive data register
UART
498
UA0STR
UARTA0 status register
UART
496
UA0TIC
Interrupt control register
INTC
594
UA0TX
UARTA0 transmit data register
UART
498
UA1CTL0
UARTA1 control register 0
UART
493
UA1CTL1
UARTA1 control register 1
UART
515
UA1CTL2
UARTA1 control register 2
UART
516
UA1OPT0
UARTA1 option control register 0
UART
495
UA1RIC
Interrupt control register
INTC
594
UA1RX
UARTA1 receive data register
UART
498
UA1STR
UARTA1 status register
UART
496
UA1TIC
Interrupt control register
INTC
594
UA1TX
UARTA1 transmit data register
UART
498
UA2CTL0
UARTA2 control register 0
UART
493
UA2CTL1
UARTA2 control register 1
UART
515
UA2CTL2
UARTA2 control register 2
UART
516
UA2OPT0
UARTA2 option control register 0
UART
495
UA2RIC
Interrupt control register
INTC
595
UA2RX
UARTA2 receive data register
UART
498
UA2STR
UARTA2 status register
UART
496
UA2TIC
Interrupt control register
INTC
595
UA2TX
UARTA2 transmit data register
UART
498
UA3CTL0
UARTA3 control register 0
UART
493
UA3CTL1
UARTA3 control register 1
UART
515
UA3CTL2
UARTA3 control register 2
UART
516
UA3OPT0
UARTA3 option control register 0
UART
495
UA3RIC
Interrupt control register
INTC
595
UA3RX
UARTA3 receive data register
UART
498
UA3STR
UARTA3 status register
UART
496
UA3TIC
Interrupt control register
INTC
595
UA3TX
UARTA3 transmit data register
UART
498
VSWC
System wait control register
CPU
84
WDTE
Watchdog timer enable register
WDT
455
WDTM2
Watchdog timer mode register 2
WDT
453, 598
WTIC
Interrupt control register
INTC
594
WTIIC
Interrupt control register
INTC
594
WTM
Watch timer operation mode register
WT
446
Preliminary User's Manual U17717EJ2V0UD
731
APPENDIX B INSTRUCTION SET LIST
B.1 Conventions
(1) Register symbols used to describe operands
Register Symbol
Explanation
reg1 General-purpose
registers: Used as source registers.
reg2
General-purpose registers: Used mainly as destination registers. Also used as source register in some
instructions.
reg3
General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits
of multiplication results.
bit#3
3-bit data for specifying the bit number
immX
X bit immediate data
dispX
X bit displacement data
regID System
register
number
vector
5-bit data that specifies the trap vector (00H to 1FH)
cccc
4-bit data that shows the conditions code
sp Stack
pointer
(r3)
ep
Element pointer (r30)
listX
X item register list
(2) Register symbols used to describe opcodes
Register Symbol
Explanation
R
1-bit data of a code that specifies reg1 or regID
r
1-bit data of the code that specifies reg2
w
1-bit data of the code that specifies reg3
d
1-bit displacement data
I
1-bit immediate data (indicates the higher bits of immediate data)
i
1-bit immediate data
cccc
4-bit data that shows the condition codes
CCCC
4-bit data that shows the condition codes of Bcond instruction
bbb
3-bit data for specifying the bit number
L
1-bit data that specifies a program register in the register list
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
732
(3) Register symbols used in operations
Register Symbol
Explanation
Input for
GR [ ]
General-purpose register
SR [ ]
System register
zero-extend (n)
Expand n with zeros until word length.
sign-extend (n)
Expand n with signs until word length.
load-memory (a, b)
Read size b data from address a.
store-memory (a, b, c)
Write data b into address a in size c.
load-memory-bit (a, b)
Read bit b of address a.
store-memory-bit (a, b, c)
Write c to bit b of address a.
saturated (n)
Execute saturated processing of n (n is a 2's complement).
If, as a result of calculations,
n
7FFFFFFFH, let it be 7FFFFFFFH.
n
80000000H, let it be 80000000H.
result
Reflects the results in a flag.
Byte Byte
(8
bits)
Halfword
Half word (16 bits)
Word
Word (32 bits)
+ Addition
Subtraction
ll Bit
concatenation
Multiplication
Division
% Remainder
from
division results
AND Logical
product
OR Logical
sum
XOR Exclusive
OR
NOT Logical
negation
logically shift left by
Logical shift left
logically shift right by
Logical shift right
arithmetically shift right by Arithmetic
shift
right
(4) Register symbols used in execution clock
Register Symbol
Explanation
i
If executing another instruction immediately after executing the first instruction (issue).
r
If repeating execution of the same instruction immediately after executing the first instruction (repeat).
l
If using the results of instruction execution in the instruction immediately after the execution (latency).
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
733
(5) Register symbols used in flag operations
Identifier Explanation
(Blank) No
change
0
Clear to 0
X
Set or cleared in accordance with the results.
R
Previously saved values are restored.
(6) Condition codes
Condition Code
(cccc)
Condition Formula
Explanation
0 0 0 0
OV = 1
Overflow
1 0 0 0
OV = 0
No overflow
0 0 0 1
CY = 1
Carry
Lower (Less than)
1 0 0 1
CY = 0
No carry
Not lower (Greater than or equal)
0 0 1 0
Z = 1
Zero
1 0 1 0
Z = 0
Not zero
0 0 1 1
(CY or Z) = 1
Not higher (Less than or equal)
1 0 1 1
(CY or Z) = 0
Higher (Greater than)
0 1 0 0
S = 1
Negative
1 1 0 0
S = 0
Positive
0 1 0 1
-
Always (Unconditional)
1 1 0 1
SAT = 1
Saturated
0 1 1 0
(S xor OV) = 1
Less than signed
1 1 1 0
(S xor OV) = 0
Greater than or equal signed
0 1 1 1
((S xor OV) or Z) = 1
Less than or equal signed
1 1 1 1
((S xor OV) or Z) = 0
Greater than signed
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
734
B.2 Instruction Set (in Alphabetical Order)
(1/6)
Execution
Clock
Flags
Mnemonic Operand
Opcode
Operation
i r l
CY
OV
S Z
SAT
reg1,reg2 r r r r r 0 0 1 1 1 0 R RRR R
GR[reg2]
GR[reg2]+GR[reg1]
1 1 1
ADD
imm5,reg2
r r r r r 0 1 0 0 1 0 i i i i i GR[reg2]
GR[reg2]+sign-extend(imm5)
1 1 1
ADDI imm16,reg1,reg2
r r r r r 1 1 0 0 0 0 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]+sign-extend(imm16)
1 1 1
AND reg1,reg2
r r r r r 0 0 1 0 1 0 R RRR R
GR[reg2]
GR[reg2]AND
GR[reg1]
1 1 1 0
ANDI imm16,reg1,reg2
r r r r r 1 1 0 1 1 0 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]AND
zero-extend(imm16)
1 1 1 0
When conditions
are satisfied
2
Note 2
2
Note 2
2
Note 2
Bcond disp9
ddddd1011dddcccc
Note 1
if conditions are satisfied
then PC
PC+sign-extend(disp9)
When conditions
are not satisfied
1 1 1
BSH reg2,reg3
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000010
GR[reg3]
GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
1 1 1
0
BSW reg2,reg3
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000000
GR[reg3]
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
[reg2] (23 : 16) ll GR[reg2] (31 : 24)
1 1 1
0
CALLT imm6
0 0 0 0 0 0 1 0 0 0 i i i i i i
CTPC
PC+2(return PC)
CTPSW
PSW
adr
CTBP+zero-extend(imm6 logically shift left by 1)
PC
CTBP+zero-extend(Load-memory(adr,Halfword))
4 4 4
bit#3,disp16[reg1] 10bbb111110RRRRR
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
Z flag
Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,0)
3
Note 3
3
Note 3
3
Note 3
CLR1
reg2,[reg1] r r r r r 1 1 1 1 1 1 R RRR R
0000000011100100
adr
GR[reg1]
Z flag
Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,0)
3
Note 3
3
Note 3
3
Note 3
cccc,imm5,reg2,reg3 r r r r r 1 1 1 1 1 1 i i i i i
wwwww011000cccc0
if conditions are satisfied
then GR[reg3]
sign-extended(imm5)
else GR[reg3]
GR[reg2]
1 1 1
CMOV
cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R RRR
wwwww011001cccc0
if conditions are satisfied
then GR[reg3]
GR[reg1]
else GR[reg3]
GR[reg2]
1
1
1
reg1,reg2 r r r r r 0 0 1 1 1 1 R RRR R
result
GR[reg2]GR[reg1]
1 1 1
CMP
imm5,reg2
r r r r r 0 1 0 0 1 1 i i i i i result
GR[reg2]sign-extend(imm5)
1 1 1
CTRET
0000011111100000
0000000101000100
PC
CTPC
PSW
CTPSW
3 3 3 R R R R R
DBRET
0000011111100000
0000000101000110
PC
DBPC
PSW
DBPSW
3 3 3 R R R R R
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
735
(2/6)
Execution
Clock
Flags
Mnemonic Operand
Opcode
Operation
i r l
CY OV
S Z
SAT
DBTRAP
1111100001000000 DBPC
PC+2 (restored PC)
DBPSW
PSW
PSW.NP
1
PSW.EP
1
PSW.ID
1
PC
00000060H
3
3
3
DI
0000011111100000
0000000101100000
PSW.ID
1
1
1
1
imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L
LLLLLLLLLLL00000
sp
sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]
Load-memory(sp,Word)
sp
sp+4
repeat 2 steps above until all regs in list12 is loaded
n+1
Note 4
n+1
Note 4
n+1
Note 4
DISPOSE
imm5,list12,[reg1] 0 0 0 0 0 1 1 0 0 1 i i i i i L
LLLLLLLLLLLRRRRR
Note 5
sp
sp+zero-extend(imm5 logically shift left by 2)
GR[reg in list12]
Load-memory(sp,Word)
sp
sp+4
repeat 2 steps above until all regs in list12 is loaded
PC
GR[reg1]
n+3
Note 4
n+3
Note 4
n+3
Note 4
DIV reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R RRR R
wwwww01011000000
GR[reg2]
GR[reg2]GR[reg1]
GR[reg3]
GR[reg2]%GR[reg1]
35 35 35
reg1,reg2 r r r r r 0 0 0 0 1 0 R RRR R
GR[reg2]
GR[reg2]GR[reg1]
Note 6
35 35 35
DIVH
reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R RRR R
wwwww01010000000
GR[reg2]
GR[reg2]GR[reg1]
Note 6
GR[reg3]
GR[reg2]%GR[reg1]
35 35 35
DIVHU reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R RRR R
wwwww01010000010
GR[reg2]
GR[reg2]GR[reg1]
Note 6
GR[reg3]
GR[reg2]%GR[reg1]
34 34 34
DIVU reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R RRR R
wwwww01011000010
GR[reg2]
GR[reg2]GR[reg1]
GR[reg3]
GR[reg2]%GR[reg1]
34 34 34
EI
1000011111100000
0000000101100000
PSW.ID
0
1
1
1
HALT
0000011111100000
0000000100100000
Stop
1
1
1
HSW reg2,reg3
r r r r r 1 1 1 1 1 1 0 0 0 0 0
wwwww01101000100
GR[reg3]
GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
1
1
1
0
JARL disp22,reg2
r r r r r 1 1 1 1 0 d d d d d d
ddddddddddddddd0
Note 7
GR[reg2]
PC+4
PC
PC+sign-extend(disp22)
2
2
2
JMP [reg1]
00000000011RRRRR
PC
GR[reg1]
3
3
3
JR disp22
0000011110dddddd
ddddddddddddddd0
Note 7
PC
PC+sign-extend(disp22)
2
2
2
LD.B disp16[reg1],reg2
r r r r r 1 1 1 0 0 0 R RRR R
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
sign-extend(Load-memory(adr,Byte))
1 1
Note
11
LD.BU disp16[reg1],reg2
r r r r r 1 1 1 1 0 b R RRR R
dddddddddddddd1
Notes 8, 10
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
zero-extend(Load-memory(adr,Byte))
1 1
Note
11
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
736
(3/6)
Execution
Clock
Flags
Mnemonic Operand
Opcode
Operation
i r l
CY
OV
S Z
SAT
LD.H disp16[reg1],reg2
rrrrr111001RRRRR
ddddddddddddddd0
Note 8
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
sign-extend(Load-memory(adr,Halfword))
1 1
Note
11
Other than regID = PSW
1
1
1
LDSR reg2,regID
rrrrr111111RRRRR
0000000000100000
Note 12
SR[regID]
GR[reg2]
regID = PSW
1
1
1
LD.HU disp16[reg1],reg2
r r r r r 1 1 1 1 1 1 R RRR R
ddddddddddddddd1
Note 8
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
zero-extend(Load-memory(adr,Halfword)
1 1
Note
11
LD.W disp16[reg1],reg2
r r r r r 1 1 1 0 0 1 R RRR R
ddddddddddddddd1
Note 8
adr
GR[reg1]+sign-extend(disp16)
GR[reg2]
Load-memory(adr,Word)
1 1
Note
11
reg1,reg2 r r r r r 0 0 0 0 0 0 R RRR R
GR[reg2]
GR[reg1]
1 1 1
imm5,reg2
r r r r r 0 1 0 0 0 0 i i i i i GR[reg2]
sign-extend(imm5)
1 1 1
MOV
imm32,reg1
00000110001RRRRR
i i i i i i i i i i i i i i i i
I I I I I I I I I I I I I I I I
GR[reg1]
imm32
2 2 2
MOVEA imm16,reg1,reg2 r r r r r 1 1 0 0 0 1 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]+sign-extend(imm16)
1 1 1
MOVHI imm16,reg1,reg2 rr r r r 1 1 0 0 1 0 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]+(imm16 ll 0
16
)
1 1 1
reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R RRR R
wwwww01000100000
GR[reg3] ll GR[reg2]
GR[reg2]xGR[reg1]
Note 14
1 4 5
MUL
imm9,reg2,reg3
r r r r r 1 1 1 1 1 1 i i i i i
w w w w w 0 1 0 0 1 I I I I 0 0
Note 13
GR[reg3] ll GR[reg2]
GR[reg2]xsign-extend(imm9)
1 4 5
reg1,reg2 r r r r r 0 0 0 1 1 1 R RRR R
GR[reg2]
GR[reg2]
Note 6
xGR[reg1]
Note 6
1 1 2
MULH
imm5,reg2
r r r r r 0 1 0 1 1 1 i i i i i GR[reg2]
GR[reg2]
Note 6
xsign-extend(imm5)
1 1 2
MULHI imm16,reg1,reg2
r r r r r 1 1 0 1 1 1 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]
Note 6
ximm16
1 1 2
reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R RRR R
wwwww01000100010
GR[reg3] ll GR[reg2]
GR[reg2]xGR[reg1]
Note 14
1 4 5
MULU
imm9,reg2,reg3
r r r r r 1 1 1 1 1 1 i i i i i
w w w w w 0 1 0 0 1 I I I I 1 0
Note 13
GR[reg3] ll GR[reg2]
GR[reg2]xzero-extend(imm9)
1 4 5
NOP
0000000000000000 Pass at least one clock cycle
doing
nothing.
1 1 1
NOT reg1,reg2
r r r r r 0 0 0 0 0 1 R RRR R
GR[reg2]
NOT(GR[reg1])
1 1 1 0
bit#3,disp16[reg1] 01bbb111110RRRRR
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
Z flag
Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
3
Note 3
3
Note 3
3
Note 3
NOT1
reg2,[reg1] r r r r r 1 1 1 1 1 1 R RRR R
0000000011100010
adr
GR[reg1]
Z flag
Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
3
Note 3
3
Note 3
3
Note 3
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
737
(4/6)
Execution
Clock
Flags
Mnemonic Operand
Opcode
Operation
i r l
CY OV
S Z
SAT
OR reg1,reg2
r r r r r 0 0 1 0 0 0 R RRR R
GR[reg2]
GR[reg2]OR
GR[reg1]
1 1 1 0
ORI imm16,reg1,reg2
r r r r r 1 1 0 1 0 0 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]OR
zero-extend(imm16)
1 1 1 0
list12,imm5 0 0 0 0 0 1 1 1 1 0 i i i i i L
LLLLLLLLLLL00001
Store-memory(sp4,GR[reg in list12],Word)
sp
sp4
repeat 1 step above until all regs in list12 is stored
sp
sp-zero-extend(imm5)
n+1
Note 4
n+1
Note 4
n+1
Note 4
PREPARE
list12,imm5,
sp/imm
Note 15
0 0 0 0 0 1 1 1 1 0 i i i i i L
L L L L L L L L L L L f f 0 1 1
imm16/imm32
Note 16
Store-memory(sp4,GR[reg in list12],Word)
sp
sp+4
repeat 1 step above until all regs in list12 is stored
sp
sp-zero-extend (imm5)
ep
sp/imm
n+2
Note 4
Note 17
n+2
Note 4
Note 17
n+2
Note 4
Note 17
RETI
0000011111100000
0000000101000000
if PSW.EP=1
then PC
EIPC
PSW
EIPSW
else if PSW.NP=1
then
PC
FEPC
PSW
FEPSW
else
PC
EIPC
PSW
EIPSW
3 3 3 R R R R R
reg1,reg2 r r r r r 1 1 1 1 1 1 R RRR R
0000000010100000
GR[reg2]
GR[reg2]arithmetically shift right
by GR[reg1]
1 1 1
0
SAR
imm5,reg2
r r r r r 0 1 0 1 0 1 i i i i i GR[reg2]GR[reg2]arithmetically shift right
by zero-extend (imm5)
1 1 1
0
SASF cccc,reg2
r r r r r 1 1 1 1 1 1 0 c c c c
0000001000000000
if conditions are satisfied
then GR[reg2]
(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]
(GR[reg2]Logically shift left by 1)
OR 00000000H
1
1
1
reg1,reg2 r r r r r 0 0 0 1 1 0 R RRR R
GR[reg2]
saturated(GR[reg2]+GR[reg1]) 1
1
1
SATADD
imm5,reg2
r r r r r 0 1 0 0 0 1 i i i i i GR[reg2]
saturated(GR[reg2]+sign-extend(imm5) 1
1
1
SATSUB reg1,reg2
r r r r r 0 0 0 1 0 1 R RRR R
GR[reg2]
saturated(GR[reg2]GR[reg1]) 1
1
1
SATSUBI imm16,reg1,reg2 r r r r r 1 1 0 0 1 1 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
saturated(GR[reg1]sign-extend(imm16) 1 1 1
SATSUBR reg1,reg2
r r r r r 0 0 0 1 0 0 R RRR R
GR[reg2]
saturated(GR[reg1]GR[reg2]) 1
1
1
SETF cccc,reg2
r r r r r 1 1 1 1 1 1 0 c c c c
0000000000000000
If conditions are satisfied
then GR[reg2]
00000001H
else GR[reg2]
00000000H
1
1
1
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
738
(5/6)
Execution
Clock
Flags
Mnemonic Operand
Opcode
Operation
i r l
CY
OV
S Z
SAT
bit#3,disp16[reg1] 00bbb111110RRRRR
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
Z flag
Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
3
Note 3
3
Note 3
3
Note 3
SET1
reg2,[reg1] r r r r r 1 1 1 1 1 1 R RRR R
0000000011100000
adr
GR[reg1]
Z flag
Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
3
Note 3
3
Note 3
3
Note 3
reg1,reg2 r r r r r 1 1 1 1 1 1 R RRR R
0000000011000000
GR[reg2]
GR[reg2] logically shift left by GR[reg1]
1
1
1
0
SHL
imm5,reg2
r r r r r 0 1 0 1 1 0 i i i i i GR[reg2]GR[reg2] logically shift left
by zero-extend(imm5)
1 1 1
0
reg1,reg2 r r r r r 1 1 1 1 1 1 R RRR R
0000000010000000
GR[reg2]
GR[reg2] logically shift right by GR[reg1]
1
1
1
0
SHR
imm5,reg2
r r r r r 0 1 0 1 0 0 i i i i i GR[reg2]GR[reg2] logically shift right
by zero-extend(imm5)
1 1 1
0
SLD.B disp7[ep],reg2 r r r r r 0 1 1 0 d d d d d d d
adr
ep+zero-extend(disp7)
GR[reg2]
sign-extend(Load-memory(adr,Byte))
1 1
Note 9
SLD.BU disp4[ep],reg2
r r r r r 0 0 0 0 1 1 0 d d d d
Note 18
adr
ep+zero-extend(disp4)
GR[reg2]
zero-extend(Load-memory(adr,Byte))
1 1
Note 9
SLD.H disp8[ep],reg2 r r r r r 1 0 0 0 d d d d d d d
Note 19
adr
ep+zero-extend(disp8)
GR[reg2]
sign-extend(Load-memory(adr,Halfword))
1 1
Note 9
SLD.HU disp5[ep],reg2
r r r r r 0 0 0 0 1 1 1 d d d d
Notes 18, 20
adr
ep+zero-extend(disp5)
GR[reg2]
zero-extend(Load-memory(adr,Halfword))
1 1
Note 9
SLD.W disp8[ep],reg2
r r r r r 1 0 1 0 d d d d d d 0
Note 21
adr
ep+zero-extend(disp8)
GR[reg2]
Load-memory(adr,Word)
1 1
Note 9
SST.B reg2,disp7[ep] r r r r r 0 1 1 1 d d d d d d d
adr
ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
1 1 1
SST.H reg2,disp8[ep] r r r r r 1 0 0 1 d d d d d d d
Note 19
adr
ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Halfword)
1 1 1
SST.W reg2,disp8[ep] r r r r r 1 0 1 0 d d d d d d 1
Note 21
adr
ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
1 1 1
ST.B reg2,disp16[reg1]
r r r r r 1 1 1 0 1 0 R RRR R
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
1 1 1
ST.H reg2,disp16[reg1]
r r r r r 1 1 1 0 1 1 R RRR R
ddddddddddddddd0
Note 8
adr
GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Halfword)
1 1 1
ST.W reg2,disp16[reg1]
rrrrr111011RRRRR
ddddddddddddddd1
Note 8
adr
GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
1 1 1
STSR regID,reg2
r r r r r 1 1 1 1 1 1 R RRR R
0000000001000000
GR[reg2]
SR[regID]
1 1 1
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
739
(6/6)
Execution
Clock
Flags
Mnemonic Operand
Opcode
Operation
i r l
CY OV
S Z
SAT
SUB reg1,reg2
r r r r r 0 0 1 1 0 1 R RRR R
GR[reg2]
GR[reg2]GR[reg1] 1
1
1
SUBR reg1,reg2
r r r r r 0 0 1 1 0 0 R RRR R
GR[reg2]
GR[reg1]GR[reg2] 1
1
1
SWITCH reg1
00000000010RRRRR
adr
(PC+2) + (GR [reg1] logically shift left by 1)
PC
(PC+2) + (sign-extend
(Load-memory (adr,Halfword))
logically shift left by 1
5
5
5
SXB reg1
00000000101RRRRR
GR[reg1]
sign-extend
(GR[reg1] (7 : 0))
1
1
1
SXH reg1
00000000111RRRRR
GR[reg1]
sign-extend
(GR[reg1] (15 : 0))
1
1
1
TRAP vector
0 0 0 0 0 1 1 1 1 1 1 i i i i i
0000000100000000
EIPC
PC+4 (Restored PC)
EIPSW
PSW
ECR.EICC
Interrupt code
PSW.EP
1
PSW.ID
1
PC
00000040H
(when vector is 00H to 0FH)
00000050H
(when vector is 10H to 1FH)
3
3
3
TST reg1,reg2
r r r r r 0 0 1 0 1 1 R RRR R
result
GR[reg2]
AND
GR[reg1]
1 1 1 0
bit#3,disp16[reg1] 11bbb111110RRRRR
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
Z flag
Not (Load-memory-bit (adr,bit#3))
3
Note 3
3
Note 3
3
Note 3
TST1
reg2, [reg1]
r r r r r 1 1 1 1 1 1 R RRR R
0000000011100110
adr
GR[reg1]
Z flag
Not (Load-memory-bit (adr,reg2))
3
Note 3
3
Note 3
3
Note 3
XOR reg1,reg2
r r r r r 0 0 1 0 0 1 R RRR R
GR[reg2]
GR[reg2] XOR GR[reg1]
1
1
1
0
XORI imm16,reg1,reg2
r r r r r 1 1 0 1 0 1 R RRR R
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1] XOR zero-extend (imm16)
1
1
1
0
ZXB reg1
00000000100RRRRR
GR[reg1]
zero-extend (GR[reg1] (7 : 0))
1
1
1
ZXH reg1
00000000110RRRRR
GR[reg1]
zero-extend (GR[reg1] (15 : 0))
1
1
1
Notes 1. dddddddd: Higher 8 bits of disp9.
2. 3 if there is an instruction that rewrites the contents of the PSW immediately before.
3. If there is no wait state (3 + the number of read access wait states).
4. n is the total number of list12 load registers. (According to the number of wait states. Also, if there
are no wait states, n is the total number of list12 registers. If n = 0, same operation as when n = 1)
5. RRRRR: other than 00000.
6. The lower halfword data only are valid.
7. ddddddddddddddddddddd: The higher 21 bits of disp22.
8. ddddddddddddddd: The higher 15 bits of disp16.
9. According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
APPENDIX B INSTRUCTION SET LIST
Preliminary User's Manual U17717EJ2V0UD
740
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
r r r r r
= regID specification
RRRRR = reg2 specification
13. i i i i i : Lower 5 bits of imm9.
I I I I : Higher 4 bits of imm9.
14. Do not specify the same register for general-purpose registers reg1 and reg3.
15. sp/imm: specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm = imm32, n + 3 clocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
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For further information,
please contact:
G05.11-1A
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