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MOS INTEGRATED CIRCUIT
PD720100A
USB2.0 HOST CONTROLLER
Document No.
S15535EJ2V0DS00 (2nd edition)
Date Published
October 2002 NS CP (K)
Printed in Japan
DATA SHEET
The mark shows major revised points.
2001
The
PD720100A complies with the Universal Serial Bus Specification Revision 2.0
and Open Host Controller
Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for
high-speed signaling and works up to 480 Mbps. The
PD720100A is integrated three host controller cores with PCI
interface and USB2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.
PD720100A User's Manual: S15534E
FEATURES
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
Compliant with Open Host Controller Interface Specification for USB Rev 1.0a
Compliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI
host controller core for high-speed signaling.
Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction.
Configurable number of downstream facing ports (2 to 5)
32-bit 33 MHz host interface compliant to PCI Specification release 2.2.
Supports PCI Mobile Design Guide Revision 1.1.
Supports PCI-Bus Power Management Interface Specification release 1.1.
PCI Bus bus-master access
System clock is generated by 30 MHz X'tal or 48 MHz clock input.
Operational registers direct-mapped to PCI memory space
Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard
implementation.
3.3 V power supply, PCI signal pins have 5 V tolerant circuit.
ORDERING INFORMATION
Part Number
Package
PD720100AGM-8ED
160-pin plastic LQFP (Fine pitch) (24
24)
PD720100AGM-8EY
160-pin plastic LQFP (Fine pitch) (24
24)
PD720100AS1-2C
176-pin plastic FBGA (15
15)
Data Sheet S15535EJ2V0DS
3
PD720100A
PCI Bus Interface
:handles 32-bits 33 MHz PCI Bus master and target function which comply with PCI
specification release 2.2. The number of enabled ports are set by bit in configuration
space.
Arbiter
:arbitrates among two OHCI Host controller cores and one EHCI Host controller core.
OHCI Host Controller #1
:handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.
OHCI Host Controller #2
:handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.
EHCI Host Controller
:handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.
Root Hub
:handles USB hub function in Host controller and controls connection (routing)
between Host controller core and port.
PHY
:consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,
etc
INTA0
:is the PCI interrupt signal for OHCI Host Controller #1.
INTB0
:is the PCI interrupt signal for OHCI Host Controller #2.
INTC0
:is the PCI interrupt signal for EHCI Host Controller.
SMI0
:is the interrupt signal which is specified by Open Host Controller Interface
Specification for USB Rev 1.0a. The SMI signal of each OHCI Host Controller
appears at this signal.
PME0
:is the interrupt signal which is specified by PCI-Bus Power Management Interface
Specification release 1.1. Wakeup signal of each host controller core appears at this
signal.
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