The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.

MOS INTEGRATED CIRCUIT

PD720113

USB 2.0 HUB CONTROLLER

Document No. S16618EJ3V0DS00 (3rd edition)
Date Published March 2005 NS CP (N)
Printed in Japan

DATA SHEET

The mark shows major revised points.

2003

The

PD720113 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision

2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The

PD720113 works backward compatible either when any one of the downstream ports is connected to a USB 1.1

compliant device, or when the upstream port is connected to a USB 1.1 compliant host.

Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.

PD720113 User's Manual: S16619E

FEATURES

· Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
· Certified by USB implementers forum and granted the USB 2.0 high-speed Logo
· High-speed or full-speed packet protocol sequencer for Endpoint 0/1
· 7 (Max.) downstream facing ports
· All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5

Mbps) transaction.

· Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when

Hub controller is working in high-speed mode.

· One Transaction Translator per Hub and supports four non-periodic buffers
· Support self-powered mode
· Supports Over-current detection and Individual or ganged power control
· Supports configurable vendor ID, product ID, string descriptors and others with external Serial ROM
· Supports "non-removable" attribution on individual port
· Uses 30 MHz X'tal, or clock input
· 2.5 V and 3.3 V power supplies

Data Sheet S16618EJ3V0DS

PD720113

ORDERING INFORMATION

Part Number

Package

Remark

PD720113GK-9EU

80-pin plastic TQFP (Fine pitch) (12

× 12)

PD720113GK-9EU-A

80-pin plastic TQFP (Fine pitch) (12

× 12)

Lead-free product

BLOCK DIAGRAM

Upstream facing port

UP_PHY

Downstream facing port #1

SERDES

SIE_2H

CDR

APLL

OSB

UPC

ROM I/F

ALL_TT

F_TIM

EP1

EP0

DP(1)_PHY

Downstream facing port #2

DP(2)_PHY

Downstream facing port #3

DP(3)_PHY

Downstream facing port #4

DP(4)_PHY

DPC

FS_REP

To Host/Hub
downstream
facing port

X1_CLK/X2

PPB(

:
1

)

CSB(

:
1
)

To Hub/Function
upstream facing port

External
Serial ROM

CDR

Downstream facing port #5

DP(5)_PHY

Downstream facing port #6

DP(6)_PHY

Downstream facing port #7

DP(7)_PHY

To Hub/Function
upstream facing port

Data Sheet S16618EJ3V0DS

PD720113

APLL

: Generates all clocks of Hub.

ALL_TT

: Translates the high-speed transactions (split transactions) for full/low-speed device

to full/low-speed transactions. ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.

CDR

: Data & clock recovery circuit

DPC

: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and

Resume

DP(n)_PHY

: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and

low-speed (1.5 Mbps) transaction

EP0

: Endpoint 0 controller

EP1

: Endpoint 1 controller

F_TIM (Frame Timer)

: Manages hub's synchronization by using micro-SOF which is received at upstream

port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.

FS_REP

: Full/low-speed repeater is enabled when the

PD720113 are worked at full-speed

mode

OSB :

Oscillator

Block

ROM I/F

: Interface block for external Serial ROM which contains user-defined descriptors

SERDES :

Serializer

and

Deserializer

SIE_2H

: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.

UP_PHY

: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)

transaction

UPC

: Upstream Port Controller handles Suspend and Resume

Data Sheet S16618EJ3V0DS

PD720113

PIN CONFIGURATION (TOP VIEW)

· 80-pin plastic TQFP (Fine pitch) (12 × 12)

PD720113GK-9EU

PD720113GK-9EU-A

DD33

DD25

DM6

DP6

DD33

DM7

DP7

DD25

TEST

SCAN_MODE

LPWRM

EXROM_EN

SCL

SDA/GANG_B

DD33

VBUSM

YSRSTB

PPB1

CSB1

PPB2

CSB2

PPB3

CSB3

PPB4

DD25

CSB4

PPB5

CSB5

PPB6

CSB6

PPB7

CSB7

DD33

RPU

DD25

DPU
DMU
V

DD33

DD25

(R)

RREF
AV

DD25

X1_CLK
V

DD2

DD3

DD2

Data Sheet S16618EJ3V0DS

PD720113

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

1 V

DD33

DM1

2 V

DD25

CSB7 42

X1_CLK

DP1

3 V

PPB7

X2 63

DD25

4 DM6

24 CSB6

DD25

5 DP6

25 PPB6

DM2

6 V

DD33

CSB5 46

RREF 66

DP2

7 V

PPB5

(R) 67

DD33

8 DM7

28 CSB4

9 DP7

29 V

DM3

10 V

DD25

DP3

11 V

DD25

PPB4 51

DD33

12 V

CSB3

DD25

13 TEST

33 PPB3

53 V

DD33

DD25

14 SCAN_MODE

34 CSB2

54 V

15 V

PPB2

DMU

DM4

16 LPWRM 36 CSB1

56 DPU

76 DP4

17 EXROM_EN

37 PPB1

57 V

DD25

18 SCL

38 SYSRSTB 58 V

19 SDA/GANG_B

39 VBUSM

59 RPU

79 DM5

20 V

DD33

DP5

Remark AV

(R) should be used to connect RREF through 1 % precision reference resistor of 2.43 k

Data Sheet S16618EJ3V0DS

PD720113

1. PIN INFORMATION

Pin Name

I/O

Buffer Type

Active

Level

Function

X1_CLK

2.5 V Input

Crystal oscillator in or clock input

2.5 V Output

Oscillator out

SYSRSTB

5 V tolerant Schmitt Input

Low

Asynchronous chip reset

RPU

A (O)

USB Pull-up control

External 1.5 k

pull-up resistor control

DP(7:1) I/O

USB

+ signal I/O

USB's downstream facing port D

+ signal

DM(7:1) I/O

USB

- signal I/O

USB's downstream facing port D

- signal

DPU I/O

USB

+ signal I/O

USB's upstream facing port D

+ signal

DMU I/O

USB

- signal I/O

USB's upstream facing port D

- signal

LPWRM

3.3 V Schmitt Input

Local power monitor

RREF

A (O)

Analog

Reference resistor

CSB(7:1)

5 V tolerant Input

Low

Port's over-current status input

PPB(7:1)

5 V tolerant N-ch open drain

Low

Port's power supply control output

VBUSM

5 V tolerant Schmitt input

BUS

monitor

SCL

3.3 V Output

External serial ROM clock out

SDA/GANG_B

I/O

3.3 V Schmitt I/O

External serial ROM data IO or power
management mode select

EXROM_EN

3.3 V Schmitt Input

External serial ROM input enable

TEST

3.3 V Input

Test signal

SCAN_MODE

3.3 V Input

Test signal

DD33

3.3 V V

DD25

2.5 V V

for analog circuit

(R)

for reference resistor. Connect to AV

Remark "5 V tolerant" means that the buffer is 3 V buffer with 5 V tolerant circuit.

Data Sheet S16618EJ3V0DS

PD720113

2.2 Terminology

Terms Used in Absolute Maximum Ratings

Parameter Symbol

Meaning

Power supply voltage

DD33

DD25

Indicates voltage range within which damage or reduced reliability will not
result when power is applied to a V

pin.

Input voltage

Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an input pin.

Output voltage

Indicates voltage range within which damage or reduced reliability will not
result when power is applied to an output pin.

Output current

Indicates absolute tolerance values for DC current to prevent damage or
reduced reliability when current flows out of or into an output pin.

Operating temperature

Indicates the ambient temperature range for normal logic operations.

Storage temperature

stg

Indicates the element temperature range within which damage or reduced
reliability will not result while no voltage or current are applied to the device.

Terms Used in Recommended Operating Range

Parameter Symbol

Meaning

Power supply voltage

DD33

DD25

Indicates the voltage range for normal logic operations to occur when V

= 0

High-level input voltage

Indicates the voltage, applied to the input pins of the device, which indicates
the high level state for normal operation of the input buffer.

* If a voltage that is equal to or greater than the "MIN." value is applied, the

input voltage is guaranteed as high level voltage.

Low-level input voltage

Indicates the voltage, applied to the input pins of the device, which indicates
the low level state for normal operation of the input buffer.

* If a voltage that is equal to or less than the "MAX." value is applied, the

input voltage is guaranteed as low level voltage.

Hysteresis voltage

Indicates the differential between the positive trigger voltage and the negative
trigger voltage.

Input rise time

Indicates allowable input signal transition time from 0.1

× V

to 0.9

× V

Input fall time

Indicates allowable input signal transition time from 0.9

× V

to 0.1

× V

Data Sheet S16618EJ3V0DS

PD720113

Terms Used in DC Characteristics

Parameter Symbol

Meaning

Off-state output leakage current

Indicates the current that flows into a 3-state output pin when it is in a high-
impedance state and a voltage is applied to the pin.

Output short circuit current

Indicates the current that flows from an output pin when it is shorted to GND
while it is at high-level.

Input leakage current

Indicates the current that flows into an input pin when a voltage is applied to
the pin.

Low-level output current

Indicates the current that can flow into an output pin in the low-level state
without raising the output voltage above the specified V

High-level output current

Indicates the current that can flow out of an output pin in the high-level state
without reducing the output voltage below the specified V

. (A negative

current indicates current flowing out of the pin.)

2.3 Electrical

Specifications

Absolute Maximum Ratings

Parameter Symbol

Condition

Rating Unit

Power supply voltage

DD33

-0.5 to +4.6 V

DD25

-0.5 to +3.6

Input/output voltage

2.5 V input/output voltage

2.3 V

DD25

2.7 V

< V

DD25

+ 0.9 V

-0.5 to +3.6 V

3.3 V input/output voltage

3.0 V

DD33

3.6 V

< V

DD33

+ 1.0 V

-0.5 to +4.6 V

5 V input/out voltage

3.0 V

DD33

3.6 V

< V

DD33

+ 3.0 V

-0.5 to +6.6 V

Output current

= 3 mA

= 6 mA

= 12 mA

10
20
40

mA
mA
mA

Operating temperature

+70

°C

Storage temperature

stg

-65 to +150

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameters. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions
that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent the
quality assurance range during normal operation.

Data Sheet S16618EJ3V0DS

PD720113

Recommended Operating Ranges

Parameter Symbol

Condition

MIN.

TYP.

MAX.

Unit

Operating voltage

DD33

3.3 V for V

DD33

pins

3.14

3.30

3.46

DD25

2.5 V for V

DD25

pins

2.3

2.5

2.7

2.5 V for AV

pins

2.3

2.5

2.7

High-level input voltage

2.5 V High-level input voltage

1.7

DD25

3.3 V High-level input voltage

2.0

DD33

5.0 V High-level input voltage

2.0

5.5

Low-level input voltage

2.5 V Low-level input voltage

0.7

3.3 V Low-level input voltage

0.8

5.0 V Low-level input voltage

0.8

Hysteresis voltage

5 V Hysteresis voltage

0.3

1.5

3.3 V Hysteresis voltage

0.2

1.0

Input rise time for SYSRSTB

rst

Input rise time

Normal buffer

200

Schmitt buffer

Input fall time

Normal buffer

200

Schmitt buffer

Two power supply rails limitation.

The

PD720113 has two power supply rails (2.5 V, 3.3 V).

The system will require the time when power supply

rail is stable at V

level. And, there will be difference between the time of V

DD25

and V

DD33

. The

PD720113

requires that V

DD25

should be stable before V

DD33

becomes stable. At any case, the system must ensure that the

absolute maximum ratings for V

are not exceeded. System reset signaling should be asserted more than

specified time after both V

DD25

and V

DD33

are stable.

Data Sheet S16618EJ3V0DS

PD720113

DC Characteristics

Parameter Symbol

Condition

MIN.

MAX.

Unit

Off-state output leakage current

= V

DD33,

DD25

or V

±10

Output short circuit current

Note

-250 mA

Low-level output current

3.3 V low-level output current

= 0.4 V

3.3 V low-level output current

= 0.4 V

5.0 V low-level output current

= 0.4 V

High-level output current

3.3 V high-level output current

= 2.4 V

-3 mA

3.3 V high-level output current

= 2.4 V

-6 mA

5.0 V high-level output current

= 2.4 V

-2 mA

Input leakage current

3.3 V buffer

= V

or V

±10

5.0 V buffer

= V

or V

±10

Note The output short circuit time is measured at one second or less and is tested with only one pin on the LSI.

Data Sheet S16618EJ3V0DS

PD720113

USB Interface Block

Parameter Symbol

Conditions

MIN

MAX

Unit

Output pin impedance

HSDRV

Includes

resistor

40.5

49.5

Bus pull-up resistor on upstream facing
port

1.425 1.575 k

Bus pull-up resistor on downstream
facing port

14.25 15.75 k

Termination voltage for upstream facing
port pullup (full-speed)

TERM

3.0

3.6

Input Levels for Low-/full-speed:

High-level input voltage (drive)

2.0

High-level input voltage (floating)

IHZ

2.7 3.6 V

Low-level input voltage

0.8 V

Differential input sensitivity

(D+) - (D-) 0.2

Differential common mode range

Includes

range

0.8

2.5

Output Levels for Low-/full-speed:

High-level output voltage

of 14.25 k

to GND

2.8

3.6

Low-level output voltage

of 1.425 k

to 3.6 V

0.0

0.3

SE1 V

OSE1

0.8

Output signal crossover point voltage

CRS

1.3

2.0 V

Input Levels for High-speed:

High-speed squelch detection threshold
(differential signal)

HSSQ

100

150 mV

High-speed disconnect detection
threshold (differential signal)

HSDSC

525

625 mV

High-speed data signaling common
mode voltage range

HSCM

-50

+500 mV

High-speed differential input signaling
levels

See Figure 2-4.

Output Levels for High-speed:

High-speed idle state

HSOI

-10.0

+10 mV

High-speed data signaling high

HSOH

360

440 mV

High-speed data signaling low

HSOL

-10.0

+10 mV

Chirp J level (different signal)

CHIRPJ

700

1100 mV

Chirp K level (different signal)

CHIRPK

-900

-500 mV

Data Sheet S16618EJ3V0DS

PD720113

Figure 2-1. Differential Input Sensitivity Range for Low-/full-speed

4.6

-1.0

Input Voltage Range (Volts)

Differential Input Voltage Range

Differential Output

Crossover

Voltage Range

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

Figure 2-2. Full-speed Buffer V

Characteristics for High-speed Capable Transceiver

Max.

Min.

0.3

OUT

(V)

OUT

(mA)

2.3

3.3

0.8

1.3

1.8

2.8

Figure 2-3. Full-speed Buffer V

Characteristics for High-speed Capable Transceiver

Max.

Min.

0.5

1.5

2.5

OUT

(V)

OUT

(mA)

Data Sheet S16618EJ3V0DS

PD720113

Power Consumption

Parameter Symbol

Condition

TYP. Unit

Power Consumption

W-0

The power consumption under the state without suspend.
All the ports do not connect to any function.

Note

Hub controller is operating at full-speed mode.

Hub controller is operating at high-speed mode.

2.2

84
23

mA (2.5 V)
mA (3.3 V)
mA (2.5 V)
mA (3.3 V)

W-5

The power consumption under the state without suspend.
The number of active ports is 5.

Hub controller is operating at full-speed mode.

Hub controller is operating at high-speed mode.

8.9

138

mA (2.5 V)
mA (3.3 V)
mA (2.5 V)
mA (3.3 V)

W-6

The power consumption under the state without suspend.
The number of active ports is 6.

Hub controller is operating at full-speed mode.

Hub controller is operating at high-speed mode.

44
10

148

mA (2.5 V)
mA (3.3 V)
mA (2.5 V)
mA (3.3 V)

W-7

The power consumption under the state without suspend.
The number of active ports is 7.

Hub controller is operating at full-speed mode.

Hub controller is operating at high-speed mode.

44
12

158
111

mA (2.5 V)
mA (3.3 V)
mA (2.5 V)
mA (3.3 V)

W_S

The power consumption under suspend state.
The internal clock is stopped.

0.68
0.24

mA (2.5 V)
mA (3.3 V)

Note

When any device is not connected to all the ports, the power consumption does not depend on the number
of active ports.

Data Sheet S16618EJ3V0DS

PD720113

Over-current Response Timing

Parameter Symbol

Condition

MIN.

TYP.

MAX.

Unit

Over-current response time from CSB
low to PPB high (Figure 2-7)

500

625

Figure 2-7. Over-current Response Timing

CSB(7:1)

PPB(7:1)

Figure 2-8. CSB/PPB Timing

Bus reset

500

Hub power supply

PPB pin output

CSB pin input

CSB pin operation region

Up port D

line

Port power
supply ON

Output
cut-off

Overcurrent
generation

CSB detection
delay time

CSB active
period

Device

connection

inrush current

Bus power: Up port connection
Self power: Power supply ON

Remark The active period of the CSB pin is in effect only when the PPB pin is ON.

There is a delay time of approximately 500

s duration at the CSB pin.

Data Sheet S16618EJ3V0DS

PD720113

External Serial ROM Timing

Parameter Symbol

Condition

MIN.

TYP.

MAX.

Unit

Clock frequency

SCL

94.6

100

kHz

Clock pulse width low

LOW

4700

Clock pulse width high

HIGH

4000

Clock low to data out valid

100

3500

Time the bus must be free before a new
transmission can start

BUF

4700

Start hold time

HD.STA

4000 ns

Start setup time

SU.STA

4700 ns

Data in hold time

HD.DTA

0 ns

Data in setup time

SU.DTA

250 ns

Stop setup time

SU.STO

4700 ns

Data out hold time

300

Write cycle time

Figure 2-9. External Serial ROM Bus Timing

SCL

SDA

(Output)

SDA

(Input)

SU.STA

HD.STA

SU.DAT

HIGH

LOW

HD.DAT

SU.STO

BUF

Figure 2-10. External Serial ROM Write Cycle Timing

SCL

SDA

Word n

8th bit

ACK

Stop

condition

Start

condition

Data Sheet S16618EJ3V0DS

PD720113

USB Interface Block

(1/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Low-speed Electrical Characteristics

Rise time (10% to 90%)

= 200 pF to 600 pF

300

Fall time (90% to 10%)

= 200 pF to 600 pF

300

Differential rise and fall time matching

LRFM

)

Note

125

Low-speed data rate

LDRATHS

Average bit rate

1.49925

1.50075

Mbps

Downstream facing port source jitter total
(including frequency tolerance) (Figure
2-15):

To next transition

For paired transitions

DDJ1

DDJ2

-25
-14

+25
+14

ns
ns

Downstream facing port differential
receiver jitter total (including frequency
tolerance) (Figure 2-17):

To next transition

For paired transitions

UJR1

UJR2

-152
-200

+152
+200

ns
ns

Source SE0 interval of EOP (Figure 2-16)

LEOPT

1.25

1.5

Receiver SE0 interval of EOP (Figure 2-16)

LEOPR

670

Width of SE0 interval during differential
transition

LST

210

Hub differential data delay (Figure 2-13)

LHDD

300 ns

Hub differential driver jitter (including cable)
(Figure 2-13):

Downstream facing port
To next transition
For paired transitions

Upstream facing port
To next transition
For paired transitions

LDHJ1

LDHJ2

LUHJ1

LUHJ2

-45
-15

-45
-45

+45
+15

+45
+45

ns
ns

Data bit width distortion after SOP (Figure
2-13)

LSOP

-60

+60 ns

Hub EOP delay relative to t

HDD

(Figure

2-14)

LEOPD

200 ns

Hub EOP output width skew (Figure 2-14)

LHESK

-300

+300 ns

Full-speed Electrical Characteristics

Rise time (10% to 90%)

= 50 pF,

= 36

4 20

Fall time (90% to 10%)

= 50 pF,

= 36

4 20

Differential rise and fall time matching

FRFM

) 90

111.11

Full-speed data rate

FDRATHS

Average bit rate

11.9940

12.0060

Mbps

Frame interval

FRAME

0.9995 1.0005 ms

Note Excluding the first transition from the Idle state.

Data Sheet S16618EJ3V0DS

PD720113

(2/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Full-speed Electrical Characteristics (Continued)

Consecutive frame interval jitter

RFI

No clock adjustment

Source jitter total (including frequency
tolerance) (Figure 2-15):
To next transition
For paired transitions

DJ1

DJ2

Note

-3.5
-4.0

+3.5
+4.0

ns
ns

Source jitter for differential transition to
SE0 transition (Figure 2-16)

FDEOP

-2

+5 ns

Receiver jitter (Figure 2-17):
To Next Transition
For

Paired

Transitions

JR1

JR2

-18.5

-9

+18.5

ns
ns

Source SE0 interval of EOP (Figure 2-16)

FEOPT

160

175 ns

Receiver SE0 interval of EOP (Figure 2-16)

FEOPR

Width of SE0 interval during differential
transition

FST

14 ns

Hub differential data delay (Figure 2-13)

(with cable)
(without cable)

HDD1

HDD2

70
44

ns
ns

Hub differential driver jitter (including cable)
(Figure 2-13):
To next transition
For paired transitions

HDJ1

HDJ2

-3
-1

+3
+1

ns
ns

Data bit width distortion after SOP (Figure
2-13)

FSOP

-5

+5 ns

Hub EOP delay relative to t

HDD

(Figure

2-14)

FEOPD

Hub EOP output width skew (Figure 2-14)

FHESK

-15

+15 ns

High-speed Electrical Characteristics

Rise time (10% to 90%)

HSR

500

Fall time (90% to 10%)

HSF

500

Driver waveform

See Figure 2-11.

High-speed data rate

HSDRAT

479.760 480.240 Mbps

Microframe interval

HSFRAM

124.9375 125.0625

Consecutive microframe interval difference

HSRFI

high-

speed

Bit

times

Data source jitter

See Figure 2-11.

Receiver jitter tolerance

See Figure 2-4.

Hub data delay (without cable)

HSHDD

high-

speed

+4 ns

Bit

times

Hub data jitter

See Figure 2-4, Figure 2-11.

Hub delay variation range

HSHDV

high-

speed

Bit

times

Note Excluding the first transition from the Idle state.

Data Sheet S16618EJ3V0DS

PD720113

(3/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Hub Event Timings

Time to detect a downstream facing port
connect event (Figure 2-19):
Awake

hub

Suspended

hub

DCNN

2.5
2.5

2000

12000

Time to detect a disconnect event at a
hub's downstream facing port (Figure 2-18)

DDIS

2.0

2.5

Duration of driving resume to a
downstream port (only from a controlling
hub)

DRSMDN

Time from detecting downstream resume
to rebroadcast

URSM

1.0 ms

Duration of driving reset to a downstream
facing port (Figure 2-20)

DRST

Only for a SetPortFeature
(PORT_RESET) request

10 20

Time to detect a long K from upstream

URLK

2.5

100

Time to detect a long SE0 from upstream

URLSE0

2.5

10000

Duration of repeating SE0 upstream (for
low-/full-speed repeater)

URPSE0

23 FS

Bit

times

Inter-packet delay (for high-speed) of
packets traveling in same direction

HSIPDSD

Bit

times

Inter-packet delay (for high-speed) of
packets traveling in opposite direction

HSIPDOD

Bit

times

Inter-packet delay for device/root hub
response with detachable cable for high-
speed

HSRSPIPD1

192

Bit

times

Time of which a Chirp J or Chirp K must be
continuously detected (filtered) by hub or
device during Reset handshake

FILT

2.5

Time after end of device Chirp K by which
hub must start driving first Chirp K in the
hub's chirp sequence

WTDCH

100

Time for which each individual Chirp J or
Chirp K in the chirp sequence is driven
downstream by hub during reset

DCHBIT

Time before end of reset by which a hub
must end its downstream chirp sequence

DCHSE0

100

500

Time from internal power good to device
pulling D

+ beyond V

IHZ

(Figure 2-20)

SIGATT

100 ms

Debounce interval provided by USB
system software after attach (Figure 2-20)

ATTDB

100 ms

Maximum duration of suspend averaging
interval

SUSAVGI

Period of idle bus before device can initiate
resume

WTRSM

Duration of driving resume upstream

DRSMUP

Data Sheet S16618EJ3V0DS

PD720113

(4/4)

Parameter Symbol

Conditions

MIN.

MAX.

Unit

Hub Event Timings (Continued)

Resume recovery time

RSMRCY

Remote-wakeup

enabled

Time to detect a reset from upstream for
non high-speed capable devices

DETRST

2.5

10000

Reset recovery time (Figure 2-20)

RSTRCY

Inter-packet delay for full-speed

IPD

Bit

times

Inter-packet delay for device response with
detachable cable for full-speed

RSPIPD1

6.5

Bit

times

SetAddress() completion time

DSETADDR

Time to complete standard request with no
data

DRQCMPLTND

Time to deliver first and subsequent
(except last) data for standard request

DRETDATA1

500

Time to deliver last data for standard
request

DRETDATAN

Time for which a suspended hub will see a
continuous SE0 on upstream before
beginning the high-speed detection
handshake

FILTSE0

2.5

Time a hub operating in non-suspended
full-speed will wait after start of SE0 on
upstream before beginning the high-speed
detection handshake

WTRSTFS

2.5

3000

Time a hub operating in high-speed will
wait after start of SE0 on upstream before
reverting to full-speed

WTREV

3.0

3.125 ms

Time a hub will wait after reverting to full-
speed before sampling the bus state on
upstream and beginning the high-speed
will wait after start of SE0 on upstream
before reverting to full-speed

WTRSTHS

100

875

Minimum duration of a Chirp K on
upstream from a hub within the reset
protocol

UCH

1.0

Time after start of SE0 on upstream by
which a hub will complete its Chirp K within
the reset protocol

UCHEND

7.0

Time between detection of downstream
chip and entering high-speed state

WTHS

500

Time after end of upstream Chirp at which
hub reverts to full-speed default state if no
downstream Chirp is detected

WTFS

1.0

2.5 ms

Data Sheet S16618EJ3V0DS

PD720113

Timing Diagram

Figure 2-13. Hub Differential Delay, Differential Jitter, and SOP Distortion

C. Upstream Hub Delay with or without Cable

D. Measurement Points

50% Point of

Initial Swing

50% Point of

Initial Swing

Upstream

End of

Cable

Upstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Upstream Port

End of Cable

A. Downstream Hub Delay with Cable

B. Downstream Hub Delay without Cable

Hub Delay

Downstream

HDD1

Hub Delay

Upstream

HDD1

HDD2

Crossover

Point

Crossover

Point

Crossover

Point

Hub Differential Jitter:
t

HDJ1

= t

HDDx

(J)

HDDx

(K) or t

HDDx

(K)

HDDx

(J) Consecutive Transitions

HDJ2

= t

HDDx

(J)

HDDx

(J) or t

HDDx

(K)

HDDx

(K) Paired Transitions

Bit after SOP Width Distortion (same as data jitter for SOP and next J transition):
t

FSOP

= t

HDDx

(next J)

HDDx

(SOP)

Low-speed timings are determined in the same way for:
t

LHDD

, t

LDHJ1

, t

LDJH2

, t

LUHJ1

, t

LUJH2

, and t

LSOP

Host or

Hub

Function

Upstream end of cable

Upstream port

Downstream port

Downstream signaling

Upstream signaling

Plug

Receptacle

Hub Delay

Downstream

HDD2

Data Sheet S16618EJ3V0DS

PD720113

Figure 2-14. Hub EOP Delay and EOP Skew

EOP-

EOP+

EOP-

EOP+

EOP-

EOP+

C. Upstream EOP Delay with or without Cable

Upstream

End of

Cable

Upstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Downstream

Port of Hub

Upstream Port

End of Cable

A. Downstream EOP Delay with Cable

B. Downstream EOP Delay without Cable

50% Point of

Initial Swing

Crossover

Point

Extended

Crossover

Point

Extended

Crossover

Point

Extended

EOP Delay:
t

FEOPD

= t

EOPy

HDDx

EOPy

means that this equation applies to t

EOP-

and t

EOP+

)

EOP Skew:
t

FHESK

= t

EOP+

EOP-

Low-speed timings are determined in the same way for:
t

LEOPD

and t

LHESK

Data Sheet S16618EJ3V0DS

PD720113

Figure 2-15. USB Differential Data Jitter for Low-/full-speed

PERIOD

Differential
Data Lines

Crossover

Points

Consecutive

Transitions

PERIOD

xDJ1

Paired

Transitions

PERIOD

xDJ2

Figure 2-16. USB Differential-to-EOP Transition Skew and EOP Width for Low-/full-speed

PERIOD

Differential
Data Lines

Crossover

Point

Crossover

Point Extended

Source EOP Width: t

FEOPT

Receiver EOP Width: t

FEOPR

LEOPT

LEOPR

Diff. Data-to-

SE0 Skew

PERIOD

xDEOP

Figure 2-17. USB Receiver Jitter Tolerance for Low-/full-speed

Differential
Data Lines

PERIOD

xJR

xJR1

xJR2

Consecutive

Transitions

PERIOD

xJR1

Paired

Transitions

PERIOD

xJR2

Data Sheet S16618EJ3V0DS

PD720113

4. RECOMMENDED SOLDERING CONDITIONS

The

PD720113 should be soldered and mounted under the following recommended conditions.

For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales

representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

PD720113GK-9EU:

80-pin plastic TQFP (Fine pitch) (12

× 12)

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: Three times or less

Exposure limit: 3 days

Note

(after that, prebake at 125°C for 10 hours)

IR35-103-3

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

PD720113GK-9EU-A:

80-pin plastic TQFP (Fine pitch) (12

× 12) Lead-free product

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

Package peak temperature: 245°C, Time: 60 seconds max. (at 220°C or higher),

Count: Three times or less

Exposure limit: 7 days

Note

(after that, prebake at 125°C for 10 hours)

IR45-107-3

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Data Sheet S16618EJ3V0DS

PD720113

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V

(MAX) and V

(MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V

(MAX) and

(MIN).

HANDLING OF UNUSED INPUT PINS

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V

or GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

NOTES FOR CMOS DEVICES

PD720113

USB logo is a trademark of USB Implementers Forum, Inc.

The information in this document is current as of March, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.

(Note)

M8E 02. 11-1

(1)

(2)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).

Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.

"Standard":

"Special":

"Specific":

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD720113

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD720113