Document Outline

COVER
FEATURES
ORDERING INFORMATION
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
1. PIN FUNCTIONS
- 1.1 PIN FUNCTIONS
2. IEBus OPERATION
- 2.1 OVERVIEW
- 2.2 IEBus COMMUNICATION PROTOCOL
  - 2.2.1 Bus Mastership Determination (Arbitration)
  - 2.2.2 Communication Mode
  - 2.2.3 Communication Address
  - 2.2.4 Broadcast
- 2.3 TRANSMISSION PROTOCOL
- 2.4 TRANSMISSION DATA (CONTENTS OF THE DATA FIELD)
- 2.5 BIT FORMAT
3. MICROCOMPUTER INTERFACE
- 3.1 TRANSFER METHOD
- 3.2 DATA TRANSFER FORMAT
  - 3.2.1 Three-Wire Data Transfer (SEL = 1)
  - 3.2.2 Two-Wire Data Transfer (SEL = 0)
- 3.3 CONNECTION TO A MICROCOMPUTER
- 3.4 STANDBY MODE SETTING AND CANCELLATION
- 3.5 RESET MODE SETTING AND CANCELLATION
4. REGISTERS
5. EXAMPLE TIMINGS FOR COMMUNICATION
6. EXAMPLE MICROCOMPUTER PROCESSING FLOW
- 6.1 COMMUNICATION FLAGS
- 6.2 MAIN ROUTINE
- 6.3 INTERRUPT ROUTINE
- 6.4 PROCESSING ROUTINES
  - 6.4.1 uPD72042A or uPD72042B Initial Setting Routine
  - 6.4.2 Communication Flag Initialization Routine
  - 6.4.3 Command Processing Routine
  - 6.4.4 Master Communication Processing Routine
  - 6.4.5 Slave Data Transmission Processing Routine
  - 6.4.6 Transmission Processing Routine
  - 6.4.7 Reception Processing Routine
7. ELECTRICAL CHARACTERISTICS
8. PACKAGE DRAWING
9. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A MAIN DIFFERENCES BETWEEN uPD72042A, uPD72042B, AND uPD6708
APPENDIX B IEBus PROTOCOL ANALYZER

1995

DATA SHEET

LSI DEVICES FOR Inter Equipment Bus

(IEBus

)

PROTOCOL CONTROL

MOS INTEGRATED CIRCUIT

PD72042A, 72042B

The

PD72042A and

PD72042B are microcomputer peripheral LSI devices for IEBus protocol control.

The

PD72042A and

PD72042B perform all the processing required for layers 1 and 2 of the IEBus. The devices

incorporate large transmission and reception buffers, allowing the microcomputer to perform IEBus operations without

interruption. They also contain an IEBus driver and receiver, allowing them to directly connected to the bus directly.

FEATURES

·
·

Control of layers 1 and 2 of the IEBus protocol

· Support of a multi-master scheme

· Broadcast function

· Two communication modes having different

transmission speeds can be selected.

·
·

Microcomputer interface

Three-/two-wire serial I/O

· Transfer starting with MSB

PD72042A

· Transfer starting with LSB

PD72042B

·
·

Program crashes can be detected by means of a

watchdog timer.

·
·

Low power consumption (standby mode):

A (max)

·
·

Oscillator frequency (f

): 6 MHz, 6.29 MHz

· frequency accuracy:

1.5%

·
·

Operating voltage: 5 V

10%

When operating

at 6 MHz

at 6.29 MHz

Mode 0

Approx. 3.9 Kbps

Approx. 4.1 Kbps

Mode 1

Approx. 17 Kbps

Approx. 18 Kbps

Document No. S13990EJ2V0DS00 (2nd edition)
(Previous No. ID-3649)
Date Published January 1999 N CP(N)
Printed in Japan

Built-in IEBus driver and receiver

Transmission and reception buffers

Transmission buffer

: 33 bytes, FIFO

Reception buffer

: 40 bytes, FIFO (capable of

holding more than one frame

of reception data.)

ORDERING INFORMATION

Part number

Package

Starting with MSB/LSB

PD72042AGT

16-pin plastic SOP (375 mil)

MSB

PD72042BGT

16-pin plastic SOP (375 mil)

LSB

The mark shows major revised points.

The information in this document is subject to change without notice.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

CONTENTS

PIN FUNCTIONS .............................................................................................................................

1.1

PIN FUNCTIONS .....................................................................................................................................

IEBus OPERATION .........................................................................................................................

2.1

OVERVIEW ..............................................................................................................................................

2.2

IEBus COMMUNICATION PROTOCOL ................................................................................................

2.2.1

Bus Mastership Determination (Arbitration) ...............................................................................

2.2.2

Communication Mode .................................................................................................................

2.2.3

Communication Address .............................................................................................................

2.2.4

Broadcast .....................................................................................................................................

2.3

TRANSMISSION PROTOCOL ...............................................................................................................

2.4

TRANSMISSION DATA (CONTENTS OF THE DATA FIELD) .............................................................

2.5

BIT FORMAT ...........................................................................................................................................

MICROCOMPUTER INTERFACE .................................................................................................. 22

3.1

TRANSFER METHOD ............................................................................................................................

3.2

DATA TRANSFER FORMAT ..................................................................................................................

3.2.1

Three-Wire Data Transfer (SEL = 1) ..........................................................................................

3.2.2

Two-Wire Data Transfer (SEL = 0) .............................................................................................

3.3

CONNECTION TO A MICROCOMPUTER .............................................................................................

3.4

STANDBY MODE SETTING AND CANCELLATION ............................................................................

3.5

RESET MODE SETTING AND CANCELLATION .................................................................................

REGISTERS .................................................................................................................................... 31

EXAMPLE TIMINGS FOR COMMUNICATION .............................................................................. 61

EXAMPLE MICROCOMPUTER PROCESSING FLOW ................................................................ 69

6.1

COMMUNICATION FLAGS ....................................................................................................................

6.2

MAIN ROUTINE ......................................................................................................................................

6.3

INTERRUPT ROUTINE ...........................................................................................................................

6.4

PROCESSING ROUTINES .....................................................................................................................

6.4.1

PD72042A or

PD72042B Initial Setting Routine ....................................................................

6.4.2

Communication Flag Initialization Routine .................................................................................

6.4.3

Command Processing Routine ...................................................................................................

6.4.4

Master Communication Processing Routine ..............................................................................

6.4.5

Slave Data Transmission Processing Routine ...........................................................................

6.4.6

Transmission Processing Routine ..............................................................................................

6.4.7

Reception Processing Routine ...................................................................................................

ELECTRICAL CHARACTERISTICS .............................................................................................. 84

PACKAGE DRAWING ..................................................................................................................... 88

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

1. PIN FUNCTIONS

1.1 PIN FUNCTIONS

Pin No.

Note

SCK

SI (SIO)

SO (NC)

IRQ

C/D

GND

BUS

BUS+

SEL

I/O

Note

Input

Input (I/O)

Output

(none)

Output

Input

I/O

Input

Function

Serial clock input pin for CPU interface

Serial data pin for CPU interface. (This pin

functions as an input pin when 3-wire serial

I/O mode is selected, or as an I/O pin when

2-wire serial I/O mode is selected.)

Serial data output pin for CPU interface. (The

pin functions as an output when 3-wire serial I/O

mode is selected. When 2-wire serial I/O mode

is selected, the pin is left open.)

Output pin for making an interrupt request to the

CPU. When a return code or a program crash is

detected, a high-level signal is output on this pin

for at least 8

Input pin used to select control mode or data

read/write mode. When this pin is driven high,

internal register address setting and data read/

write are enabled. When the mode changes, the

serial clock counter is reset.

Pins for connecting a system clock resonator. A

6- or 6.29-MHz crystal or ceramic resonator

must be used. The accuracy of the frequency is

as follows;

Mode 0, 1:

1.5%

Ground pin

I/O pins connected to the IEBus bus

Main power supply pin for the IEBus bus driver/

receiver. When used, this pin must be tied to

Input pin used to select either 3- or 2-wire serial

I/O mode. A high-level signal on this pin selects

3-wire serial I/O mode. A low-level signal on this

pin selects 2-wire serial I/O mode.

Chip select pin. When this pin is driven low, the

serial interface is enabled. When this pin is

driven high, the SO pin becomes high-imped-

ance, and the serial clock counter is reset.

When reset

[for both hardware

and software]

Input

High-impedance

Low level

Input

When reset by

hardware (Oscil-

lation stopped)

XI = GND

XO = High level

When reset by

software (Oscil-

lation continued)

High-impedance

Input

I/O format

Note

CMOS input

(CMOS I/O)

CMOS output

(none)

CMOS output

CMOS input

Note

Parentheses indicate the state corresponding to two-wire serial I/O mode.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

2.2 IEBus COMMUNICATION PROTOCOL

The IEBus is outlined below.

· Communication method: Half duplex asynchronous communication

· Multi-master method

All units connected to the IEBus can transmit data to every other connected unit.

· Broadcast function (one-unit-to-multiple-units communication)

Group broadcast

: Broadcast to a specific group of units

General broadcast

: Broadcast to all units

· Two modes, each offering different transmission speeds, can be selected.

Maximum number of bytes

transmitted (bytes/frame)

Mode 0

Approx. 3.9 Kbps

Approx. 4.1 Kbps

Mode 1

Approx. 17 Kbps

Approx. 18 Kbps

= 6 MHz

= 6.29 MHz

· Access control: Carrier Sense Multiple Access with Collision Detection (CSMA/CD)

Bus mastership priority is as follows:

1 Broadcast takes priority over ordinary communication (one-unit-to-one-unit communication).

2 Units having lower master addresses have a higher priority.

· Communication scale

Number of units

: 50 max

Cable length

: 150 m max (when twisted-pair cable is used <resistance 0.1

/m or less>)

Load capacity

: 8000 pF max <between BUS- and BUS+>, f

= 6 MHz

7100 pF max <between BUS- and BUS+>, f

= 6.29 MHz

Terminating resistance

: 120

Caution For the

PD72042A and

PD72042B, as a protective resistance, connect a 180-

resistor in series

with the BUS and BUS+ pins.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

2.2.1 Bus Mastership Determination (Arbitration)

Before devices connected to the IEBus can control other devices, they must first acquire the bus. This operation

is called arbitration.

When more than one unit starts transmission at the same time, arbitration determines which of those units is allowed

to use the bus.

When arbitration results in only one device being granted bus mastership, the following bus mastership priority

conditions are used:

Remark Those devices that are defeated in arbitration can automatically enter retransmission mode. (For the

PD72042A and

PD72042B, the number of retransmissions can be set by specifying a value between

0 and 7 in the MCR register.)

(1) Priority by communication type

Broadcast (one-unit-to-multiple-units communication) takes priority over ordinary communication (one-unit-to-

one-unit communication).

(2) Priority by master address

If the communication type is the same, the smallest master address value has the highest priority.

Example Each master address consists of 12 bits. A unit having master address 000H has the highest priority,

while a unit having master address FFFH has the lowest priority.

2.2.2 Communication Mode

The IEBus supports two communication modes, each having a different transmission speed. Table 2-1 lists the

transmission speed for each communication mode and the maximum number of bytes transmitted within one

communication frame.

Table 2-1

Transmission Speed and Maximum Number of Transmission

Bytes in Each Communication Mode

Communication mode

Maximum number of transmission

Effective transmission speed

Note 1

(Kbps)

bytes (bytes/frame)

= 6 MHz

Note 2

= 6.29 MHz

Note 2

Approx. 3.9

Approx. 4.1

Approx. 17

Approx. 18

Notes 1. Effective transmission speed at which the maximum transfer rate is achieved

2. Oscillator frequencies for the

PD72042A and

PD72042B

Cautions 1. Before devices connected to the IEBus can perform communication, an appropriate commu-

nication mode must be set. Note that if a master unit and an associated unit (slave unit) have

different communication modes, they will not be able to communicate properly.

2. Communication cannot be performed properly between a unit operating at an oscillator

frequency of 6 MHz and another operating at 6.29 MHz, even when set to the same communication

mode. Units must use the same oscillator frequency to be able to communicate.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

2.2.3 Communication Address

With the IEBus, each device is assigned a unique 12-bit communication address. The communication address

consists of the following parts:

High-order 4 bits

: Group number (number identifying the group to which a device belongs)

Low-order 8 bits

: Unit number (number identifying a device in a group)

2.2.4 Broadcast

In ordinary communication, transmission and reception are performed between one master unit and one associated

slave unit. Broadcast can also be done between one master unit and more than one slave unit. In this case master

unit transmits data to an arbitrary number of slave units. In this case, the slave units do not return on acknowledge

signal to the master unit.

Whether the communication to be performed is broadcast or ordinary communication is determined by the setting

of the broadcast bit. (For details of the broadcast bit, see (1) 2 in Section 2.3.)

There are two types of broadcast.

(1) Group broadcast

Broadcast is performed to the devices in a particular group. These devices all have the same group number,

as indicated by the high-order 4 bits of each communication address.

(2) General broadcast

Broadcast is performed to all devices, regardless of their group numbers.

These two types of broadcast are distinguished by the slave address. (For details of the slave address, see (3)

in Section 2.3.)

2.3 TRANSMISSION PROTOCOL

Fig. 2-1 shows the IEBus transmission signal format.

Communication data is transmitted as a sequence of signals called a communication frame. The transmission

speed and the maximum amount of data that can be transmitted in one communication frame depend on the

communication mode.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Fig. 2-1 Transmission Signal Format

Field name

Number of bits

Header

Master

address field

Slave

address field

Control field

Data-length

field

Data field

Start

bit

Broad-
cast
bit

Master

address

Slave

address

A Control

bits

Data-

length

bits

Data

bits

Data

bits

Transmission

time

Mode 0

Mode 1

(When f

= 6 MHz)

Approx. 7330

Approx. 2090

Approx. 1590

Approx. 410

P : Parity bit (1 bit)

A : Acknowledge bit (1 bit)

When A = 0: ACK

When A = 1: NAK

N : Number of data bytes

Remark For broadcast, the value of the acknowledge bit is ignored.

(1) Header

The header consists of a start bit and a broadcast bit. These are explained below.

Start bit

The start bit is a signal used to notify the other units of the beginning of data transmission.

Before a unit starts data transmission, it outputs a low-level signal (start bit) for a specified duration, then

outputs the broadcast bit.

When the unit attempts to output the start bit, another unit may have already output the start bit. In such

a case, the unit does not output the start bit, and instead waits for the other unit to stop outputting the start

bit. Then, synchronized with the completion of start bit output by the other unit, the unit starts output of the

broadcast bit.

All units, except that unit which started the transmission, detect the start bit and become ready for reception.

Broadcast bit

The broadcast bit is used to distinguish between broadcast and ordinary communication.

If the broadcast bit is 0, broadcast is indicated. If the broadcast bit is 1, ordinary communication is indicated.

There are two types of broadcast: group broadcast and general broadcast. These types are distinguished

by the slave address. (For details of the slave address, see (3).)

For broadcast, more than one slave unit can exist as an associated communication station. Therefore, the

acknowledge bits for the master address field and subsequent fields are not returned.

When more than one unit starts sending a communication frame at the same time, broadcast takes

precedence over ordinary communication and wins arbitration.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(2) Master address field

The master address field is used to transmit the local unit address (master address) to other units.

The master address field consists of master address bits and a parity bit.

A master address consists of 12 bits. It is output starting with the MSB.

When more than one unit starts transmitting the same broadcast bit value at the same time, arbitration

determination is performed by the master address field.

Each time a unit transmits one bit of the master address field, the unit compares its output data with the data

on the bus. If the comparison indicates that the master address output by the unit differs from the data on the

bus, the unit determines that it has lost an arbitration. The unit stops transmission, and readies itself for reception.

The IEBus is organized by wired AND. When arbitration is performed between units (arbitration masters), the

unit having the smallest master address value wins the arbitration.

After the 12-bit master address has been output, only one unit is finally determined as being the master unit,

such that that unit remains in the transmission state.

Next, the master unit outputs a parity bit

Note

to post the master address to other units. Then, the master unit

proceeds to the slave address field.

Note

Even parity is used. When the number of 1's in the master address bits is odd, the parity bit is set to 1.

(3) Slave address field

The slave address field is used to transmit the address (slave address) of a unit (slave unit) with which the master

unit wants to communicate.

The slave address field consists of slave address bits, a parity bit, and an acknowledge bit.

A slave address consists of 12 bits. It is output starting with the MSB. After a 12-bit slave address has been

transmitted, a parity bit is output to prevent the slave address from being received incorrectly. Then, the master

unit attempts to detect the acknowledge signal from a slave unit to confirm that the slave unit exists on the bus.

When the acknowledge signal is detected, the master unit outputs a control field. Note, however, that when

performing broadcast, the master unit outputs the control field without attempting to detect the acknowledge bit.

The slave unit outputs an acknowledge signal when the slave unit recognizes a match between the slave unit's

address and the slave address transmitted by the master unit match, and that both the master address and slave

address have even parity. If the slave unit detects odd parity, it does not recognize the addresses as matching,

so does not output an acknowledge signal. In this case, the master unit is placed in the standby (monitor) state,

and communication terminates.

For broadcast, the slave address is used to distinguish between group broadcast or general broadcast, as follows:

When the slave address is FFFH

General broadcast

When the slave address is other than FFFH

Group broadcast

Remark For group broadcast, the number of a target group is indicated by the high-order 4 bits of the slave

address.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(4) Control field

The control field indicates the type and direction of the next data field.

The control field consists of control bits, a parity bit, and an acknowledge bit.

The four control bits are output starting with the MSB.

Following the control bits, a parity bit is output. If even parity is detected, and the function requested by the master

unit can be performed by the slave unit, the slave unit outputs an acknowledge signal. Then, the slave unit

proceeds to the data-length field. If the slave unit cannot perform the processing requested by the master unit,

even when even parity is detected, or if odd parity is detected, the slave unit does not output an acknowledge

signal, and it enters the standby (monitor) state again.

After detecting the acknowledge signal, the master unit proceeds to the data-length field.

If an acknowledge signal is not detected, the master unit enters the standby state, terminating communication.

For broadcast, however, the master unit proceeds to the next data-length field without attempting to detect the

acknowledge signal.

Table 2-3 lists the meanings of the control bits.

(5) Data-length field

The data-length field specifies the communication data length, in bytes.

The data-length field consists of the data-length bits, a parity bit, and an acknowledge bit.

The eight data-length bits are output starting with the MSB. The data-length bits indicate the communication

data length, in bytes, as shown in Table 2-2.

Table 2-2 Values of the Data-Length Bits and Their Meanings

Data-length bit (hexadecimal)

Transmission data length, in bytes

01H

02H

FFH

255

00H

256

Remark If the data length set in the data-length bits exceeds the maximum number of transmission bytes, the

latter varying with the communication mode, more than one frame is transmitted. In the second and

subsequent frames, the data-length bits indicate the remaining communication data length, in bytes.

The operation performed for this field differs depending on whether master transmission (when bit 3 of the control

bits is 1) or master reception (when bit 3 of the control bits is 0) is performed.

Master transmission

The data-length bits and parity bit are output by the master unit. When the slave unit detects even parity,

the slave unit outputs an acknowledge signal, then proceeds to the data field. For broadcast,

however, the slave unit does not output an acknowledge signal.

If the slave unit detects odd parity, the slave unit does not output an acknowledge signal, regarding the

received data-length bits as being incorrect. Then, the slave unit enters the standby (monitor) state again.

At this time, the master unit also enters the standby state again, and communication terminates.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Master reception

The data-length bits and parity bit are output by the slave unit. When the master unit detects even parity,

the master unit outputs the acknowledge signal.

If the master unit detects odd parity, the master unit does not output an acknowledge signal, regarding the

received data-length bits as being incorrect. Then, the master unit enters the standby state again. At this

time, the slave unit also enters the standby state again, and communication terminates.

(6) Data field

The data field is used for data transmission and reception to and from a slave unit.

The master unit uses the data field to transmit data to the slave unit, or to receive data from the slave unit.

The data field consists of data bits, a parity bit, and an acknowledge bit.

The eight data bits are output, starting with the MSB.

After the data bits have been output, the parity bit and acknowledge bit are output from the master unit and slave

unit, respectively.

Broadcast is performed only when the master unit transmits data. At this time, any acknowledge signal is ignored.

The operations related to master transmission and master reception are explained below.

Master transmission

When the master unit performs a write to a slave unit, the master unit transmits the data bits and a parity

bit to the slave unit. The slave unit receives the data bits and parity bit, then outputs an acknowledge signal

if even parity is detected and the reception buffer is empty. If odd parity is detected, or if the reception buffer

is not empty, the slave unit rejects the corresponding data, and does not output an acknowledge signal.

If no acknowledge signal is received from the slave unit, the master unit transmits the same data

again. The master unit repeats this operation until it receives an acknowledge signal from the slave unit,

or until the data exceeds the maximum number of transmission bytes.

When even parity is detected, and an acknowledge signal is received from the slave unit, the master unit

transmits the subsequent data, if any, and provided the maximum number of transmission bytes is not

reached.

For broadcast, an acknowledge signal is not output by any slave unit. The master unit transfers data one

byte at a time.

Master reception

When the master unit reads data from a slave unit, the master unit outputs a synchronization signal for each

bit as it is read.

The slave unit outputs data and a parity bit to the bus according to the synchronization signal output by the

master unit.

The master unit reads the data and parity bit output by the slave unit, and checks the parity.

If the master unit detects odd parity, or if the reception buffer is not empty, the master unit rejects the data,

and does not output an acknowledge signal. The master unit repeats the read operation for the same data

provided the maximum allowable number of transmission bytes per communication frame has not been

reached.

If the master unit confirms even parity, and the reception buffer is empty, the master unit accepts the data,

and returns an acknowledge signal to the slave unit. Then, the master unit reads the next data, provided

the maximum allowable number of transmission bytes per frame has not been reached.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(7) Parity bit

A parity bit is used to check for errors in the transmission data.

A parity bit is added to the master address bits, slave address bits, control bits, data-length bits, and data bits.

Even parity is used. If the number of 1's in the data is odd, the parity bit is set to 1. If the number of 1's in the

data is even, the parity bit is set to 0.

(8) Acknowledge bit

In ordinary communication (one-unit-to-one-unit communication), an acknowledge bit is added in the following

positions to confirm that data has been received correctly:

· At the end of the slave address field

· At the end of the control field

· At the end of the data-length field

· At the end of the data field

The acknowledge bit is defined as follows:

· 0: Indicates that transmission data has been recognized. (ACK)

· 1: Indicates that no transmission data has been recognized. (NAK)

For broadcast, the acknowledge bit is ignored.

Acknowledge bit at the end of the slave address field

If any of the following is detected, the acknowledge bit at the end of the slave address field is set to NAK,

and transmission is stopped:

· The parity of the master address bits or slave address bits is incorrect.

· A timing error occurred (bit format error).

· No slave unit is found.

Acknowledge bit at the end of the control field

If any of the following is detected, the acknowledge bit at the end of the control field is set to NAK, and

transmission is stopped:

· The parity of the control bits is incorrect.

· Although the slave reception buffer

Note

is not empty, bit 3 of the control bits is 1 (write operation).

· Although the slave transmission buffer

Note

is empty, the control bits indicate data read (3H, 7H).

· For a locked unit, a unit other than the unit that specified the lock makes a request by using control bits

indicating 3H, 6H, 7H, AH, BH, EH, or FH.

· Although no lock has been set, control bits indicating lock address read (4H) are set.

· A timing error occurred.

· An undefined control bit setting has been made.

Note

See (1) in Section 2.4.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Acknowledge bit at the end of the data-length field

If any of the following is detected, the acknowledge bit at the end of the data-length field is set to NAK, and

transmission is stopped:

· The parity of the data-length bits is incorrect.

· A timing error occurred.

Acknowledge bit at the end of the data field

If any of the following is detected, the acknowledge bit at the end of the data field is set to NAK, and

transmission is stopped:

· The parity of the data bits is incorrect

Note

· A timing error occurred after the previous acknowledge bit.

· The reception buffer is full, such that no more data can be accepted

Note

In this case, if the maximum allowable number of transmission bytes per frame has not yet been reached,

the transmitter retries transmission of the data field until the maximum number of transmission bytes is

reached.

2.4 TRANSMISSION DATA (CONTENTS OF THE DATA FIELD)

The contents of the data field are indicated by the control bits.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Table 2-3 Meanings of the Control Bits

Bit 3

Note 1

Bit 2

Bit 1

Bit 0

Function

Note 2

Read slave status (SSR)

Undefined

Read data and locking

Read lock address (low-order 8 bits)

Read lock address (high-order 4 bits)

Read slave status (SSR) and unlocking

Read data

Undefined

Write command and locking

Write data and locking

Undefined

Write command

Write data

Notes 1. The transfer direction of the data-length bits of the subsequent data-length field and data in the data

field changes according to the value of bit 3 (MSB).

When bit 3 is 1: Transfer from the master unit to the slave unit

When bit 3 is 0: Transfer from the slave unit to the master unit

2. The values of control bits 3H, 6H, AH, and BH specify locking and unlocking. When an undefined value,

1H, 2H, 8H, 9H, CH, or DH, is transmitted, no acknowledge signal is returned.

Once a unit has been locked by a master unit, the locked unit rejects the control bits received from other than the

master unit that requested the lock, unless the value of the control bits is one of the values listed in Table 2-4. Then,

the unit does not output the acknowledge bit.

Table 2-4 Control Field Acceptable to a Locked Slave Unit

Bit 3

Bit 2

Bit 1

Bit 0

Function

Read slave status

Read lock address (low-order 8 bits)

Read lock address (high-order 4 bits)

(1) Reading the slave status (SSR) (control bits: 0H, 6H)

A master unit can read the slave status (0H, 6H) to determine why the slave unit did not return the acknowledge

bit (ACK).

The slave status is determined from the result of the communication last performed by the slave unit.

All slave units can provide slave status information.

Table 2-5 lists the slave status meanings.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Fig. 2-2 Slave Status (SSR) Bit Format

MSB

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

LSB

Table 2-5 Slave Status Meanings

Bit

Value

Meaning

Bit 0

Note 1

The slave transmission buffer is empty.

The slave transmission buffer is not empty.

Bit 1

Note 2

The slave reception buffer is empty.

The slave reception buffer is not empty.

Bit 2

The unit is not locked.

The unit is locked.

Bit 3

Fixed at 0

Bit 4

Note 3

Slave transmission disabled

Slave transmission enabled

Bit 5

Fixed at 0

Bit 7

Mode 0

Bit 6

Mode 1

Reserved for future expansion

Indicates the highest

mode supported by the

unit

Note 4

Notes 1. The slave transmission buffer is accessed during a data read operation (control bits: 3H, 7H).

For the

PD72042A and

PD72042B, this buffer corresponds to the TBF available when STRQ of the

FLG register is set to 1.

2. The slave reception buffer is accessed during a data write operation (control bits: 8H, AH, BH, EH, FH).

For the

PD72042A and

PD72042B, this buffer corresponds to the RBF available when SLRE of the

FLG register is set to 1.

3. The value of bit 4 can be selected by using the UAR1 register.

4. Bits 7 and 6 are currently fixed to 10 in the hardware of the

PD72042A and

PD72042B.

(2) Data/command transfer (control bits: Read (3H, 7H), write (AH, BH, EH, FH))

When data read (3H, 7H) is set, the data in the data buffer of the slave unit is read into the master unit.

When data write (BH, FH) or command write (AH, EH) is set, the data received by the slave unit is processed

according to the operation specifications for the slave unit.

Remarks 1. The user can select data and commands as necessary according to the system.

2. 3H, AH, and BH may cause locking, depending on the communication conditions and status.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(3) Reading a lock address (control bits: 4H, 5H)

When a lock address read operation (4H, 5H) is specified, the address (12 bits) of the master unit that

issued the lock instruction is read in one-byte form, as shown below.

Fig. 2-3 Lock Address Format

MSB

LSB

Control bits : 4H

Control bits : 5H

Low-order 8 bits

Undefined

High-order 4 bits

(4) Locking and unlocking (control bits: Locking (3H, AH, BH), unlocking (6H))

The lock function is used to enable the transfer a message using more than one communication frame.

When locked, a unit cannot receive data from other than the unit that requested the lock.

Locking and unlocking are performed as follows:

Locking

The master unit can lock the slave unit by specifying the lock with the corresponding control bits (3H, AH,

BH). In this case, when the transmission or reception of acknowledge bit 0 for the data-length field has been

completed, but the communication frame is then terminated before transmission or reception of as many data

bytes as are specified by the data-length bits is completed, the slave unit is locked. At this time, the bit

indicating the lock status (bit 2) in the slave status byte is set to 1.

Unlocking

The master unit can unlock a locked slave unit when the control bits specify locking (3H, AH, or BH) or

unlocking (6H). The slave unit is unlocked once as many data bytes as are specified by the data-length bits

have been transmitted or received within one communication frame. At this time, the bit indicating the lock

status (bit 2) in the slave status byte is reset to 0.

For broadcast, locking or unlocking is not performed.

Caution When a locked unit is to be unlocked by the unit itself, hardware reset or software reset must

be performed. (The lock status can be checked by referring to the contents of the LOR2 register.)

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

2.5 BIT FORMAT

Fig. 2-4 illustrates the bits that constitute an IEBus communication frame.

Fig. 2-4 IEBus Bit Format (Concept)

Logic "1"

Logic "0"

Preparation

period

Synchronization

period

Data period

Preparation

period

Synchronization

period

Data period

Logic 1: The potential difference between the bus lines (the BUS+ and BUS- pins) is 20 mV or less (low level).

Logic 0: The potential difference between the bus lines (the BUS+ and BUS- pins) is 120 mV or more (high level).

Preparation period

: First and subsequent low-level (logic 1) periods

Synchronization period

: Next high-level (logic 0) period

Data period

: Period in which a bit value is indicated (logic 1 = low level, logic 0 = high level)

The synchronization and data periods are almost equal in duration.

For the IEBus, synchronization is established for each bit. The specifications of the total time required for a bit

and the duration of each period allotted within the bit vary depending on the type of the transmission bits, and whether

the unit is a master or slave.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

3. MICROCOMPUTER INTERFACE

3.1 TRANSFER METHOD

Either of two microcomputer interface modes can be selected: three-wire serial I/O mode or two-wire serial I/O

mode.

Whether three-wire serial I/O mode or two-wire serial I/O mode is selected depends on the input level of the SEL

pin (pin 12). (See Section 3.3 for details.)

SEL

1: Three-wire serial I/O

SEL

0: Two-wire serial I/O

(1) Three-wire serial I/O (SEL

Three wires are used to read and write data. The three wires are the serial clock input (SCK), serial data input

(SI

Note 1

), and serial data output (SO

Note 2

(a) Read operation

Data is output to the SO pin upon detecting the falling edge of the SCK pin.

(b) Write operation

Data is input via the SI pin upon detecting the rising edge of the SCK pin. At this time, 1 is output on the

SO pin.

(2) Two-wire serial I/O (SEL

Two wires are used to read and write data. The two wires are the serial clock input (SCK) and serial data I/O

(SIO

Note 1

(a) Read operation

The SIO pin is placed in the output state, and data is output upon detecting the falling edge of the SCK pin.

(b) Write operation

The SIO pin is placed in the input state, and data is input upon detecting the rising edge of the SCK pin.

Notes 1. The SI pin for three-wire serial I/O mode is also used as the SIO pin for two-wire serial I/O mode.

2. The impedance of the SO pin for three-wire serial I/O mode goes high in two-wire serial I/O mode. So,

connect the SO pin to GND or V

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Table 3-1 I/O States of the SIO (SI) and SO Pins

RESET

SEL

C/D

SI (SIO)

State

Three-wire/two-wire

Operating mode

Hi-Z

Reset state

Hi-Z

Chip nonselected state

Three-wire

Control mode

Data write mode

Data read mode

Hi-Z

Two-wire

Control mode

Data write mode

Data read mode

: Input state

Hi-Z : High-impedance state

: Output state

: Don't care

O* : State in which 1 is output

3.2 DATA TRANSFER FORMAT

3.2.1 Three-Wire Data Transfer (SEL = 1)

(1) Control mode

When the C/D input is set high, control mode is set to control data transfer. Data transfer control involves the

following processing.

(a)

PD72042A (starting with MSB)

(b)

PD72042B (starting with LSB)

C/D

SCK

A3 A2 A1 A0

× × ×

C/D

SCK

× × ×

Remark After reset (RESET) cancellation, the state enabling writing to the register at address 0000B is set.

Caution In control mode, each data item is read every eighth clock pulse. (Data of less than eight clock

periods is ignored.)

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(2) Data read mode

When the C/D pin is set low after register read is selected in control mode, the data read mode is set. In data

read mode, the data in a read register is read on the SO pin upon detecting the falling edge of the SCK pin.

(a)

PD72042A (starting with MSB)

C/D

SCK

D7 D6

D5 D4

D3 D2

D1 D0

State

Control mode

(selection of register read)

Data read mode

Serial clock counter

reset pointer

"1"

(b)

PD72042B (starting with LSB)

C/D

SCK

D0 D1

D2 D3

D4 D5

D6 D7

State

Control mode

(selection of register read)

Data read mode

Serial clock counter

reset pointer

"1"

Caution When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore, the

remaining bits of the byte cannot be read; at the next falling edge, read is performed starting from

the next byte in the case of RBF, or from the first bit for other registers.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(2) Data read mode

(a)

PD72042A (starting with MSB)

C/D

SCK

SIO

Note

Serial clock counter

reset pointer

State

Control mode

(selection of register read)

Data read mode

(b)

PD72042B (starting with LSB)

C/D

SCK

SIO

Note

Serial clock counter

reset pointer

Control mode

(selection of register read)

Data read mode

State

Note

SIO pin input state

SIO pin output state

Cautions 1. When the C/D pin is set high in data read mode, the serial clock counter is reset. Therefore,

the remaining bits of the byte cannot be read; at the next falling edge, a read operation is

performed starting from the next byte in the case of RBF, or from the first bit for other registers.

2. The SIO pin is a CMOS I/O pin. So, be careful to avoid an output collision between the SIO

pin and the microcomputer. Further, a pull-up resistor is required when N-ch open-drain

output of the microcomputer is used. Note that if the last output level is low upon the

termination of read mode, current will flow constantly.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

3.3 CONNECTION TO A MICROCOMPUTER

(1) Three-wire serial I/O

120

5 V

TEST

BUS+

BUS

GND

SEL

Note 1

C/D

SCK

IRQ

Note 2

RESET

Output port

SCK

INT

Low

voltage

detection

circuit

75XL series
78K series

180

6 MHz

120

5 V

PD72042A
PD72042B

Microcomputer

(2) Two-wire serial I/O

Microcomputer

120

5 V

180

6 MHz

120

75XL series
78K series

Low

voltage

detection

circuit

TEST

BUS+

BUS

GND

SEL

Note 1

C/D

SCK

SIO

IRQ

Note 2

RESET

Output port

SCK

SIO

INT

Note 3

PD72042A
PD72042B

5 V

Notes 1. When only the

PD72042A or

PD72042B is to be controlled from a microcomputer via a serial I/O

interface, the CS pin must be tied low (by connecting it to GND).

2. When an interrupt is detected by polling (in FLG register read), IRQ may be left open. When high-volume

or high-speed data transfer is required, however, the system described above is recommended to ensure

reliable data transfer.

3. Required when the microcomputer's N-ch open-drain output is used. The SIO pin of the

PD72042A

and

PD72042B is a CMOS I/O pin.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

3.4 STANDBY MODE SETTING AND CANCELLATION

Standby mode can be set by setting STREQ of the CTR register to 1. The XI pin for oscillation is tied to GND,

and the impedance of the XO pin goes high.

In standby mode (with the STM flag of the FLG register set to 1), only the following registers can be accessed:

Writable register

: CTR (address 0000B)

Readable register : FLG (address 0001B)

Standby mode can be cancelled by setting STREQ of the CTR register to 0.

Caution Do not read any data from internal registers via the serial I/O during the period from when a

microcomputer sets the STREQ flag to 1 to when the

PD72042A or

PD72042B enters the

standby mode. This period is one-communication frame at maximum.

3.5 RESET MODE SETTING AND CANCELLATION

For hardware reset, the registers are initialized and standby mode is set. (During this period, oscillation is stopped.)

For software reset, the registers are initialized, and operation is started.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Address

Name

High-order 4 bits

Low-order 4 bits

Note

Reference page

0000

CTR

REEN SRST

STREQ

p. 33

0001

CMR

LOCK

BUFC

COMC

p. 34

IRS

MFC

DERC

0010

UAR1

Local station address

Condition code

p. 36

(low-order 4 bits)

0011

UAR2

Local station address (high-order 8 bits)

p. 36

0100

SAR1

Slave address

p. 37

(low-order 4 bits)

0101

SAR2

Slave address (high-order 8 bits)

p. 37

0110

MCR

Broadcast bits

Number of

Control bits

p. 38

arbitrations

0111

1000

1110

TBF

Number of bytes of transmission data, transmission data

p. 40

Table 4-1

PD72042A and

PD72042B Registers

(a) Write registers

(b) Read registers

Address

Name

High-order 4 bits

Low-order 4 bits

Note

Reference page

0000

STR

TFL

TEP

RFL

REP

p. 41

0001

FLG

MARQ STRQ SLRE

CEX

RAW

STM

IRQ

p. 42

0010

RDR1

Number of bytes of master reception data

p. 44

0011

RDR2

Number of bytes of slave reception data or

p. 44

broadcast reception data

0100

LOR1

Lock address (low-order 8 bits)

p. 45

0101

LOR2

Lock state

Lock address

p. 45

(high-order 4 bits)

0110

DAR1

Broadcast address

p. 46

(low-order 4 bits)

0111

DAR2

Broadcast address (high-order 8 bits)

p. 46

1000

RCR

Return codes (MARC, SLRC)

p. 47

1110

RBF

Transmitter address, reception data

p. 59

Note

Writable and readable periods of the registers of the

PD72042A and

PD72042B

A: Arbitrary

B: After system reset cancellation

C: While CEX of the FLG register (address 0001) is set to 0

D: While MARQ of the FLG register (address 0001) is set to 0

E: After SLRC of the RCR register (address 1000) is set to 1100 (broadcast reception error)

F: While TFL of the STR register (address 0000) is set to 0

G: While REP of the STR register (address 0000) is set to 0

H: When CEX of the FLG register (address 0001) is set to 0 after LOCK of the CMR register (address 0001)

is set to 1

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Cautions 1. In standby mode (with STM of the FLG register set to 1), the user can only write to the CTR

register (including standby mode cancellation) and read from the FLG register.

2. Never access a free address.

3. Slave status (SSR) can be read into RBF by setting the control bits to 0H or 6H from the master

unit.

CTR

Address

: 0000B (0H)

Read/write

: Write

Control register

When reset :

×××

××

CTR is a one-byte write register used to control

PD72042A and

PD72042B operations.

CTR

REEN

SRST

STREQ

[REEN]

When REEN is set to 1, the SLRE flag of the FLG register is immediately set to 1 to enable both slave and broadcast

reception.

[SRST]

When SRST is set to 1, the

PD72042A or

PD72042B is immediately reset. (Note, however, that STREQ is set

to a written value.)

[STREQ]

1: Requests standby mode.

0: Exits from standby mode.

· Standby mode setting and cancellation

The

PD72042A or

PD72042B is requested to enter the standby mode by setting the STREQ flag to 1 from the

microcomputer. The

PD72042A or

PD72042B enters standby mode when the standby mode input enabled state

(carrier sense state) is set. In this case, the impedance of the BUS+ and BUS pins goes high (logic 1), and the

STM flag of the FLG register is set to 1. In standby mode, oscillation is stopped, and all operations are stopped

while preserving the internal data, thus minimizing power consumption.

When, in standby mode, the STREQ flag is set to 0 from the microcomputer, standby mode is cancelled

after the period (about 20 ms at f

= 6 MHz) needed for oscillation to stabilize; the halted operations are resumed

from the point at which standby mode was set. At this time, the STM flag of the FLG register changes to 0.

In standby mode, only writing to the CTR register (for standby mode cancellation) and reading from the FLG register

can be performed from the microcomputer.

Cautions 1. When the SRST flag and STREQ flag are simultaneously set to 1, standby mode is set after

software reset. (This state is the same as that set by hardware reset.) Note, however, that

when the SRST flag is set to 1 in standby mode, a software reset is performed, but this is not

reflected in the FLG register.

2. Do not read any data from internal registers via the serial I/O during the period from when a

microcomputer sets the STREQ flag to 1 to when the

PD72042A or

PD72042B enters the

standby mode. This period is one-communication frame at maximum.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

CMR

Address

: 0001B (1H)

Read/write

: Write

Command register

When reset : 00000000B

CMR is a one-byte write register used to set a command for communication control, transmission/reception buffer

control, or optional function setting.

When data is set in CMR from the microcomputer, CEX of the FLG register is set to 1. When the

PD72042A

PD72042B processes the data set in CMR, CEX is set to 0.

After the microcomputer checks that CEX of the FLG register is set to 0, new data can be set in CMR.

The following describes the data that is set in CMR.

(1) When bit 7 (MSB) of CMR is 0

LOCK

BUFC

COMC

CMR

[LOCK]: Lock state setting command

1 : The value representing the lock state (0001 for locked or 0000 for not-locked) and lock address are output

to LOR1 and LOR2. Note, however, that when 0000 (not-locked) is output, any lock address value is ignored.

0 : The contents of LOR1 and LOR2 remain as is.

[BUFC]: Transmission/reception buffer control command

00 : The transmission and reception buffers remain as is.

01 : The transmission buffer (TBF) is cleared.

10 : The reception buffer (RBF) is cleared.

11 : The data of the previous (latest) communication frame to be stored in the reception buffer (RBF) is

cleared

Note 1

[COMC]: Communication control command

0000: Communication operation remains as is.

0001: The locked state is cancelled.

1000: Master communication is requested

Note 2

1001: Master communication is requested, with the previous master transmission state held

Note 3

1010: Master communication is aborted.

1011: Slave data transmission is requested

Note 4

1100: Slave data transmission is requested, with the previous slave data transmission state held

Note 5

1101: Slave data transmission is aborted.

1111: Slave reception and broadcast reception are disabled.

Notes 1. If the microcomputer has already read the data for the previous (latest) communication frame from RBF,

or optional function setting in CMR is selected and MFC = 0, clear RBF with BUFC = 10.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Notes 2. When the MSB of the control bits set in MCR is 1 (for master transmission), set the number of bytes

of transmission data, and at least one byte of transmission data in TBF before command setting.

3. When the MSB of the control bits set in MCR is 1 (for master transmission), set at least one byte of

transmission data before command setting. This operation is not required if all transmission data has

already been set in TBF.

4. Set the number of bytes of transmission data, and at least one byte of transmission data in TBF before

command setting.

5. Set at least one byte of transmission data in TBF before command setting. This operation is not required

if all transmission data has already been set in TBF.

(2) When bit 7 (MSB) of CMR is 1

An optional function is set.

IRS

CMR

MFC

DERC

[MFC]: Selection of one frame/multiple frames

1 : Data for multiple frames is stored in RBF.

0 : Data for only one frame is stored in RBF.

[DERC]: Broadcast reception selection

1 : The issue of return code 1100 (broadcast reception error) for SLRC of the RCR register is enabled.

0 : The issue of return code 1100 (broadcast reception error) for SLRC of the RCR register is disabled.

[IRS]: Interrupt generation condition selection

0 : An interrupt is requested when the data of the RCR register changes.

1 : An interrupt is requested when the data of the RCR register changes to other than the following:

MARC = 0000B (start of master transmission)

MARC = 0100B (start of master reception)

SLRC = 0000B (start of slave data transmission)

SLRC = 0100B (start of slave reception)

SLRC = 1000B (start of broadcast reception)

Caution Set an optional function in initialization processing after reset cancellation for the

PD72042A

PD72042B. Until an optional function has been set, the

PD72042A and

PD72042B will not

accept IEBus communication.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

UAR1

Address

: 0010B (2H) (UAR1)

UAR2

0011B (3H) (UAR2)

Read/write

: Write

Local station unit address register

When reset : Undefined (with the

previous data held)

UAR1 and UAR2 are registers used to set a local station unit address (12 bits) and condition code.

Set UAR1 and UAR2 after reset cancellation.

Local station address

(low-order 4 bits)

Condition code

UAR1

Local station address (high-order 8 bits)

UAR2

[Local station address]

A local station address is used as a master address when the local station performs communication as the master

unit. A local station address is used as a slave address when the local station performs communication as a slave.

[Condition code]

Bit position

Condition code

Condition setting

b3, b2

Communication is performed in mode 0.

Communication is performed in mode 1.

Undefined

The slave transmission section is disabled.

The slave transmission section is enabled.

Remark Bit 1 of a condition code is not used. (Set the bit to either 0 or 1.)

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

[Control bits]

This control field is used to set the control bits (four bits).

· Contents of control bits

Bit 3

Note 1

Bit 2

Bit 1

Bit 0

Function

Note 2

Slave status (SSR) read

Undefined

Data read and lock

Lock address read (low-order 8 bits)

Lock address read (high-order 4 bits)

Slave status (SSR) read and unlock

Data read

Undefined

Command write and lock

Data write and lock

Undefined

Command write

Data write

Notes 1. The value of bit 3 (MSB) determines the transfer direction of the subsequent data-length field data and

data field data.

When bit 3 is set to 1: Data is transferred from the master unit to a slave unit.

When bit 3 is set to 0: Data is transferred from a slave unit to the master unit.

2. 3H, 6H, AH, and BH are control bits used for lock setting and cancellation.

When an undefined value of 1H, 2H, 8H, 9H, CH, or DH is sent, no acknowledgement is returned.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

TBF

Address

: 1110B (EH)

Read/write

: Write

Transmission buffer

When reset : Empty

TBF is a 33-byte FIFO buffer used to hold the number of bytes of transmission data and transmission data for master

transmission and slave data transmission.

TBF can be written from the microcomputer when the TFL flag of the STR register is set to 0 (indicating that TBF

is not full).

In master transmission and slave data transmission, the following format is used to load data into TBF from the

microcomputer.

Byte 1

Number of bytes of transmission data

Byte 2

First byte of transmission data

Byte 3

Second byte of transmission data

Byte 33

...

[Byte 1]: Number of bytes of transmission data

Between 1 and 256 bytes can be set.

[Bytes 2 and up]: Transmission data

As much transmission data as is set in byte 1 is set in byte 2 and subsequent bytes.

TBF

Number of bytes of

Data set in byte 1 of TBF

transmission data

01H

02H

255

FFH

256

00H

......

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

FLG

Address

: 0001B (1H)

Read/write

: Read

Flag register

When reset : 00000010B

FLG is a one-byte read register used to indicate statuses such as the communication state, command execution

state, and interrupt state.

MARQ

STRQ

RAW

FLG

SLRE

CEX

STM

IRQ

[MARQ]

1 : A request for communication as the master unit is being made.

0 : No request for communication as the master unit is being made. Data can be written to the SAR1, SAR2, and

MCR registers.

The MARQ flag is set and reset as described below.

· Set

: When the CEX flag of the FLG register is set to 0 after 1000 or 1001 is set in COMC of the CMR register

· Reset : When master communication is terminated

[STRQ]

1 : A request for slave unit data transmission is being made.

0 : No request for slave unit data transmission is being made.

The STRQ flag is set and reset as described below.

· Set

: When the CEX flag of the FLG register is set to 0 after 1011 or 1100 is set in COMC of the CMR register

· Reset : When slave data transmission is terminated

[SLRE]

1 : Slave reception or broadcast is allowed.

0 : Slave reception and broadcast are not allowed.

The SLRE flag is set and reset as described below.

· Set

: When REEN of the CTR register is set to 1

· Reset : When slave reception or broadcast reception is terminated normally or suspended, or when CEX of

the FLG register is set to 0 after 1111 is set in COMC of the CMR register

When SLRE = 0, bit 1 of the slave status is set to 1 regardless of the state of RBF; communication frame reception

based on the AH, BH, EH, and FH control bits, received from the master station, is not performed.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

[CEX]

1 : A command is currently being executed.

0 : Execution of a command has terminated. A command code can be set in CMR.

The CEX flag is set and reset as described below.

· Set

: When a command code is set in CMR

· Reset : When

PD72042A or

PD72042B command processing is terminated

[RAW]

1 : The

PD72042A or

PD72042B is running away.

0 : The

PD72042A or

PD72042B is not running away.

The RAW flag is used to indicate a microprogram crash in the

PD72042A or

PD72042B, as detected by a

watchdog timer.

When the RAW flag is set to 1, a request to interrupt the microcomputer is issued. An interrupt pulse signal is

output on the IRQ pin, and the IRQ flag of the FLG register is set. At this time. The microcomputer must reset the

PD72042A or

PD72042B by driving the RESET pin of the

PD72042A or

PD72042B low or by setting the SRST

flag of the CTR register to 1.

[STM]

1 : Standby mode is set.

0 : Standby mode is not set.

[IRQ]

1 : An interrupt request was made.

0 : No interrupt request is made.

The IRQ flag is set when a return code including the code in the RCR register is changed

Note

, or when the RAW

flag changes from 0 to 1 (crash). When the FLG register is read with the IRQ flag set to 1, the IRQ flag is reset.

For details of the return codes, see the description of the RCR register.

Note

IRQ flag setting depends on the IRS value of the CMR register.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

RDR1

Address

: 0010B (2H) (RDR1)

RDR2

0011B (3H) (RDR2)

Read/write

: Read

Reception data register

When reset : 00H

The RDR1 and RDR2 registers are used to hold the number of bytes of reception data stored in RBF for each frame

received during master, slave, or broadcast reception.

Number of bytes of master reception data

RDR1

Number of bytes of slave or broadcast reception data

RDR2

[RDR1]

RDR1 indicates the number of bytes of data set in RBF by a communication frame during master reception. One

of the following values is set in RDR1:

· When master communication is requested (COMC = 1000 or 1001)

: RDR1 = 0

· When master reception is started (MARC = 0100)

: RDR1 = 3

· Each time one byte of data is received

: RDR1 is incremented by 1.

[RDR2]

RDR2 indicates the number of bytes of data set in RBF by a communication frame in slave reception or broadcast

reception. One of the following values is set in RDR2:

· When slave reception is started (SLRC = 0100)

: RDR2 = 3

· When broadcast reception is started (SLRC = 1000)

: RDR2 = 3

· Each time one byte of data is received

: RDR2 is incremented by 1.

· Example of RDR2 setting

Note

+ 3

Control bits P

Data-

length bits P

Data

RDR2

Communication

frame

Note

N: Number of bytes of data received with the previous communication frame

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

DAR1

Address

: 0110B (6H) (DAR1) High-order 4 bits

DAR2

0111B (7H) (DAR2)

Read/write

: Read

Broadcast address register

When reset : Undefined

The DAR1 and DAR2 registers are used to hold a broadcast address (master address) involved when a broadcast

reception error occurs.

DAR1 and DAR2 are updated each time a broadcast reception error occurs (SLRC of the RCR register is set to

1100). So, ensure that when a broadcast reception error occurs, the contents of DAR1 and DAR2 are read by the

microcomputer within the time indicated below.

Broadcast address (low-order 4 bits)

DAR1

Broadcast address (high-order 8 bits)

DAR2

· Maximum allowable DAR1 and DAR2 read time (t: At f

= 6 MHz):

Approx. 5420

s (mode 0)

Approx. 1490

s (mode 1)

Cautions 1. If the microcomputer cannot read the data in DAR1 and DAR2 within the times indicated above,

DAR1 and DAR2 may be updated by the occurrence of another broadcast reception error, and

the subsequently updated broadcast address may be read.

2. A broadcast address is stored in DAR1 and DAR2 when DERC (broadcast reception selection)

of the CMR register is set to 1.

IRQ

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

RCR

Address

: 1000B (8H)

Read/write

: Read

Return code register

When reset : 11111111B

RCR is a one-byte read register used to indicate the IEBus communication status (return code).

RCR consists of two return codes: MARC and SLRC. MARC indicates the communication status in master

transmission or master reception. SLRC indicates the communication status in slave data transmission, slave

reception, or broadcast reception. When the contents of RCR change, an interrupt request is sent to the

microcomputer according to the setting of the IRS flag of the CMR register.

The MARC and SLRC flags are set independently, such that the microcomputer can simultaneously read the master

communication status and slave communication status.

MARC

SLRC

RCR

Caution When IRQ is set as a result of a program crash, the previous value of RCR is preserved.

[MARC]

MARC represents a return code issued during master transmission or master reception.

(a) Master transmission

Master transmission is performed when the microcomputer performs the setting explained below.

· Master transmission setting

1 In the low-order 4 bits of the MCR register, control bits (1010, 1011, 1110, or 1111) are set for master-

to-slave data transfer.

2 In COMC of the CMR register, a command (1000 or 1001) for requesting master communication is set.

Table 4-2 lists the MARC return codes for master transmission.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Table 4-2 MARC Return Codes for Master Transmission

MARC

Description

0000

1. Meaning: Master transmission is started.

2. Occurrence condition: This return code is issued when the master address field in a communication

frame has been transmitted, and the unit has won the arbitration to become the master unit.

0001

1. Meaning: Master transmission data is not available.

2. Occurrence condition: This return code is issued if the next transmission data is not set in TBF during

master transmission.

3. Microcomputer processing: If data consisting of one or more bytes is not set in TBF within the time

below, transmission may be terminated prior to its completion.

· Transmission data setting time:

Approx. 1570

s (mode 0)

Approx. 390

s (mode 1)

0010

1. Meaning: Master transmission was terminated normally.

2. Occurrence condition: This return code is issued when as much data as the amount specified in the

data-length field has been transmitted normally. In this case, the MARQ flag of the FLG register changes

from 1 to 0.

0011

1. Meaning: Master transmission was aborted.

2. Occurrence condition: This return code is issued in any of the following cases. In each case, the MARQ

flag of the FLG register changes from 1 to 0.

· When the unit has lost the arbitration to become the master unit.

· When a transmission is stopped because the NAK is returned from the slave unit at the end of the slave

address field, the control field, or the data-length field of a communication frame (excluding the broadcast).

· When a communication is terminated prior to the transmission of as much data as the amount specified

in the data-length field of a communication frame.

(b) Master reception

Master reception is performed when the microcomputer performs the setting below.

· Master reception setting

1 In the low-order 4 bits of the MCR register, control bits (0000, 0011, 0100, 0101, 0110, or 0111) are set

for slave-to-master data transfer.

2 In COMC of the CMR register, a command (1000 or 1001) for requesting master communication is set.

Table 4-3 indicates the MARC return codes for master reception.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Table 4-3 MARC Return Codes for Master Communication

MARC

Description

0100

1. Meaning: Master reception has started.

2. Occurrence condition:

1 The unit has won the arbitration to become the master unit, and a communication frame up to the

data-length field was transferred successfully.

2 When the control field is received, RBF becomes ready for reception

Note

After the data-length field, 0000 is set in MARC, and three-byte data consisting of a slave address,

control bits, and data-length bits is set in RBF. If RBF becomes full when this three-byte data is set,

0001 is set in MARC.

3. Microcomputer processing: Three-byte data consisting of a slave address, control bits, and data-

length bits can be read from RBF.

0101

1. Meaning: The master reception buffer is full.

2. Occurrence condition: This return code is issued when RBF becomes full during data reception as the

master unit, and reception data cannot be set in RBF.

3. Microcomputer processing: If data consisting of one or more bytes is not read from RBF within the

time below, the one-byte data cannot be received, and the

PD72042A or

PD72042B returns an NAK.

· Reception data read time:

Approx. 1570

s (mode 0)

Approx. 390

s (mode 1)

0110

1. Meaning: Master reception was terminated normally.

2. Occurrence condition: This return code is issued when as much data as the amount specified in the

data-length field has been received normally in a communication frame. In this case, the MARQ flag of

the FLG register changes from 1 to 0.

3. Microcomputer processing: Reception data can be read from RBF, and the number of bytes of

master reception data can be read from RDR1.

0111

1. Meaning: Master reception was aborted.

2. Occurrence condition: This return code is issued in any of the following cases. In each case, the

MARQ flag of the FLG register changes from 1 to 0.

When the unit has lost the arbitration to become the master unit.

When a transmission is stopped because the NAK is returned from the slave unit at the end of the

slave address field or the control field of a communication frame or because the NAK is sent to the

slave unit at the end of the data-length field of a communication frame (excluding the broadcast).

When a communication is terminated prior to the reception of as much data as the amount specified

in the data-length field of a communication frame.

3. Microcomputer processing: Reception data can be read from RBF, and the number of bytes of

master reception data can be read from RDR1.

Note

See Note of Table 4-9.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

[SLRC]

SLRC indicates the communication status for slave data transmission, slave reception, or broadcast reception.

(a) Slave data transmission

Slave data transmission is performed when the microcomputer makes the setting described below.

· Slave data transmission setting

In COMC of the CMR register, a command (1011 or 1100) for requesting slave data transmission is set

from the microcomputer.

Table 4-6 SLRC Return Codes in Slave Data Transmission

SLRC

Description

0000

1. Meaning: Slave data transmission has been started.

2. Occurrence condition: This return code is issued when the control bits (0011 or 0111) requesting data

transmission are received from the master unit.

0001

1. Meaning: Slave transmission data is not available.

2. Occurrence condition: This return code is issued when the next transmission data is not set in TBF

during slave data transmission.

3. Microcomputer processing: If data consisting of one or more bytes is not set in TBF within the time

below, transmission may be terminated prior to its completion.

· Transmission data setting time: Approx. 1570

s (mode 0)

Approx. 390

s (mode 1)

0010

1. Meaning: Slave data transmission was terminated normally.

2. Occurrence condition: This return code is issued when as much data as the amount specified in the

data-length field has been transmitted normally. In this case, the STRQ flag of the FLG register

changes from 1 to 0.

0011

1. Meaning: Slave data transmission was aborted.

2. Occurrence condition: This return code is issued when communication is terminated prior to the

transmission of as much data as the amount specified in the data-length field in a communication frame.

In this case, the STRQ flag of the FLG register changes from 1 to 0.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(b) Slave reception

Slave reception is performed when the broadcast bit is set to 1, and a communication frame with the local

station address specified in the slave address field is received.

Table 4-7 indicates the SLRC return codes for slave reception.

Table 4-7 SLRC Return Codes for Slave Reception

SLRC

Description

0100

1. Meaning: Slave reception is started.

2. Occurrence condition:

1 A separate communication frame up to the data-length field was received normally from the

master unit.

2 Once the control field has been received, RBF is ready for reception

Note

After the data-length field, 0100 is set in SLRC, and three-byte data consisting of a master address,

control bits, and data-length bits is set in RBF.

3. Microcomputer processing: Three-byte data consisting of a master address, control bits, and data-

length bits can be read from RBF.

0101

1. Meaning: The slave reception buffer is full.

2. Occurrence condition: This return code is issued when RBF becomes full during data reception as a

slave unit, and reception data cannot be set in RBF.

3. Microcomputer processing: If data consisting of one or more bytes is not read from RBF within the

period indicated below, the one-byte data cannot be received, and the

PD72042A or

PD72042B

returns an NAK.

· Reception data read time:

Approx. 1570

s (mode 0)

Approx. 390

s (mode 1)

0110

1. Meaning: Slave reception was terminated normally.

2. Occurrence condition: This return code is issued when as much data as the amount specified in the

data-length field has been received normally in a communication frame. In this case, the SLRE flag of

the FLG register changes from 1 to 0.

3. Microcomputer processing: Reception data can be read from RBF, and the number of bytes of slave

reception data can be read from RDR2.

0111

1. Meaning: Slave reception was aborted.

2. Occurrence condition: This return code is issued when reception is terminated prior to the reception

of as much data as the amount specified in the data-length field of a communication frame. In this

case, the SLRE flag of the FLG register changes from 1 to 0.

3. Microcomputer processing: Reception data can be read from RBF, and the number of bytes of slave

reception data can be read from RDR2.

Note

See Note of Table 4-9.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(c) Broadcast reception

Broadcast reception is performed when the broadcast bit is set to 0, and a communication frame with FFH

(general broadcast) or the local station group address specified in the slave address field is received.

Table 4-8 indicates the SLRC return codes for broadcast reception.

Table 4-8 SLRC Return Codes for Broadcast Reception

SLRC

Description

1000

1. Meaning: Broadcast reception is started.

2. Occurrence condition:

1 A broadcast frame up to the data-length field was received from the master unit normally.

2 Once the control field has been received, RBF is ready for reception

Note

After the data-length field, 1000 is set in SLRC, and three-byte data consisting of a master address,

control bits, and data-length bits is set in RBF.

3. Microcomputer processing: Three-byte data consisting of a master address, control bits, and data-

length bits can be read from RBF.

1001

1. Meaning: The broadcast reception buffer is full.

2. Occurrence condition: This return code is issued when RBF becomes full during data reception as a

slave unit, preventing subsequent reception data from being set in RBF.

3. Microcomputer processing: If data consisting of one or more bytes is not read from RBF within the

time below, broadcast reception is aborted.

· Reception data read time:

Approx. 1570

s (mode 0)

Approx. 390

s (mode 1)

1010

1. Meaning: Broadcast reception was terminated normally.

2. Occurrence condition: This return code is issued when as much data as the amount specified in the

data-length field has been received normally in a communication frame. In this case, the SLRE flag of

the FLG register changes from 1 to 0.

3. Microcomputer processing: Reception data can be read from RBF, and the number of bytes of

broadcast reception data can be read from RDR2.

1011

1. Meaning: Broadcast reception was aborted.

2. Occurrence condition: This return code is issued when reception is terminated prior to the reception

of as much data as the amount specified in the data-length field in a communication frame. In this case,

the SLRE flag of the FLG register changes from 1 to 0.

3. Microcomputer processing: Reception data can be read from RBF, and the number of bytes of

broadcast reception data can be read from RDR2.

Note

See Note of Table 4-9.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Table 4-9 indicates the SLRC return code issued in broadcast reception when an optional function is set in the

CMR register with DERC = 1.

Table 4-9 SLRC Return Code in Broadcast Reception When the Optional Function Is Set (DERC = 1)

SLRC

Description

1100

1. Meaning: Broadcast reception error

2. Occurrence condition: This return code is issued if RBF is not ready for reception

Note

when the

control field is received. In this case, the master address in the communication frame is set as a

broadcast address in DAR2 and DAR1.

3. Microcomputer processing: A broadcast address can be read from DAR1 and DAR2. However, the

data of DAR1 and DAR2 is updated each time a broadcast reception error occurs. So, ensure that data

is read from DAR1 and DAR2 within the interval indicated below.

· Read time:

Approx. 5420

s (mode 0)

Approx. 1490

s (mode 1)

Note

RBF is ready for reception according to the optional function setting in CMR, as described below.

(i) When MFC = 0

The SLRE flag of the FLG register is 1 (slave reception and broadcast reception only); and

RBF is empty.

(ii) When MFC = 1

The SLRE flag of the FLG register is 1 (slave reception and broadcast reception only); and

RBF has at least 4 bytes of free space.

When RBF is ready for reception, bit 1 of slave status transmitted from the master unit with control bits 0000 or

0110 is set to 0.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

RBF

Address

: 1110B (EH)

Read/write

: Read

Reception buffer

When reset : Undefined

RBF is a 40-byte FIFO buffer used to hold a transmitter address, control bits, data-length bits, and reception data

for master reception, slave reception, or broadcast reception.

RBF can be read by the microcomputer when the REP flag of the STR register is 0 (indicating that RBF is not empty).

When an optional function is set in the CMR register with MFC = 1, multiple communication frames can be held

in RBF until RBF becomes full.

In master reception, slave reception, and broadcast reception, the format below is used to transfer data from RBF

to the microcomputer.

RBF

High-order 4 bits

Low-order 4 bits

Byte 2

Byte 1

Byte 3

Byte 4

Byte 5

Byte 40

Transmitter address (high-order 8 bits)

Transmitter address (low-order 4 bits)

Control bits

Data-length bits

First byte of reception data

Second byte of reception data

Last reception data

Transmitter address (high-order 8 bits)

Transmitter address (low-order 4 bits)

Control bits

Data-length bits

First byte of reception data

Second byte of reception data

Last reception data

Communication frame 1

Communication frame 2

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

[Byte 1, byte 2 (high-order 4 bits)]: Transmitter address

As indicated below, the transmitter address depends on whether the communication mode is master reception,

slave reception, or broadcast reception.

· Transmitter address

Case

Transmitter address

Master reception

Slave address

Slave reception

Master address

Broadcast reception

[Byte 2 (low-order 4 bits)] : Control bits

[Byte 3]

: Data-length bits

[Byte 4 and up]

: Reception data

The number of bytes of reception data is set in the RDR1 or RDR2 register, as described below.

RDR1: Number of bytes of reception data in master reception

RDR2: Number of bytes of reception data in slave reception or broadcast reception

The number of bytes of reception data indicates the number of bytes of data received normally within a

communication frame. This means that the number of bytes of reception data will match the length set in the data-

length field of a communication frame only when the data has been received normally.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

5. EXAMPLE TIMINGS FOR COMMUNICATION

This chapter provides examples of the timings at which the contents of internal registers change during

communication. The following seven examples are given:

(1) Master transmission timing example 1

Timing at which a return code is generated upon the start of master transmission and at the normal termination

of transmission

(2) Master transmission timing example 2

Timing at which a return code is generated upon the start of master transmission, transmission data empty, and

the suspension of transmission

(3) Slave data transmission timing example

Timing at which a return code is generated upon the start of slave data transmission and the normal termination

of transmission

(4) Master reception timing example

Timing at which a return code is generated upon the start of master reception and the normal termination of

reception

(5) Slave reception timing example 1

Timing at which a return code is generated upon the start of slave reception and the normal termination of

reception

(6) Slave reception timing example 2

Timing at which a return code is generated upon the start of slave reception, reception buffer full, and the normal

termination of reception

(7) Broadcast reception timing example

Timing at which a return code is generated upon the occurrence of an error during broadcast reception

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Name

Description

RAWF

Program crash detection flag (1: Detected, 0: Not detected)

TRRQ

Transmission processing request flag (1: Requested, 0: Not requested)

TRCF

Transmission status (TRC stored)

Number of bytes in transmission data set in TBF

RERQ

Note

Reception processing request flag (1: Requested, 0: Not requested)

RECF

Note

Reception status (REC stored)

SIZE

Note

Number of bytes in reception data which can be read from RBF (RDR1/RDR2 stored)

Note

Write pointer for RERQ, RECF, and SIZE

Note

Read pointer for RERQ, RECF, and SIZE

Number of bytes in reception data which has actually been read from RBF

MCRQ

Master communication processing request flag (1: Requested, 0: Not requested)

SDRQ

Slave data transmission processing request flag (1: Requested, 0: Not requested)

CORQ

Command processing request flag (1: Requested, 0: Not requested)

MTRQF

Master transmission request flag (1: Requested, 0: Not requested)

MRRQF

Master reception request flag (1: Requested, 0: Not requested)

STRQF

Slave data transmission request flag (1: Requested, 0: Not requested)

SLREF

Slave broadcast reception enable flag (1: Enabled, 0: Disabled)

Pointer

RERQ

RECF

SIZE

............

6.1 COMMUNICATION FLAGS

Table 6-1 lists the communication flags used in the main and interrupt routines, excluding those flags assigned

to the registers of the

PD72042A or

PD72042B.

Table 6-1 Communication Flags

Note

RERQ, RECF, and SIZE are stored in a buffer pair pointed to by PW and PR.

· Buffer configuration

Remark Buffers pointed to by the write pointer (PW)

: RERQ

, RECF

, and SIZE

Buffers pointed to by the read pointer (PR)

: RERQ

, RECF

, and SIZE

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Fig. 6-3 Flow of Interrupt Routine

Start

Disable interrupts from

Read FLG

RAW?

; Program crash?

Read RCR

; See Note 1.

Is return

code in MARC

enabled?

MARC?

011

××

010

; Classify MARC.

RERQ

SIZE

RDR1

RECF

MARC

Is return

code in SLRC

enabled?

RERQ

SIZE

RDR2

RECF

SLRC

SLRC?

010

100

011

, 101

××

TRCF

SLRC

TRRQ

Enable interrupts from

End

RETI

; Initialize RERQ.
; Initialize SIZE.

; Classify SLRC.

; See Note 2.

; Initialize RERQ.
; Initialize SIZE.

RAWF

TRCF

MARC

TRRQ

Increment PW
RERQ

SIZE

RERQ

SIZE

RDR1

RECF

MARC

RERQ

SIZE

RDR2

RECF

SLRC

REEN

Increment PW
RERQ

SIZE

PD72042A or

PD72042B

PD72042A or

PD72042B

Notes 1. The return code in MARC is enabled when any of conditions, 1 , 2 , or 3 , below, is satisfied:

1 MARC has been changed

Note 3

2 MTRQF = 1 and MARQ = 0

3 MRRQF = 1 and MARQ = 0

2. The return code in SLRC is enabled when any of conditions, 1 , 2 , or 3 , below, is satisfied:

1 SLRC has been changed

Note 3

2 STRQF = 1 and STRQ = 0

3 SLREF = 1 and SLRE = 0

3. When MARC is 0001 or 0101, the same value may be generated consecutively, such that MARC is set

to 1111 to enable the detection of a change in MARC the next time it is generated. When SLRC is 0001,

0101, or 1001, it is again set to 1111 for the same reason.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

6.4 PROCESSING ROUTINES

This section describes the processing routines called from the main routine.

6.4.1

PD72042A or

PD72042B Initial Setting Routine

This routine is executed when the

PD72042A or

PD72042B is first started or upon the detection of a program

crash (RAW = 1).

Fig. 6-4 shows the flow of the

PD72042A or

PD72042B initial setting routine.

Fig. 6-4

PD72042A or

PD72042B Initial Setting Routine

Start

Reset PD72042A
or PD72042B

Note

UAR1

Local station address (four low-order bits)

UAR2

Local station address (eight high-order bits)

End

CMR

100000 b1 b0

; Set local address and condition code.

; Set condition code.

; Set optional functions.

Condition code

Note

There are two methods of performing reset, as follows:

1 Set the RESET pin to low.

2 Set SRST in CTR to 1.

Type 1 reset causes the

PD72042A or

PD72042B to enter standby mode, thus requiring the subsequent

release of standby mode.

Caution To enable normal IEBus communication, always perform the above initial setting.

6.4.2 Communication Flag Initialization Routine

This routine initializes the communication flags listed in Table 6-1, as follows:

RAWF

TRRQ

RERQ

SIZE

MCRQ

SDRQ

CORQ

MTRQF

MRRQF

STRQF

SLREF

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

6.4.3 Command Processing Routine

This routine is executed when CORQ has been set by the application processing routine.

The command processing routine sets a command code, in the CMR register, to set the lock state, control

transmission/reception buffers, control communication, and set optional functions.

The commands for master communication and slave data transmission request are described in Sections 6.4.4

and 6.4.5.

Fig. 6-5 shows the flow of the command processing routine.

Fig. 6-5 Command Processing Routine

Start

Read FLG

CMR

Command code

End

;

CEX?

Waiting for termination
of previous command?

6.4.4 Master Communication Processing Routine

This routine is executed when MCRQ has been set by the application processing routine.

The master communication processing routine consists of the following three processing routines:

· Master transmission processing routine 1

This routine is used to transmit data, as the master unit, starting from the first data in TBF.

· Master transmission processing routine 2

This routine is used to start master transmission from the point at which the previous master transmission was

suspended.

· Master reception processing routine

This routine is used to receive data, as the master unit, from a slave unit.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

(1) Master transmission processing routine 1

Fig. 6-6 shows the flow of master transmission processing routine 1.

Fig. 6-6 Flow of Master Transmission Processing Routine 1

Start

SAR1

Slave address (four low-order bits)

SAR2

Slave address (eight high-order bits)

MCR

Broadcast bits, number of arbitrations,

and control bits (The MSB is 1.)

Read STR

TEP?

Read FLG

CEX?

CMR

00010000

Read FLG

CEX?

TBF

Number of bytes

in transmission data

I >

Read STR

TFL?

| + 1

TBF

Transmission data (I-th byte)

Read FLG

CEX?

End

CMR

00001000

MTRQF

;

Waiting for termination of previous command?

;

Set clear command for transmission buffer.

; Waiting for termination of processing of

transmission buffer clear command?

;

Initialize |.

;

Setting tranmission data in TBF completed?

;

; Waiting for termination of

processing of master communication
request command?

Number of bytes
in tranmission data

Set master communication
request command.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

7. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Conditions

Rated value

Unit

Supply voltage

, AV

| V

| < 0.5 V

0.5 to +7.0

Input voltage for logic section

0.5 to V

+ 0.3

Output voltage for logic section

0.5 to V

+ 0.3

Bus input voltage

0.5 to +6.0

Bus output voltage

0.5 to +6.0

Operating ambient temperature

40 to +85

Storage temperature

STG

65 to +150

Caution Absolute maximum ratings are rated values beyond which physical damage may be caused to

the unit; if any of the parameters in the table above exceeds its rated value, even momentarily,

the performance and/or reliability of the product may deteriorate. Therefore, never exceed the

product's rated values.

DC CHARACTERISTICS (T

= 40 to +85

C, V

= 5 V

10 %)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Input high voltage

0.8V

Input low voltage

0.2V

Output high voltage

= 400

0.7V

Output low voltage

= 2.5 mA

0.4

Input leakage current, high

LIH

= V

Input leakage current, low

LIL

= 0 V

Output leakage current, high

LOH

= V

Output leakage current, low

LOL

= 0 V

Supply current (normal

DD1

3.5

operation mode)

Supply current (standby mode)

DD2

CAPACITANCE CHARACTERISTICS (T

= 25

C, V

= 0 V)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Input capacitance

I/O capacitance

= 1 MHz

Excluding the BUS+ and BUS-
pins.
0 V for pins others than the
measured pins.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

AC CHARACTERISTICS (T

= 40 to +85

C, V

= 5 V

10 %)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

System clock

= 6 MHz

5.91

6.00

6.09

MHz

= 6.29 MHz

6.20

6.29

6.38

MHz

SCK cycle time

KCY

0.8

SCK high-level width

0.4

SCK low-level width

0.4

SI (SIO)

Note 1

setup time

SIK

Referred to SCK

100

SI (SIO)

Note 1

hold time

KSI

Referred to SCK

400

SO (SIO)

Note 2

output delay

KSO

Referred to SCK

300

CS, C/D setup time

Referred to SCK

CS, C/D hold time

Referred to SCK

400

IRQ output high-level width

RESET low-level width

SERIAL TRANSFER TIMING

KCY

KSI

SIK

KSO

CS, C/D

SCK

SI (SIO)

Note 1

SO (SIO)

Note 2

Input data

Output data

Notes 1. For 3-wire serial I/O: SI

For 2-wire serial I/O: SIO

2. For 3-wire serial I/O: SO

For 2-wire serial I/O: SIO

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

Oscillator circuit (External system clock)

Caution When using system clock oscillator, wire the portion enclosed in broken lines in the figure as

follows to avoid adverse influences on the wiring capacitance:

Keep the wiring length as short as possible.

Do not cross the wiring over the other signal lines.

Do not route the wiring in the vicinity of lines through which a high fluctuating current flows.

Always keep the ground point of the capacitor of the oscillator circuit at the same potential

as GND.

Do not connect the power source pattern through which a high current flows.

Do not extract signals from the oscillator.

IEBus DRIVER/RECEIVER CHARACTERISTICS (T

= 40 to +85

C, V

= 5 V

10 %)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Output high voltage

= 60

5 %, R = 180

5 %

2.73

6.22

Output low voltage

1.0

Common mode output voltage

OCOM

For high and low levels

1/2V

X +

X = 1/2V

0.25

Input high voltage

120

Input low voltage

20.0

Input hysteresis voltage

IHYS

Common mode input voltage, high

IHCOM

1.00

1.0

Common mode input voltage, low

ILCOM

Driver output resistance

Between BUS+ and BUS

100

Driver output capacitance

Receiver input capacitance

Between BUS+ and BUS, between BUS+

and GND, and between BUS and GND

GND

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

9. RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering

processes are used, or if the soldering is performed under different conditions, please make sure to consult with our

sales offices.

For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"

(C10535E).

Surface mount devices

PD72042AGT: 16-pin plastic SOP (375 mil)

PD72042BGT: 16-pin plastic SOP (375 mil)

Process

Conditions

Symbol

Infrared ray reflow

Peak temperature: 235

C or below (Package surface temperature),

IR35-00-2

Reflow time: 30 seconds or less (at 210

C or higher),

Maximum number of reflow processes: 2 times.

VPS

Peak temperature: 215

C or below (Package surface temperature),

VP15-00-2

Reflow time: 40 seconds or less (at 200

C or higher),

Maximum number of reflow processes: 2 times.

Wave soldering

Solder temperature: 260

C or below, Flow time: 10 seconds or less,

WS60-00-1

Maximum number of flow processes: 1 time,

Pre-heating temperature: 120

C or below (Package surface temperature).

Partial heating method

Pin temperature: 300

C or below,

Heat time: 3 seconds or less (Per each side of the device).

Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or

the device will be damaged by heat stress.

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

APPENDIX A MAIN DIFFERENCES BETWEEN

PD72042A,

PD72042B, AND

PD6708

Item

PD72042A

PD72042B

PD6708

Product

Oscillation frequency (f

)

6 MHz

12 MHz

Operating voltage (V

)

5 V

10 %

Operating ambient temperature (T

)

40 to +85

IEBus

Communication mode

Mode 0, 1

Mode 0, 1, 2

Driver/receiver

Built-in

Transmission buffer

33 bytes

4 bytes

Reception buffer

40 bytes

20 bytes

Interface with microcomputer

Note

Serial interface (3-wire/2-wire)

Serial interface (3-wire)

MSB first

LSB first

MSB first

Package

16-pin SOP (375 mil)

16-pin SOP (300 mil)

16-pin DIP (300 mil)

Note

The setting method for the commands, data, and related pins for the

PD72042A and

PD72042B differs

from that for the

PD6708.

APPENDIX B IEBus PROTOCOL ANALYZER

Naito Densei Co., Ltd. offers an IEBus protocol analyzer for monitoring communication on IEBus and evaluating

application systems. For details of its functions and to place an order, contact:

Naito Densei Machida Mfg. Co., Ltd.

3-9-25, Hisamoto, Takatsu-ku

Kawasaki, Kanagawa 213-0011, JAPAN

TEL 044 (822) 3813

FAX 044 (822) 3681

PD72042A, 72042B

DATA SHEET S13990EJ2V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

PD72042A, 72042B

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

IEBus and Inter Equipment are trademarks of NEC Corporation.

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