Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- 1. PIN FUNCTIONS
- 1.1 Cable Interface Pins
- 1.2 Link Interface Pins
- 1.3 Control Pins
- 1.4 IC
- 1.5 Power Supply Pins
- 1.6 Other Pins
- 2. PHY REGISTERS
- 2.1 Complete Structure for PHY Registers
- 2.2 Port Status Page (Page 000)
- 2.3 Vendor ID Page (Page 001)
- 2.4 Vendor Dependent Page (Page 111 : Port_select 0000)
- 2.5 Vendor Dependent Page (Page 111 : Port_select 0001)
- 3. INTERNAL FUNCTION
- 3.1 Link Interface
- 3.1.1 Connection Method
- 3.1.2 LPS (Link Power Status)
- 3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins
- 3.1.4 SCLK
- 3.1.5 LKON
- 3.1.6 DIRECT
- 3.1.7 Isolation Barrier
- 3.2 Cable Interface
- 3.2.1 Connections
- 3.2.2 Cable Interface Circuit
- 3.2.3 Unused Ports
- 3.2.4 CPS
- 3.3 Suspend/Resume
- 3.3.1 Suspend/Resume On Mode (SUS/RES = H)
- 3.3.2 Suspend/Resume Off Mode (SUS/RES = L)
- 3.4 PLL and Crystal Oscillation Circuit
- 3.4.1 Crystal Oscillation Circuit
- 3.4.2 PLL
- 3.5 CMC
- 3.6 PC0-PC2
- 3.7 RESETB
- 3.8 RI1
- 4. PHY/LINK INTERFACE
- 4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface
- 4.2 Link-on Indication
- 4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)
- 4.3.1 CTL0, CTL1
- 4.3.2 LREQ
- 4.3.3 SCLK Timing
- 4.4 Acceleration Control
- 4.5 Transmit Status
- 4.6 Transmit
- 4.7 Cancel
- 4.8 Receive
- 5. CABLE PHY PACKET
- 5.1 Self_ID Packet
- 5.2 Link-on Packet
- 5.3 PHY Configuration Packet
- 5.4 Extended PHY Packet
- 5.4.1 Ping Packet
- 5.4.2 Remote Access Packet
- 5.4.3 Remote Reply Packet
- 5.4.4 Remote Command Packet
- 5.4.5 Remote Confirmation Packet
- 5.4.6 Resume Packet
- 6. ELECTRICAL SPECIFICATIONS
- 7. APPLICATION CIRCUIT EXAMPLE
- 8. PACKAGE DRAWING
- 9. RECOMMENDED SOLDERING CONDITIONS
2003
The mark shows major revised points.
PD72852A
MOS INTEGRATED CIRCUIT
DATA SHEET
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
Document No.
S16725EJ2V0DS00 (2nd edition)
Date Published
March 2004 NS CP (K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
The
PD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
FEATURES
The two-port physical layer LSI complies with IEEE1394a-2000
Fully interoperable with IEEE1394 std 1394 Link (FireWire
TM
, i.LINK
TM
)
Meets
Intel
TM
Mobile Power Guideline 2000
Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed
concatenation, arbitration acceleration, fly-by concatenation
Suspend Debounce timer for ESD
"BIAS Detected" signal output
Double speed signal filter for BIAS Ringing
Small package: 64-pin plastic LQFP
Super low power : 68 mA (Operating mode)
:
115
A (Suspend mode)
Data rate: 400/200/100 Mbps
Supports PHY pinging and remote PHY access packets
3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)
24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
64-bit flexible register incorporated in PHY register
Electrically isolated Link interface
Supports LPS/Link-on as part of PHY/Link interface
External filter capacitors for PLL not required
Extended Resume signaling for compatibility with legacy DV devices
System power management by signaling of node power class information
Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number
Package
PD72852AGB-8EU
64-pin plastic LQFP (10
10)
Data Sheet S16725EJ2V0DS
2
PD72852A
BLOCK DIAGRAM
Link
Interface
I/O
Voltage
and
Current
Generator
Cable
Power
Status
Crystal
Oscillator
PLL
System
and
Transmit
Clock
Generator
Receive Data
Decoder and
Retimer
Transmit Data
Encoder
Arbitration
and Control
State Machine
Logic
LREQ
LPS
DIRECT
SCLK
LKON
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
CMC
PC0
PC1
PC2
SUS/RES
TpA0p
TpA0n
TpB0p
TpB0n
Cable
Port0
Cable
Port1
TpBias0
TpBias1
RI1
XI
XO
RESETB
CPS
TpA1p
TpA1n
TpB1p
TpB1n
BDB
Data Sheet S16725EJ2V0DS
3
PD72852A
PIN CONFIGURATION (Top View)
PD72852AGB-8EU
64-pin plastic LQFP (10
10)
DGND
SCLK
IC(DL)
DV
DD
CTL0
CTL1
DGND
D0
D1
DV
DD
D2
D3
DGND
D4
D5
DGND
TpBias1
AV
DD
TpA1p
TpA1n
TpB1p
TpB1n
AGND
TpBias0
AV
DD
TpA0p
TpA0n
TpB0p
TpB0n
AGND
RI1
AGND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D6
D7
SU
S/R
E
S
DV
DD
DGND
XO
XI
AG
N
D
AV
DD
PC
0
PC
1
PC
2
IC(AL)
CM
C
AV
DD
CP
S
DGND
LRE
Q
FN
Se
l
SPD
/
BD
B
DV
DD
L
PS
LK
ON
DGND
DV
DD
R
ESE
T
B
AV
DD
A
G
ND
A
G
ND
IC
(
A
L
)
DI
RE
CT
A
G
ND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
Data Sheet S16725EJ2V0DS
4
PD72852A
PIN NAME
AGND
: Analog GND
AV
DD
: Analog Power
CMC
: Configuration Manager Capable
CPS
: Cable Power Status
CTL0
: Link Interface Control (bit 0)
CTL1
: Link Interface Control (bit 1)
D0-D7
: Data Input/Output
DGND
: Digital GND
DIRECT
: PHY/Link Isolation Barrier Control Input
DV
DD
: Digital V
DD
FNSel
: Function Select
IC(AL)
: Internally Connected (Low Clamped)
IC(DL)
: Internally Connected (Low Clamped)
LKON
: Link-on Signal Output
LPS
: Link Power Status Input
LREQ
: Link Request Input
PC0-PC2
: Power Class Set Input
RESETB
: Power-on Reset Input
RI1
: Reference Power Set, Connect Resistor 1
SCLK
: Link Control Output Clock
SPD/BDB
: Speed Select input / BIAS Detected output
SUS/RES
: Suspend/Resume Function Select
TpA0n
: Port 0 Twisted Pair Cable A Negative Phase I/O
TpA0p
: Port 0 Twisted Pair Cable A Positive Phase I/O
TpA1n
: Port 1 Twisted Pair Cable A Negative Phase I/O
TpA1p
: Port 1 Twisted Pair Cable A Positive Phase I/O
TpB0n
: Port 0 Twisted Pair Cable B Negative Phase I/O
TpB0p
: Port 0 Twisted Pair Cable B Positive Phase I/O
TpB1n
: Port 1 Twisted Pair Cable B Negative Phase I/O
TpB1p
: Port 1 Twisted Pair Cable B Positive Phase I/O
TpBias0
: Port 0 Twisted Pair Output
TpBias1
: Port 1 Twisted Pair Output
XI
: Crystal Oscillator Connection XI
XO
: Crystal Oscillator Connection XO
Data Sheet S16725EJ2V0DS
5
PD72852A
CONTENTS
1. PIN FUNCTIONS..................................................................................................................................... 7
1.1 Cable Interface Pins ........................................................................................................................ 7
1.2 Link Interface Pins .......................................................................................................................... 7
1.3 Control Pins ..................................................................................................................................... 8
1.4 IC ....................................................................................................................................................... 8
1.5 Power Supply Pins .......................................................................................................................... 8
1.6 Other Pins ........................................................................................................................................ 9
2. PHY REGISTERS .................................................................................................................................. 10
2.1 Complete Structure for PHY Registers ....................................................................................... 10
2.2 Port Status Page (Page 000) ........................................................................................................ 13
2.3 Vendor ID Page (Page 001)........................................................................................................... 14
2.4 Vendor Dependent Page (Page 111 : Port_select 0000)............................................................ 14
2.5 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................ 15
3. INTERNAL FUNCTION.......................................................................................................................... 16
3.1 Link Interface ................................................................................................................................. 16
3.1.1 Connection Method ............................................................................................................................... 16
3.1.2 LPS (Link Power Status) ....................................................................................................................... 16
3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins..................................................................................................... 16
3.1.4 SCLK..................................................................................................................................................... 16
3.1.5 LKON .................................................................................................................................................... 17
3.1.6 DIRECT................................................................................................................................................. 17
3.1.7 Isolation Barrier ..................................................................................................................................... 17
3.2 Cable Interface............................................................................................................................... 19
3.2.1 Connections .......................................................................................................................................... 19
3.2.2 Cable Interface Circuit........................................................................................................................... 20
3.2.3 Unused Ports ........................................................................................................................................ 20
3.2.4 CPS....................................................................................................................................................... 20
3.3 Suspend/Resume .......................................................................................................................... 20
3.3.1 Suspend/Resume On Mode (SUS/RES = "H")...................................................................................... 20
3.3.2 Suspend/Resume Off Mode (SUS/RES = "L") ...................................................................................... 20
3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 21
3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 21
3.4.2 PLL........................................................................................................................................................ 21
3.5 CMC ................................................................................................................................................ 21
3.6 PC0-PC2 ......................................................................................................................................... 21
3.7 RESETB.......................................................................................................................................... 21
3.8 RI1 ................................................................................................................................................... 21
4. PHY/LINK INTERFACE ......................................................................................................................... 22
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................ 22
4.2 Link-on Indication ......................................................................................................................... 23
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ...................................................... 24
4.3.1 CTL0, CTL1 .......................................................................................................................................... 24
4.3.2 LREQ .................................................................................................................................................... 24
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