Document Outline

COVER
FEATURES
ORDERING INFORMATION
Firewarden(TM) ROADMAP
BLOCK DIAGRAMS
PIN CONFIGURATION (TOP VIEW)
PIN NAME
1. PIN FUNCTIONS
- 1.1 PCI/Cardbus Interface Signals: (52 pins)
- 1.2 PHY Signals: (20 pins)
- 1.3 PHY Control Signals: (4 pins)
- 1.4 PCI/Cardbus Select Signal: (1 pin)
- 1.5 Serial ROM Interface Signals: (3 pins)
- 1.6 D3cold Wake Up Function Signals: (2 pins)
- 1.7 IC: (7 pins)
- 1.8 VDD
- 1.9 GND
2. PHY REGISTERS
- 2.1 Complete Structure for PHY Registers
- 2.2 Port Status Page (Page 000)
- 2.3 Vendor ID Page (Page 001)
- 2.4 Vendor Dependent Page (Page 111 : Port_select 0001)
3. CONFIGURATION REGISTERS
- 3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)
  - 3.1.1 Offset_00 Vendor ID Register
  - 3.1.2 Offset_02 Device ID Register
  - 3.1.3 Offset_04 Command Register
  - 3.1.4 Offset_06 Status Register
  - 3.1.5 Offset_08 Revision ID Register
  - 3.1.6 Offset_09 Class Code Register
  - 3.1.7 Offset_0C Cache Line Size Register
  - 3.1.8 Offset_0D Latency Timer Register
  - 3.1.9 Offset_0E Header Type Register
  - 3.1.10 Offset_0F BIST Register
  - 3.1.11 Offset_10 Base Address 0 Register
  - 3.1.12 Offset_2C Subsystem Vendor ID Register
  - 3.1.13 Offset_2E Subsystem ID Register
  - 3.1.14 Offset_34 Cap_Ptr Register
  - 3.1.15 Offset_3C Interrupt Line Register
  - 3.1.16 Offset_3D Interrupt Pin Register
  - 3.1.17 Offset_3E Min_Gnt Register
  - 3.1.18 Offset_3F Max_Lat Register
  - 3.1.19 Offset_40 PCI_OHCI_Control Register
  - 3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register
  - 3.1.21 Offset_62 Power Management Capabilities Register
  - 3.1.22 Offset_64 Power Management Control/Status Register
- 3.2 CardBus Mode Configuration Register (CARD_ON = High)
  - 3.2.1 Offset_14/18 Base Address 1/2 Register (Cardbus Status Registers)
  - 3.2.2 Offset_28 Cardbus CIS Pointer
  - 3.2.3 Offset_80 CIS Area
4. PHY FUNCTION
- 4.1 Cable Interface
  - 4.1.1 Connections
  - 4.1.2 Cable Interface Circuit
  - 4.1.3 CPS
  - 4.1.4 Unused Ports
- 4.2 PLL and Crystal Oscillation Circuit
  - 4.2.1 Crystal Oscillation Circuit
  - 4.2.2 PLL
- 4.3 PC0 to PC2
- 4.4 P_RESET#
- 4.5 RI0, RI1
5. ELECTRICAL SPECIFICATIONS
6. PACKAGE DRAWING
7. RECOMMENDED SOLDERING CONDITIONS

2001

IEEE1394 OHCI 1.1 COMPLIANT 3PORT PHY-LINK 1-CHIP HOST CONTROLLER

PRELIMINARY DATA SHEET

MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD72874

Document No. S15306EJ2V0DS00 (2nd edition)
Date Published April 2002 NS CP (K)
Printed in Japan

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

The

µPD72874 is the LSI that integrated OHCI-Link and PHY function into a single chip. The µPD72874 complies

with the 1394 OHCI Specification 1.1 and the IEEE Std 1394a-2000 specifications, and works up to 400 Mbps.

It makes design so compact for PC and PC card application.

FEATURES

Compliant with Link Layer Services as defined in 1394 Open Host Controller Interface specification release 1.1

Compliant with Physical Layer Services as defined in IEEE Std 1394a-2000

Provides three cable ports at 100/200/400 Mbps

Super Low power consumption for Physical Layer

Compliant with protocol enhancement as defined in IEEE Std1394a-2000

Modular 32-bit host interface compliant to PCI Specification release 2.2

Supports PCI-Bus Power Management Interface Specification release 1.1

Modular 32-bit host interface compliant to Card Bus Specification

Cycle Master and Isochronous Resource Manager capable

Built-in FIFOs for isochronous transmit (2048 bytes), asynchronous transmit (2048 bytes), and receive (3072

bytes)

Supports D0, D1, D2, D3hot

Supports wake up function from D3cold

32-bit CRC generation and checking for receive/transmit packets

4 isochronous transmit DMAs and 4 isochronous receive DMAs supported

32-bit DMA channels for physical memory read/write

Clock generation by 24.576 MHz X'tal

2-wire Serial EEPROM

interface supported

Separate power supply Link and PHY

Programmable latency timer from serial EEPROM in Cardbus mode (CARD_ON = 1)

ORDERING INFORMATION

Part number

Package

µPD72874GC-YEB

120-pin plastic TQFP (Fine pitch) (14 x 14)

The mark shows major revised points.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

BLOCK DIAGRAMS

Cor

a
t
e
M

i
n
e

gic

o
nt

ll
er

AT FI

I
F

Mana

gem

o
nt

ll
er

Reg

i
s
t
er

r
f
a
c
e

DMA

o
nt

ll
er

a
n

Con

f
i
gur

i
o
n

Reg

i
s
t
er

0
t

o
AD

3
1

BE0 t

o

C

BE3

GNT

I
RDY

RDY

EVS

STOP IN

PAR

I
D

SEL

CLK

PER

SER

L
K

MRS

D3CS

r
f
a
c
e

ROM

r
f
a
c
e

GROM_EN

GROM_SCL

GROM_SDA

RD_

r
bi

t
r
at

d Co

rol

a
t
e
M

i
n
e

gic

r
f
a
c
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Rec

e
i
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e Dat

Dec

oder

and

Ret

i
m

e
r

r
ans

i
t
Da

t
a

n
c
oder

o
l
t
age

Cur

r
e

n
t

ene

t
o
r

y
s
t
a
l

sci

l
l
a
t
o
r

s
t
e
m

r
ans

i
t

ene

t
o
r

Cab

l
e

a
t
u
s

CPS

PC0

PC1

PC2

0
p

0
n

0
p

0
n

1
p

1
n

1
p

1
n

2
p

2
n

2
p

2
n

Cab

l
e

Cab

l
e

Cab

l
e

i
a

s
0

i
a

s
1

i
a

s
2

R0 R1

P_RESET

L_V

PCI_V

P_DV

P_AV

GND

LINK BLOCK

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

PIN CONFIGURATION (TOP VIEW)

· 120-pin plastic TQFP (Fine pitch) (14 x 14)

µ
µ
µ
µPD72874GC-YEB

L_V

CLKRUN

PME

INTA

PRST

PCLK

GNT

REQ

GND

AD31
AD30

AD29

AD27
AD26
AD25

AD28

AD24

L_V

GND

CBE3

IDSEL

AD23
AD22

AD21
AD20

GND

AD19
AD18

PCI_V

L_V

GND
XO
XI
P_AV

IC(N)
GND
GND
P_DV

IC(L)

P_RESET

L_V

IC(L)
IC(H)
RSMRST
P_DV

PC2
PC1
PC0
GND

IC(L)
P_DV

90
89
88

86
85
84
83

82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64

AD4

GND

STO

1
5

1
4

1
3

1
2

1
1

1
0

L_V

BE0

1
7

1
6

L_V

RDY

GND

PER

SER

PAR

L_V

GND

120

119

118

116

115

114

113

117

112

111

110

109

108

107

106

105

104

103

102

101

100

TpA2p

TpBias

RD_ON

(
L
)

D3CS

TpA2n

TpB2n

GND

TpA1p

TpA1n

TpB1p

TpB1n

TpA0p

TpA0n

TpB0p

TpB0n

TpBias

GND

TpB2p

1
2
3
4
5
6
7
8
9
10
11
12
13

15
16
17
18

19
20
21
22
23
24
25
26
27
28
29
30

GROM

AD0
AD1
AD2
AD3

GND

AD5

P_AV

IC(L)

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

PIN NAME

AD0 to AD31 : PCI Multiplexed Address and Data

CARD_ON

: PCI/Card Select

CBE0 to

CBE3

: Command/Byte Enables

CLKRUN

: PCICLK Running

CPS

: Cable Power Status Input

D3CSUP

: D3cold Support

DEVSEL

: Device Select

FRAME

: Cycle Frame

GND

: GND

GNT

: Bus_master Grant

GROM_EN : Serial EEPROM Enable

GROM_SCL : Serial EEPROM Clock Output

GROM_SDA : Serial EEPROM Data Input / Output

IC(H)

: Internally Connected (High Clamped)

IC(L)

: Internally Connected (Low Clamped)

IC(N)

: Internally Connected (Open)

IDSEL

: ID Select

INTA

: Interrupt

IRDY

: Initiator Ready

L_V

: V

for Link Digital Core and Link I/Os

PAR

: Parity

PC0 to PC2

: Power Class Input

PCI_V

: V

for PCI I/Os

PCLK

: PCI Clock

PERR

: Parity Error

PME

: PME Output

PRST

: Reset

P_AV

: PHY Analog V

P_DV

: PHY Digital V

P_RESET

: PHY Power on Reset Input

REQ

: Bus_master Request

RI0

: Resistor0 for Reference Current Setting

RI1

: Resistor1 for Reference Current Setting

RSMRST

: Resume Reset

SERR

: System Error

STOP

: PCI Stop

TpA0n

: Port-1 Twisted Pair A Negative Input/Output

TpA0p

: Port-1 Twisted Pair A Positive Input/Output

TpA1n

: Port-2 Twisted Pair A Negative Input/Output

TpA1p

: Port-2 Twisted Pair A Positive Input/Output

TpA2n

: Port-3 Twisted Pair A Negative Input/Output

TpA2p

: Port-3 Twisted Pair A Positive Input/Output

TpB0n

: Port-1 Twisted Pair B Negative Input/Output

TpB0p

: Port-1 Twisted Pair B Positive Input/Output

TpB1n

: Port-2 Twisted Pair B Negative Input/Output

TpB1p

: Port-2 Twisted Pair B Positive Input/Output

TpB2n

: Port-3 Twisted Pair B Negative Input/Output

TpB2p

: Port-3 Twisted Pair B Positive Input/Output

TpBias0

: Port-1 Twisted Pair Bias Voltage Output

TpBias1

: Port-2 Twisted Pair Bias Voltage Output

TpBias2

: Port-3 Twisted Pair Bias Voltage Output

TRDY

: Target Ready

: X'tal XI

: X'tal XO

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

CONTENTS

1. PIN FUNCTIONS..................................................................................................................................... 8

1.1 PCI/Cardbus Interface Signals: (52 pins) ...................................................................................... 8

1.2 PHY Signals: (20 pins) .................................................................................................................. 10

1.3 PHY Control Signals: (4 pins)....................................................................................................... 10

1.4 PCI/Cardbus Select Signal: (1 pin)............................................................................................... 10

1.5 Serial ROM Interface Signals: (3 pins)......................................................................................... 11

1.6 D3cold Wake Up Function Signals: (2 pins) ............................................................................... 11

1.7 IC: (7 pins) ...................................................................................................................................... 11

1.8 V

................................................................................................................................................... 12

1.9 GND................................................................................................................................................. 12

2. PHY REGISTERS................................................................................................................................... 13

2.1 Complete Structure for PHY Registers........................................................................................ 13

2.2 Port Status Page (Page 000)......................................................................................................... 16

2.3 Vendor ID Page (Page 001) ........................................................................................................... 17

2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 17

3. CONFIGURATION REGISTERS .......................................................................................................... 18

3.1 PCI Bus Mode Configuration Register (CARD_ON = Low)........................................................ 18

3.1.1 Offset_00 Vendor ID Register ........................................................................................................... 19

3.1.2 Offset_02 Device ID Register............................................................................................................ 19

3.1.3 Offset_04 Command Register ........................................................................................................... 19

3.1.4 Offset_06 Status Register ................................................................................................................. 20

3.1.5 Offset_08 Revision ID Register ......................................................................................................... 21

3.1.6 Offset_09 Class Code Register......................................................................................................... 21

3.1.7 Offset_0C Cache Line Size Register................................................................................................. 21

3.1.8 Offset_0D Latency Timer Register .................................................................................................... 21

3.1.9 Offset_0E Header Type Register ...................................................................................................... 21

3.1.10 Offset_0F BIST Register .................................................................................................................. 21

3.1.11 Offset_10 Base Address 0 Register ................................................................................................ 22

3.1.12 Offset_2C Subsystem Vendor ID Register ...................................................................................... 22

3.1.13 Offset_2E Subsystem ID Register................................................................................................... 22

3.1.14 Offset_34 Cap_Ptr Register ............................................................................................................ 22

3.1.15 Offset_3C Interrupt Line Register.................................................................................................... 22

3.1.16 Offset_3D Interrupt Pin Register ..................................................................................................... 23

3.1.17 Offset_3E Min_Gnt Register ........................................................................................................... 23

3.1.18 Offset_3F Max_Lat Register ........................................................................................................... 23

3.1.19 Offset_40 PCI_OHCI_Control Register ........................................................................................... 23

3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register .................................................................................. 23

3.1.21 Offset_62 Power Management Capabilities Register...................................................................... 24

3.1.22 Offset_64 Power Management Control/Status Register.................................................................. 25

3.2 CardBus Mode Configuration Register (CARD_ON = High)...................................................... 26

3.2.1 Offset_14/18 Base Address 1/2 Register (Cardbus Status Registers).............................................. 27

3.2.2 Offset_28 Cardbus CIS Pointer ......................................................................................................... 28

3.2.3 Offset_80 CIS Area ........................................................................................................................... 28

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

4. PHY FUNCTION.................................................................................................................................... 29

4.1 Cable Interface............................................................................................................................... 29

4.1.1 Connections ......................................................................................................................................... 29

4.1.2 Cable Interface Circuit.......................................................................................................................... 30

4.1.3 CPS ...................................................................................................................................................... 30

4.1.4 Unused Ports........................................................................................................................................ 30

4.2 PLL and Crystal Oscillation Circuit ............................................................................................. 30

4.2.1 Crystal Oscillation Circuit ..................................................................................................................... 30

4.2.2 PLL ....................................................................................................................................................... 30

4.3 PC0 to PC2 ..................................................................................................................................... 30

4.4 P_RESET ........................................................................................................................................ 30

4.5 RI0, RI1 ........................................................................................................................................... 30

5. ELECTRICAL SPECIFICATIONS......................................................................................................... 31

6. PACKAGE DRAWING .......................................................................................................................... 34

7. RECOMMENDED SOLDERING CONDITIONS................................................................................... 35

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

1. PIN FUNCTIONS

1.1 PCI/Cardbus Interface Signals: (52 pins)

(1/2)

Name

I/O

Pin No.

Volts(V)

Function

Block *

PAR

I/O

PCI/Cardbus

5/3.3

Parity is even parity across AD0 to AD31 and CBE0

to CBE3. It is an input when AD0 to AD31 is an

input; it is an output when AD0 to AD31 is an output.

Link

AD0 to AD31

I/O

9, 10, 12, 13,

15 to18, 23, 24,

26 to 29, 32, 33,

47 to 50, 52, 53,

55, 56, 58, 59, 62,

63, 65 to 68

PCI/Cardbus

5/3.3

PCI Multiplexed Address and Data

Link

CBE0 to

CBE3

I/O

21, 34, 45, 57

5/3.3

Command/Byte Enables are multiplexed bus

commands & byte enables.

Link

FRAME

I/O

PCI/Cardbus

5/3.3

Frame is asserted by the initiator to indicate the

cycle beginning and is kept asserted during the

burst cycle. If Cardbus mode (CARD_ON = 1), this

pin should be pulled up to V

Link

TRDY

I/O

PCI/Cardbus

5/3.3

Target Ready indicates that the current data phase

of the transaction is ready to be completed.

Link

IRDY

I/O

PCI/Cardbus

5/3.3

Initiator Ready indicates that the current bus

master is ready to complete the current data phase.

During a write, its assertion indicates that the

initiator is driving valid data onto the data bus.

During a read, its assertion indicates that the

initiator is ready to accept data from the currently-

addressed target.

Link

REQ

PCI/Cardbus

5/3.3

Bus_master Request indicates to the bus arbiter

that this device wants to become a bus master.

Link

GNT

5/3.3

Bus_master Grant indicates to this device that

access to the bus has been granted.

Link

IDSEL

5/3.3

Initialization Device Select is used as chip select

for configuration read/write transaction during the

phase of device initialization. If Cardbus mode

(CARD_ON = 1), this pin should be pulled up to V

Link

DEVSEL

I/O

PCI/Cardbus

5/3.3

Device Select when actively driven, indicates that

the driving device has decoded its address as the

target of the current access.

Link

STOP

I/O

PCI/Cardbus

5/3.3

PCI Stop when actively driven, indicates that the

target is requesting the current bus master to stop

the transaction.

Link

PME

PCI/Cardbus

5/3.3

PME Output for power management event.

Link

Remark *: If the Link pin is pulled up, it should be connected to L_V

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
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PD72874

1.2 PHY Signals: (20 pins)

Name

I/O

Pin No.

Volts(V)

Function

Block *

TpA0p

I/O

101

Port-1 Twisted Pair A Positive Input/Output

Note 1

PHY Analog

TpA0n

I/O

100

Port-1 Twisted Pair A Negative Input/Output

Note 1

PHY Analog

TpB0p

I/O

Port-1 Twisted Pair B Positive Input/Output

Note 1

PHY Analog

TpB0n

I/O

Port-1 Twisted Pair B Negative Input/Output

Note 1

PHY Analog

TpA1p

I/O

105

Port-2 Twisted Pair A Positive Input/Output

Note 1

PHY Analog

TpA1n

I/O

104

Port-2 Twisted Pair A Negative Input/Output

Note 1

PHY Analog

TpB1p

I/O

103

Port-2 Twisted Pair B Positive Input/Output

Note 1

PHY Analog

TpB1n

I/O

102

Port-2 Twisted Pair B Negative Input/Output

Note 1

PHY Analog

TpA2p

I/O

110

Port-3 Twisted Pair A Positive Input/Output

Note 1

PHY Analog

TpA2n

I/O

109

Port-3 Twisted Pair A Negative Input/Output

Note 1

PHY Analog

TpB2p

I/O

108

Port-3 Twisted Pair B Positive Input/Output

Note 1

PHY Analog

TpB2n

I/O

107

Port-3 Twisted Pair B Negative Input/Output

Note 1

PHY Analog

CPS

Cable Power Status Input

Note2

PHY Digital

TpBias0

Port-1 Twisted Pair Bias Voltage Output

Note 1

PHY Analog

TpBias1

Port-2 Twisted Pair Bias Voltage Output

Note 1

PHY Analog

TpBias2

111

Port-3 Twisted Pair Bias Voltage Output

Note 1

PHY Analog

RI0

Resistor0 for Reference Current Setting

Note 3

PHY Analog

RI1

Resistor1 for Reference Current Setting

Note 3

PHY Analog

X'tal XI

PHY Analog

X'tal XO

PHY Analog

Notes 1. If unused port, please refer to 4.1.4 Unused Ports.

2. Please refer to 4.1.3 CPS.

3. Please refer to 4.5 RI0, RI1.

Remark *: If the PHY Digital pin is pulled up, it should be connected to P_DV

If the PHY Analog pin is pulled up, it should be connected to P_AV

1.3 PHY Control Signals: (4 pins)

Name

I/O

Pin No.

Volts(V)

Function

Block *

PC0 to PC2

70 to 72

3.3

Power Class Input

Note 1

PHY Digital

P_RESET

PHY Power on Reset Input

Note 2

PHY Digital

Notes 1. Please refer to 4.3 PC0 to PC2.

2. Please refer to 4.4 P_RESET.

Remark *: If the PHY Digital pin is pulled up, it should be connected to P_DV

1.4 PCI/Cardbus Select Signal: (1 pin)

Name

I/O

Pin No.

Volts(V)

Function

Block *

CARD_ON

119

3.3

PCI/CardBus Select

1:Cardbus mode

0:PCI bus mode

Link

Remark *: If the Link pin is pulled up, it should be connected to L_V

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

1.5 Serial ROM Interface Signals: (3 pins)

Name

I/O

Pin No.

Volts(V)

Function

Block *

GROM_SDA

I/O

116

6 mA

3.3

Serial EEPROM Data Input / Output

Link

GROM_SCL

117

6 mA

3.3

Serial EEPROM Clock Output

Link

GROM_EN

118

3.3

Serial EEPROM Enable

1: GUID Load enable

0: GUID Load disable

Link

Remark *: If the Link pin is pulled up, it should be connected to L_V

1.6 D3cold Wake Up Function Signals: (2 pins)

Name

I/O

Pin No.

Volts(V)

Function

Block *

D3CSUP

114

5/3.3

D3cold Support

1: D3cold wake up enable

0: D3cold wake up disable

Link

RSMRST

5/3.3

Resume Reset

D3cold support (114 pin) = `1'

As this mode supports D3cold wake up,

RSMRST must connect system RSMRST

signal.

D3cold support (114 pin) = `0'

As this mode is the

µPD72872 compatible,

RSMRST clamp to `1'.

Link

Remark *: If the Link pin is pulled up, it should be connected to L_V

1.7 IC: (7 pins)

Name

I/O

Pin No.

Volts(V)

Function

Block *

IC(H)

Internally Connected (High clamped)

Link

IC(L)

76 to 78, 80, 115

Internally Connected (Low clamped)

IC(N)

Internally Connected (Open)

Remark *: If the Link pin is pulled up, it should be connected to L_V

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

2. PHY REGISTERS

2.1 Complete Structure for PHY Registers

Figure 2-1. Complete Structure of PHY Registers

0000

Physical_ID

0001

RHB

IBR

Gap_count

0010

Extended (7)

Reserved

Total_ports

0011

Max_speed

Reserved

Delay

0100

Link_active

Contender

Jitter

Pwr_class

0101

Watchdog

ISBR

Loop

Pwr_fail

Timeout

Port_event

Enab_accel

Enab_multi

0110

Reserved

0111

Page_select

Reserved

Port_select

1000

Register0 (page_select)

1001

Register1 (page_select)

1010

Register2 (page_select)

1011

Register3 (page_select)

1100

Register4 (page_select)

1101

Register5 (page_select)

1110

Register6 (page_select)

1111

Register7 (page_select)

Table 2-1. Bit Field Description (1/3)

Field

Size

R/W

Reset value

Description

Physical_ID

000000

Physical_ID value selected from Self_ID period.

If this bit is 1, the node is root.

1: Root

0: Not root

Cable power status.

1: Cable power on

0: Cable power off

RHB

R/W

Root Hold -off bit. If 1, becomes root at the bus reset.

IBR

R/W

Initiate bus reset.

Setting to 1 begins a long bus reset.

Long bus reset signal duration: 166

µsec.

Returns to 0 at the beginning of bus reset.

Gap_count

R/W

111111

Gap count value.

It is updated by the changes of transmitting and receiving the PHY

configuration packet Tx/Rx.

The value is maintained after first bus reset.

After the second bus reset it returns to reset value.

Extended

111

Shows the extended register map.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

Table 2-1. Bit Field Description (2/3)

Field

Size

R/W

Reset value

Description

Total_ports

0011

Supported port number.

0011: 3 ports

Max_speed

010

Indicate the maximum speed that this node supports.

010: 98.304, 196.608 and 393.216 Mbps

Delay

0000

Indicate worst case repeating delay time. 144 + (Delay x 20) = 144 nsec

Link_active

R/W

Link active.

1: Enable

0: Disable

The logical AND status of this bit and LPS.

State will be referred to "L bit" of Self-ID Packet#0.

The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is

an internal signal in the

µPD72874.

Contender

R/W

Contender.

"1" indicate this node support bus manager function. This bit will be referred

to "C bit" of Self-ID Packet#0.

Jitter

010

The difference of repeating time (Max.-Min.). (2+1) x 20=60 nsec

Pwr_class

R/W

See

Description

Power class.

Please refer to IEEE1394a-2000 [4.3.4.1].

This bit will be referred to Pwr field of Self-ID Packet#0.

Watchdog

R/W

Watchdog Enable.

This bit serves two purposes.

When set to 1, if any one port does resume, the Port_event bit becomes 1.

To determine whether or not an interrupt condition shall be indicated to the

link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop,

Pwr_fail, Timeout is not output.

ISBR

R/W

Initiate short (arbitrated) bus reset.

Setting to 1 acquires the bus and begins short bus reset.

Short bus reset signal output : 1.3

µsec

Returns to 0 at the beginning of the bus reset.

Loop

R/W

Loop detection output.

1: Detection

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

Pwr_fail

R/W

Power cable disconnect detect.

It becomes 1 when there is a change from 1 to 0 in the CPS bit.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

Table 2-1. Bit Field Description (3/3)

Field

Size

R/W

Reset value

Description

Timeout

R/W

Arbitration state machine time-out.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

Port_event

R/W

Set to 1 when the Int_enable bit in the register map of each port is 1 and

there is a change in the ports connected, Bias, Disabled and Fault bits.

Set to 1 when the Watchdog bit is 1 and any one port does resume.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

Enab_accel

R/W

Enables arbitration acceleration.

Ack-acceleration and Fly-by arbitration are enabled.

1: Enabled

0: Disabled

If this bit changes while the bus request is pending, the operation is not

guaranteed.

Enab_multi

R/W

Enable multi-speed packet concatenation.

Setting this bit to 1 follows multi-speed transmission.

When this bit is set to 0,the packet will be transmitted with the same speed

as the first packet.

Page_select

R/W

000

Select page address between 1000 to 1111.

000: Port Status Page

001: Vendor ID Page

111: Vendor Dependent Page

Others: Unused

Port_select

R/W

0000

Port Selection.

Selecting 000 (Port Status Page) with the Page_select selects the port.

Selecting 111 (Vendor Dependent Page) with the Page_select have to select

the Port 1.

0000: Port 0

0001: Port 1

0010: Port 2

Others: Unused

Reserved

000...

Reserved. Read as 0.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

2.2 Port Status Page (Page 000)

Figure 2-2. Port Status Page

1000

AStat

BStat

Child

Connected

Bias

Disabled

1001

Negotiated_speed

Int_enable

Fault

Reserved

1010

Reserved

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

Table 2-2. Bit Field Description

Field

Size

R/W

Reset value

Description

AStat

A port status value.

00: invalid, 10: "0"

01: "1", 11: "Z"

BStat

B port status value.

00: invalid, 10: "0"

01: "1", 11: "Z"

Child

Child node status value.

1: Connected to child node

0: Connected to parent node

Connected

Connection status value.

1: Connected

0: Disconnected

Bias

Bias voltage status value.

1: Bias voltage

0: No bias voltage

Disabled

R/W

See

Description

The reset value is set to 0: Enabled.

Negotiated_

Speed

Shows the maximum data transfer rate of the node connected to this port.

000: 100 Mbps

001: 200 Mbps

010: 400 Mbps

Int_enable

R/W

When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias,

Disabled or Fault bits change state.

Fault

R/W

Set to 1 if an error occurs during Suspend/Resume.

Writing 1 to this bit clears it to 0.

Writing 0 has no effect.

Reserved

000...

Reserved. Read as 0.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.1 Offset_00 Vendor ID Register

This register identifies the manufacturer of the

µPD72874. The ID is assigned by the PCI_SIG committee.

Bits

R/W

Description

15-0

Constant value of 1033H.

3.1.2 Offset_02 Device ID Register

This register identifies the type of the device for the

µPD72874. The ID is assigned by NEC Corporation.

Bits

R/W

Description

15-0

Constant value of 00F2H.

3.1.3 Offset_04 Command Register

The register provides control over the device's ability to generate and respond to PCI cycles.

Bits

R/W

Description

I/O enable Constant value of 0. The

µPD72874 does not respond to PCI I/O accesses.

R/W

Memory enable Default value of 1. It defines if the

µPD72874 responds to PCI memory

accesses. This bit should be set to one upon power-up reset.

0: The

µPD72874 does not respond to PCI memory cycles

1: The

µPD72874 responds to PCI memory cycles

R/W

Master enable Default value of 1. It enables the

µPD72874 as bus-master on the PCI-bus.

0: The

µPD72874 cannot generate PCI accesses by being a bus-master

1: The

µPD72874 is capable of acting as a bus-master

Special cycle monitor enable Constant value of 0. The special cycle monitor is always

disabled.

R/W

Memory write and invalidate enable Default value of 0. It enables Memory Write and Invalid

Command generation.

0: Memory write must be used

1: The

µPD72874, when acts as PCI master, can generate the command

VGA

color palette invalidate enable Constant value of 0. VGA color palette invalidate is

always disabled.

R/W

Parity error response Default value of 0. It defines if the

µPD72874 responds to PERR.

0: Ignore parity error

1: Respond to parity error

Stepping enable Constant value of 0. Stepping is always disabled.

R/W

System error enable Default value of 0. It defines if the

µPD72874 responds to SERR.

0: Disable system error checking

1: Enable system error checking

Fast back-to-back enable Constant value of 0. Fast back-to-back transactions are only

allowed to the same agent.

15-10

Reserved Constant value of 000000.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.4 Offset_06 Status Register

This register tracks the status information of PCI-bus related events which are relevant to the

µPD72874. "Read"

and "Write" are handled somewhat differently.

Bits

R/W

Description

3-0

Reserved Constant value of 0000.

New capabilities Constant value of 1. It indicates the existence of the Capabilities List.

6,5

Reserved Constant value of 00.

Fast back-to-back capable Constant value of 1. It indicates that the

µPD72874, as a target,

cannot accept fast back-to-back transactions when the transactions are not to the same agent.

R/W

Signaled parity error Default value of 0. It indicates the occurrence of any "Data Parity".

0: No parity detected (default)

1: Parity detected

10,9

DEVSEL timing Constant value of 01. These bits define the decode timing for DEVSEL.

0: Fast (1 cycle)

1: Medium (2 cycles)

2: Slow (3 cycles)

3: undefined

R/W

Signaled target abort Default value of 0. This bit is set by a target device whenever it

terminates a transaction with "Target Abort".

0: The

µPD72874 did not terminate a transaction with Target Abort

1: The

µPD72874 has terminated a transaction with Target Abort

R/W

Received target abort Default value of 0. This bit is set by a master device whenever its

transaction is terminated with a "Target Abort".

0: The

µPD72874 has not received a Target Abort

1: The

µPD72874 has received a Target Abort from a bus-master

R/W

Received master abort Default value of 0. This bit is set by a master device whenever its

transaction is terminated with "Master Abort". The

µPD72874 asserts "Master Abort" when a

transaction response exceeds the time allocated in the latency timer field.

0: Transaction was not terminated with a Master Abort

1: Transaction has been terminated with a Master Abort

R/W

Signaled system error Default value of 0. It indicates that the assertion of SERR by the

µPD72874.

0: System error was not signaled

1: System error was signaled

R/W

Received parity error Default value of 0. It indicates the occurrence of any PERR.

0: No parity error was detected

1: Parity error was detected

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.5 Offset_08 Revision ID Register

This register specifies a revision number assigned by NEC Corporation for the

µPD72874.

Bits

R/W

Description

7-0

Default value of 01H. It specifies the silicon revision. It will be incremented for subsequent

silicon revisions.

3.1.6 Offset_09 Class Code Register

This register identifies the class code, sub-class code, and programming interface of the

µPD72874.

Bits

R/W

Description

7-0

Constant value of 10H. It specifies an IEEE1394 OHCI-compliant Host Controller.

15-8

Constant value of 00H. It specifies an "IEEE1394" type.

23-16

Constant value of 0CH. It specifies a "Serial Bus Controller".

3.1.7 Offset_0C Cache Line Size Register

This register specifies the system cache line size, which is PC-host system dependent, in units of 32-bit words.

The following cache line sizes are supported: 2, 4, 8, 16, 32, 64, and 128. All other values will be recognized as 0,

i.e. cache disabled.

Bits

R/W

Description

7-0

R/W

Default value of 00H.

3.1.8 Offset_0D Latency Timer Register

This register defines the maximum amount of time that the

µPD72874 is permitted to retain ownership of the bus

after it has acquired bus ownership and initiated a subsequent transaction.

Bits

R/W

Description

7-0

R/W

Default value of 00H. It specifies the number of PCI-bus clocks that the

µPD72874 may hold

the PCI bus as a bus-master.

3.1.9 Offset_0E Header Type Register

Bits

R/W

Description

7-0

Constant value of 00H. It specifies a single function device.

3.1.10 Offset_0F BIST Register

Bits

R/W

Description

7-0

Constant value of 00H. It specifies whether the device is capable of Built-in Self Test.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.11 Offset_10 Base Address 0 Register

This register specifies the base memory address for accessing all the "Operation registers" (i.e. control,

configuration, and status registers) of the

µPD72874, while the BIOS is expected to set this value during power-up

reset.

Bits

R/W

Description

11-0

Constant value of 000H. These bits are "read-only".

31-12

R/W

3.1.12 Offset_2C Subsystem Vendor ID Register

This register identifies the subsystem that contains the NEC's

µPD72874 function. While the ID is assigned by the

PCI_SIG committee, the value should be loaded into the register from the external serial ROM after power-up reset.

Access to this register through PCI-bus is prohibited.

Bits

R/W

Description

15-0

Default value of 1033H.

3.1.13 Offset_2E Subsystem ID Register

This register identifies the type of the subsystem that contains the NEC's

µPD72874 function. While the ID is

assigned by the manufacturer, the value should be loaded into the register from the external serial EEPROM after

power-up reset. Access to this register through PCI-bus is prohibited.

Bits

R/W

Description

15-0

Default value of 00F2H.

3.1.14 Offset_34 Cap_Ptr Register

This register points to a linked list of additional capabilities specific to the

µPD72874, the NEC's implementation of

the 1394 OHCI specification.

Bits

R/W

Description

7-0

Constant value of 60H. The value represents an offset into the

µPD72874's PCI Configuration

Space for the location of the first item in the New Capabilities Linked List.

3.1.15 Offset_3C Interrupt Line Register

This register provides the interrupt line routing information specific to the

µPD72874, the NEC's implementation of

the 1394 OHCI specification.

Bits

R/W

Description

7-0

R/W

Default value of 00H. It specifies which input of the host system interrupt controller the

interrupt pin of the

µPD72874 is connected to.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.16 Offset_3D Interrupt Pin Register

This register provides the interrupt line routing information specific to the

µPD72874, the NEC's implementation of

the 1394 OHCI specification.

Bits

R/W

Description

7-0

Constant value of 01H. It specifies PCI INTA is used for interrupting the host system.

3.1.17 Offset_3E Min_Gnt Register

This register specifies how long of a burst period the

µPD72874 needs, assuming a clock rate of 33 MHz.

Resolution is in units of ¼

µs. The value should be loaded into the register from the external serial EEPROM upon

power-up reset, and access to this register through PCI-bus is prohibited.

Bits

R/W

Description

7-0

Default value of 00H. Its value contributes to the desired setting for Latency Timer value.

3.1.18 Offset_3F Max_Lat Register

This register specifies how often the

µPD72874 needs to gain access to the PCI-bus, assuming a clock rate of 33

MHz. Resolution is in units of ¼

µs. The value should be loaded into the register from the external serial EEPROM

after hardware reset, and access to this register through PCI-bus is prohibited.

Bits

R/W

Description

7-0

Default value of 00H. Its value contributes to the desired setting for Latency Timer value.

3.1.19 Offset_40 PCI_OHCI_Control Register

This register specifies the control bits that are IEEE1394 OHCI specific. Vendor options are not allowed in this

Bits

R/W

Description

R/W

PCI global SWAP Default value of 0. When this bit is 1, all quadrates read from and written to

the PCI Interface are byte swapped, thus a "PCI Global Swap". PCI addresses for expansion

ROM and PCI Configuration registers, are, however, unaffected by this bit. This bit is not

required for motherboard implementations.

31-1

Reserved Constant value of all 0.

3.1.20 Offset_60 Cap_ID & Next_Item_Ptr Register

The Cap_ID signals that this item in the Linked List is the registers defined for PCI Power Management, while the

Next_Item_Ptr describes the location of the next item in the

µPD72874's Capability List.

Bits

R/W

Description

7-0

Cap_ID Constant value of 01H. The default value identified the Link List item as being the PCI

Power Management registers, while the ID value is assigned by the PCI SIG.

15-8

Next_Item_Ptr Constant value of 00H. It indicated that there are no more items in the Link

List.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.21 Offset_62 Power Management Capabilities Register

This is a 16-bit read-only register that provides information on the power management capabilities of the

µPD72874.

Bits

R/W

Description

2-0

Version Constant value of 010. The power management registers are implemented as

defined in revision 1.1 of PCI Bus Power Management Interface Specification.

PME clock Constant value of 0.

Reserved Constant value of 0.

DSI Constant value of 0.

8-6

Auxiliary Power Default value of 000. This field reports the Vaux power requirements for the

µPD72874. This data is programable from EEPROM.

111 375 mA maximum current required for a 3.3 Vaux,

110 320 mA maximum current required for a 3.3 Vaux,

101 270 mA maximum current required for a 3.3 Vaux,

100 220 mA maximum current required for a 3.3 Vaux,

011 160 mA maximum current required for a 3.3 Vaux,

010 100 mA maximum current required for a 3.3 Vaux,

001 55 mA maximum current required for a 3.3 Vaux,

000 0 (self powered)

D1_support Constant value of 1. The

µPD72874 supports the D1 Power Management state.

D2_support Constant value of 1. The

µPD72874 supports the D2 Power Management state.

15-11

PME_support

D3SUP = `High' : Constant value of 11111.

D3SUP = `Low' : Constant value of 01111.

This field indicates the power states in which the

µPD72874 may assert PME. A value of "0" for

any bit indicates that the function is not capable of asserting the PME signal while in that power

state.

bit (11) PME_D0. PME can be asserted from D0.

bit (12) PME_D1. PME can be asserted from D1.

bit (13) PME_D2. PME can be asserted from D2.

bit (14) PME_D3hot. PME can be asserted from D3hot.

bit (15) PME_D3cold. PME can be asserted from D3cold.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

3.1.22 Offset_64 Power Management Control/Status Register

This is a 16-bit register that provides control status information of the

µPD72874.

Bits

R/W

Description

1,0

R/W

PowerState Default value is undefined. This field is used both to determine the current power

state of the

µPD72874 and to set the µPD72874 into a new power state.

00: D0 (DMA contexts: ON, Link Layer: ON, PME will be asserted upon INTA being active.)

01: D1 (DMA contexts: OFF, Link Layer: ON, PME will be asserted upon INTA being active)

10: D2 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon

LinkON being active)

11: D3 (DMA contexts: OFF, Link Layer: OFF, LPS: OFF, PME will be asserted upon

LinkON being active)

The LPS is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in

the

µPD72874.

7-2

Reserved Constant value of 000000.

R/W

PME_En Default value of 0. This field is used to enable the specific power management

features of the

µPD72874.

12-9

Data_Select Constant value of 0000.

14,13

Data_Scale Constant value of 00.

R/W

PME_Status Default value is undefined. A write of `1' clears this bit, while a write of `0' is

ignored.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

(3) Function Reset Status Register (FRSR) (Base Address 1 (2) + 8H)

Bits

R/W

Description

Write Protect (No Use).

Read only as `0'

Ready Status (No Use).

Read only as `0'

Battery Voltage Detect 2 (No Use).

Read only as `0'

Battery Voltage Detect 1 (No Use).

Read only as `0'

R/W

General Wake Up Mask

14-5

Reserved. Read only as `0'

R/W

Interrupt

31-16

Reserved. Read only as `0'

(4) Function Force Event Register (FFER) (Base Address 1 (2) + CH)

Bits

R/W

Description

Write Protect (No Use).

Read only as `0'

Ready Status (No Use).

Read only as `0'

Battery Voltage Detect 2 (No Use).

Read only as `0'

Battery Voltage Detect 1 (No Use).

Read only as `0'

R/W

General Wake Up Mask

14-5

No Use

R/W

Interrupt

31-16

Reserved. Read only as `0'

3.2.2 Offset_28 Cardbus CIS Pointer

This register specifies start memory address of the Cardbus CIS Area.

Bits

R/W

Description

31-0

Starting Pointer of CIS Area.

Constant value of 00000080H.

3.2.3 Offset_80 CIS Area

The

µPD72874 supports external Serial ROM (AT24C02 compatible) interface.

CIS Area Register can be loaded from external Serial ROM in the CIS area when CARD_ON is 1.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

4.1.2 Cable Interface Circuit

Each port is configured with two twisted-pairs of TpA and TpB.

TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables.

During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is

encoded, converted from parallel to serial and transmitted.

While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel

after synchronization by SCLK

Note

, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate

of 100/200/400 Mbps.

The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of

the 1394 bus is transmitted to the state machine in the LSI.

Note The SCLK is a PHY/Link interface signal and is defined in P1394a-2000. It is an internal signal in the

µPD72874.

4.1.3 CPS

Connect an external resistor of 390 k

between the CPS pin and the power cable, and an external resistor of 100

between the CPS pin and the GND to monitor the power of the power cable.

If the cable power falls under 7.5 V there is an indication to the Link layer that the power has failed.

4.1.4 Unused Ports

TpAp, TpAn : Not connected

TpBp, TpBn : AGND

TpBias : Not connected

4.2 PLL and Crystal Oscillation Circuit

4.2.1 Crystal Oscillation Circuit

To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.

4.2.2 PLL

The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).

4.3 PC0 to PC2

The PC0 to PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer

to Section 4.3.4.1 of the IEEE1394-1995 specification for information regarding the Pwr_class. The value of Pwr can

be changed with software through the Link layer; this pin sets the initial value during Power-on Reset. Use a pull-up

or pull-down resistor of 1 k

based on the application.

4.4 P_RESET

Connect an external capacitor of 0.1

µF between the pins P_RESET and GND. If the voltage drops below 0 V, a

reset pulse is generated. All of the circuits are initialized, including the contents of the PHY register.

4.5 RI0, RI1

Connect an external resistor of 9.1 k

± 0.5 % to limit the LSI's current.

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

DC Characteristics (V

= 3.3 V

±
±
±
± 10 %, V

= 0 V, T

= 0 to +70

°
°
°
°C)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

High-level input voltage

2.0

+0.5

Low-level input voltage

0.5

+0.8

High-level output current

= 2.4 V,

GROM_SDA, GROM_SCL

Low-level output current

= 0.4 V,

GROM_SDA, GROM_SCL

Input leakage current

= V

or GND

±10.0

µA

PCI interface

High-level input voltage

2.0

5.5

Low-level input voltage

0.5

+0.8

High-level output current

= 2.4 V

Low-level output current

= 0.4 V

Input leakage current

= V

or GND

±10.0

µA

Cable interface

Cable input, 100 Mbps operation

142

260

Cable input, 200 Mbps operation

132

260

Differential input voltage

Cable input, 400 Mbps operation

118

260

100 Mbps speed signaling off

1.165

2.515

200 Mbps speed signaling

0.935

2.515

TpB common mode input voltage

ICM

400 Mbps speed signaling

0.523

2.515

Differential output voltage

Cable output (Test load 55

)

172.0

265.0

100 Mbps speed signaling off

1.665

2.015

200 Mbps speed signaling

1.438

2.015

TpA common mode output voltage

OCM

400 Mbps speed signaling

1.030

2.015

100 Mbps speed signaling off

0.81

+0.44

200 Mbps speed signaling

4.84

2.53

TpA common mode output current

400 Mbps speed signaling

12.40

8.10

Power status threshold voltage

CPS

7.5

TpBias output voltage

TPBIAS

1.665

2.015

Remarks 1. Digital core runs at 3.3 V.

2. PCI Interface can run at 5 or 3.3 V, depending on the choice of 5 V-PCI or 3.3 V-PCI.

3. All other I/Os are 3.3 V driving, and 5 V tolerant.

4. 5 V are used only for 5 V-PCI clamping diode.

3.3 V

Protection Circuit

5.0 V

I/O Buffer

Preliminary Data Sheet S15306EJ2V0DS

µ
µ
µ
µ

PD72874

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

µ
µ
µ
µ

PD72874

EEPROM and Firewarden are trademarks of NEC Corporation.

VGA is a trademark of IBM Corporation.

M8E 00. 4

The information in this document is current as of April, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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