DESCRIPTION

The

PD75008 is one of the 75X Series 4-bit single-chip microcomputer.

In addition to high-speed operation with 0.95

s minimum instruction execution time for the CPU, the

PD75008 employs a serial bus interface with standard NEC format, the

PD75004 is a powerful product with

a high cost/performance ratio.

The

PD75P008 with PROM, which is provided with

PD75008, is applicable for evaluating systems under

development, or for small-scale production of developed systems.

Detailed functions are described in the following user's manual. Be sure to read it for designing.

PD7500X Series User's Manual: IEM-5033

FEATURES

Capable of high-speed operation and variable instruction execution time to power save

· 0.95

s, 1.91

s, 15.3

s (Main system clock: operating at 4.19 MHz)

· 122

s (Subsystem clock: operating at 32.768 kHz)

75X architecture comparable to that for an 8-bit microcomputer is employed

Built-in NEC standard serial bus interface (SBI)

Clock operation at reduced power dissipation (5

A TYP. : operating at 3 V)

Enhanced timer function (3 channels)

Interrupt functions especially enhanced for applications, such as remote control receiver

APPLICATIONS

VCRs, CD players, telephones, cameras, blood pressure gauges, etc.

NEC Corporation 1990

Document No.

IC-2633C

(O. D. No.

IC-7673E)

Date Published

November 1993 P

Printed in Japan

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75004, 75006, 75008

The information in this document is subject to change without notice.

4-BIT SINGLE-CHIP MICROCOMPUTER

The mark 5 shows major revised points.

Unless otherwise specified,

PD75008 is treated as the representative model throughout this manual.

PD75004, 75006, 75008

ORDERING INFORMATION

Part Number

Package

Quality Grade

PD75004CU-xxx

42-pin plastic shrink DIP (600 mil)

Standard

PD75004GB-xxx-3B4

44-pin plastic QFP (

10 mm)

Standard

PD75006CU-xxx

42-pin plastic shrink DIP (600 mil)

Standard

PD75006GB-xxx-3B4

44-pin plastic QFP (

10 mm)

Standard

PD75008CU-xxx

42-pin plastic shrink DIP (600 mil)

Standard

PD75008GB-xxx-3B4

44-pin plastic QFP (

10 mm)

Standard

Remarks: xxx is ROM code number.

Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

PD75004, 75006, 75008

FUNCTIONAL OUTLINE

Item

Function

Instruction

0.95, 1.91, and 15.3

s, (Main system clock: operating at 4.19 MHz)

Execution Time

122

s (Subsystem clock: operating at 32.768 kHz)

4096

8-bit (

PD75004)

ROM

6016

8-bit (

PD75006)

8064

8-bit (

PD75008)

RAM

512

4-bit

General-Purpose

· 4-bit manipulation: 8

Registers

· 8-bit manipulation: 4

CMOS Input pins

Internal pull-up resistor
specification by software

CMOS input/output pins

is possible. : 25

Can directly drive LED: 4

N-ch open-drain

Withstand voltage: 10V

input/output

Internal pull-up resistor

Can directly drive LED: 8

specification by mask option
is possible.

Timer/event counter

Timer

3 chs

Basic interval timer: Also serves as watchdog timer

Watch timer: Buzzer output possible

Serial

3-line serial I/O mode

Interface

2-line serial I/O mode
SBI mode

Bit Sequential

16 bits

Buffer

Clock Output Function

Vector Interrupt

External: 3, Internal: 3

Test Input

External: 1, Internal: 1

System Clock

Main system clock oscillation ceramic/crystal oscillator

Oscillator

Subsystem clock oscillation crysal ocillator

Standby Function

STOP/HALT mode

Operating

40 to +85

Temperature Range

Operating Supply

2.7 to 6.0 V

Voltage

Package

42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (

10 mm)

Internal
Memory

I/O Port

PD75004, 75006, 75008

CONTENTS

PIN CONFIGURATION (TOP VIEW) ...............................................................................................

BLOCK DIAGRAM ...........................................................................................................................

PIN FUNCTIONS ..............................................................................................................................

3.1

PORT PINS .............................................................................................................................................

3.2

NON PORT PINS ...................................................................................................................................

3.3

PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................

3.4

SELECTION OF MASK OPTION ..........................................................................................................

3.5

RECOMMENDED PROCESSING OF UNUSED PINS ..........................................................................

3.6

NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................

MEMORY CONFIGURATION ..........................................................................................................

PERIPHERAL HARDWARE FUNCTIONS ........................................................................................

5.1

PORTS ....................................................................................................................................................

5.2

CLOCK GENERATOR CIRCUIT ............................................................................................................

5.3

CLOCK OUTPUT CIRCUIT ....................................................................................................................

5.4

BASIC INTERVAL TIMER .....................................................................................................................

5.5

WATCH TIMER ......................................................................................................................................

5.6

TIMER/EVENT COUNTER .....................................................................................................................

5.7

SERIAL INTERFACE ..............................................................................................................................

5.8

BIT SEQUENTIAL BUFFER ...................................................................................................................

INTERRUPT FUNCTIONS ................................................................................................................

STANDBY FUNCTIONS ..................................................................................................................

RESET FUNCTION ...........................................................................................................................

INSTRUCTION SET .........................................................................................................................

10. ELECTRICAL SPECIFICATIONS ......................................................................................................

11. CHARACTERISTIC CURVES ...........................................................................................................

PD75004, 75006, 75008

PIN CONFIGURATION (Top View)

· 42-pin plastic shrink DIP (600 mil)

P72/KR6

P03/TI0

P73/KR7

PD75004GBxxx3B4

P20/PTO0

P21

P22/PCL

P23/BUZ

P10/INT0

P11/INT1

P12/INT2

P43

P42

P40

XT1

XT2

RESET

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

P60/KR0

P53

P52

P51

P50

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P80

P81

P30

P31

P32

P33

P41

PD75006GBxxx3B4

PD75008GBxxx3B4

XT1

PD75004CU-xxx

XT2

RESET

P33

P32

P31

P30

P81

P80

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT4/P00

TI0/P13

INT2/P12

INT1/P11

INT0/P10

P40

P41

P42

P43

P50

P51

P52

P53

P60/KR0

P61/KR1

P62/KR2

P63/KR3

P70/KR4

P71/KR5

P72/KR6

P73/KR7

P20/PTO0

P21

P22/PCL

P23/BUZ

PD75006CU-xxx

PD75008CU-xxx

· 44-pin plastic QFP (

10 mm)

PD75004,

75006,

75008

BLOCK DIAGRAM

TI0/P13

BASIC

INTERVAL

TIMER

INTBT

TIMER/EVENT

COUNTER

INTT0

PTO0/P20

BUZ/P23

WATCH
TIMER

INTW

INTCSI

CLOCKED

SERIAL

INTERFACE

SI/SB1/P03

SO/SB0/P02

SCK/P01

PROGRAM
COUNTER *

ALU

SP (8)

BANK

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0/P60

KR7/P73

INTERRUPT

CONTROL

BIT SEQ.

BUFFER (16)

PROGRAM

MEMORY

(ROM)

4096 8 BITS

( PD75004)

6016 8 BITS

( PD75006)

8064 8 BITS

( PD75008)

DECODE

AND

CONTROL

GENERAL REG.

DATA

MEMORY

(RAM)

512 4 BITS

f /2

RESET

PCL/P22

XT1

XT2 X1

SUB

MAIN

CLOCK

OUTPUT

CONTROL

CLOCK

DIVIDER

SYSTEM CLOCK

GENERATOR

STAND BY
CONTROL

CPU
CLOCK

PORT 8

P80-P81

PORT 6

P60-P63

PORT 5

P50-P53

PORT 4

P40-P43

PORT 3

P30-P33

PORT 2

P20-P23

PORT 1

P10-P13

PORT 0

P00-P03

PORT 7

P70-P73

*: For PD75004, 12 bits. For PD75006 and PD75008, 13 bits.

PD75004, 75006, 75008

PIN FUNCTIONS

3.1

PORT PINS (1/2)

Input/

Output

Circuit

TYPE*

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30*

P31*

P32*

P33*

P40-43*

P50-53*

Pin Name Input/Output

Function

8-Bit I/O

When Reset

Also Served
As

INT4

SCK

SO/SB0

SO/SB1

INT0

INT1

INT2

TI0

PTO0

PCL

BUZ

4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.

With noise elimination function

4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.

4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.

Programmable 4-bit input/output port
(PORT3)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.

N-ch open-drain 4-bit input/output port
(PORT4)
Internal pull-up resistors can be
specified in bit units. (mask option)
Resistive voltage is 10 V in the open-
drain mode.

N-ch open-drain 4-bit input/output port
(PORT5)
Internal pull-up resistors can be
specified in bit units. (mask option)
Resistive voltage is 10 V in the open-
drain mode.

Input

High level
(with internal
pull-up
resistor) or
high imped-
ance

B -C

E-B

*1: Circles indicate Schmitt trigger inputs.

2: Can directly drive LED.

Input

Input/

Output

Input/

Output

Input/

Output

Input

Input/

Output

Input/

Output

Input/

Output

Input/

Output

F -A

M -C

F -B

High level
(with internal
pull-up
resistor) or
high imped-
ance

PD75004, 75006, 75008

P60

P61

P62

P63

P70

P71

P72

P73

P80

P81

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

Input/

Output

Input/

Output

Input/

Output

Also Served
As

3.1

PORT PINS (2/2)

Input/

Output

Circuit

TYPE*

Programmable 4-bit input/output port
(PORT6)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.

Input

F -A

4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.

Input

F -A

Pin Name Input/Output

Function

8-Bit I/O

When Reset

2-bit input/output port (PORT8)
Internal pull-up resistors can be
specified in 2-bit units by software.

Input

E-B

*1: Circles indicate Schmitt trigger inputs.

2: Can directly drive LED.

PD75004, 75006, 75008

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0-KR3

KR4-KR7

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60-P63

P70-P73

Input

B -C

E-B

F -A

F -B

M -C

B -C

F -A

Pin Name Input/Output

Also Served
As

Functon

When Reset

Input/

Output

Circuit

TYPE*

3.2

NON PORT PINS

Timer/event counter external event pulse Input

Timer/event counter output

Clock output

Fixed frequency output (for buzzer or for trim-
ming the system clock)

Serial clock input/output

Serial data output
Serial bus input/output

Serial data input
Serial bus input/output

Edge detection vector interrupt input (both
rising and falling edge detection are effective)

Edge detection vector
interrupt input (detection
edge can be selected)

Edge detection testable
input (rising edge detection)

Clock synchronous

Asynchronous

X1, X2

RESET

NC *

Input

*1: Circles indicate Schmitt trigger inputs.

2: When sharing the printed circut board with the

PD75P008, the NC pin must be directly

connected to V

Input

Input/
Output

Input

Input/
Output

XT1

XT2

Input

Parallel falling edge detection testable input

To connect the crystal/ceramic oscillator to the
main system clock generator. When inputting the
external clock, input the external clock to pin X1,
and the reverse phase of the external clock to pin
X2.

To connect the crystal oscillator to the subsystem
clock generator.
When the external clock is used, pin XT1 inputs
the external clock. In this case, pin XT2 must be
left open.

System reset input

No connection

Positive power supply

GND

PD75004, 75006, 75008

3.3

PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the

PD75008.

TYPE A (for TYPE EB)

TYPE D (for TYPE E

B, F

TYPE B

TYPE EB

Input buffer of CMOS standard

data

output
disable

OUT

Pch

Nch

Pushpull output that can be set in a output
highimpedance state (both Pch and Nch are off)

Schmitt trigger input with hysteresis characteristics

data

output
disable

Type D

Type A

P.U.R.
enable

P.U.R.

Pch

IN/OUT

P.U.R. : PullUp Resistor

P.U.R.
enable

P.U.R.

Pch

TYPE BC

TYPE FA

data

output
disable

Type D

Type B

P.U.R.
enable

P.U.R.

Pch

IN/OUT

P.U.R. : PullUp Resistor

PD75004, 75006, 75008

3.4

SELECTION OF MASK OPTION

The following mask operations are available and can be specified for each pin.

Table 3-1 Mask Option Selection

Mask Option

P40-P43,

P50-P53

· With pull-up resistor

· Without pull-up resistor

*: Mask option can be specified in bit units.

3.5

RECOMMENDED PROCESSING OF UNUSED PINS

Table 3-2 Processing of Unused Pins

Recommended Connections

P00/INT4

Connect to V

P01/SCK

P02/SO/SB0

Connect to V

or V

P03/SI/SB1

P10/INT0-P12/INT2

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30-P33

Input

: Connect to V

or V

P40-P43

Output: Open

P50-P53

P60-P63

P70-P73

P80-P81

XT1

Connect to V

or V

XT2

Open

Connect to V

PD75004, 75006, 75008

3.6

NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 PORT PINS and 3.2 NON PORT PINS, an exclusive

function for setting the test mode, in which the internal fuctions of the

PD75008 are tested (solely used for

IC tests), is provided to the P00/INT4 and RESET pins.

If a voltage exceeding V

is applied to either of these pins, the

PD75008 is put into test mode. Therefore,

even when the

PD75008 is in normal operation, if noise exceeding the V

is input into any of these pins, the

PD75008 will enter the test mode, and this will cause problems for normal operation.

As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up

and the above montioned problem may occur.

Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot

be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

Connect a capacitor across P00/INT4 and

RESET, and V

P00/INT4, RESET

Low V

diode

Connect a diode having a low V

across

P00/INT4 and RESET, and V

. (0.3 V max.)

PD75004, 75006, 75008

MEMORY CONFIGURATION

Program memory (ROM) ... 4096

8 bits (0000H-0FFFH) :

PD75004

... 6016

8 bits (0000H-177FH) :

PD75006

... 8064

8 bits (0000H-1F7FH) :

PD75008

· 0000H-0001H : Vector table to which address from which program is started is written after reset

· 0002H-000BH: Vector table to which address from which program is started is written after interrupt

· 0020H-007FH : Table area referenced by GETI instruction

Data memory (RAM)

· Data area .... 512

4 bits (000H1FFH)

· Peripheral hardware area .... 128

4 bits (F80HFFFH)

MBE

Internal reset start address (upper 4 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 4 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 4 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 4 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 4 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 4 bits)

INTT0 start address (lower 8 bits)

000H

002H

004H

006H

008H

00AH

020H

07FH
080H

7FFH
800H

FFFH

GETI instruction reference table

CALLF

!faddr

instruction

entry

address

BRCD ! caddr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(15 to 1,
+2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

Fig. 4-1 Program Memory Map (

PD75004)

PD75004, 75006, 75008

MBE

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 5 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 5 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 5 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

07FFH
0800H

0FFFH
1000H

177FH

GETI instruction reference table

BRCB

! caddr

instruction

branch

address

CALLF
! faddr

instruction

entry

address

BR ! addr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(15 to 1,
+2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

BRCB ! caddr

instruction

branch address

Fig. 4-2 Program Memory Map (

PD75006)

PD75004, 75006, 75008

MBE

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 5 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 5 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 5 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

07FFH
0800H

0FFFH
1000H

1F7FH

GETI instruction reference table

BRCB

! caddr

instruction

branch

address

CALLF
! faddr

instruction

entry

address

BR ! addr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(15 to 1,
+2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

BRCB ! caddr

instruction

branch address

Fig. 4-3 Program Memory Map (

PD75008)

PD75004, 75006, 75008

PERIPHERAL HARDWARE FUNCTIONS

5.1

PORTS

I/O ports are classified into the following 3 kinds:

CMOS input (PORT0, 1)

CMOS input/output (PORT2, 3, 6, 7, and 8) : 18

N-ch open-drain input/output (PORT4, 5)

Total

: 34

Remarks

Multiplexed with SO/SB0,
SI/SB1, SCK, INT0-2, 4,
and TIO

Port 6 is multiplexed with
KR0 to KR3.

Port 2 is multiplexed with
PTO0, PCL, and BUZ.

Port 7 is multiplexed with
KR4-KR7.

Can be connected to a
pull-up resistor in 1-bit
units by using mask
option.

PORT0

PORT1

PORT3*

PORT6

PORT2

PORT7

PORT4*

PORT5*

PORT8

Function

4-bit input

4-bit input/output

4-bit input/output
(N-ch open-drain,
10 V)

2-bit input/output

Table 5-1 Port Function

Operation and Feature

Can be always read or tested regardless of opera-
tion mode of multiplexed pin.

Can be set in input or output mode in 1-bit units.

Can be set in input or output mode in 4-bit units.
Ports 6 and 7 are used in pairs to input/output data
in 8-bit units.

Can be set in input or output mode in 4-bit units.
Ports 4 and 5 are used in pairs to input/output data
in 8-bit units.

Can be set input or output mode in 2-bit units.

*: Can directly drive LED.

Port Name

(Symbol)

PD75004, 75006, 75008

5.2

CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and

system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

0.95

s, 1.91

s, 15.3

s (main system clock: 4.19 MHz)

122

s (subsystem clock: 32.768 kHz)

*: instruction execution.

Remarks 1: f

= Main system clock frequency

2: f

= Subsystem clock frequency

CPU clock

4: PCC: Processor clock control register

5: SCC: System clock control register

6: One clock cysle (t

) of

is one machine cycle of an instruction. For t

, refer to AC

characteristics in 10. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

XT1

XT2

Watch timer

Subsystem

clock

oscillator

Main system

clock

oscillator

1/2 1/16

1/8 to 1/4096

Frequency divider

· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· INT0 noise rejecter circuit
· Clock output circuit

Internal bus

WM.3

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

HALT*

STOP*

PCC2, PCC3

clear signal

STOP F/F

HALT F/F

Oscillator

disable

signal

Frequency

divider

1/4

Selector

· CPU
· INT0 noise
rejecter circuit
· Clock output
circuit

Wait release
signal from BT

RESET signal

Standby release
signal from interrupt
control circuit

PD75004, 75006, 75008

5.3

CLOCK OUTPUT CIRCUIT

The clock output circuit outputs clock pulse from the P22/PCL pin. This clock output circuit is used to output

clock pulses to the remote control output, peripheral LSIs, etc.

Clock output (PCL)

, 524, 262, 65.5 kHz (operating at 4.19 MHz)

Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz, or 32.768 kHz)

Fig. 5-2 shows the clock output circuit configuration.

Selector

Output
buffer

PCL/P22

Bit 2 of PMGB

PORT2.2

Port 2 input/
output mode
specification
bit

P22 output
latch

Internal bus

CLOM3 CLOM2 CLOM1 CLOM0 CLOM

From the

clock

generator

Fig. 5-2 Clock Output Circuit Configuration

Remarks:

A measures to prevent outputting narrow width pulse when selecting clock output enable/

disable is taken.

PD75004, 75006, 75008

5.4

BASIC INTERVAL TIMER

The basic interval timer has these functions:

Interval timer operation which generates a reference time interrupt

Watchdog timer application which detects a program runaway

Selects the wait time for releasing the standby mode and counts the wait time

Reads out the count value

Remarks : *: Instruction execution

Fig. 5-3 Basic Interval Timer Configuration

From the
clock generator

MPX

Clear

Basic interval timer

(8-bit frequency divider circuit)

Clear

Set
signal

interrupt

request flag

IRQBT

Wait release signal
for standby release

Vector
interrupt
request
signal

Internal bus

BTM3

BTM2

BTM1

BTM0

BTM

SET1*

PD75004, 75006, 75008

5.5

WATCH TIMER

The

PD75008 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4.

Sets the test flag (IRQW) with 0.5 sec interval.

The standby mode can be released by IRQW.

0.5 second interval can be generated either from the main system clock or subsystem clock.

Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient

for program debugging, test, etc.

Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock

frequency trimming.

The frequency divider circuit can be cleared so that zero second watch start is possible.

WM7 WM6 WM5 WM4 WM3 WM2 WM1 WM0

Selector

Frequency divider

(256 Hz: 3.91 ms)

INTW
(IRQW
set signal)

(2 Hz
0.5 sec)

Selector

(32.768
kHz)

(2.048
kHz)

Clear

128
(32.768 kHz)

(32.768 kHz)

From the
clock
generator

PORT2.3

Bit 2 of PMGB

Output buffer

P23/BUZ

P23
output
latch

Port 2
input/output
mode

Bit test
instruction

Internal bus

( ) is for f

= 4.194304 MHz, f

= 32.768 kHz.

Fig. 5-4 Watch Timer Block Diagram

5.6

TIMER/EVENT COUNTER

The

PD75008 has a built-in 1-ch timer/event counter. The timer/even counter has these functions:

Programmable interval timer operation

Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.

Event counter operation

Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).

Supplies serial shift clock to the serial interface circuit.

Count condition read out function

PD75004, 75006, 75008

5.8

BIT SEQUENTIAL BUFFER .... 16 BITS

The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this

buffer is very useful for processing long data in bit units.

Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.

Fig. 5-7 Bit Sequential Buffer Format

6. INTERRUPT FUNCTIONS

The

PD75008 has 8 different interrupt sources and multiplexed interrupt through the software control.

In addition to that, the

PD75008 is also provided with two types of edge detection testable inputs.

The interrupt control circuit of the

PD75008 has these functions:

Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by

using the interrupt flag (IExxx) and interrupt master enable flag (IME).

The interrupt start address can be arbitrarily set.

Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of

software).

Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).

Address bit

Symbol

L register

L = F

L = C L = B

L = 8 L = 7

L = 4 L = 3

L = 0

BSB3

BSB2

BSB1

BSB0

DECS L

INCS L

FC3H

FC2H

FC1H

FC0H

PD75004, 75006, 75008

7. STANDBY FUNCTIONS

The

PD75008 has two different standby modes (STOP mode and HALT mode) to reduce the power

consumption while waiting for program execution.

Table 7-1 Each Status in Standby Mode

Setting Instruction

STOP instrtuction

HALT instruction

Can be set only when operating on
the main system clock

Can be set either with the main
system clock or the subsystem clock

Operation
Status

Clock Generator

Only the main system clock stops its
operation.

Only the CPU clock

stops its

operation. (oscillation continues)

Basic Interval
Timer

No operation

Can operate only when main system
clock oscillates (Sets IRQBT at
reference time interval)

Serial Interface

Can operate only when the external
SCK input is selected for the serial
clock

Can operate only when external SCK
input is selected as serial clock, or
when main system clock oscillates

Timer/Event
Counter

Can operate only when the TI0 pin
input is selected for the count clock

Can operate only when TI0 pin input
is selected as count clock, or when
main system clock oscillates

Watch Timer

Can operate when f

is selected as

the count clock

Can operate

STOP Mode

HALT Mode

System Clock for Setting

Release Signal

An interrupt request signal from a
hardware whose operation is
enabled by the interrupt enable flag
or the RESET signal input

External Interrupt

INT1, INT2, and INT4 can operate.
Only INT0 can not operate.

CPU

No operation

PD75004, 75006, 75008

8. RESET FUNCTION

When the RESET signal is input, the

PD75008 is reset and each hardware is initialized as indicated in Table

8-1. Fig. 8-1 shows the reset operation timing.

RESET input

Wait

(31.3ms/4.19MHz)

Operation mode
or standby mode

HALT mode

Operation mode

Internal reset operation

Fig. 8-1 Reset Operation by RESET Input

Table 8-1 Status of Each Hardware after Reset (1/2)

Hardware

RESET Input in Standby Mode

RESET Input during Operation

Program Counter (PC)

The contents of the lower 4 bits
of address 000H of the program
memory are set to PC11-8, and
the contents of address 001H are
set to PC7-0.

Same as at left

PSW

Carry Flag (CY)

Retained

Undefined

Skip Flag (SK0-2)

Interrupt Status Flag (IST0)

Bank Enable Flag (MBE)

The contents of bit 7 of address
000H of the program memory is
set to MBE.

Same as at left

Stack Pointer (SP)

Undefined

Data Memory (RAM)

Retained

Undefined

General-Purpose Register
(X, A, H, L, D, E, B, C)

Bank Selection Register (MBS)

Undefined

Timer/Event
Counter

Counter (T0)

Module Register
(TMOD0)

Mode Register (TM0)

TOE0, TOUT F/F

0, 0

Mode Register (BTM)

Mode Register (WM)

Watch Timer

Basic Interval
Timer

Counter (BT)

Undefined

*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.

Retained

Undefined

FFH

PD75004, 75006, 75008

Serial

Shift Register (SIO)

Retained

Undefined

Interface

Operation Mode

SBI Control Register

(SBIC)

Slave Address Register

Retained

Undefined

(SVA)

Clock

Processor Clock Control

Generator,

Clock Output

System Clock Control

Circuit

Clock Output Mode

Interrupt

Interrupt Enable Flag

Function

(IExxx)

Interrupt Master Enable

Flag (IME)

INT0, INT1, INT2 Mode

0, 0, 0

Registers (IM0, 1, 2)

Digital Port

Output Buffer

Off

Output Latch

Clear (0)

Input/Output Mode

Pull-Up Resistor

Specification Register
(POGA, B)

Bit sequential buffer (BSB0-3)

Retained

Specified

Hardware

RESET Input during Operation

RESET Input in Standby Mode

Table 8-1 Status of Each Hardware after Reset (2/2)

PD75004, 75006, 75008

INSTRUCTION SET

(1)

Operand representation and description

Describe one or more operands in the operand field of each instruction according to the operand

representation and description methods of the instruction (for details, refer to RA75X Assembler Package

User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from

several operands. The uppercase characters, +, and are keywords and must be described as is.

Describe an appropriate numeric value or label as immediate data.

The symbols in the register and flag symbols can be described as labels in the places of mem, fmem,

pmem, and bit (for details, refer to

PD7500X Series User`s Manual (IEM-5033)). However, fmem and

pmem restricts the label that can be described.

Representation

Description

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rpa

HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem*

8-bit immediate data or label

bit

2-bit immediate data or label

fmem

FB0H to FBFH,FF0H to FFFH immediate data or label

pmem

FC0H to FFFH immediate data or label

PD75004

0000H to 0FFFH immediate data or label

addr

PD75006

0000H to 177FH immediate data or label

PD75008

0000H to 1F7FH immediate data or label

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H to 7FH immediate data (where bit0 = 0) or label

PORTn

PORT0 to PORT8

IExxx

IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW

MBn

MB0, MB1, MB15

*: Only even address can be described as mem for 8-bit data processing.

PD75004, 75006, 75008

(2)

Legend of operation field

: A register; 4-bit accumulator

: B register; 4-bit accumulator

: C register; 4-bit accumulator

: D register; 4-bit accumulator

: E register; 4-bit accumulator

: H register; 4-bit accumulator

: L register; 4-bit accumulator

: X register; 4-bit accumulator

: Register pair (XA); 8-bit accumulator

: Register pair (BC); 8-bit accumulator

: Register pair (DE); 8-bit accumulator

: Register pair (HL); 8-bit accumulator

: Program counter

: Stack pointer

: Carry flag; or bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

PORTn : Port n (n = 0 to 8)

IME

: Interrupt mask enable flag

IExxx

: Interrupt enable flag

MBS

: Memory bank selector register

PCC

: Processor clock control register

: Delimiter of address and bit

(xx)

: Contents addressed by xx

xxH

: Hexadecimal data

PD75004, 75006, 75008

(3)

Symbols in addressing area field

MB = MBE . MBS
(MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (00H-7FH)

Data memory

MB = 15 (80H-FFH)

addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H-FBFH,

FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr = 000H-FFFH (

PD75004)

0000H-177FH (

PD75006)

0000H-1F7FH (

PD75008)

addr = (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

Program

caddr = 000H-FFFH (

PD75004)

memory

0000H-0FFFH (PC

= 0 :

PD75006, 75008)

addressing

0000H-177FH (PC

= 1 :

PD75006)

0000H-1F7FH (PC

= 1 :

PD75008)

faddr = 0000H-07FFH

*10

taddr = 0020H-007FH

Remarks 1:

MB indicates memory bank that can be accessed.

In *2, MB = 0 regardless of MBE and MBS.

In *4 and *5, MB = 15 regardless of MBE and MBS.

*6 to *10 indicate areas that can be addressed.

(4)

Machine cycle field

In this field, S indicates the number of machine cycles required when an instruction having a skip

function skips. The value of S varies as follows:

When no instruction is skipped ........................................................................

S = 0

When 1-byte or 2-byte instruction is skipped .................................................

S = 1

When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ..................

S = 2

Note : The GETI instruction is skipped in one machine cycle.

One machine cycle equals to one cycle of the CPU clock

, (=t

), and can be changed in three steps

depending on the setting of the processor clock control register (PCC).

PD75004, 75006, 75008

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

Transfer MOV

A, #n4

String effect A

reg1, #n4

reg1

XA, #n8

String effect A

HL, #n8

String effect B

rp2, #n8

rp2

A, @HL

(HL)

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A,mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg

reg

XA, rp

reg1, A

reg1

rp1, XA

rp1

XCH

A, @HL

(HL)

A, @rpa1

(rpa1)

XA, @HL

(HL)

A, mem

(mem)

XA, mem

(mem)

A, reg1

reg1

XA, rp

MOVT

XA, @PCDE

PD75004

(PC

11-8

+DE)

ROM

PD75006, 75008

(PC

12-8

+DE)

ROM

XA, @PCXA

PD75004

(PC

11-8

+XA)

ROM

PD75006, 75008

(PC

12-8

+XA)

ROM

Arith-

ADDS

A, #n4

1+S

A+n4

carry

metic

A, @HL

1+S

A+(HL)

carry

Opera-

ADDC

A, @HL

A, CY

A+(HL)+CY

tion

SUBS

A, @HL

1+S

A-(HL)

borrow

SUBC

A, @HL

A, CY

A-(HL)-CY

AND

A, #n4

A, @HL

(HL)

A, #n4

A, @HL

(HL)

XOR

A, #n4

A, @HL

(HL)

Accumu- RORC

, A

CY, A

n-1

lator
Manipu-

NOT

lation

PD75004, 75006, 75008

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

Incre-

INCS

reg

1+S

reg

reg+1

reg = 0

ment/

@HL

2+S

(HL)

(HL)+1

(HL) = 0

Decre-

mem

2+S

(mem)

(mem)+1

(mem) = 0

ment

DECS

reg

1+S

reg

reg-1

reg = FH

Compare SKE

reg, #n4

2+S

Skip if reg = n4

reg = n4

@HL, #n4

2+S

Skip if (HL) = n4

*1 (HL) = n4

A, @HL

1+S

Skip if A = (HL)

A = (HL)

A, reg

2+S

Skip if A = reg

A = reg

Carry

SET1

flag

CLR1

Manipu- SKT

1+S

Skip if CY = 1

CY = 1

lation

NOT1

Memory/ SET1

mem.bit

(mem.bit)

Bit

fmem.bit

(fmem.bit)

Manipu-

pmem.@L

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

lation

@H+mem.bit

(H + mem

3-0

.bit)

CLR1

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

@H+mem.bit

(H+mem

3-0

.bit)

SKT

mem.bit

2+S

Skip if (mem.bit) = 1

(mem.bit) = 1

fmem.bit

2+S

Skip if (fmem.bit) = 1

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit (L

1-0

)) = 1

(pmem.@L) = 1

@H+mem.bit

2+S

Skip if (H + mem

3-0

.bit) = 1

(@H+mem.bit) = 1

SKF

mem.bit

2+S

Skip if (mem.bit) = 0

(mem.bit) = 0

fmem.bit

2+S

Skip if (fmem.bit) = 0

(fmem.bit) = 0

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit (L

1-0

)) = 0

(pmem.@L) = 0

@H+mem.bit

2+S

Skip if (H + mem

3-0

.bit) = 0

(@H+mem.bit) = 0

SKTCLR fmem.bit

2+S

Skip if (fmem.bit) = 1 and clear

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit

(pmem.@L) = 1

1-0

)) = 1 and clear

@H+mem.bit

2+S

Skip if (H+mem

3-0

bit) = 1 and clear

(@H+mem.bit) = 1

AND1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

.bit(L

1-0

)) *5

CY,@H+mem.bit

(H+mem

3-0

.bit)

OR1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

.bit (L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

XOR1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

bit (L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

PD75004, 75006, 75008

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

Branch

addr

PD75004

11-0

addr

(The most suitable instruction
is selectable from among
BRCB !caddr, and BR $addr
depending on the assembler.)

PD75006, 75008

12-0

addr

(The most suitable instruction
is selectable from among BR
!addr, BRCB !caddr, and BR
$addr depending on the
assembler.)

!addr

PD75006, 75008

12-0

addr

$addr

PD75004

11-0

addr

PD75006, 75008

12-0

addr

BRCB

!caddr

PD75004

11-0

caddr

11-0

PD75006, 75008

12-0

+ caddr

11-0

Subrou-

CALL

!addr

PD75004

tine/

(SP-4)(SP-1)(SP-2)

11-0

Stack

(SP-3)

MBE, 0, 0, 0

Control

11-0

addr, SP

SP-4

PD75006, 75008

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, 0, 0, PC

12-0

addr, SP

SP-4

CALLF

!faddr

PD75004

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, 0, 0, 0

11-0

faddr, SP

SP-4

PD75006, 75008

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, 0, 0, PC

12-0

0, 0, faddr, SP

SP-4

RET

PD75004

MBE, x, x, x

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4

PD75006, 75008

MBE, x, x, PC

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4

RETS

3+S

PD75004

Undefined

MBE, x, x, x

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4,

then skip unconditionally

PD75006, 75008

MBE, x, x, PC

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4,

then skip unconditionally

PD75004, 75006, 75008

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

RETI

PD75004

MBE, x, x, x

(SP+1)

11-0

(SP)(SP+3)(SP+2)

PSW

(SP+4)(SP+5), SP

SP+6

PD75006, 75008

MBE, x, x, PC

(SP+1)

11-0

(SP)(SP+3)(SP+2)

PSW

(SP+4)(SP+5), SP

SP+6

PUSH

(SP-1)(SP-2)

rp, SP

SP-2

(SP-1)

MBS, (SP-2)

0, SP

SP-2

POP

(SP+1)(SP), SP

SP+2

MBS

(SP+1), SP

SP+2

Inter-

IME

rupt

IExxx

Control

IME

IExxx

I/O

IN *

A, PORTn

PORT

(n = 0-8)

XA, PORTn

PORT

n+1

,PORT

(n = 4, 6)

OUT *

PORTn, A

PORT

(n = 2-8)

PORTn, XA

PORT

n+1

, PORT

(n = 4, 6)

CPU

HALT

Set HALT Mode (PCC.2

Control

STOP

Set STOP Mode (PCC.3

NOP

No Operation

Special

SEL

MBn

MBS

n (n = 0, 1, 15)

GETI

taddr

PD75004

*10

Where TBR instruction,

11-0

(taddr)

3-0

+(taddr+1)

Where TCALL instruction,

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, 0, 0, 0

11-0

(taddr)

3-0

+(taddr+1)

SP-4

Except for TBR and TCALL

Depends on

instructions,

referenced

Instruction execution of

instruction

(taddr)(taddr+1)

PD75006, 75008

Where TBR instruction,

12-0

(taddr)

4-0

+(taddr+1)

Where TCALL instruction,

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, 0, 0, PC

12-0

(taddr)

4-0

+(taddr+1)

SP-4

Except for TBR and TCALL

Depends on

instructions,

referenced

Instruction execution of

instruction

(taddr)(taddr+1)

*: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.

.........................................................

.............................

.........................................................

.............................

.........................................................

.............................

.........................................................

.............................

Subrou-

tine/

Stack

Control

(Cont`d)

PD75004, 75006, 75008

10. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply Voltage

-0.3 to +7.0

Other than ports 4, 5

-0.3 to V

+0.3

Input Voltage

Ports 4, 5

w/pull-up

-0.3 to V

+0.3

resistor

Open drain

-0.3 to +11

Output Voltage

-0.3 to V

+0.3

High-Level Output

1 pin

-10

Current

All pins

-30

Low-Level Output

Ports 0, 3, 4, 5

Peak

Current

1 pin

rms

Other than ports 0, 3, 4, 5

Peak

1 pin

rms

Total of ports 0, 3, 4, 5, 8

Peak

160

rms

120

Total of ports 2, 6, 7

Peak

rms

Operating Temperature

opt

-40 to +85

Storage Temperature

stg

-65 to +150

*: rms = Peak value x

Duty

CAPACITANCE (T

= 25

C, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Capacitance

f = 1 MHz

Output Capacitance

OUT

Pins other than thosemeasured are at 0 V

Input/Output

Capacitance

PD75004, 75006, 75008

MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

= -40 to +85

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation

= Oscillation

1.0

5.0

MHz

frequency(f

voltage range

Oscillation stabiliza- After V

come to

tion time*

MIN. of oscillation
voltage range

Crystal

Oscillation

1.0

4.19

5.0

MHz

frequency (f

Oscillation stabiliza- V

= 4.5 to 6.0 V

tion time*

External Clock

X1 input frequency

1.0

5.0

MHz

X1 input high-,
low-level widths
(t

, t

)

100

500

*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics

of the oscillator circuit. For instruction execution time, refer to AC Characteristics.

2: Time required for oscillation to stabilize after V

has been applied or the STOP mode has been

released.

3: When the oscillation frequency is 4.19 MHz

5.0 MHz, do not select PCC = 0011 as the

instruction execution time: otherwise, one machine cycle is set to less than 0.95

s, falling short

of the rated minimum value of 0.95

Note:

When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted

line in the figures as follows to avoid adverse influences on the wiring capacity:

· Keep the wiring length as short as possible.

· Do not cross the wiring over the other signal lines.

· Do not route the wiring in the vicinity of lines through which a high alternating current flows.

· Always keep the ground point of the capacitor of the osccillator circuit at the same potential

as V

. Do not connect the ground pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

PD74HCU04

PD75004, 75006, 75008

SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

= -40 to +85

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Crystal

Oscillation

32.768

kHz

frequency (f

Oscillation stabiliza- V

= 4.5 to 6.0 V

1.0

tion time*

External Clock

XT1 input frequency

100

kHz

XT1 input high-,
low-level widths

XTH

, t

XTL

)

XT1

XT2

XT1

XT2

Open

*1: Express the characteristcs of the oscillator circuit.

2: Time required for oscillator to stabilize after V

has been applied.

Note: When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line

in the figures as follows to avoid adverse influences on the wiring capacity:

Keep the wiring length as short as possible.

Do not cross the wiring over the other signal lines.

Do not route the wiring in the vicinity of lines through which a high alternating current flows.

Always keep the ground point of the capacitor of the oscillator circuit at the same potential as V

Do not connect the ground pattern through which a high current flows.

Do not extract signals from the oscillation circuit.

The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce

the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise

more easily than the main system clock oscillation circuit. When using the subsystem clock,

therefore, exercise utmost care in wiring the circuit.

PD75004, 75006, 75008

RECOMMENDED OSCILLATION CIRCUIT CONSTANTS

MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (T

= -40 to +85

CSA x.xxMK*

1.00 to 1.99

2.7

CSA x.xxMG093*

2.7

CST x.xxMG093*

2.7

CSA x.xxMGU*

2.7

CST x.xxMGU*

2.7

CSA x.xxMG*

3.0

CST x.xxMG*

3.0

KBR-1000H

1.00

100

2.7

KBR-2.0MS

2.00

2.7

KBR-4.0MS

4.00

2.7

6.0

KBR-5.0M

5.00

3.0

CRHB4.00M

4.00

3.0

C1 (pF)

Murata
Mfg.

Frequency

(MHz)

Product Name

Manufac-
turer

MAX. (V)

MIN. (V)

Recommended Circuit
Constants

Operating
Voltage Range

C2 (pF)

Kyoto
Ceramic

2.00 to 2.44

2.45 to 5.00

2.00 to 5.00

*: x.xx indicates frequency.

HC-6U

1.0 to 2.0

HC-18U

2.0 to 5.0

20 *

2.7

6.0

HC-43U, 49/U

C1 (pF)

Kinseki

Frequency

(MHz)

Product Name

Manufac-
turer

MAX. (V)

MIN. (V)

Recommended Circuit
Constants

Operating
Voltage Range

C2 (pF)

MAIN SYSTEM CLOCK: XTAL (T

= -20 to +70

*: Adjust the oscillation frequency in a range of C

= 15 to 33 pF.

P-3

32.768

18 *

330

2.7

C3 (pF)

Kinseki

Frequency

(MHz)

Product Name

Manufac-
turer

MAX. (V)

MIN. (V)

Recommended Circuit
Constants

Operating
Voltage Range

6.0

SUBSYSTEM CLOCK: XTAL (T

= -10 to +60

C4 (pF)

R (k

)

*: Adjust the oscillation frequency in a range of C3 = 10 to 33 pF.

6.0

Toko

PD75004, 75006, 75008

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

High-Level Input

IH1

Ports 2, 3, 8

0.7V

Voltage

IH2

Ports 0, 1, 6, 7, RESET

0.8V

IH3

Ports 4, 5

w/pull-up resistor

0.7V

Open-drain

0.7V

IH4

X1, X2, XT1

-0.5

Low-level Input

IL1

Ports 2, 3, 4, 5, 8

0.3V

Voltage

IL2

Ports 0, 1, 6, 7, RESET

0.2V

IL3

X1, X2, XT1

0.4

High-Level Output

OH1

= 4.5 to 6.0 V,

-1.0

Voltage

= -1 mA

= -100

-0.5

Low-Level Output

OL1

Ports 4 and 5

Voltage

= 4.5 to 6.0 V

0.4

2.0

= 15 mA

Ports 3
V

= 4.5 to 6.0 V

0.6

2.0

= 15 mA

= 4.5 to 6.0 V

= 1.6 mA

0.4

= 400

0.5

SB0, 1

Pull-up

1 k

0.2V

OL2

Open-drain

= 4.5 to 6.0 V

Pull-up

5 k

0.2V

High-Level Input

LIH1

= V

Other than below

Leakage Current

LIH2

X1, X2, XT1

LIH3

= 10 V

Ports 4, 5

(open-drain)

Low-Level Input

LIL1

= 0 V

Other than below

-3

Leakage Current

LIL2

X1, X2, XT1

-20

High-Level Output

LOH1

OUT

= V

Other than below

Leakage Current

LOH2

OUT

= 10 V

Ports 4, 5

(open-drain)

Low-Level Output

LOL

OUT

= 0 V

-3

Leakage Current

Internal Pull-Up Resistor

Ports 0, 1, 2, 3, 6, 7, 8 V

= 5.0 V

10%

(except P00) V

= 0V

= 3.0 V

10%

300

Ports 4, 5

= 5.0 V

10%

OUT

= V

-2.0 V

= 3.0 V

10%

Ports 0, 2, 3, 6, 7,
8

.....

DC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Ports 0, 2, 3, 4, 5,
6, 7, 8

PD75004, 75006, 75008

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply Current *

DD1

4.19 MHz*

= 5.0 V

10%*

2.5

crystal oscillator

= 3.0 V

10%*

0.35

1.2

DD2

C1 = C2 = 22pF

HALT mode

= 5 V

10%

500

1500

= 3 V

10%

150

450

DD3

32.768 kHz*

= 3 V

10%

DD4

crystal oscillator

HALT mode

= 3 V

10%

DD5

XT1 = 0 V

= 5 V

10%

0.5

STOP mode

= 3 V

10%

0.1

= 25

0.1

*1: Current for the built-in pull-up resistor is not included.

2: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.

3: When operated in the low-speed mode with the PCC set to 0000.

4: Including when the subsystem clock is operated.

5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1011

to stop the main system clock operation.

PD75004, 75006, 75008

AC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU Clock Cycle Time*

w/main system clock

= 4.5 to 6.0 V

0.95

(Minimum Instruction

3.8

Execution Time

w/subsystem clock

114

122

125

= 1 Machine Cycle)

TI0 Input Frequency

= 4.5 to 6.0 V

MHz

275

kHz

TI0 Input High-, Low-

TIH

= 4.5 to 6.0 V

0.48

Level Widths

TIL

1.8

Interrupt Input High-,

INTH

INT0

Low-Level Widths

INTL

INT1, 2, 4

KR0-7

RESET Low-Level Width

RSL

0.5

Supply voltage V

[V]

Cycle time t

[ s]

vs V

(with main system clock)

Operation
guaranteed
range

*1: The CPU clock (

) cycle time (minimum

instruction execution time) is

determined by the oscillation frequency

of the connected oscillator, system clock

control register (SCC), and processor

clock control register (PCC).

The figure on the right is cycle time t

vs. supply voltage V

characteristics

at the main system clock.

2: 2t

or 128/f

depending on the setting

of the interrupt mode register (IM0).

PD75004, 75006, 75008

SERIAL TRANSFER OPERATION

Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output):

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY1

= 4.5 to 6.0 V

1600

3800

SCK High-, Low-Level

KL1

= 4.5 to 6.0 V

KCY1

/2-50

Widths

KH1

KCY1

/2-150

SI Set-Up Time (vs. SCK

)

SIK1

150

SI Hold Time (vs. SCK

) t

KSI1

400

SCK

SO Output

KSO1

= 1 k

= 4.5 to 6.0 V

250

Delay Time

= 100 pF*

1000

TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input):

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY2

= 4.5 to 6.0 V

800

3200

SCK High-, Low-Level

KL2

= 4.5 to 6.0 V

400

Widths

KH2

1600

SI Set-Up Time (vs. SCK

)

SIK2

100

SI Hold Time (vs. SCK

)

KSI2

400

SCK

SO Output

KSO2

= 1 k

, C

= 100 pF*

= 4.5 to 6.0 V

300

Delay Time

1000

*: R and C are load resistance and load capacitance of the SO output line.

PD75004, 75006, 75008

SBI MODE (SCK: internal clock output (master)):

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY3

= 4.5 to 6.0 V

1600

3800

SCK High-, Low-Level

KL3

= 4.5 to 6.0 V

KCY3

/2-50

Widths

KH3

KCY3

/2-150

SB0, 1 Set-Up Time

SIK3

150

(vs. SCK

)

SB0, 1 Hold Time

KSI3

KCY3

(vs. SCK

)

SCK

SB0, 1 Output

KSO3

= 1 k

= 4.5 to 6.0 V

250

Delay Time

= 100 pF*

1000

SCK

SB0, 1

KSB

KCY3

SB0,1

SCK

SBK

KCY3

SB0, 1 Low-Level Width

SBL

KCY3

SB0, 1 High-Level Width

SBH

KCY3

SBI MODE (SCK: external clock input (slave)):

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY4

= 4.5 to 6.0 V

800

3200

SCK High-, Low-Level

KL4

= 4.5 to 6.0 V

400

Widths

KH4

1600

SB0, 1 Set-Up Time

SIK4

100

(vs. SCK

)

SB0, 1 Hold Time

KSI4

KCY4

(vs. SCK

)

SCK

SB0, 1 Output

KSO4

= 1 k

= 4.5 to 6.0 V

300

Delay Time

= 100 pF*

1000

SCK

SB0, 1

KSB

KCY4

SB0,1

SCK

SBK

KCY4

SB0, 1 Low-Level Width

SBL

KCY4

SB0, 1 High-Level Width

SBH

KCY4

*: R and C are load resistance and load capacitance of the SB0 and SB1 output lines.

PD75004, 75006, 75008

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

= 40 to +85

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data Retention Supply

DDDR

2.0

6.0

Voltage

Data Retention Supply

DDDR

= 2.0 V

0.1

Current*

Release Signal Set Time

SREL

Oscillation Stabilization

WAIT

Released by RESET

Wait Time*

Released by interrupt request

*1: Does not include current flowing through internal pull-up resistor

2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent

unstable operation when oscillation is started.

3: Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3

BTM2

BTM1

BTM0

WAIT time ( ): f

= 4.19 MH

(approx. 250 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

DATA RETENTION TIMING (releasing STOP mode by RESET)

STOP mode

Data retention mode

STOP instruction
execution

RESET

DDDR

SREL

WAIT

Operation
mode

Internal reset operation

HALT mode

STOP mode

Data retention mode

STOP instruction execution

DDDR

SREL

WAIT

Operation
mode

HALT mode

Standby release signal

(interrupt request)

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

PD75004, 75006, 75008

f [MHz]

vs f

(V = 5V, T = 25°C)

Main system clock
HALT mode

vs f

(V = 3V, T = 25°C)

0.5

0.4

0.3

0.2

0.1

f [MHz]

High-speed mode
PCC = 0011

Middle-speed
mode
PCC = 0010

Low-speed mode
PCC = 0000

Main system clock
HALT mode

vs I

(T = 25°C)

(Port 0)

V [V]

V = 5 V

V = 4 V

V = 3 V

V = 2.7 V

vs I

(Port 2, 6, 7)

[mA]

V = 6 V

[mA]

V = 5 V

V = 4 V

V = 2.7 V

V = 3 V

V [V]

(T = 25°C)

High-speed mode
PCC = 0011

Middle-speed
mode
PCC = 0010

Low-speed mode
PCC = 0000

[mA]

V =
6 V

[mA]

PD75004, 75006, 75008

12. PACKAGE DRAWINGS

42PIN PLASTIC SHRINK DIP (600 mil)

ITEM MILLIMETERS

INCHES

39.13 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

1.78 MAX.

0.17

15.24 (T.P.)

5.08 MAX.

0.9 MIN.

1.541 MAX.

0.070 MAX.

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.600 (T.P.)

0.007

0.070 (T.P.)

P42C-70-600A-1

NOTES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

0.50±0.10

0.020

0.25

0.010

+0.10

0.05

0~15°

+0.004

0.003

+0.004

0.005

13.2

0.520

2) Item "K" to center of leads when formed parallel.

PD75004, 75006, 75008

44 PIN PLASTIC QFP ( 10)

NOTE

Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.

P44GB-80-3B4-3

ITEM

MILLIMETERS

INCHES

13.6±0.4

10.0±0.2

0.535

0.394

13.6±0.4

0.535

1.0

0.039

1.0

0.039

0.35±0.10

0.014

0.15

0.006

0.8 (T.P.)

0.031 (T.P)

1.8±0.2

0.071

0.8±0.2

0.031

0.15

0.006

0.10

0.004

2.7

0.106

0.1±0.1

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

+0.017

0.016

+0.008

0.009

+0.008

0.009

+0.017

0.016

+0.004

0.005

+0.008

0.009

+0.009

0.008

+0.004

0.003

detail of lead end

+0.10

0.05

PD75004, 75006, 75008

13. RECOMMENDED SOLDERING CONDITIONS

It is recommended that

PD75004, 75006, and 75008 be soldered under the following conditions.

For details on the recommended soldering conditions, refer to Information Document "Semiconductor

Devices Mounting Manual" (IEI-616).

The soldering methods and conditions are not listed here, consult NEC.

Table 13-1 Soldering Conditions

PD75004GB - xxx - 3B4: 44-pin plastic QFP (

10 mm)

PD75006GB - xxx - 3B4: 44-pin plastic QFP (

10 mm)

PD75008GB - xxx - 3B4: 44-pin plastic QFP (

10 mm)

Soldering Method

Soldering Conditions

Infrared Reflow

Package peak temperature: 230

C, time: 30 seconds max.

IR30-107-1

(210

C min.), number of times: 1, number of days: 7 days*,

(afterwards, 10 hours of prebaking at 125

C is required.)

VPS

Package peak temperature: 215

C, time: 40 seconds max.

VP15-107-1

(200

C min.), number of times: 1, number of days: 7 days*,

(afterwards, 10 hours of prebaking at 125

C is required.)

Wave Soldering

Soldering bath temperature: 260

C max., time: 10 seconds

WS60-00-1

max., number of times: 1, number of days: 7 days*,
(afterwards, 10 hours of prebaking at 125

C is required.)

pre-heating temperature: 120

C max. (package surface

temperature)

Pin Partial Heating

Pin temperature: 300

C max.,

time: 3 seconds max. (per side)

This means the number of days after unpacking the dry pack. Storage conditions are 25

C and 65%

RH max.

Caution: Do not use two or more soldering methods in combination (except the pin partial heating

method).

Table 13-2 Soldering Conditions of Through-Hole Type

PD75004CU - xxx : 42-pin plastic shrink DIP (600 mil)

PD75006CU - xxx : 42-pin plastic shrink DIP (600 mil)

PD75008CU - xxx : 42-pin plastic shrink DIP (600 mil)

Symbol for Recommended

Condition

Soldering Method

Soldering Conditions

Wave Soldering

Soldering bath temperature: 260

C max., Time: 10 seconds max.

(Only for lead part)

Pin Partial Heating

Pin temperature: 260

C max., Time: 10 seconds max.

Notice

A model that can be soldered under the more stringent conditions (infrared reflow peak temperature:

235

C, number of times: 2, and an extended number of days) is also available.

For details, consult NEC.

PD75004, 75006, 75008

APPENDIX A.

DEVELOPMENT TOOLS

The following development support tools are readily available to support development of systems using

PD75008:

Hardware

IE-75000-R *

In-circuit emulator for 75X series

IE-75001-R

IE-75000-R-EM *

Emulation board for IE-75000-R and IE-75001-R

EP-75008CU/GB-R

Emulation prove for

PD75004CU/GB, 75006CU/GB, 75008CU/GB

PG-1500

PROM programmer

PA-75P008CU

PROM programmer adapter solely used for

PD75P008CU/GB.

It is connected to PG-1500.

Software

IE Control Program

PG-1500 Controller

RA75X Relocatable
Assembler

*1: Maintenance product

2: Not provided with IE-75001-R.

3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function.

Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).

Host machine
· PC-9800 series (MS-DOS

Ver.3.30 to Ver.5.00A*

)

· IBM PC/AT

(PC DOS

Ver.3.1)

PD75004, 75006, 75008

STATIC ELECTRICITY (ALL MOS DEVICES)

Exercise care so that MOS devices are not adversely influenced by static electricity while being

handled.

The insulation of the gates of the MOS device may be destroyed by a strong static charge.

Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,

or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use

grounding when assembling the MOS device system. Do not leave the MOS device on a plastic

plate and do not touch the pins of the device.

Handle boards on which MOS devices are mounted similarly .

PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)

Fix the input level of CMOS devices.

Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its

input pin, intermediate level input may be generated due to noise, and an inrush current may flow

through the device, causing the device to malfunction. Therefore, fix the input level of the device

by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an

output pin (whose timing is not specified), each pin should be connected to V

or GND through

a resistor.

Refer to "Processing of Unused Pins" in the documents of each devices.

STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)

The initial status of MOS devices is undefined upon power application.

Since the characteristics of an MOS device are determined by the quantity of injection at the

molecular level, the initial status of the device is not controlled during the production process. The

output status of pins, I/O setting, and register contents upon power application are not guaranteed.

However, the items defined for reset operation and mode setting are subject to guarantee after

the respective operations have been executed.

When using a device with a reset function, be sure to reset the device after power application.

GENERAL NOTES ON CMOS DEVICES

PD75004, 75006, 75008

[MEMO]

No p

art of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which

may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other

intellectual property rights of third parties b y or arising from use of a device described herein or any

other liability arising from use of such device. No license, either express, implied or otherwise, is granted

under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,

nuclear reactor control systems and life support systems. If customers intend to use NEC devices for

above applications or they intend to use "Standard" quality grade NEC devices for the applications not

intended by NEC, please contact our sales people in advance.

Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special:

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime system, etc.

MS-DOS is a trademark of Microsoft Corporation.

PC/AT and PC DOS are trademarks of IBM Corporation.

M4 92.6

Document Outline

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