DESCRIPTION

PD75108 is a 4-bit single-chip microcomputer integrating timer/event counters, serial interface, and vector

interrupt function, in addition to a CPU, ROM, RAM, and I/O ports, on a single chip. Operating at high speeds,

the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation

instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with

peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog

inputs,

PD75108 is suitable for controlling such systems as VTRs, acoustic products, button telephones, radio

communications equipment, and printers. A pin-compatible EPROM model is also available for evaluation of

system development and small-scale production of application systems.

Detailed functions are described in the following user's manual. Be sure to read it for designing.

PD751XX Series User's Manual: IEM-922

FEATURES

Internal memory

· Program memory (ROM)

: 8068

8 bits (

PD75108)

: 6016

8 bits (

PD75106)

: 4096

8 bits (

PD75104)

· Data memory (RAM)

: 512

4 bits (

PD75108)

: 320

4 bits (

PD75106, 75104)

New architecture "75X series" rivaling 8-bit microcomputers

43 systematically organized instructions

· A wealth of bit manipulation instructions

· 8-bit data transfer, compare, operation, increment, and decrement instructions

· 1-byte relative branch instructions

· GETI instruction executing 2-/3-byte instruction with one byte

High speed. Minimum instruction execution time: 0.95

s (at 4.19 MHz), 5 V

Power-saving, instruction time change function: 0.95

s/1.91

s/15.3

s (at 4.19 MHz)

I/O port pins as many as 58

Three channels of 8-bit timers

8-bit serial interface

Multiplexed vector interrupt function

Model with PROM is available:

PD75P108B (One-time PROM, EPROM)

NEC Corporation 1989

Document No.

IC-2520B

(O. D. No.

IC-6906B)

Date Published

January 1994 P

Printed in Japan

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75104, 75106, 75108

4-BIT SINGLE-CHIP MICROCOMPUTER

The mark 5 shows major revised points.

The information in this document is subject to change without notice.

Unless there are differences among

PD75104, 75106, and 75108 functions,

PD75108 is treated as the

representative model throughout this manual.

PD75104, 75106, 75108

ORDERING INFORMATION

Part Number

Package

Quality Grade

PD75104CW-xxx

64-pin plastic shrink DIP (750 mil)

Standard

PD75104GF-xxx-3BE

64-pin plastic QFP (14

20 mm)

Standard

PD75106CW-xxx

64-pin plastic shrink DIP (750 mil)

Standard

PD75106GF-xxx-3BE

64-pin plastic QFP (14

20 mm)

Standard

PD75108CW-xxx

64-pin plastic shrink DIP (750 mil)

Standard

PD75108GF-xxx-3BE

64-pin plastic QFP (14

20 mm)

Standard

Remarks: xxx is ROM code number.

Please refer to "Quality Grade on NEC Semiconductor Devices" (Document Number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

PD75104, 75106, 75108

FUNCTIONAL OUTLINE

Item

Specifications

Number of Basic Instructions

Minimum Instruction

Changeable in three steps: 0.95

s, 1.91

s, and 15.3

s at 4.19 MHz

Execution Time

ROM

8064

8 bits (

PD75108), 6016

8 bits (

PD75106), 4096

8 bits (

PD75104)

RAM

512

4 bits (

PD75108), 320

4 bits (

PD75106, 75104)

General-Purpose Register

4 bits

4 banks (memory mapped)

Three accumulators selectable according to the bit length of manipulated data:

· 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA)

58 port pins

· CMOS input pins: 10

I/O Port

· CMOS I/O pins (can directly drive LEDs): 32

· Medium voltage N-ch open-drain I/O pins: 12

(can directly drive LEDs. Pull-up resistor can be connected to each bit)

· Comparator input pins (4-bit accuracy): 4

· 8-bit timer/event counter

Timer/Counter

· 8-bit basic interval timer (can be used as watchdog timer)

· 8 bits

Serial Interface

· LSB first/MSB first mode selectable

· Two transfer modes (transfer/reception and reception only modes)

Vector Interrupt

External: 3, Internal: 4

Test Input

External: 2

Standby

· STOP and HALT modes

· Various bit manipulation instructions (set, reset, test, Boolean operation)

Instruction Set

· 8-bit data transfer, compare, operation, increment, and decrement

· 1-byte relative branch instructions

· GETI instruction constituting 2 or 3-byte instruction with 1 byte

· Power-ON reset circuit (mask option)

Others

· Bit manipulation memory (bit sequential buffer: 16 bits)

Package

· 64-pin plastic shrink DIP (750 mil)

· 64-pin plastic QFP (14

20 mm)

Internal Memory

Accumulator

PD75104, 75106, 75108

CONTENTS

PIN CONFIGURATION (TOP VIEW) ...............................................................................................

BLOCK DIAGRAM ...........................................................................................................................

PIN FUNCTIONS ..............................................................................................................................

3.1

PORT PINS .............................................................................................................................................

3.2

PINS OTHER THAN PORTS .................................................................................................................

3.3

PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................

3.4

RECOMMENDED PROCESSING OF UNUSED PINS ..........................................................................

3.5

NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................

MEMORY CONFIGURATION ..........................................................................................................

PERIPHERAL HARDWARE FUNCTIONS ........................................................................................

5.1

PORTS ....................................................................................................................................................

5.2

CLOCK GENERATOR CIRCUIT ............................................................................................................

5.3

CLOCK OUTPUT CIRCUIT ....................................................................................................................

5.4

BASIC INTERVAL TIMER .....................................................................................................................

5.5

TIMER/EVENT COUNTER .....................................................................................................................

5.6

SERIAL INTERFACE ..............................................................................................................................

5.7

PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ....................................................

5.8

BIT SEQUENTIAL BUFFER .... 16 BITS ...............................................................................................

5.9

POWER-ON FLAG (MASK OPTION) ....................................................................................................

INTERRUPT FUNCTIONS ................................................................................................................

STANDBY FUNCTIONS ..................................................................................................................

RESET FUNCTION ...........................................................................................................................

INSTRUCTION SET .........................................................................................................................

PD75104, 75106, 75108

10. APPLICATION EXAMPLES ..............................................................................................................

10.1

VTR SYSTEM CONTROLLER ...............................................................................................................

10.2

VTR CAMERA ........................................................................................................................................

10.3

COMPACT DISC PLAYER .....................................................................................................................

10.4

AUTOMOBILE APPLICATIONS (TRIP COMPUTER) ............................................................................

10.5

PUSHBUTTON TELEPHONE ................................................................................................................

10.6

DISPLAY PAGER ...................................................................................................................................

10.7

PLAIN PAPER COPIER (PPC) ...............................................................................................................

10.8

PRINTER CONTROLLER .......................................................................................................................

11. MASK OPTION SELECTION ...........................................................................................................

12. ELECTRICAL SPECIFICATIONS ......................................................................................................

13. CHARACTERISTIC DATA ................................................................................................................

14. PACKAGE DRAWINGS ...................................................................................................................

15. RECOMMENDED SOLDERING CONDITIONS ...............................................................................

APPENDIX A.

FUNCTIONAL DIFFERENCES AMONG PRODUCTS IN

PD751XX SERIES .........

APPENDIX B.

DEVELOPMENT TOOLS ..............................................................................................

APPENDIX C.

RELATED DOCUMENTS ..............................................................................................

PD75104, 75106, 75108

PIN CONFIGURATION (Top View)

· 64-Pin Plastic Shrink DIP (750 mil)

P13/INT3

PD75104CW-

PD75106CW-

PD75108CW-

×××

P12/INT2
P11/INT1
P10/INT0

PTH03
PTH02
PTH01
PTH00

TI0
TI1

P23

P22/PCL

2
3
4
5
6
7
8
9

10
11
12

P21 PTO1

P20 PTO0

P90

P91

P92

P93

P80

P81

P82

P83

P70

P71

P72

P73

P60

P03/SI

P61

P02/SO

P62

P01/SCK

P63

P00/INT4

P123

P122

RESET

P121

P50

P120

P51

P133

P52

P132

P53

P131

P40

P130

P41

P143

P42

P142

P43

P141

P30

P140

P31

P32

P33

P131

P41

P42

P43

P30

P31

P32

P33

P140

P141

P142

P143

P130

63 62 61 60 59 58 57 56 55 54 53 52

20 21 22 23 24 25 26 27 28 29 30 31 32

P81

P80

P93

P92

P91

P90

P13/INT3

P12/INT2

P11/INT1

P10/INT0

PTH03

PTH02

PD75104GF-

PD75106GF-

PD75108GF-

×××

-3BE

P132

P40

P133

P53

P120

P52

P121

P51

P122

P50

P123

RESET

P00/INT4

P01/SCK

P02/SO

P63

P03/SI

P62

P20/PTO0

P61

P21/PTO1

P60

P22/PCL

P73

P23

P72

TI1

P71

TI0

P70

PTH00

P83

PTH01

P82

· 64-Pin Plastic QFP (14

20 mm)

PD75104,

75106,

75108

BLOCK DIAGRAM

TI0

PTO0/P20

BASIC
INTERVAL
TIMER

INTBT

PROGRAM
COUNTER*

ALU

SP (8)

BANK

GENERAL REG.

DECODE

AND

CONTROL

ROM
PROGRAM
MEMORY
8064 8BITS
: PD75108
6016 8BITS
: PD75106
4096 8BITS
: PD75104

µ
µ
µ

RAM
DATA MEMORY
512 4BITS
: PD75108
320 4BITS
: PD75106, 75104

µ
µ

f /2

CPU CLOCK

PCL/P22

RESET

CLOCK
OUTPUT
CONTROL

CLOCK
DIVIDER

CLOCK
GENERATOR

STAND BY
CONTROL

TIMER/EVENT
COUNTER
#0

TIMER/EVENT
COUNTER
#1

SERIAL
INTERFACE

INTERRUPT
CONTROL

PROGRAM-
MABLE
THRESHOLD
PORT #0

TI1

PTO1/P21

SI/P03

SO/P02

SCK/P01

INT0/P10

INT1/P11

INT2/P12

INT3/P13

INT4/P00

PTH00-PTH03

BIT SEQ.
BUFFER (16)

PORT 0

P00 - P03

P10 - P13

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 8

PORT 9

PORT 12

PORT 13

PORT 14

P20 - P23

P30 - P33

P40 - P43

P50 - P53

P60 - P63

P70 - P73

P80 - P83

P90 - P93

P120 - P123

P130 - P133

P140 - P143

*: 13 bits: PD75106, 75108

12 bits: PD75104

INTT0

INTT1

INTSIO

PD75104, 75106, 75108

PIN FUNCTIONS

3.1

PORT PINS

I/O

Pin Name

I/O

Shared with:

Function

At Reset

Circuit

TYPE*

P00

Input

INT4

P01

I/O

SCK

4-bit input port (PORT 0)

Input

P02

I/O

P03

Input

P10

INT0

P11

INT1

Input

4-bit input port (PORT 1)

Input

P12

INT2

P13

INT3

P20*

PTO0

P21*

PTO1

I/O

4-bit I/O port (PORT 2)

Input

P22*

PCL

P23*

4-bit programmable I/O port (PORT 3)

P30-P33*

I/O

Input

Can be specified for input or output bitwise.

P40-P43*

I/O

4-bit I/O port (PORT 4)

Input

P50-P53*

I/O

4-bit I/O port (PORT 5)

Input

4-bit programmable I/O port (PORT 6)

P60-P63*

I/O

Input

Can be specified for input or output bitwise.

P70-P73*

I/O

4-bit I/O port (PORT 7)

Input

P80-P83*

I/O

4-bit I/O port (PORT 8)

Input

P90-P93*

I/O

4-bit I/O port (PORT 9)

Input

4-bit N-ch open-drain I/O port (PORT 12)

Built-in pull-up resistors can be specified in bit

P120-P123*

I/O

units by mask option.

Open-drain withstanding voltage: 12 V

4-bit N-ch open-drain I/O port (PORT 13)

Built-in pull-up resistors can be specified in bit

P130-P133*

I/O

units by mask option.

Open-drain withstanding voltage: 12 V

4-bit N-ch open-drain I/O port (PORT 14)

Built-in pull-up resistors can be specified in bit

P140-P143*

I/O

Input*

units by mask option.

Open-drain withstanding voltage: 12 V

*1: Circles indicate Schmitt trigger input pins.

2: With drain open: high impedance

With pull-up resistor connected: high level

3: Can directly drive LEDs.

8-Bit

I/O

Input*

PD75104, 75106, 75108

3.2

PINS OTHER THAN PORTS

I/O

Pin Name

I/O

Shared with:

Function

At Reset

Circuit

TYPE*

PTH00-PTH03

Input

4-bit variable threshold voltage analog input port

TI0

External event pulse inputs for timer/event counter.

Input

Also serves as edge-detected vector interrupt input.

TI1

1-bit input also possible.

PTO0

P20

I/O

Outputs for timer/event counter

Input

PTO1

P21

SCK

I/O

P01

Serial clock I/O

Input

I/O

P02

Serial data output

Input

P03

Serial data input

Input

Edge-detected vectored interrupt input (both rising and

INT4

Input

P00

Input

falling edges detected)

INT0

P10

Edge-detected vectored interrupt inputs (valid

Input

INT1

P11

edge selectable)

INT2

P12

Input

Edge-detected testable inputs (rising edge detected)

Input

INT3

P13

PCL

I/O

P22

Clock output

Input

Crystal/ceramic system clock oscillator connections.

X1, X2

Input external clock to X1, and signal in reverse phase

with X1 to X2.

RESET

Input

System reset input (low level active type)

NC*

No Connection

Positive power supply

GND

*1: Circles indicate Schmitt trigger input pins.

2: Connect the NC pin directly to the V

pin when

PD75P108B and a printed circuit board are shared.

PD75104, 75106, 75108

3.3

PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the

PD75108.

TYPE A

TYPE E

TYPE B

TYPE F

Input buffer of CMOS standard

Pch

Nch

Schmitt trigger input with hysteresis characteristics

data

output
disable

Type D

Type A

IN/OUT

TYPE D

TYPE M

data

output
disable

Type D

Type B

IN/OUT

data

output
disable

OUT

Push pull output that can be set in a output

high impedance state (both P ch and N ch are off)

P-ch

N-ch

I/O circuit consisting of Type D push-pull output circuit
and Type A input buffer

I/O circuit consisting of Type D push-pull output and Type
B Schmitt trigger input

P.U.R.

(mask option)

IN/OUT

data

output

disable

N-ch
(+12 V
withstand)

Medium-voltage input
buffer (+12 V withstand)
P.U.R.: Pull-Up Resistor

PD75104, 75106, 75108

TYPE N

Comparator

V (threshold voltage)

REF

3.4

RECOMMENDED PROCESSING OF UNUSED PINS

Recommended connections

PTH00-PTH03

TI0

Connect to V

or V

TI1

P00

Connect to V

P01-P03

Connect to V

or V

P10-P13

Connect to V

P20-P23

P30-P33

P40-P43

P50-P53

P60-P63

Input: Connect to V

or V

P70-P73

P80-P83

Output: Open

P90-P93

P120-P123

P130-P133

P140-P143

RESET*

Connect to V

NC*

Open

*1: Connect this pin to the V

pin only when a power-ON reset circuit

is provided as a mask option.

2: Connect the NC pin to the V

pin when

PD75P108 and a printed

circuit board are shared.

PD75104, 75106, 75108

3.5

NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode,

in which the internal fuctions of the

PD75108 are tested (solely used for IC tests), is provided to the P00/INT4

and RESET pins.

If a voltage exceeding V

is applied to either of these pins, the

PD75108 is put into test mode. Therefore,

even when the

PD75108 is in normal operation, if noise exceeding the V

is input into any of these pins, the

PD75108 will enter the test mode, and this will cause problems for normal operation.

As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up

and the above montioned problem may occur.

Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot

be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

Connect a capacitor across P00/INT4 and

RESET , and V

Connect a diode across P00/INT4 and

RESET , and V

P00/INT4, RESET

PD75104, 75106, 75108

MEMORY CONFIGURATION

Program memory (ROM) ... 8064

8 bits (0000H-1F7FH) :

PD75108

... 6016

8 bits (0000H-177FH) :

PD75106

... 4096

8 bits (0000H-0FFFH) :

PD75104

· 0000H, 0001H :

Vector table to which address from which program is started is written after reset

· 0002H-000BH: Vector table to which address from which program is started is written after interrupt

· 0020H-007FH : Table area referenced by GETI instruction

Data memory (RAM)

· Data area ....512

4 bits (000H1FFH) :

PD75108

320

4 bits (000H-13FH) :

PD75106, 75104

· Peripheral hardware area .... 128

4 bits (F80HFFFH)

PD75104, 75106, 75108

(a)

PD75108

MBE RBE

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0/INT1 start address (upper 5 bits)

INT0/INT1 start address (lower 8 bits)

INTSIO start address (upper 5 bits)

INTSIO start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (upper 5 bits)

INTT1 start address (lower 8 bits)

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

07FFH
0800H

0FFFH
1000H

1F7FH

GETI instruction reference table

BRCB

! caddr

instruction

branch

address

CALLF
! faddr

instruction

entry

address

BR ! addr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(15 to 1,
+2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

BRCB ! caddr

instruction

branch address

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC

with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

Fig. 4-1 Program Memory Map (1/3)

PD75104, 75106, 75108

(b)

PD75106

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC

with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

Fig. 4-1 Program Memory Map (2/3)

MBE RBE

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0/INT1 start address (upper 5 bits)

INT0/INT1 start address (lower 8 bits)

INTSIO start address (upper 5 bits)

INTSIO start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (upper 5 bits)

INTT1 start address (lower 8 bits)

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

07FFH
0800H

0FFFH
1000H

177FH

GETI instruction reference table

BRCB

! caddr

instruction

branch

address

CALLF
! faddr

instruction

entry

address

BR ! addr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(15 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Address

BRCB ! caddr

instruction

branch address

PD75104, 75106, 75108

(c)

PD75106

MBE RBE

Internal reset start address (upper 4 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 4 bits)

INTBT/INT4 start address (lower 8 bits)

INT0/INT1 start address (upper 4 bits)

INT0/INT1 start address (lower 8 bits)

INTSIO start address (upper 4 bits)

INTSIO start address (lower 8 bits)

INTT0 start address (upper 4 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (upper 4 bits)

INTT1 start address (lower 8 bits)

000H

002H

004H

006H

008H

00AH

020H

07FH
080H

7FFH
800H

FFFH

GETI instruction reference table

CALLF
! faddr

instruction

entry

address

BRCB ! caddr

instruction

branch address

CALL ! addr

instruction
subroutine

entry address

Address

BR $addr

instruction

relational

branch address

(15 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC

with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

Fig. 4-1 Program Memory Map (3/3)

PD75104, 75106, 75108

PERIPHERAL HARDWARE FUNCTIONS

5.1

PORTS

I/O ports are classified into the following 3 kinds:

CMOS input (PORT0, 1)

CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32

N-ch open-drain input/output (PORT12, 13, 14)

: 12

Total

: 52

PORT0

PORT1

PORT3

PORT6

PORT2

PORT4

PORT5

PORT7

PORT8

PORT9

PORT12

PORT13

PORT14

Function

4-bit input

4-bit I/O*

(N-ch open- drain.

12V)

Table 5-1 Port Function

Operation and Features

Can always be read or tested regardless of opera-

tion mode of shared pin

Can be set in input or output mode bitwise

Can be set in input or output mode in units of 4 bits.

Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs

to input or output 8-bit data

Can be set in input or output mode in units of 4 bits.

Ports 12 and 13 can be used in pairs to input or

output 8-bit data

Port

(Symbol)

Remarks

Shared with SI, SO, SCK, and

INT0 to 4 pins

Port 2 pins are shared with

PTO0, PTO1, and PCL pins

Each bit can be connected to

pull-up resistor by mask option

*: Can directly drive LED.

PD75104, 75106, 75108

5.2

CLOCK GENERATOR CIRCUIT

The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and

peripheral hardware. In addition, this circuit can change the instruction execution time.

· 0.95

s/1.91

s/15.3

s (operating at 4.19 MHz)

· Basic interval timer (BT)
· Clock output circuit
· Timer/event counter
· Serial interface

f or

1/2 1/16

1/8 to 1/4096

Frequency civider

System clock
generator
circuit

Oscillation
stops

Selector

1/4

Frequency
divider

· CPU
· Clock output
circuit

HALT F/F

PCC

PCC0

PCC1

PCC2

PCC3

Internal bus

HALT*

STOP*

Clears
PCC2,
PCC3

STOP F/F

Wait release signal from BT

RES (internal reset) signal

Standby release signal from
interrupt control circuit

*: Execution of the instruction

Remarks 1: f

= Crystal/ceramic oscillator

2: f

= External clock frequency

3: PCC: Processor clock control register

4: One clock cycle (t

) of

is one machine cycle of an instruction. For t

, refer to AC

characteristics in 12. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

PD75104, 75106, 75108

5.4

BASIC INTERVAL TIMER

The basic interval timer has these functions:

Interval timer operation which generates a reference time interrupt

Watchdog timer application which detects a program runaway

Selects the wait time for releasing the standby mode and counts the wait time

Reads out the count value

Remarks : *: Instruction execution

Fig. 5-3 Basic Interval Timer Configuration

From the
clock generator

MPX

Clear

Basic interval timer

(8-bit frequency divider circuit)

Clear

Set
signal

interrupt

request flag

IRQBT

Wait release signal
for standby release

Vector
interrupt
request
signal

Internal bus

BTM3

BTM2

BTM1

BTM0

BTM

SET1*

5.5

TIMER/EVENT COUNTER

PD75108 contains two channels of timer/event counters.

These two channels are almost identical in terms of configuration and function except the count pulse (CP) that

can be selected and the function to supply clocks to the serial interface.

The functions of the timer/event counter include:

· Programmable interval timer operation

· Output of square wave at an arbitrary frequency to PTOn pin

· Event counter operation

· Input of TIn pin signal as external interrupt input signal

· Dividing TIn pin input by N to output to PTOn pin (frequency divider operation)

· Supply of serial shift clock to serial interface circuit (channel 0 only)

· Reading counting status

PD75104, 75106, 75108

5.7

PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT)

PD75108 is equipped with a 4-bit analog input port (consisting of PTH00 to PTH03 pins) whose threshold voltage

is programmable.

This programmable threshold port is configured as shown in Figure 5-6.

The threshold voltage (V

REF

) can be changed in 16 steps (V

0.5/16 V

15.5/16), and analog signals can be

directly input.

When V

REF

is set to V

7.5/16, the programmable threshold port can also be used as a digital signal input port.

Input buffer

PTH00

PTH01

PTH02

PTH03

Internal bus

Programmable threshold port

input latch (4)

Operates
/stops

PTH0

MPX

PTHM7

PTHM6

PTHM5

PTHM4

PTHM3

PTHM2

PTHM1

PTHM0

PTHM

1
2

REF

Fig. 5-6 Programmable Threshold Port Configuration

PD75104, 75106, 75108

5.8

BIT SEQUENTIAL BUFFER .... 16 BITS

The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this

buffer is very useful for processing long data in bit units.

Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.

Fig. 5-7 Bit Sequential Buffer Format

5.9

POWER-ON FLAG (MASK OPTION)

The power-ON flag (PONF) is set to only when the power-ON reset circuit operates and power-ON reset signal

has been generated (see Fig. 8-1).

The PONF flag is mapped at bit 0 of memory space address FD1H, and can be manipulated by a bit manipulation

instruction. However, it cannot be set by the SET1 instruction.

6. INTERRUPT FUNCTIONS

The

PD75108 has 7 different interrupt sources and can perform multiplexed interrupt processing with

priority assigned.

In addition to that, the

PD75108 is also provided with two types of edge detection testable inputs.

The interrupt control circuit of the

PD75108 has these functions:

Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by

using the interrupt enable flag (IExxx) and interrupt master enable flag (IME).

The interrupt start address can be arbitrarily set.

Multiplexed interrupt function that can specify priority by the interrupt priority selector register (IPS).

Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of

software).

Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).

Address bit

Symbol

L register

L = F

L = C L = B

L = 8 L = 7

L = 4 L = 3

L = 0

BSB3

BSB2

BSB1

BSB0

DECS L

INCS L

FC3H

FC2H

FC1H

FC0H

PD75104, 75106, 75108

7. STANDBY FUNCTIONS

The

PD75108 has two different standby modes (STOP mode and HALT mode) to reduce the power

consumption of the microcomputer chip while waiting for program execution.

Table 7-1 Each Status in Standby Mode

Setting Instruction

STOP instruction

HALT instruction

Clock Generator

circuit

Basic Interval

Timer

Operates (sets IRQBT at reference

time intervals)

Operates only when input of external

SCK or output of TO0 is selected as

serial clock (where external TI0 is input

to timer/event counter 0)

Operates when serial clock other

than

is specified

Operates

Stops

Serial Interface

Clock output

STOP Mode

HALT Mode

Clock oscillation stops

Only CPU clock

is stopped

Operation

Status

Timer/Event

Counter

circuit

Operates only when TIn pin input

signal is specified as count clock

Operates when clock other than CPU

clock

is used

Stops

CPU

Stops

Release Signal

Interrupt request signal enabled by interrupt enable flag, or RESET input

Stops

PD75104, 75106, 75108

RESET FUNCTION

The reset ( RES ) signal generator circuit is configured as shown in Figure 8-1.

RESET

SWB

SWA

Power-ON
reset
generator
circuit

Internal reset signal
(RES)

Power-ON
flag (PONF)

Execution of bit
manipulation
instruction*

Internal bus

*: PONF cannot be set to 1 by SET1 instruction.

Fig. 8-1 Reset Signal Generator Circuit

The Power-ON reset generator circuit generates an internal reset signal when the supply voltage rises. This pulse

can be used in three ways by specifying a mask option through SWA and SWB shown in Fig. 8-1. (Refer to 11. MASK

OPTION SELECTION.)

The reset operations performed by the Power-On reset circuit and the RESET input signal are illustrated in Figs.

8-2 and 8-3, respectively.

Supply voltage

0 V

Internal reset signal
(RES)

Wait*

(approx. 31.3 ms: 4.19 MHz)

HALT mode

Operation mode

Internal reset operation

*: The wait time does not include the time required after the RES signal has been generated until the

oscillation starts.

Fig. 8-2 Reset by Power-ON Reset Circuit

PD75104, 75106, 75108

Table 8-1 Hardware Device Status After Reset

RESET input during

Power-ON Reset or RESET

standby mode

Input during Operation

Lower 4 bits of program

memory address 000H are

Program Counter (PC)

set to PC

12-8

and

set to PC

12-8

and

contents of address 001H

are set to PC

7-0

are set to PC

7-0

Carry Flag (CY)

Retained

Undefined

Skip Flags (SK0-SK2)

PSW

Interrupt Status Flags (IST0, 1)

Bit 6 of program memory

Bank Enable Flags (MBE, RBE)

address 000H is set in

RBE, and bit 7 is set in

MBE.

Stack Pointer (SP)

Undefined

Data Memory (RAM)

Retained*

Undefined

General-Purpose Registers (X,A,H,L,D,E,B,C)

Retained

Undefined

Bank Selector Registers (MBS, RBS)

0, 0

Counter (BT)

Undefined

Mode Register (BTM)

Counter (Tn)

Modulo Register (TMODn)

FFH

Mode Register (TMn)

TOEn, TOFn

0, 0

Serial Interface

Shift Register (SIO)

Retained

Undefined

Mode Register (SIOM)

Processor Clock Control Register

(PCC)

Clock Output Mode Register

(CLOM)

Interrupt Request Rlags

Reset (0)

(IRQxxx)

Interrupt Enable Flags (IExxx)

Interrupt

Priority Selector Register (IPS)

INT0, 1 Mode Registers

0, 0

(IM0, IM1)

Output Buffer

OFF

Digital Port

Output Latch

Cleared (0)

I/O Mode Registers

(PMGA, PMGB, PMGC)

PTH00-PTH03 Input Latches

Undefined

Analog Port

Mode Register (PTHM)

Power-ON Flag (PONF)

Retained

1 or undefined*

Bit Sequential Buffer (BSB0-BSB3)

*1: PC

11-8

for

PD75104

2: Power-ON reset: 1

RESET input during operation: undefined

Note: Data at data memory addresses 0F8H to 0FDH become undefined when the RESET signal has been input.

Hardware

Basic interval timer

Timer/Event Counter

(n = 0, 1)

Clock Generator Circuit,

Clock Output Circuit

PD75104, 75106, 75108

INSTRUCTION SET

(1)

Operand representation and description

Describe one or more operands in the operand field of each instruction according to the operand

representation and description methods of the instruction (for details, refer to RA75X Assembler Package

User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from

several operands. The uppercase characters, +, and are keywords and must be described as is.

Describe an appropriate numeric value or label as immediate data.

The symbols in the register and flag symbols can be described as labels in the places of mem, fmem,

pmem, and bit (for details, refer to

PD751XX Series User`s Manual (IEM-922)). However, fmem and pmem

restricts the label that can be described.

Representation

Description

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label*

bit

2-bit immediate data or label

fmem

FB0H to FBFH,FF0H to FFFH immediate data or label

pmem

FC0H to FFFH immediate data or label

PD75104

0000H to 0FFFH immediate data or label

addr

PD75106

0000H to 177FH immediate data or label

PD75108

0000H to 1F7FH immediate data or label

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H to 7FH immediate data (where bit0 = 0) or label

PORTn

PORT0 - PORT9, PORT12 - PORT14

IExxx

IEBT, IESIO, IET0, IET1, IE0 - IE4

RBn

RB0 - RB3

MBn

MB0, MB1, MB15

*: Only even address can be described as mem for 8-bit data processing.

PD75104, 75106, 75108

(2)

Legend of operation field

: A register; 4-bit accumulator

: B register; 4-bit accumulator

: C register; 4-bit accumulator

: D register; 4-bit accumulator

: E register; 4-bit accumulator

: H register; 4-bit accumulator

: L register; 4-bit accumulator

: X register; 4-bit accumulator

: Register pair (XA); 8-bit accumulator

: Register pair (BC); 8-bit accumulator

: Register pair (DE); 8-bit accumulator

: Register pair (HL); 8-bit accumulator

XA'

: Expansion register pair (XA')

BC'

: Expansion register pair (BC')

DE'

: Expansion register pair (DE')

HL'

: Expansion register pair (HL')

: Program counter

: Stack pointer

: Carry flag; or bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn : Port n (n = 0 - 9, 12 - 14)

IME

: Interrupt mask enable flag

IPS

: Interrupt priority selection register

IExxx

: Interrupt enable flag

RBS

: Register bank selection register

MBS

: Memory bank selection register

PCC

: Processor clock control register

: Delimiter of address and bit

(xx)

: Contents addressed by xx

xxH

: Hexadecimal data

PD75104, 75106, 75108

(4)

Machine cycle field

In this field, S indicates the number of machine cycles required when an instruction having a skip

function skips. The value of S varies as follows:

When no instruction is skipped ........................................................................

S = 0

When 1-byte or 2-byte instruction is skipped .................................................

S = 1

When 3-byte instruction (BR ! adder or CALL ! adder) is skipped ..............

S = 2

Note : The GETI instruction is skipped in one machine cycle.

One machine cycle equals to one cycle of the CPU clock

, (= t

), and can be changed in three steps

depending on the setting of the processor clock control register (PCC).

(3)

Symbols in addressing area field

MB = MBE . MBS
(MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (00H-7FH)

Data memory

MB = 15 (80H-FFH)

addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H-FBFH,

FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

PD75104

addr = 0000H-0FFFH

PD75106

addr = 0000H-177FH

PD75108

addr = 0000H-1F7FH

addr = (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

Program memory

PD75104

caddr = 0000H-0FFFH (PC

= 0)

addressing

PD75106

caddr = 0000H-0FFFH (PC

= 0) or 1000H-177FH (PC

= 1)

PD75108

caddr = 0000H-0FFFH (PC

= 0) or 1000H-1F7FH (PC

= 1)

faddr = 000H-7FFH

*10

taddr = 020H-07FH

Remarks · MB indicates memory bank that can be accessed.

· In *2, MB = 0 regardless of MBE and MBS.

· In *4 and *5, MB = 15 regardless of MBE and MBS.

· *6 to *10 indicate areas that can be addressed.

PD75104, 75106, 75108

Ma-

Instruc-

Mne-

Operand

Bytes

chine

Operation

Addressing

Skip

tions

monics

Cyc-

Area

Conditions

les

Transfer MOV

A, #n4

String effect A

reg1, #n4

reg1

XA, #n8

String effect A

HL, #n8

String effect B

rp2, #n8

rp2

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A,mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg

reg

XA, rp'

rp'

reg1, A

reg1

rp'1, XA

rp'1

XCH

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

A, mem

(mem)

XA, mem

(mem)

A, reg1

reg1

XA, rp'

rp'

MOVT

XA, @PCDE

PD75104

(PC

11-8

+DE)

ROM

PD75106, 75108

(PC

12-8

+DE)

ROM

XA, @PCXA

PD75104

(PC

11-8

+XA)

ROM

PD75106, 75108

(PC

12-8

+XA)

ROM

Table

Refer-

ence

PD75104, 75106, 75108

Ma-

Instruc-

Mne-

Operand

Bytes

chine

Operation

Addressing

Skip

tions

monics

Cyc-

Area

Conditions

les

Bit

MOV1

CY,fmem.bit

(fmem.bit)

transfer

CY,pmem.@L

(pmem

7-2

3-2

.bit(L

1-0

))

CY,@H+mem.

(H+mem

3-0.

bit)

bit

fmem.bit,CY

(fmem.bit)

pmem.@L,CY

(pmem

7-2

3-2.

bit(L

1-0

))

@H+mem.bit,

(H+mem

3-0

.bit)

Arith-

ADDS

A, #n4

1+S

A+n4

carry

metic

XA, #n8

2+S

XA+n8

carry

opera-

A, @HL

1+S

A+(HL)

carry

tion

XA, rp'

2+S

XA+rp'

carry

rp'1, XA

2+S

rp'1

rp'1+XA

carry

ADDC

A, @HL

A, CY

A+(HL)+CY

XA, rp'

XA, CY

XA+rp'+CY

rp'1, XA

rp'1,CY

rp'1+XA+CY

SUBS

A, @HL

1+S

A-(HL).

borrow

XA, rp'

2+S

XA-rp'

borrow

rp'1, XA

2+S

rp'1

rp'1-XA

borrow

SUBC

A, @HL

A, CY

A-(HL)-CY

XA, rp'

XA, CY

XA-rp'-CY

rp'1, XA

rp'1,CY

rp'1-XA-CY

AND

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

XOR

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

RORC

, A

CY, A

n-1

NOT

Incre-

INCS

reg

1+S

reg

reg+1

reg = 0

ment/

rp1

1+S

rp1

rp1+1

rp1 = 00H

decre-

@HL

2+S

(HL)

(HL)+1

(HL) = 0

ment

mem

2+S

(mem)

(mem)+1

(mem) = 0

DECS

reg

1+S

reg

reg-1

reg = FH

rp'

2+S

rp'

rp'-1

rp' = FFH

Accumulator

Manipulation

PD75104, 75106, 75108

Ma-

Instruc-

Mne-

Operand

Bytes

chine

Operation

Addressing

Skip

tions

monics

Cyc-

Area

Conditions

les

Com-

SKE

reg, #n4

2+S

Skip if reg = n4

reg = n4

pare

@HL, #n4

2+S

Skip if (HL) = n4

(HL) = n4

A, @HL

1+S

Skip if A = (HL)

A = (HL)

XA, @HL

2+S

Skip if XA = (HL)

XA = (HL)

A, reg

2+S

Skip if A = reg

A = reg

XA, rp'

2+S

Skip if XA = rp'

XA = rp'

Carry

SET1

flag

CLR1

Manipu- SKT

1+S

Skip if CY = 1

CY = 1

lation

NOT1

Memory/ SET1

mem.bit

(mem.bit)

Bit

fmem.bit

(fmem.bit)

Manipu-

pmem.@L

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

lation

@H+mem.bit

(H + mem

3-0

.bit)

CLR1

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

@H+mem.bit

(H+mem

3-0

.bit)

SKT

mem.bit

2+S

Skip if (mem.bit) = 1

(mem.bit) = 1

fmem.bit

2+S

Skip if (fmem.bit) = 1

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit (L

1-0

)) = 1

(pmem.@L) = 1

@H+mem.bit

2+S

Skip if (H + mem

3-0

.bit) = 1

(@H+mem.bit) = 1

SKF

mem.bit

2+S

Skip if (mem.bit) = 0

(mem.bit) = 0

fmem.bit

2+S

Skip if (fmem.bit) = 0

(fmem.bit) = 0

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit (L

1-0

)) = 0

(pmem.@L) = 0

@H+mem.bit

2+S

Skip if (H + mem

3-0

.bit) = 0

(@H+mem.bit) = 0

SKTCLR fmem.bit

2+S

Skip if (fmem.bit) = 1 and clear

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit

(pmem.@L) = 1

1-0

)) = 1 and clear

@H+mem.bit

2+S

Skip if (H+mem

3-0

bit) = 1 and clear

(@H+mem.bit) = 1

AND1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

.bit(L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

OR1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

bit (L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

XOR1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

bit (L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

PD75104, 75106, 75108

Ma-

Instruc-

Mne-

Operand

Bytes

chine

Operation

Addressing

Skip

tions

monics

Cyc-

Area

Conditions

les

Branch

addr

PD75104

11-0

addr

The most suitable instruction

is selectable from among

BRCB ! caddr, and BR $ addr

depending on the assembler.

PD75106, 75108

12-0

addr

The most suitable instruction

is selectable from among BR

! addr, BRCB ! caddr, and BR

$ addr depending on the

assembler.

! addr

PD75106, 75108

12-0

addr

$ addr

PD75104

11-0

addr

PD75106, 75108

12-0

addr

BRCB

! caddr

PD75104

11-0

caddr

11-0

PD75106, 75108

12-0

+ caddr

11-0

PCDE

PD75104

11-0

11-8

+ DE

PD75106, 75108

12-0

12-8

+ DE

PCXA

PD75104

11-0

11-8

+ XA

PD75106, 75108

12-0

12-8

+ XA

Subrou-

CALL

! addr

PD75104

tine/

(SP-4)(SP-1)(SP-2)

11-0

Stack

(SP-3)

MBE, RBE, 0, 0

Control

11-0

addr, SP

SP-4

PD75106, 75108

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, 0, PC

12-0

addr, SP

SP-4

PD75104, 75106, 75108

Ma-

Instruc-

Mne-

Operand

Bytes

chine

Operation

Addressing

Skip

tions

monics

Cyc-

Area

Conditions

les

CALLF

! faddr

PD75104

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, 0, 0

11-0

faddr, SP

SP-4

PD75106, 75108

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, 0, PC

12-0

00, faddr, SP

SP-4

RET

PD75104

MBE, RBE, x, x

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4

PD75106, 75108

MBE, RBE, x, PC

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4

RETS

3+S

PD75104

Unconditioned

MBE, RBE, x, x

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4, then skip unconditionally

PD75106, 75108

MBE, RBE, x, PC

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4, then skip unconditionally

RETI

PD75104

MBE, RBE, x, x

(SP+1)

11-0

(SP)(SP+3)(SP+2)

PSW

(SP+4)(SP+5), SP

SP+6

PD75106, 75108

MBE, RBE, x, PC

(SP+1)

11-0

(SP)(SP+3)(SP+2)

PSW

(SP+4)(SP+5), SP

SP+6

PUSH

(SP-1)(SP-2)

rp, SP

SP-2

(SP-1)

MBS, (SP-2)

RBS,

SP-2

POP

(SP+1)(SP), SP

SP+2

MBS

(SP+1), RBS

(SP),

SP+2

Subrou-

tine/

Stack

Control

(Cont`d)

PD75104, 75106, 75108

Ma-

Instruc-

Mne-

Operand

Bytes

chine

Operation

Addressing

Skip

tions

monics

Cyc-

Area

Conditions

les

Inter-

IME (IPS.3)

rupt

IExxx

Control

IME (IPS.3)

IExxx

I/O

IN*

A, PORTn

PORT

(n = 0-9, 12-14)

XA, PORTn

PORT

n+1

,PORT

n (n = 4, 6, 8, 12)

OUT*

PORTn, A

PORT

(n = 2-9, 12-14)

PORTn, XA

PORT

n+1

PORT

(n = 4, 6, 8, 12)

CPU

HALT

Set HALT Mode (PCC.2

Control

STOP

Set STOP Mode (PCC.3

NOP

No Operation

Special

SEL

RBn

RBS

n (n = 0-3)

MBn

MBS

n (n = 0, 1, 15)

GETI

taddr

PD75104

*10

· Where TBR instruction,

11-0

(taddr)

3-0

+(taddr+1)

· Where TCALL instruction,

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, 0, 0

11-0

(taddr)

3-0

+(taddr+1)

SP-4

· Except for TBR and TCALL

Depends on

instructions,

referenced

Instruction execution of

instruction

(taddr)(taddr+1)

PD75106, 75108

· Where TBR instruction,

12-0

(taddr)

4-0

+(taddr+1)

· Where TCALL instruction,

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, 0, PC

12-0

(taddr)

4-0

+(taddr+1)

SP-4

· Except for TBR and TCALL

Depends on

instructions,

referenced

Instruction execution of

instruction

(taddr)(taddr+1)

*: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.

Remarks: TBR and TCALL instructions are assembler instructions for GETI instruction table definition.

.........................................................

.............................

.........................................................

.............................

PD75104, 75106, 75108

10. APPLICATION EXAMPLES

10.1

VTR SYSTEM CONTROLLER

PD75108

Remote
controller
signal
receiver

Operation
mode LED
indicator

Servo
system
control
circuit

Motor
driver
circuit,
etc.

High-
current
output

System
controller/
tape counter/
remote controller/
remaining tape
computation

INT

Comparator

input

INT

Audio video system
control circuit

12 V

SIO

Key
matrix

Take-up reel pulse

Supply reel pulse

Sensor circuit
Exposure sensor
Tape start/end
sensor

On-screen
display
controller

PD752
timer/tuner/OSD

××

PWM output

MNOS
PD6252
PD6253
PD6254

Tuner

FIP

10.2

VTR CAMERA

PD75108

Operation
mode LED
indicator

Servo
system
control
circuit

INT

Motor
plunger
driver
circuit,
etc.

System control/
editing
function

INT

Key matrix
(including
message
input)

Reel pulse

Battery sensor

Sensor circuit
Exposure sensor
Tape start/end
sensor

Power-
down
detector

On-screen
display
controller

12 V

Audio video system
control circuit

Comparator
input

High-
current
output

PD75104, 75106, 75108

10.5

PUSHBUTTON TELEPHONE

Filter

PD75108

Comparator

input

SIO

INT

Code ROM

Piezoelectric
buzzer

Switch

RAM
PD4464

LED indicator

Battery
check

LCD indicator

LCD controller/
driver
PD7228/7229

High-
current
output

Hook switch

To main
equipment

LED
indicator

Key
matrix

Data
receiver
circuit

Data
transmitter
circuit

PD75108

Filter

SIO

PD7228G

LCD
controller/
driver

LCD indicator

Microphone

Speaker

Transmitter/
receiver

MPX

High-
current
output

Transmitter/
receiver/
speaker
selector

Communication
circuit

Speaker
amplifier

Microphone
amplifier

Call sound

10.6

DISPLAY PAGER

PD75104, 75106, 75108

11. MASK OPTION SELECTION

PD75108 has the following mask options. Options to be built in can be selected.

(1)

Mask Option

P120 - P123

P130 - P133

Pull-down resistor can be built in bitwise.

P140 - P143

(2)

Power-ON reset generation circuit, power-ON flag (PONF)

One from the following three ways can be selected.

Switching Selection

Power-On Reset

Power-On Flag

Internal Reset Signal

(Refer to Fig. 8-1.)

Generation Circuit

(PONF)

(RES)

SWA

SWB

Provided

Generates automatically

OFF

Provided

Not generates autoamtically

OFF

Not provided

PD75104, 75106, 75108

12. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply Voltage

-0.3 to +7.0

Other than ports 12, 13, 14

-0.3 to V

+0.3

Input Voltage

Ports 12 to 14

w/pull-up

-0.3 to V

+0.3

resistor

Open drain

-0.3 to +13

Output Voltage

-0.3 to V

+0.3

High-Level Output

1 pin

-15

Current

All pins

-30

Low-Level Output

1 pin

Peak

Current

rms

Total of ports 0, 2 to 4, 12 to 14 Peak

100

rms

Total of ports 5 to 9

Peak

100

rms

Operating Temperature

opt

-40 to +85

Storage Temperature

stg

-65 to +150

*1: The power supply impedance (pull-up resistance) must be 50 k

or higher when a voltage higher than

10 V is applied to ports 12, 13, and 14.

2: rms = Peak value x

Duty

PD75104, 75106, 75108

OSCILLATOR CIRCUIT CHARACTERISTICS

= -40 to +85

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation

= Oscillation

2.0

5.0

MHz

frequency(f

voltage range

Oscillation stabiliza- After V

come to

tion time*

MIN. of oscillation
voltage range

Crystal

Oscillation

2.0

4.19

5.0

MHz

frequency (f

Oscillation stabiliza- V

= 4.5 to 6.0 V

tion time*

External Clock

X1 input frequency

2.0

5.0

MHz

X1 input high-,
low-level widths
(t

, t

)

100

250

*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics

of the oscillator circuit. For instruction execution time, refer to AC Characteristics.

2: Time required for oscillation to stabilize after V

has come to MIN. of oscillation volrage range

or the STOP mode has been released.

3: When the oscillation frequency is 4.19 MHz

5.0 MHz, do not select PCC = 0011 as the

instruction execution time: otherwise, one machine cycle is set to less than 0.95

s, falling short

of the rated minimum value of 0.95

Note:

When using the oscillation circuit of the system clock, wire the portion enclosed in dotted line

in the figures as follows to avoid adverse influences on the wiring capacity:

· Keep the wiring length as short as possible.

· Do not cross the wiring over the other signal lines. Also, do not route the wiring in the vicinity

of lines through which a high alternating current flows.

· Always keep the ground point of the capacitor of the osccillator circuit at the same potential

as V

. Do not connect the ground pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

PD74HCU04

PD75104, 75106, 75108

RECOMMENDED OSCILLATOR CIRCUITS CONSTANTS

RECOMMENDED CERAMIC OSCILLATORS

External

Oscillation

Manufacturer

Product Name

Capacitance (pF)

Voltage Range (V)

MIN.

MAX.

CSA 2.00MG

2.7

6.0

Murata Mfg.

CSA 4.19MG

3.0

6.0

Co., Ltd.

CSA 4.19MGU

2.7

6.0

CST 4.19T

Provided

3.0

6.0

KBR-2.0MS

100

3.0

6.0

Kyoto Ceramic

KBR-4.0MS

3.0

6.0

Co., Ltd.

KBR-4.19MS

3.0

6.0

KBR-4.9152M

3.0

6.0

RECOMMENDED CRYSTAL OSCILLATOR

External

Oscillation

Manufacturer

Product Name

Capacitance (pF)

Voltage Range (V)

MIN.

MAX.

Kinseki

HC-49/U

2.7

6.0

PD75104, 75106, 75108

DC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Item

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

IH1

Other than below

0.7V

High-Level

IH2

Ports 0, 1, TI0, 1, RESET

0.8 V

Input Voltage

Pull-up resistor

0.7 V

Open drain

0.7 V

IH4

X1, X2

-0.5

IL1

Other than below

0.3 V

Low-Level Input Voltage

IL2

Ports 0, 1, TI0, 1, RESET

0.2 V

IL3

X1, X2

0.4

= 4.5 to 6.0 V,I

= -1 mA

-1.0

= -100

-0.5

Ports 0, 2 to 9, I

= 15 mA

0.35

2.0

4.5 to 6.0 V

Ports 12 to 14, I

= 10 mA

0.35

2.0

= 4.5 to 6.0 V, I

= 1.6 mA

0.4

= 400

0.5

LIH1

Other than below

LIH2

X1,X2

LIH3

= 12 V

Ports 12 to 14 (open drain)

Low-Level

LIL1

Other than X1, X2

Input Leakage Current

LIL2

X1, X2

High-Level

LOH1

OUT

= V

Other than below

Output Leakage Current

LOH2

OUT

= 12 V

Ports 12 to 14 (open drain)

Low-Level Output

LOL

OUT

= 0 V

Leakage Current

= 5 V

10%

4.19MHz

= 5 V

10%*

crystal

= 3 V

10%*

0.55

1.5

Supply Current*

oscillator

HALT

= 5 V

10%

600

1800

C1 = C2 = 22pF

mode

= 3

10%

200

600

DD3

STOP mode, V

= 3 V

10%

0.1

*1: The current flowing into the internal pull-up resistor, power-ON reset circuit (mask option), and comparator

circuit is not included.

2: When the high-speed mode is set by setting the processor clock control register (PCC) to 0011.

3: When the low-speed mode is set by setting the PCC to 0000.

Low-Level Output Voltage

High-Level Output Voltage

= V

= 0 V

High-Level Input Leakage

Current

Internal Pull-Up Resistor*

Ports 12 to 14

DD1

DD2

IH3

Ports 12 to 14

PD75104, 75106, 75108

CAPACITANCE (T

= 25

C, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Capacitance

f = 1 MHz

Output Capacitance

OUT

Pins other than thosemeasured are at 0 V

Input/Output

Capacitance

COMPARATOR CHARACTERISTICS (T

= -40 to +85

C, V

= 4.5 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Comparison Accuracy

ACOMP

100

Threshold Voltage

PTH Input voltage

IPTH

Comparator circuit

PTHM7 is set to "1"

current dissipation

POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (T

= -40 to +85

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power-On Reset

High-Level

DDH

4.5

6.0

Operating Voltage

Power-On Reset

Low-Level

DDL

0.2

Operating Voltage

Supply Voltage

Rise Time

Supply Voltage

off

Off Time

Power-On Reset Circuit

DDPR

= 5 V

10%

100

Current Dissipation*

= 2.5 V

*1: 2

(31.3 ms at f

= 4.19 MHz)

2: Current flowing when power-ON reset circuit or power-ON Flag is incorporeated.

Note: Apply power gradually and smoothly.

DDH

DDL

off

PD75104, 75106, 75108

AC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 4.5 to 6.0 V

0.95

3.8

= 4.5 to 6.0 V

MHz

275

kHz

TIH

= 4.5 to 6.0 V

0.48

TIL

1.8

= 4.5 to 6.0 V

Input

0.8

Output

0.95

Input

3.2

Output

3.8

= 4.5 to 6.0 V

Input

0.4

Output

KCY

/2-50

Input

1.6

Output

KCY

/2-150

SI Setup Time

SIK

100

(vs. SCK

)

SI Hold Time

KSI

400

(vs. SCK

)

= 4.5 to 6.0 V

300

1000

INT0 to 4

INTH,

High-/Low-Level Width

INTL

RESET Low-Level Width

RSL

*: The cycle time of the CPU clock (

) is

determined by the input frequency of

the ceramic or crystal oscillator circuit

and the set value of the processor clock

control register. The t

vs. V

charac-

teristics are as shown on the right.

0.5

[V]

[ s]

vs. V

Operation
guaranteed
range

CPU Clock Cycle Time*
(Minimum Instruction
Execution Time = 1
Machine Cycle)

TI0, TI1 Input Frequency

TI0, TI1 Input High-/
Low-Level Width

SCK Cycle Time

KCY

SCK High-/Low-Level
Width

KH,

SCK

SO Output

delay Time

KSO

PD75104, 75106, 75108

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

= 40 to +85

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data Retention Supply

DDDR

2.0

6.0

Voltage

Data Retention Supply

DDDR

= 2.0 V

0.1

Current*

Release Signal Set Time

SREL

Oscillation Stabilization

WAIT

Released by RESET

Wait Time*

Released by interrupt request

*1: The current flowing through internal pull-up resistor, power-ON reset circuit (mask option), and

comparator circuit is not included

2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent

unstable operation when oscillation is started.

3: Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3

BTM2

BTM1

BTM0

Wait time ( ): f

= 4.19 MHz

(approx. 250 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

DATA RETENTION TIMING (releasing STOP mode by RESET)

STOP mode

Data retention mode

STOP instruction
execution

RESET

DDDR

SREL

WAIT

Operation
mode

Internal reset operation

HALT mode

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

STOP mode

Data retention mode

STOP instruction execution

DDDR

SREL

WAIT

Operation
mode

HALT mode

Standby release signal

(interrupt request)

PD75104, 75106, 75108

13. CHARACTERISTIC DATA

5000

1000

500

100

0.5

I vs. V Characteristics (crystal oscillation)

Supply voltage V [V]

Supply current I [ A]

High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]

HALT mode [0100]

STOP mode [1000]

When power-ON
reset circuit and
power-ON flag are
incorporated.

Figure in [ ] indicate
set values of PCC.

Crystal
oscillation
4.194304 MHz

22 pF

I vs. f Characteristics (crystal oscillation)

Supply current I [mA]

f [MHz]

3.0

2.5

2.0

1.5

1.0

0.5

Figure in [ ] indicate
set values of PCC.

High-speed mode [0011]

Medium-speed mode [0010]

Low-speed mode [0000]

HALT mode [0100]

(V = 5.0 V, T = 25°C)

(T = 25°C)

PD75104, 75106, 75108

5000

1000

500

100

0.5

I vs. V Characteristics (ceramic oscillation)

High-speed mode [0011]
Medium-speed mode [0010]
Low-speed mode [0000]

STOP mode [1000]

When power-ON
reset circuit and
power-ON flag are
incorporated.

Figure in [ ] indicate
set values of PCC.

Ceramic
oscillation
4.19 MHz

30 pF

I vs. f Characteristics (ceramic oscillation)

f [MHz]

3.0

2.5

2.0

1.5

1.0

0.5

Figure in [ ] indicate
set values of PCC.

High-speed mode [0011]

Medium-speed mode [0010]

Low-speed mode [0000]

HALT mode [0100]

(T = 25°C)

(V = 5.0 V, T = 25°C)

Supply voltage V [V]

Supply current I [ A]

Supply current I [mA]

PD75104, 75106, 75108

14. PACKAGE DRAWINGS

F
D

NOTE

Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

P64C-70-750A,C-1

ITEM MILLIMETERS

INCHES

58.68 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

1.78 MAX.

0.17

0.25

19.05 (T.P.)

5.08 MAX.

17.0

0~15°

0.50±0.10

0.9 MIN.

2.311 MAX.

0.070 MAX.

0.020

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.010

0.007

0~15°

+0.004

0.003

0.070 (T.P.)

Item "K" to center of leads when formed parallel.

+0.10

0.05

+0.004

0.005

64 PIN PLASTIC SHRINK DIP (750 mil)

PD75104, 75106, 75108

64 PIN PLASTIC QFP (14

20)

P64GF-100-3B8,3BE,3BR-2

ITEM

MILLIMETERS

INCHES

23.6±0.4

20.0±0.2

14.0±0.2

0.929±0.016

0.795

0.551

17.6±0.4

0.693±0.016

1.0

0.039

1.0

0.039

0.40±0.10

0.016

0.20

0.008

1.0 (T.P.)

0.039 (T.P)

1.8±0.2

0.071

0.8±0.2

0.031

0.15

0.006

0.10

0.004

2.7

0.106

0.1±0.1

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

+0.008

0.009

+0.009

0.008

+0.004

0.005

+0.008

0.009

+0.009

0.008

+0.004

0.003

NOTE

Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.

detail of lead end

+0.10

0.05

PD75104, 75106, 75108

15. RECOMMENDED SOLDERING CONDITIONS

It is recommended that

PD75104, 75106, and 75108 be soldered under the following conditions.

For details on the recommended soldering conditions, refer to Information Document "Semiconductor

Devices Mounting Manual" (IEI-616).

For other soldering methods and conditions, please consult NEC.

Table 15-1 Soldering Conditions of Surface Mount Type

PD75108GF - xxx - 3BE: 64-pin plastic QFP (14 x 20 mm)

Soldering Method

Soldering Conditions

Infrared Reflow

Package peak temperature: 230

C, time: 30 seconds max.

IR30-00-1

(210

C min.), number of times: 1

VPS

Package peak temperature: 215

C, time: 40 seconds max.

VP15-00-1

(200

C min.), number of times: 1

Wave Soldering

Soldering bath temperature: 260

C max., time: 10 seconds

WS60-00-1

max., number of times: 1,
pre-heating temperature: 120

C max. (package surface

temperature)

Pin Partial Heating

Pin temperature: 300

C max.,

time: 3 seconds max. (per side)

Caution: Do not use two or more soldering methods in combination (except the pin partial heating

method).

Symbol for Recommended

Condition

Table 15-2 Soldering Conditions of Through-Hole Type

PD75108CW - xxx : 64-pin plastic shrink DIP (750 mil)

Soldering Method

Soldering Conditions

Wave Soldering

Soldering bath temperature: 260

C max., Time: 10 seconds max.

(Only for lead part)

Pin Partial Heating

Pin temperature: 260

C max., Time: 10 seconds max.

Caution: The wave soldering must be performed at the lead part only. Note that the solder must not be

directly contacted to the package body.

PD75104,

75106,

75108

· CMOS I/O: 32
(pull-up resistor as mask

option: 24)

· +12 V open-drain output: 12
(pull-up resistor as mask

option)

LED direct drive: 44

APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PRODUCTS IN PD751XX SERIES

Item

PD75104

PD75106

PD75108

PD75112

PD75116

PD75104A

PD75108A

PD75108F

PD75112F

PD75116F

PD75P108B

PD75P116

ROM Configuration

Mask ROM

PROM

ROM (Bits)

000H-FFFH

0000H-177FH

0000H-1F7FH

0000H-2F7FH

0000H-3F7FH

000H-FFFH

0000H-1F7FH

0000H-2F7FH

0000H-3F7FH

0000H-1F7FH

0000H-3F7FH

4096

6016

8064

12160

16256

4096

8064

12160

16256

8064

16256

320

(Bank 0:
256

(Bank 1:
64

512

(Bank 0:
256

(Bank 1:
256

512

(Bank 0: 256

(Bank 1: 256

320

(Bank 0: 256

(Bank 1: 64

512

(Bank 0: 256

(Bank 1: 256

RAM (Bits)

Instruction Set

High-end (Only PD75104 and 75104A are not provided with BR!addr instruction.)

High end

Total

I/O

· CMOS I/O: 32

· +12 V open-drain output: 12

(pull-up resistor as mask option)

LED direct drive: 44

· CMOS I/O: 32

· +10 V open-drain output: 12

(pull-up resistor as mask option)

LED direct drive: 44

· CMOS I/O: 32
· +12 V open-drain output:

LED direct drive: 44

· CMOS input: 10
(pull-up resistor as mask

option: 4)

· Comparator input: 44

· CMOS input: 10

· Comparator input: 4

· CMOS input: 10

· Comparator input: 4

Input

I/O

Lines

Power-ON
Reset Circuit

Power-ON Flag

Operating
Voltage Range

Provided (mask option)

None

2.7 to 6.0 V

2.7 to 5.0 V (T

= -40 to +50°C)

2.8 to 5.0 V (T

= -40 to +60°C)

2.7 to 6.0 V

5 V ± 10%

Minimum
Instruction
Execution
Time

0.95 s (at 5 V)

3 s (at 3 V)

0.95 s (at 4.5 V to 5.0 V)

1.91 s (at 3 V)

0.95 s
(at 5 V)

3 s
(at 3 V)

0.95 s
(at 5 V)

Pin Connections

Depends on package

Depends on package. Only PD75P108, and 75P116 are provided with
V

pin.

· 64-pin

plastic
shrink DIP
(750 mil)

· 64-pin

ceramic
shrink DIP
(w/window)

· 64-pin

plastic QFP
(14

mm)

· 64-pin

plastic
shrink DIP
(750 mil)

· 64-pin

plastic QFP
(14

mm)

· 64-pin plastic QFP (14

20 mm)

· 64-pin

plastic QFP
(14

mm)

· 64-pin

plastic QFP
(14

mm)

· 64-pin

plastic QFP
(14

mm)

· 64-pin plastic shrink DIP

(750 mil)

· 64-pin plastic QFP (14

mm)

· 64-pin plastic shrink DIP (750 mil)

· 64-pin plastic QFP (14

20 mm)

Package

PD75104, 75106, 75108

APPENDIX B. DEVELOPMENT TOOLS

The following development support tools are readily available to support development of systems using

PD75108:

Hardware

IE-75000-R*

In-circuit emulator for 75X series

IE-75001-R

IE-75000-R-EM*

Emulation board for IE-75000-R and IE-75001-R

EP-75108CW-R

Emulation prove for

PD75108CW

EP-75108GF-R

Emulation prove for

PD75108GF. It is provided with a 64-pin conversion

socket, EV-9200G-64

PG-1500

PROM programmer

PA-75P108CW

PROM programmer adapter for

PD75P108BCW and 75P108BDW.

It is connected to PG-1500.

PA-75P116GF

Programmer adapter for

PD75P108BGF.

It is connected to PG-1500.

Software

IE Control Program

PG-1500 Controller

RA75X Relocatable
Assembler

*1: Maintenance product

2: Not provided with IE-75001-R.

3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function.

Remarks:

For development tools from other companies, refer to 75X Series Selection Guide (IF-151).

EV-9200G-64

Host machine

PC-9800 series (MS-DOS

Ver.3.30 to Ver.5.00A*

)

IBM PC/AT

(PC DOS

Ver.3.1)

PD75104, 75106, 75108

STATIC ELECTRICITY (ALL MOS DEVICES)

Exercise care so that MOS devices are not adversely influenced by static electricity while being

handled.

The insulation of the gates of the MOS device may be destroyed by a strong static charge.

Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,

or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use

grounding when assembling the MOS device system. Do not leave the MOS device on a plastic

plate and do not touch the pins of the device.

Handle boards on which MOS devices are mounted similarly .

PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)

Fix the input level of CMOS devices.

Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its

input pin, intermediate level input may be generated due to noise, and an inrush current may flow

through the device, causing the device to malfunction. Therefore, fix the input level of the device

by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an

output pin (whose timing is not specified), each pin should be connected to V

or GND through

a resistor.

Refer to "Processing of Unused Pins" in the documents of each devices.

STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)

The initial status of MOS devices is undefined upon power application.

Since the characteristics of an MOS device are determined by the quantity of injection at the

molecular level, the initial status of the device is not controlled during the production process. The

output status of pins, I/O setting, and register contents upon power application are not guaranteed.

However, the items defined for reset operation and mode setting are subject to guarantee after

the respective operations have been executed.

When using a device with a reset function, be sure to reset the device after power application.

GENERAL NOTES ON CMOS DEVICES

PD75104, 75106, 75108

[MEMO]

No p

art of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which

may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other

intellectual property rights of third parties b y or arising from use of a device described herein or any

other liability arising from use of such device. No license, either express, implied or otherwise, is granted

under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,

nuclear reactor control systems and life support systems. If customers intend to use NEC devices for

above applications or they intend to use "Standard" quality grade NEC devices for the applications not

intended by NEC, please contact our sales people in advance.

Application examples recommended by NEC Corporation

Standard:

Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special:

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime system, etc.

MS-DOS is a trademark of Microsoft Corporation.

PC DOS and PC/AT are trademarks of IBM Corporation.

M4 92.6

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD75104

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD75104