4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The

PD75208 is a microcomputer with a CPU capable of 1-, 4-, and 8-bit-wise data processing, a ROM, a RAM,

I/O ports, a fluorescent display tube controller/driver, a watch timer, a timer/pulse generator capable of outputting

14-bit PWM, a serial interface and a vectored interrupt function integrated on a single-chip.

It uses the VCR, ECR and CD fluorescent display tubes as display devices and is most suitable for applications

requiring the timer/watch function and high-speed interrupt servicing. It can help to provide the unit with many

functions and to decrease performance costs.

With the

PD75208, the

PD75P216A, 75P218 one-time PROM products are available for system development

evaluation or small production.

The following manual provides detailed description of the functions of the

PD75208. Be sure to read this manual

when you design an application system.

PD75216A User's Manual: IEM-988

FEATURES

PD75208

MOS INTEGRATED CIRCUIT

DATA SHEET

The information in this document is subject to change without notice.

The mark 5 shows major revised points.

Document No.

IC-1884A

(O. D. No.

IC-7048C)

Date Published August 1993 P
Printed in Japan

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

Architecture equal to that of an 8-bit microcomputer

High-speed operation : Minimum instruction execution time : 0.95

s (when operated at 4.19 MHz)

Instruction execution time variable function realizing a wide range of operating voltages

On-chip large-capacity program memory : 8K bytes

Watch operation with an ultra low current consumption : 5

A TYP. (at the 3 V operation)

On-chip programmable fluorescent display tube controller/driver

Timer function : 4 ch

· 14-bit PWM output capability with the voltage synthesizer type electronic tuner

· Buzzer output capability

Interrupt function with importance attached to applications

· For power-off detection

· For remote controlled reception

Product with an on-chip PROM :

PD75P216A,

PD75P218 (on-chip EPROM : WQFN package)

ORDERING INFORMATION

Ordering Code

Package

Quality Grade

PD75208CW-

×××

64-pin plastic shrink DIP (750 mil)

Standard

PD75208GF-

×××

-3BE

64-pin plastic QFP (14

20 mm)

Standard

PD75208

Instruction execution time

On-chip memory

ROM

RAM

General register

Input/output port

FIP dual-function pin
included
FIP dedicated pin
excluded

FIP controller/driver

Timer

Serial interface

Vectored interrupt

Test input

System clock oscillator

Standby function

Mask option

Operating temperature range

Operating voltage

Package

· 0.95, 1.91, 15.3

s (Main system clock : 4.19 MHz operation)

· 122

s (Subsystem clock : 32.768 kHz operation)

8064

8 bits

497

4 bits

· 4-bit manipulation : 8

4 banks

· 8-bit manipulation : 4

4 banks

CMOS input pin

CMOS input/output pins

· Direct LED drive capability : 8
· On-chip pull-down resistor by mask option capability : 4

CMOS output pin

· Direct LED drive capability : 4
· PWM/pulse output : 1
· On-chip pull-down resistor by mask option capability : 4

· No. of segments : 9 to 12 segments
· No. of digits

: 9 to 16 digits

· Dimmer function : 8 levels
· On-chip pull-down resistor by mask option capability
· Key scan interrupt generation

4 channels

· Timer/pulse generator : 14-bit PWM output enabled
· Watch timer

: Buzzer output enabled

· Timer/event counter
· Basic interval timer

: Watchdog timer application capability

· MSB start/LSB start switchable
· Serial bus configuration capability

External : 3, Internal : 5

External : 1, Internal : 1

· Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz standard
· Crystal oscillator for subsystem clock oscillation : 32.768 kHz standard

STOP/HALT mode

· Power-on reset, power-on flag
· High withstand voltage port : Pull-down resistor or open-drain output
· Port 6 : Pull-down resistor

40 to +85

2.7 to 6.0 V (standby data hold : 2.0 to 6.0 V)

· 64-pin plastic shrink DIP (750 mil)
· 64-pin plastic QFP (14

20 mm)

Item

LIST OF FUNCTIONS

Function

PD75208

CONTENTS

PIN CONFIGURATION (TOP VIEW) ....................................................................................... 5

BLOCK DIAGRAM .................................................................................................................... 6

PIN FUNCTIONS ...................................................................................................................... 7

3.1

PORT PINS .................................................................................................................................... 7

3.2

NON-PORT PINS .......................................................................................................................... 8

3.3

PIN INPUT/OUTPUT CIRCUIT LIST ............................................................................................ 9

3.4

UNUSED PINS TREATMENT .................................................................................................... 10

3.5

P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS ............................................... 11

3.6

XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS ........................................................... 11

ARCHITECTURE AND MEMORY MAP OF THE

PD75208 ............................................... 12

PERIPHERAL HARDWARE FUNCTIONS .............................................................................. 14

5.1

PORTS .......................................................................................................................................... 14

5.2

CLOCK GENERATOR .................................................................................................................. 15

5.3

BASIC INTERVAL TIMER ........................................................................................................... 16

5.4

WATCH TIMER .......................................................................................................................... 17

5.5

TIMER/EVENT COUNTER ......................................................................................................... 18

5.6

TIMER/PULSE GENERATOR ..................................................................................................... 19

5.7

SERIAL INTERFACE ................................................................................................................... 20

5.8

FIP CONTROLLER/DRIVER ........................................................................................................ 22

5.9

POWER-ON FLAG (MASK OPTION) ......................................................................................... 23

INTERRUPT FUNCTIONS ...................................................................................................... 23

STANDBY FUNCTIONS ......................................................................................................... 25

RESET FUNCTIONS ............................................................................................................... 25

INSTRUCTION SET ................................................................................................................ 26

10. MASK OPTION SELECTION .................................................................................................. 35

11. APPLICATION BLOCK DIAGRAM ......................................................................................... 36

11.1

VCR TIMER TUNER .................................................................................................................... 36

11.2

COMPACT DISK PLAYER .......................................................................................................... 37

11.3

ECR ............................................................................................................................................... 37

PD75208

PIN CONFIGURATION (TOP VIEW)

S1
S0

P00/INT4

P01/SCK

P02/SO

P03/SI

P10/INT0
P11/INT1

P12/INT2

P13/TI0

P20
P21

P22

P23/BUZ

P30
P31
P32
P33
P60
P61

P62

P63
P40
P41
P42

P43

PPO

X1
X2

62
61
60

58
57
56
55

54
53
52
51

50
49

48
47
46
45
44
43

41
40
39
38

37
36

35
34

3
4
5

7
8
9
10

11
12
13
14

15
16

17
18
19
20
21
22

24
25
26
27

28
29

30
31

S5
S6
S7

S9
V

PRE

LOAD

T15/S10

T14/S11
T13/PH0
T12/PH1
T11/PH2

T10/PH3
T9

T8
T7
T6
T5
T4
T3

T1
T0
RESET
P53

P52
P51

P50
XT2

XT1

P41

P42

P43

PPO

XT1

XT2

P50

P51

P52

P53

P01/SCK

P00/INT4

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

9 10 11 12 13 14 15 16 17 18 19

P40

P63

P62

P61

P60

P33

P32

P31

P30

P23/BUZ

P22

P21

P20

P13/TI0

P12/INT2

P11/INT1

P10/INT0

P03/SI

P02/SO

RESET

PRE

T10/PH3

T11/PH2

T12/PH1

T13/PH0

T14/S11

T15/S10

LOAD

PD75208CW-

× × ×

PD75208GF-

× × ×

-3BE

PD75208

Input

Input/

output

INT4

SCK

INT0

INT1

INT2

TI0

BUZ

T13

T12

T11

T10

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30P33

P40 to P43

P50 to P53

P60 to P63

PH0

PH1

PH2

PH3

PIN FUNCTIONS

3.1

PORT PINS

Pin Name

I/O

After Reset

Input / Output

Circuit Type *1

Function

Dual-

Function Pin

8-Bit

I/O

Input/output

4-bit input port (PORT0).

Input

Noise removing function available

4-bit input port (PORT1).

4-bit input/output port (PORT2).

Input

Programmable 4-bit input/ output port (PORT3).

Input/output specifiable in 1-bit units.

Input/

output

Input

Input/

output

4-bit input/output port (PORT4).
LED direct drive capability.

Input

Input/

output

4-bit input/output port (PORT5).
LED direct drive capability.

Input

Input/

output

Programmable 4-bit input/output port (PORT6).

Input/output specifiable in 1-bit units.

On-chip pull-down resistor available (mask

option). Suitable for key input.

Input

Output

4-bit P-ch open-drain, high-dielectric, high-current

output port (PORTH).

LED direct drive capability. On-chip pull-down

resistor available (mask option).

Schmitt trigger inputs are circled.

Low level
(with an on-
chip pull-
down resistor)
or high
impedance.

PD75208

Segment output high voltage output.
Static output also possible.

Pin Name

I/O

Dual-

Function Pin

Input / Output

Circuit Type *

Function

After Reset

Digit/segment output dual-function
high-voltage high-current output.
Extra pins can be used as PORTH.

Digit output high-voltage high-current

output.

FIP controller/

driver output

pins.

Pull-down

resistor can be

incorporated in

bit units (mask

option).

T0 to T9

Digit/segment output dual-function
high-voltage high-current output.
Static output also possible.

T10 to T13

T14/S11,
T15/S10

Output

PH3 to PH0

Low

level

(with an on-
chip pull-
down
resistor ) or
high
impedance
(without a
pull-down
resistor)

3.2

NON-PORT PINS

Schmitt trigger inputs are circled.

Segment high-voltage output.

S0 to S8

High
impedance

PPO

Output

Input

Timer/pulse generator pulse output.

External event pulse input for timer/event counter.

P13

Serial clock input/output.

TI0

SCK

Serial data output pin or serial data input/output.

Serial data input or normal input.

Edge-detected vectored interrupt input (rising and falling

edge detection).

INT0

INT1

INT4

Input/output

Input

P01

P02

P03

P00

P10

P11

Edge-detected vectored interrupt input with noise

eliminate function (detection edge selection possible).

Edge-detected testable input (rising edge detection).

Fixed frequency output (for buzzer or system clock

trimming).

Crystal/ceramic connect pin for main system clock

oscillation.

External clock input to X1 and its inverted clock input to

X2.

Crystal connect pin for subsystem clock oscillation.

External clock input to XT1 and XT2 open.

INT2

Input

Input/output

P12

P23

BUZ

X1, X2

XT1

Input

FIP controller/driver output buffer power supply.

FIP controller/driver pull-down resistor connect pin.

GND potential.

XT2

System reset input (low level active).

RESET

PRE

Input

Positive power supply.

LOAD

Input

Input/output

PD75208

3.3

PIN INPUT/OUTPUT CIRCUIT LIST

TYPE A

TYPE B

TYPE D

TYPE E

TYPE F

TYPE G

TYPE V

TYPE I

P-ch

N-ch

P-ch

N-ch

OUT

data

output
disable

data

output
disable

Type D

IN/OUT

Type A

data

output
disable

Type D

IN/OUT

Type B

data

output
disable

Type D

IN/OUT

Type A

P-ch

N-ch

IN/OUT

data

P-ch output
disable

Type B

P-ch

N-ch

OUT

data

P-ch

LOAD

PRE

CMOS-Specified Input Buffer

Schmitt Trigger Input Having Hysteresis Characteristics

Push-Pull Output which can be Set to Output High Impedance
(with Both P-ch and N-ch Set to OFF)

Input/Output Circuit Consisting of Type D Push-Pull Output
and Type A Input Buffer

Pull-down Resistor
(Mask Option)

Pull-down
Resistor

(Mask Option)

Input/Output Circuit Capable of Switching between Push-Pull
Output and N-ch Open-Drain Output (with P-ch OFF).

Input/Output Circuit Consisting of Type D Push-Pull Output
and Type B Schmitt Trigger Input

PD75208

Connect diode with small V

(0.3 V or less) between

the pins and V

Connect a capacitor between the pins and V

3.6

XT1, XT2 AND P50 PIN OPERATING PRECAUTIONS

When selecting the 32.768 kHz subsystem clock connected to the XT1 and XT2 pins as the watch timer source

clock, the signal to be input or output to the P50 pin next to the XT2 pin must be a signal required to be switched

between high and low the minimum number of times (once/second or less).

If the P50 pin signal is switched frequently between high and low, a spike is generated in the XT2 pin because

of capacitance coupling of the P50 and XT2 pins and the correct watch functions cannot be achieved (the watch

becomes fast).

If it is necessary to allow the P50 pin signal to switch between high and low, mount an external capacitor to the

P50 pin as shown below.

3.5

P00/INT4 PIN AND RESET PIN OPERATING PRECAUTIONS

P00/INT4 and RESET pins have the function (especially for IC test) to test uPD75208 internal operations in addition

to the functions described in sections 3.1 and 3.2.

The test mode is set when a voltage larger than V

is applied to one of these pins. If noise larger than V

applied in normal operation, the test mode may be set thereby adversely affecting normal operation.

Since there is a display output pin having a high-voltage amplitude (35 V) next to the P00/INT4 and RESET pins,

if cables for the related signals are routed in parallel, wiring noise larger than V

may be applied to the P00/INT4

and RESET pins causing errors.

Thus, carry out wiring so that wiring noise can be minimized, If noise still cannot be suppressed, take the measure

against noise using the following external components.

P00/INT4, RESET

XT1

32.768 kHz

0.0068 F

XT2

P50

PD75208

PD75208

ARCHITECTURE AND MEMORY MAP OF THE

PD75208

The

PD75208 has three architectural features:

· Bank configuration of data memory

: Static RAM (448 words

4 bits)

Display data memory (49 words

4 bits)

Peripheral hardware (128

4 bits)

· Bank configuration of general registers: 8

4 banks (for operation in 4-bit units)

4 banks (for operation in 8-bit units)

· Memory mapped I/O

Fig. 4-1 and 4-2 show the memory maps for the

PD75208.

Fig. 4-1 Program Memory Map

Remarks

In all cases other than those listed above, branch to the address with only the lower 8 bits of the PC

changed is enabled by BR PCDE and BR PCXA instructions.

MBE RBE

0000H

Address

MBE RBE

0002H

MBE RBE

0004H

MBE RBE

0006H

MBE RBE

0008H

MBE RBE

000AH

007FH
0080H

0020H

1F7FH

Internal Reset Start Address (High-Order 5 Bits)

Internal Reset Start Address (Low-Order 8 Bits)

INTBT/INT4 Start Address (High-Order 5 Bits)

INTBT/INT4 Start Address (Low-Order 8 Bits)

INT0 Start Address (High-Order 5 Bits)

INT0 Start Address (Low-Order 8 Bits)

INT1 Start Address (High-Order 5 Bits)

INT1 Start Address (Low-Order 8 Bits)

INTSIO Start Address (High-Order 5 Bits)

INTSIO Start Address (Low-Order 8 Bits)

INTT0 Start Address (High-Order 5 Bits)

INTT0 Start Address (Low-Order 8 Bits)

NTTPG Start Address (High-Order 5 Bits)

INTTPG Start Address (Low-Order 8 Bits)

INTKS Start Address

(High-Order 5 Bits)

INTKS Start Address

(Low-Order 8 Bits)

GETI Instruction Reference Table

000EH

MBE RBE

000CH

07FFH
0800H

0FFFH
1000H

BRCB

! caddr Instruction

Branch Address

CALL ! addr
Instruction
Subroutine Entry
Address

BR ! addr
Instruction Branch
Address

BR $addr
Instruction
Relative Branch
Address
(15 to 1,
+2 to +16)

BRCB
! caddr
Instruction
Branch
Address

CALLF
! faddr
Instruction
Entry
Address

Branch Destination
Address Specified
by GETI Instruction,
Subroutine Entry
Address

PD75208

PERIPHERAL HARDWARE FUNCTIONS

5.1

PORTS

The

PD75208 has the following three types of I/O port:

· 8 CMOS input ports

· 20 CMOS I/O ports

· 4 P-ch open-drain high-voltage, large-current output ports

Total: 32 ports

Table 5-1 Functions of Ports

Remarks

Port Name

Always read or test possible irrespective of the dual-function

pin operating mode.

Always read or test possible, P10 and P11 are inputs with the

noise eliminate function.

Can be set to the input or output mode in 4-bit units.

Ports 4 and 5 can input/output data in pairs in 8-bit units.

Ports 4 and 5 can directly drive LEDs.

Can be set bit-wise to the input or output mode. Port 6 can

incorporate a pull-down resistor as a mask option.

P-ch open-drain high-voltage, high-current output port. Can

drive an FIP and LED directly. Can incorporate a pull-down

resistor bit-wise as a mask option.

Shares the pins with SI, SO, SCK

and INT4.

Shares the pins with INT0 to 2

and TI0.

P23 shares the pin with BUZ.

Shares the pins with T10 to T13.

Operation and Feature

Function

4-bit input

PORT0

PORT1

PORT2

PORT4

PORT5

PORT3

PORT6

4-bit

input/output

PORTH

4-bit output

PD75208

5.2

CLOCK GENERATOR

Operation of the clock generator is specified by the processor clock control register (PCC) and system clock control

The main system clock or subsystem clock can be selected.

The instruction execution time is variable.

· 0.95

s, 1.91

s, 15.3

s (main system clock: 4.19 MHz)

· 122

s (subsystem clock: 32.768 kHz)

Fig. 5-1 Clock Generator Block Diagram

Instruction execution

Remarks

= Main system clock frequency

= Subsystem clock frequency

= System clock frequency

= CPU clock

PCC: Processor clock control register

SCC: System clock control register

1 clock cycle (t

) of

is 1 machine cycle of an instruction. For t

, see "AC Characteristics" in

12. ELECTRICAL SPECIFICATIONS.

XT1

XT2

SCC

PCC

HALT*

STOP*

HALT F/F

STOP F/F

1/4

1/8 to 1/4096

SCC3

SCC0

PCC0

PCC1

PCC2

PCC3

Selector

1/2 1/6

Frequency Divider

Selector

Watch Timer

Timer/Pulse
Generator

Subsystem

Clock

Generator

Main System

Clock

Generator

Oscillation
Stop

Frequency
Divider

· FIP Controller
· Basic Interval Timer (BT)
· Timer/Event Counter
· Serial Interface
· Watch Timer
· INT0 Noise Eliminator

· CPU
· INT0 Noise Eliminator
· INT1 Noise Eliminator

Wait Release Signal from BT

RES Signal (Internal Reset)

Standby Release Signal from
Interrupt Control Circuit

PCC2 and
PCC3
Clear

Internal Bus

PD75208

5.4

WATCH TIMER

The

PD75208 incorporates one channel of watch timer. The watch timer has the following functions:

· Sets the test flag (IRQW) at 0.5 sec intervals.

The standby mode can be released by IRQW.

· 0.5 second interval can be set with the main system clock and subsystem clock.

· The fast mode enables to set 128-time (3.91 ms) interval useful to program debugging and inspection.

The fixed frequencies (2.048 kHz) can be output to the P23/BUZ pin for use to generate buzzer sound

and trim the system clock oscillator frequency.

· Since the frequency divider can be cleared, the watch can be started from zero second.

Fig. 5-3 Watch Timer Block Diagram

Remarks Values at f

= 4.194304 MHz and f

= 32.768 kHz are indicated in parentheses.

Internal Bus

WM7 WM6

WM5

WM4

WM2

WM1

WM0

P23
Output
Latch

Port 2
Input/Output
Mode

PORT2.3

Bit 2 of PMGB

P23/BUZ

Output Buffer

Selector

Frequency Divider

Clear

(2.048 kHz)

(256 Hz : 3.91 ms)

(32.768 kHz)

Selector

From
Clock
Generator

128

(32.768 kHz)

INTW
IRQW
Set Signal

2Hz

0.5 sec

WM3

PD75208

5.6

TIMER/PULSE GENERATOR

The

PD75208 incorporates one channel of timer/pulse generator which can be used as a timer or a pulse

generator. The timer/pulse generator has the following functions:

(a)

Functions available in the timer mode

8-bit interval timer operation (IRQTPG generation) enabling the clock source to be varied at 5 levels

Square wave output to PPO pin

(b)

Functions available in the PWM pulse generate mode

14-bit accuracy PWM pulse output to the PPO pin (Used as a digital-to-analog converter and applicable

to tuning)

Fixed time interval ( = 7.81 ms : at 4.19 MHz operation) interrupt generation

If pulse output is not necessary, the PPO pin can be used as a 1-bit output port.

Note

If the STOP mode is set while the timer/pulse generator is in operation, erroneous operation may result.

To prevent that from occurring, preset the timer/pulse generator to the stop state using its mode

register.

Fig. 5-5 Block Diagram of Timer/Pulse Generator (Timer Mode)

MODL

MODH

TPGM3

1/2

TPGM1

TPGM4 TPGM5 TPGM7

PPO

INTTPG

Internal Bus

Modulo Register L (8)

Modulo Register H (8)

Modulo Latch H (8)

Comparator (8)

Count Register (8)

Clear

Prescalar Select Latch (5)

Clear

Frequency
Divider

(Set to "1")

Set

T F/F

Selector

Output Buffer

IRQTPG
Set Signal

Match

PD75208

Fig. 5-6 Timer/Pulse Generator Block Diagram (PWM Pulse Generate Mode)

5.7

SERIAL INTERFACE

The serial interface has the following functions:

· Clock synchronous 8-bit send/receive operation (simultaneous send/receive)

· Clock synchronous 8-bit serial bus operation (data input/output from the SO pin. N-ch open-drain SO output)

· Start LSB/MSB switching

These functions facilitate data communication with another microcomputer of

PD7500 series or 78K series via

a serial bus and coupling with peripheral devices.

TPGM1

TPGM3

MODH

MODL

MODH (8)

PPO

TPGM5

TPGM7

INTTPG

1/2

MODL

7-2

(6)

Internal Bus

Modulo Register H (8)

Modulo Register L (6)

Frequency Divider

Modulo Latch (14)

PWM Pulse Generator

Selector

Output Buffer

(IRQTPG Set Signal)

(2)

(

= 7.81 ms : at 4.19 MHz operation)

PD75208

5.8

FIP CONTROLLER/DRIVER

The on-chip FIP controller/driver has the following functions:

Generates the segment and digit signals by automatically reading the display data memory executing DMA

operation.

Can select up to a total of 26 display devices in the range of 9 to 12 segments and 9 to 16 digits.

Can apply the remaining display output as static output.

Can adjust the brightness at 8 levels using the dimmer function.

Can apply key scan operations.

Generates interrupt at the key scan timing (IRQKS)

Can generate key scan data output from the segment output pin.

Owns the high-voltage output pin (40 V) which can directly drive the FIP.

Segment special pins (S0 to S9) : V

= 40 V, I

= 3 mA

Digit output pins (T0 to T15)

: V

= 40 V, I

= 15 mA

Can incorporate pull-down resistors bit-wise as mask options.

Fig. 5-8 FIP Controller/Driver Block Diagram

Note

The FIP controller/driver can only operate in the high and intermediate-speeds (PCC = 0011B or 0010B) of

the main system clock (SCC.0 = 0). It may cause errors with any other clock or in the standby mode. Thus,

be sure to stop FIP controller operation (DSPM.3 = 0) and then shift the unit to any other clock mode or

the standby mode.

Dimmer
Select
Register

Digit
Select
Register

Display
Mode
Register

Key Scan
Flag (KSF)

IRQKS
Generation
Signal

Digit Signal Generator

Display Data Memory
(48

4 Bits)

Key Scan Registers
(KS0 and KS1)

Port H

Segment Data Latch (12)

Selector

PRE

T0-T9

T13/PH0-
T10/PH3

T15/S10 and
T14/S11

S0-S9

LOAD

Hige-Voltage Output Buffer

Internal Bus

PD75208

5.9

POWER-ON FLAG (MASK OPTION)

The power-on flag (PONF) is automatically set (1) when the power-on reset circuit is activated and the power-

on reset signal is generated. (See Fig. 8-1 Reset Signal Generator)

The PONF is mapped at bit 0 of address FD1H in the data memory space and can be tested by the memory bit

manipulation instructions (SKT, SKF, SKTCLR) or cleared (CLR1).

Note

The PONF cannot be set by SET1 instruction.

INTERRUPT FUNCTIONS

The

PD75208 has eight types of interrupt sources and can generate multiple interrupts with priority order.

It is also equipped with two types of test sources. INT2 is an edge detected testable input.

The

PD75208 interrupt control circuit has the following functions:

· Hardware-controller vectored interrupt function which can control interrupt acknowledge with the interrupt

enable flag (IE

×××

) and the interrupt master enable flag (IME).

· Function of setting any interrupt start address.

· Multiple interrupt function which can specify priority order with the interrupt priority select register (IPS).

· Interrupt request flag (IRQ

×××

) test function. (Interrupt generation can be checked by software.)

· Standby mode release function. (Interrupt to be released by interrupt enable flag can be selected.)

PD75208

STANDBY FUNCTIONS

Two standby modes (STOP mode and HALT mode) are available for the

PD75208 to decrease power consump-

tion in the program standby mode.

Table 7-1 Operation Status in Standby Mode

RESET FUNCTIONS

The reset signal (RES) generator has a configuration shown in Fig. 8-1.

Fig. 8-1 Reset Signal Generator

The power-on reset generator is a circuit to generate a one-shot pulse upon detection of the start-up of the power

voltage. This pulse is used in three ways according to SWA, SWB mask option specification shown in Fig. 8-1. (See

10. MASK OPTION SELECTION.)

HALT Mode

HALT instruction

Setting enabled with either main system

clock or subsystem clock.

Stops only with CPU clock

(Oscillation

continued).

Operation (IRQBT set at reference time

intervals).

Operation enabled when serial clock other

than

is specified.

Operation enabled.

Set instruction

System clock when set

Clock oscillator

Basic interval timer

Serial interface

Timer/event counter

Timer/pulse generator

Watch timer

FIP controller/driver

CPU

STOP Mode

STOP instruction

Setting enabled only with main system

clock.

Oscillator stops only with main system

clock.

Operation stopped.

Operation enabled only when external

SCK input is selected for serial clock.

Operation enabled only when TI0 pin

input is specified for count clock.

Operation stopped.

Operation enabled only f

is selected for

count clock.

Operating State

Operation disabled (display off mode set before disabling).

Operation stopped.

Release signal

Interrupt request signal (except INT0, INT1, INT2) or RESET input enabled by

interrupt enable flag.

RESET

Power-On
Reset
Generator

Mask
Option

Internal Reset Signal
(RES)

Power-On Flag
(PONF)

Internal Bus

Bit
Manipulation
Instruction
Execution

SWA

SWB

PD75208

INSTRUCTION SET

(1)

Operand identifier and description

Enter an operand in the operand column of each instruction using the description method relating to the

operand identifier of the instruction (refer to RA75X Assembler Package User's Manual, Language (EEU-730)

for details). If more than one description method is available, select one. Capital alphabetic letters, plus and

minus signs are keywords. Describe them as they are.

In the case of immediate data, describe appropriate numerical values or labels.

For 8-bit data processing, only even addresses can be specified.

Identifier

Description Method

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL-, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label*

bit

2-bit immediate data or label

fmem

FB0H to FBFH and FF0H to FFFH immediate data or labels

pmem

FC0H to FFFH immediate data or labels

addr

0000H to 1F7FH immediate data or labels

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H to 7FH immediate data (bit0 = 0) or label

PORTn

PORT0 to PORT6

×××

IEBT, IESIO, IET0, IETPG, IE0, IE1, IEKS, IEW, IE4

RBn

RB0 to RB3

MBn

MB0, MB1, MB15

PD75208

(2)

Legend for operation description

: A register; 4-bit accumulator

: B register

: C register

: D register

: E register

: H register

: L register

: X register

: Register pair (XA); 8-bit accumulator

: Register pair (BC)

: Register pair (DE)

: Register pair (HL)

XA'

: Expanded register pair (XA')

BC'

: Expanded register pair (BC')

DE'

: Expanded register pair (DE')

HL'

: Expanded register pair (HL')

: Program counter

: Stack pointer

: Carry flag; Bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn

: Port n (n = 0 to 6)

IME

: Interrupt master enable flag

IPS

: Interrupt priority select register

×××

: Interrupt enable flag

RBS

: Register bank select register

MBS

: Memory bank select register

PCC

: Processor clock control register

: Address and bit delimiter

(

××

)

: Contents addressed by

××

: Hexadecimal data

PD75208

(3)

Description of symbols in the addressing area column

Remarks

MB indicates accessible memory bank.

In *2, MB = 0 irrespective of MBE and MBS.

In *4 and *5, MB = 15 irrespective of MBE and MBS.

*6 to *10 indicate addressable areas.

(4)

Description of the machine cycle column

S indicates the number of machine cycles required for skip operation by an instruction having skip function.

The S value varies as follows:

· When not skipped ................................................................................................... S = 0

· When 1-byte or 2-byte instructions are skipped ................................................. S = 1

· When 3-byte instructions are skipped (BR !addr, CALL !addr instruction) ..... S = 2

Note

GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle(=t

) of CPU clock

and three time periods are available according

to PCC setting.

Data Memory

Addressing

Program Memory

Addressing

* 1

MB = MBE · MBS

(MBS = 0, 1, 15)

* 2

MB = 0

* 3

MBE = 0 : MB = 0 (00H to 7FH)

MB = 15 (80H to FFH)

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

* 4

MB = 15, fmem = FB0H to FBFH,

FF0H to FFFH

* 5

MB = 15, pmem = FC0H to FFFH

* 6

addr = 0000H to 1F7FH

* 7

addr = (Current PC) 15 to (Current PC) 1,

(Current PC) + 2 to (Current PC) + 16

* 8

caddr = 0000H to 0FFFH

(PC

= 0) or

1000H to 1F7FH

(PC

= 1)

* 9

faddr = 0000H to 07FFH

*10

taddr = 0020H to 007FH

PD75208

A, #n4

Stack A

reg1, #n4

reg1

XA, #n8

Stack A

HL, #n8

Stack B

rp2, #n8

rp2

A, @HL

(HL)

A, @HL+

2 + S

(HL), then L

L+1

L = 0

A, @HL

2 + S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A, mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg

reg

XA, rp'

rp'

reg1, A

reg1

rp'1, XA

rp'1

A, @HL

(HL)

A, @HL+

2 + S

(HL), then L

L+1

L = 0

A, @HL

2 + S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

A, mem

(mem)

XA, mem

(mem)

A, reg1

reg1

XA, rp'

rp'

XA, @PCDE

(PC

128

+DE)

ROM

XA, @PCXA

(PC

128

+XA)

ROM

Machine

Cycle

Skip

Condition

Addressing

Area

No. of

Bytes

Transfer

Note

1. Instruction Group

2. Table reference

Mnemonic

Operands

Operation

Note 1

MOV

XCH

MOVT

Note 2

PD75208

Machine

Cycle

Skip

Condition

Addressing

Area

No. of

Bytes

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

fmem.bit, CY

(fmem.bit)

pmem.@L, CY

(pmem

.bit(L

))

@H+mem.bit, CY

(H+mem

.bit)

A, #n4

1 + S

A+n4

carry

XA, #n8

2 + S

XA+n8

carry

A, @HL

1 + S

A+(HL)

carry

XA, rp'

2 + S

XA+rp'

carry

rp'1, XA

2 + S

rp'1

rp'1+XA

carry

A, @HL

A, CY

A+(HL)+CY

XA, rp'

XA, CY

XA+rp'+CY

rp'1, XA

rp'1, CY

rp'1+XA+CY

A, @HL

1 + S

A(HL)

borrow

XA, rp'

2 + S

XArp'

borrow

rp'1, XA

2 + S

rp'1

rp'1XA

borrow

A, @HL

A, CY

A(HL)CY

XA, rp'

XA, CY

XArp'CY

rp'1, XA

rp'1, CY

rp'1XACY

A, #n4

A n4

A, @HL

A (HL)

XA, rp'

XA rp'

rp'1, XA

rp'1

rp'1 XA

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

Bit transfer

Operation

Note

Instruction Group

Mnemonic

Operand

Operation

Note

MOV1

ADDS

ADDC

SUBS

SUBC

AND

XOR

PD75208

, A

CY, A

reg

1 + S

reg

reg+1

reg = 0

rp1

1 + S

rp1

rp1+1

rp1 = 00H

@HL

2 + S

(HL)

(HL)+1

(HL) = 0

mem

2 + S

(mem)

(mem)+1

(mem) = 0

reg

1 + S

reg

reg1

reg = FH

rp'

2 + S

rp'

rp'1

rp = FFH

reg, #n4

2 + S

Skip if reg = n4

reg = n4

@HL, #n4

2 + S

Skip if (HL) = n4

(HL) = n4

A, @HL

1 + S

Skip if A = (HL)

A = (HL)

XA, @HL

2 + S

Skip if XA = (HL)

XA = (HL)

A, reg

2 + S

Skip if A = reg

A = reg

XA, rp'

2 + S

Skip if XA = rp'

XA = rp'

1 + S

Skip if CY = 1

CY = 1

Machine

Cycle

Skip

Condition

Addressing

Area

No. of

Bytes

RORC

NOT

Note 2

Increment/decrement

Compare

SET1

CLR1

SKT

NOT1

Carry flag

manipulation

Note

1. Instruction Group

2. Accumulator manipulation

Operands

Mnemonic

Operation

Note 1

INCS

DECS

SKE

PD75208

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

.bit(L

))

@H + mem.bit

(H+mem

.bit)

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

.bit(L

))

@H+mem.bit

(H+mem

.bit)

mem.bit

2 + S

Skip if (mem.bit) = 1

(mem.bit) = 1

fmem.bit

2 + S

Skip if (fmem.bit) = 1

(fmem.bit) = 1

pmem.@L

2 + S

Skip if (pmem

.bit(L

)) = 1

(pmem.@L) = 1

@H+mem.bit

2 + S

Skip if (H+mem

.bit) = 1

(@H+mem.bit) = 1

mem.bit

2 + S

Skip if (mem.bit) = 0

(mem.bit) = 0

fmem.bit

2 + S

Skip if (fmem.bit) = 0

(fmem.bit) = 0

pmem.@L

2 + S

Skip if (pmem

.bit(L

)) = 0

(pmem.@L) = 0

@H+mem.bit

2 + S

Skip if (H+mem

.bit) = 0

(@H+mem.bit) = 0

fmem.bit

2 + S

Skip if (fmem.bit) = 1 and clear

(fmem.bit) = 1

pmem.@L

2 + S

Skip if (pmem

.bit(L

))=1 and clear

(pmem.@L) = 1

@H+mem.bit

2 + S

Skip if (H+mem

.bit)=1 and clear

(@H+mem.bit)=1

CY, fmem.bit

CY (fmem.bit)

CY, pmem.@L

CY (pmem

.bit(L

))

CY, @H+mem.bit

CY (H+mem

.bit)

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

addr

120

addr

(Optimum instruction is

selected from among BR !addr,

BRCB !caddr and BR $addr by an

assembler.)

!addr

120

addr

$addr

120

addr

!caddr

120

+caddr

110

PCDE

120

128

+DE

PCXA

120

128

+XA

Machine

Cycle

Skip

Condition

Addressing

Area

No. of

Bytes

Memory bit manipulation

BRCB

Branch

Note

Instruction Group

Mnemonic

Operands

Operation

Note

SET1

CLR1

SKT

SKF

SKTCLR

AND1

OR1

XOR1

PD75208

!addr

(SP4) (SP1) (SP2)

110

(SP3)

MBE, RBE, 0, PC

120

addr, SP

SP4

!faddr

(SP4) (SP1) (SP2)

110

(SP3)

MBE, RBE, 0, PC

120

00, faddr, SP

SP4

MBE, RBE, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

SP+4

MBE, RBE, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

SP+4

then skip unconditionally

, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

(SP1) (SP2)

rp, SP

SP2

(SP1)

MBS, (SP2)

RBS, SP

SP2

(SP+1) (SP), SP

SP+2

MBS

(SP+1), RBS

(SP), SP

SP+2

IME(IPS.3)

×××

IME(IPS.3)

×××

A, PORTn

PORTn

(n = 0 to 6)

XA, PORTn

PORTn+1, PORTn

(n = 4)

PORTn, A

PORTn

(n = 2 to 6)

PORTn, XA

PORTn+1, PORTn

(n = 4)

Set HALT Mode (PCC.2

Set STOP Mode (PCC.3

No Operation

RBn

RBS

n (n = 0 to 3)

MBn

MBS

n (n = 0, 1, 15)

Machine

Cycle

Skip

Condition

Addressing

Area

No. of

Bytes

Subroutine stack control

Interrupt

control

Input/output

CPU control

HALT

STOP

NOP

MBE = 0 or MBE = 1 and MBS = 15 must be set for execution of IN/OUT instruction

Note

Instruction Group

Special

Mnemonic

Operands

Operation

Note

3 + S

CALL

CALLF

RET

RETS

RETI

PUSH

POP

OUT

SEL

Unconditional

PD75208

10. MASK OPTION SELECTION

The

PD75208 has the following mask options enabling or disabling on-chip components.

(1)

Pin

Note

1. In a system not using subsystem clocks, power consumption in the STOP mode can be decreased by

removing the feedback resistor from the oscillator.

2. The feedback resistor must be incorporated when the subsystem clock is used.

(2)

Power-on reset generator, power-on flag (PONF)

One of the following three can be selected.

Mask Option

P60 to P63

T0/T9

T10/PH3 to T13/PH0

T14/S11, T15/S10

S0 to S9

XT1, XT2

Pull-up resistor incorporation enabled bit-wise

Deletion of subsystem clock oscillator feedback resistor

possible

Switch Selection

(See Fig. 8-1)

SWA

SWB

OFF

Incorporated

Not incorporated

Incorporated

Not incorporated

Generate automatically

Not generate automatically

Power-On Reset Generator

Power-On Flag (PONF)

Internal Reset Signal (RES)

PD75208

LOAD

PRE

opt

stg

UNIT

RATING

TEST CONDITIONS

Power supply voltage

Input voltage

Output voltage

Output current high

Output current low

Total loss*1

Operating temperature

Storage temperature

Pins except display output pins

Display output pins

1 pins except display output pins

S0 to S9

1 pin

T0 to T15

1 pin

Total of pins except display output pins

Total of display output pins

1 pin

Total of pins

Plastic QFP

Plastic shrink DIP

0.3 to +7.0

40 to V

+0.3

12 to V

+0.3

0.3 to V

+0.3

0.3 to V

+0.3

40 to V

+0.3

120

450

600

40 to +85

65 to +150

SYMBOL

PARAMETER

CPU *2

Display controller

Time/pulse generator

Other hardware *2

TEST CONDITIONS

MIN.

4.5

2.7

MAX.

UNIT

6.0

12. ELECTRICAL SPECIFICATIONS

POWER SUPPLY VOLTAGE RANGE (Ta = 40 to +85

ABSOLUTE MAXIMUM RATINGS (Ta = 25

PD75208

(30 + 5.5 V)

40 k

10 = 315 mW

2 V

10 mA

4 = 53 mW

1. Calculation of total loss

Design so that the sum of the following three power consumption values for the

PD75208CW/GF will be less

than the total loss P

(It is recommended to use the system with 80 % or less of the rating).

CPU loss

: Given as V

(MAX.)

DD1

(MAX.)

Output pin loss

: There are normal output pin loss and display output pin loss. It is necessary

to add a loss derived from the flow of maximum current to each output pin.

Pull-down register loss : Power loss due to a pull-down resistor incorporated in the display output pin

by mask option.

Example

Suppose 4-LED output with 9

SEG

DIGIT

, V

= 5 V + 10 % and 4.19 MHz oscillation and let a maximum

of 3 mA, 15 mA and 10 mA flow to the segment pin, timing pin and LED output pin, respectively.

Further, let the voltage of fluorescent display tube (V

LOAD

voltage) be 30 V and normal voltage be small.

CPU loss : 5.5 V

9.0 mA = 49.5 mW

Pin loss

: Segment pin ..... 2 V

3 mA

9 = 54 mW

Timing pin ......... 2 V

15 mA = 30 mW

LED output ........

Pull-down resistor loss ........

= + + = 501.5 mW

In this example, the power consumption of 501.5 mW is less than the allowable total loss for the shrink

DIP package (600 mW). However, since the allowable total loss is 450 mW for the QFP package, it is

necessary to decrease power consumption by decreasing the number of on-chip pull-down resistors. In

this example, power consumption can be adjusted to 344 mW by incorporating pull-down resistors in

only 11 digit outputs and 4 segment outputs and externally mounting pull-down resistors to the 5

remaining segment outputs.

2. Except the system clock oscillator, display controller and timer/pulse generator.

3. The operating voltage range varies depending on the cycle time. Refer to the section describing AC

characteristics.

PD75208

= Oscillation

voltage range

After V

reaches the

minimum value in
the oscillation
voltage range

= 4.5 to 6.0 V

Oscillator frequency
(f

) *2

Oscillation
stabilization time *3

Oscillator frequency
(f

) *2

Oscillation stabilization
time *3

X1 input frequency
(f

) *2

X1 input high and low
level widths (t

, t

)

2.0

100

4.19

5.0*4

5.0 *4

5.0*4

250

MHz

MIN.

TYP.

MAX.

UNIT

TEST CONDITIONS

PARAMETER

RECOMMENDED CIRCUIT

RESONATOR

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

Oscillator frequency
(f

) *2

Oscillation stabilization
time *3

XT1 input frequency
(f

)

XT1 input high and low
level widths (t

XTH

, t

XTL

)

= 4.5 to 6.0 V

32.768

1.0

100

kHz

Ceramic
resonator*1

Crystal
resonator*1

External
clock

Crystal
resonator*1

External
clock

MIN.

TYP.

MAX.

UNIT

TEST CONDITIONS

PARAMETER

RECOMMENDED CIRCUIT

RESONATOR

PD74HCU04

XT1

Leave Open

XT2

XT1

XT2

330 k

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

1. Resonators are shown in the following page.

2. Oscillator characteristics only. Refer to the description of AC characteristics for details of instruction execution

time.

3. Time required for oscillation to become stabilized after V

application or STOP mode release.

4. When oscillator frequency is " 4.19 < f

5.0 MHz ", do not select " PCC = 0011 " as instruction execution time.

If " PCC = 0011 " is selected, 1 machine cycle becomes less than 0.95

s, with the result that the specified MIN.

value of 0.95

s cannot be observed.

1. Recommended resonators are shown in the following page.

2. Oscillator characteristics only. Refer to the description of AC characteristics for instruction execution time.

3. Oscillation stabilization time is a time required for oscillation to become stabilized after V

application or

STOP mode release.

PD75208

Input capacitance

Except display output

Display output

Input /output capacitance

UNIT

Output capacitance

PARAMETER

SYMBOL

MAX.

TYP.

MIN.

TEST CONDITIONS

f = 1 MHz
Unmeasured pin returned
to 0V

OUT

4.19

HC49/U

MANUFACTURER

FREQUENCY

(MHz)

HOLDER

Kinseki

EXTERNAL

CAPACITANCE (pF)

OSCILLATION

VOLTAGE RANGE (V)

MIN.

MAX.

2.7

6.0

MANUFACTURER

PRODUCT NAME

CAPACITANCE (Ta = 25

C, V

= 0 V)

RECOMMENDED OSCILLATOR CONSTANTS

MAIN SYSTEM CLOCK : CERAMIC RESONATOR (Ta = 40 to +85

MAIN SYSTEM CLOCK : CRYSTAL RESONATOR (Ta = 40 to +85

Note

Carry out fine adjustment of crystal resonator frequency with external capacitance C1 of 10 to 33 pF.

CSA 4.19MG

KBR2.09MS

KBR3.58MS

KBR4.19MS

KBR4.9M

MIN.

MAX.

EXTERNAL

CAPACITANCE (pF)

OSCILLATION

VOLTAGE RANGE (V)

Murata Mfg. Co., Ltd.

Kyocera Corp.

4.0

6.0

4.0

6.0

PD75208

DC CHARACTERISTICS (Ta = 40 to +85

C, V

= 2.7 to 6.0 V)

0.4

5.5

3.5

3.0

0.55

600

200

0.5

0.1

IH1

IH2

IH3

IL1

IL2

IL3

LIH1

LIH2

LIL1

LIL2

LOH

LOL1

LOL2

All output pins

Display output

Except display output

X1, X2, XT1

= 4.5 to 6.0V, I

= 1 mA

= 4.5 to 6.0V, I

= 15 mA

= 4.5 to 6.0V, I

= 1.6 mA

All output pins

Except below

Ports 0, 1, 6, RESET

X1, X2, XT1

Except below

Ports 0, 1, RESET

X1, X2, XT1

PARAMETER

SYMBOL

TEST CONDITIONS

Port 6

IH4

Input voltage high

Input Voltage low

= 4.5 to 6.0 V

= 100

Output voltage high

Ports 4, 5

= 400

All output pins

Except X1,X2,XT1

Output voltage low

Input leakage current
high

S0 to S9

T0 to T15

= V

= 0 V

OUT

= V

OUT

= 0 V

OUT

= V

LOAD

= V

35 V

4.5 to 6.0 V

2 V

PRE

= V

1 V*1

PRE

= 0 V

PRE

= 0 V

PRE

= V

1 V*1

Port 6
V

= V

= 4.5 to 6.0 V

Display output

LOAD

= 35 V

= 5 V

10 %*3

= 3 V

10 %*4

= 5 V

10 %

= 3 V

10 %

= 3 V

10 %

HALT mode

HALT mode V

= 3 V

10 %

= 5 V

10 %

= 3 V

10 %

4.19 MHz
crystal
oscillation
C1 = C2 =
15pF

32 kHz crystal
oscillation*5

XT1 = 0 V
STOP mode

DD5

DD4

DD3

DD2

DD1

Input leakage current
low

Output leakage current high

Output leakage current
low

Display output current

Built-in pull-down

resistor (mask option)

Supply current*2

MIN.

TYP.

0.3V

0.2V

0.4

2.0

0.4

0.5

200

1000

120

9.0

1.5

1800

600

120

MAX.

UNIT

0.7V

0.75V

0.4

0.65V

0.7V

1.0

0.5

1.5

PD75208

Power-on reset
operating voltage high

Power-on reset
operating voltage low

Power supply voltage
off time

Power supply voltage
rise time

Power-on reset circuit*2
current consumption

DDH

DDL

off

DDPR

= 5 V

10 %

= 2.7 V

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

4.5

6.0

0.2

100

PRE

LOAD

RD9. 1EL

68 k

+5 V

30 V

RD9. 1EL : Zener Diode (NEC)

Zener Voltage = 8.29 to 9.30 V

PD75208

DDH

DDL

off

1. The following external circuit is recommended.

2. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.

3. When the processor clock control register (PCC) is set to 0011 and is operated in the high-speed mode.

4. When the PCC register is set to 0000 and is operated in the low-speed mode.

5. When the system clock control register (SCC) is set to 1001 and is operated with the subsystem clock with

main system clock oscillation stopped.

POWER-ON RESET CIRCUIT CHARACTERISTICS (MASK OPTION) (Ta = -40 to +85

1. 2

(31.3 ms at f

= 4.19 MHz)

2. Current with on-chip power-on reset circuit or power-on flag.

Remarks

Start the power supply smoothly.

PD75208

AC CHARACTERISTICS (Ta = 40 to +85

C , V

= 2.7 to 6.0 V)

Input

Output

Input

Output

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Operation with main
system clock

Operation with sub-
system clock

CPU clock cycle time
(minimum instruction
execution time = 1
machine cycle) *1

TI0 input frequency

= 4.5 to 6.0 V

TI0 input high and low-
level widths

= 4.5 to 6.0 V

Input

Output

Input

Output

= 4.5 to 6.0 V

INT0

INT1

INT2, 4

TIH

TIL

KCY

RSL

INTH

INTL

KSO

KSI

SIK

RESET low-level width

Interrupt input high and
low-level widths

SCK cycle time

SCK high and low-level
widths

SI setup time (to SCK

)

SI hold time (from SCK

)

SO output delay time
from SCK

0.95

3.8

114

0.83

0.8

0.95

3.2

3.8

0.4

KCY

/250

1.6

KCY

/2150

100

400

300

1000

122

125

0.6

165

MHz

kHz

PD75208

DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = 40

to +85

2.0

6.0

DDDR

= 2.0V

0.1

Release by RESET

Release by interrupt request

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Data retention power

supply voltage

Data retention power

supply current *1

SREL

WAIT

DDDR

Release signal set time

Oscillation stabilization

wait time *2

1. Current to the on-chip pull-down resistor and power-on reset circuit (mask option) is not included.

2. Oscillation stabilization wait time is time to stop CPU operation to prevent unstable operation upon oscillation

start.

3. According to the setting of the basic interval timer mode register (BTM) (see below).

BTM3

BTM2

BTM1

BTM0

Wait Time (Values at f

= 4.19 MHz in parentheses)

(approx. 250 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

Data Retention Timing (STOP Mode Release by RESET)

STOP Instruction Execution

DDDR

Operating Mode

HALT Mode

STOP Mode

Data Retention Mode

WAIT

RESET

SREL

Internal Reset Operation

PD75208

64 PIN PLASTIC QFP (14

20)

P64GF-100-3B8,3BE,3BR-2

ITEM

MILLIMETERS

INCHES

23.6±0.4

20.0±0.2

14.0±0.2

0.929±0.016

0.795

0.551

17.6±0.4

0.693±0.016

1.0

0.039

1.0

0.039

0.40±0.10

0.016

0.20

0.008

1.0 (T.P.)

0.039 (T.P)

1.8±0.2

0.071

0.8±0.2

0.031

0.15

0.006

0.10

0.004

2.7

0.106

0.1±0.1

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

+0.008

0.009

+0.009

0.008

+0.004

0.005

+0.008

0.009

+0.009

0.008

+0.004

0.003

NOTE

Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.

detail of lead end

+0.10

0.05

PD75208

Recommended

Condition Symbol

Soldering Method

Soldiering Conditions

Solder bath temperature: 260

C or less, Duration: 10 sec. max.

Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required

at 125

Preheating temperature : 120

C max. (package surface temperature)

Package peak temperature: 230

C, Duration: 30 sec. max. (at 210

C or above),

Number of times: Once, Time limit: 7 days*(thereafter 10 hours prebaking required

at 125

Package peak temperature: 215

C, Duration: 40 sec. max. (at 200

C or above),

Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required

at 125

Pin part temperature: 300

C or below , Duration: 3 sec. max. (per device side)

Pin part heating

VPS

Infrared reflow

Wave soldering

VP15-107-1

IR30-107-1

WS60-107-1

Table 15-2 Insertion Type Soldering Conditions

PD75208CW-

×××

: 64-pin plastic shrink DIP (750 mil)

PD75208GF-

×××

-3BE : 64-pin plastic QFP (body 14

20 mm)

Soldering Method

Soldering Conditions

Wave soldering

(lead part only)

Solder bath temperature: 260

C or below , Duration: 10 sec. max.

Pin part temperature: 260

C or below , Duration: 10 sec. max.

Pin part heating

Note

Ensure that the application of wave soldering is limited to the lead part and no solder touches the main

unit directly.

15. RECOMMENDED SOLDERING CONDITIONS

This product should be soldered and mounted under the conditions recommended below.

For details of recommended soldering conditions for the surface mounting type, refer to the document

"Semiconductor Device Mount Technology" (IEI-1207).

For soldering methods and conditions other than those recommended below, contact our salesman.

Table 15-1 Surface Mounting Type Conditions

For the storage period after dry-pack decompression storage conditions are max. 25

C, 65 % RH.

Note Use of more than one soldering method should be avoided (except in the case of pin part heating).

PD75208

APPENDIX A DEVELOPMENT TOOLS

The following development tools are provided for developing systems including the

PD75208:

1. Maintenance service only

2. Not contained in the IE-75001-R

3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and Ver. 5.00A.

In-circuit emulator for the 75X series

Emulation board for the IE-75000-R and IE-75001-R

Emulation probe for the

PD75216ACW

Emulation probe for the

PD75216AGF. A 64-pin conversion socket, the EV-9200G-64, is attached

to the probe.

PROM programmer

PROM programmer adapter for the

PD75P216ACW and

PD75P218CW. Connected to the

PG-1500.

PROM programmer adapter for the

PD75P218GF. Connected to the PG-1500.

PROM programmer adapter for the

PD75P218KB. Connected to the PG-1500.

IE-75000-R *1

IE-75001-R

IE-75000-R-EM *2

EP-75216ACW-R

EP-75216AGF-R

PG-1500

PA-75P216ACW

PA-75P218GF

PA-75P218KB

EV-9200G-64

IE control program

PG-1500 controller

RA75X relocatable

assembler

Host machine

· PC-9800 series (MS-DOS

Ver. 3.30 to Ver. 5.00A *3)

· IBM PC series (PC DOS

Ver. 3.1)

Software

Hardware

PD75208

User's manual

Application note

75X series selection guide

Document Name

Document No.

IEU-1294

IEM-1294

IF-1027

APPENDIX B RELATED DOCUMENTS

Documents related to the device

Documents related to development tools

Hardware

IE-75000-R User's Manual

IE-75001-R User's Manual

IE-75000-R-EM User's Manual

EP-75216ACW-R User's Manual

EP-75216AGF-R User's Manual

PG-1500 User's Manual

Document Name

RA75X Assembler Package

User's Manual

Operation

Language

PC-9800 series

(MS-DOS) base

IBM PC series

(PC DOS) base

Software

Document No.

EEU-1297

EEU-1416

EEU-1294

EEU-1321

EEU-1309

EEU-1335

EEU-1346

PG-1500 Controller User's Manual

EEU-1363

EEU-1291

Other documents

PACKAGE MANUAL

SMD SURFACE MOUNT TECHNOLOGY MANUAL

QUALITY GRADES ON NEC SEMICONDUCTOR DEVICES

NEC SEMICONDUCTOR DEVICE RELIABILITY/QUALITY CONTROL SYSTEM

ELECTROSTATIC DISCHARGE (ESD) TEST

GUIDE TO QUALITY ASSURANCE FOR SEMICONDUCTOR DEVICES

Document Name

Document No.

IEI-1213

IEI-1207

IEI-1209

IEI-1203

IEI-1201

MEI-1202

Note

The above documents may be revised without notice. Use the latest versions when you design an

application system.

PD75208

Cautions on CMOS Devices

Countermeasures against static electricity for all MOSs

Caution

When handling MOS devices, take care so that they are not electrostatically charged.

Strong static electricity may cause dielectric breakdown in gates. When transporting or

storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal

cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during

assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.

Also handle boards on which MOS devices are mounted in the same way.

CMOS-specific handling of unused input pins

Caution

Hold CMOS devices at a fixed input level.

Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an

intermediate-level input may be caused by noise. This allows current to flow in the CMOS

device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input

level. Since unused pins may function as output pins at unexpected times, each unused

pin should be separately connected to the V

or GND pin through a resistor.

If handling of unused pins is documented, follow the instructions in the document.

Statuses of all MOS devices at initialization

Caution

The initial status of a MOS device is unpredictable when power is turned on.

Since characteristics of a MOS device are determined by the amount of ions implanted

in molecules, the initial status cannot be determined in the manufacture process. NEC

has no responsibility for the output statuses of pins, input and output settings, and the

contents of registers at power on. However, NEC assures operation after reset and items

for mode setting if they are defined.

When you turn on a device having a reset function, be sure to reset the device first.

[MEMO]

PD75208

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights

or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear

reactor control systems and life support systems. If customers intend to use NEC devices for above applications

or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact

our sales people in advance.

Application examples recommended by NEC Corporation

Standard :

Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime systems, etc.

M4 92.6

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights

or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear

reactor control systems and life support systems. If customers intend to use NEC devices for above applications

or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact

our sales people in advance.

Application examples recommended by NEC Corporation

Standard :

Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime systems, etc.

EEPROM

is a trademark of NEC Corporation.

FIP is a trademark of NEC Corporation.

MS-DOS

is a trademark of Microsoft Corporation.

PC DOS

is a trademark of IBM Corporation.

Document Outline

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Document Outline

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