Document Outline

1. PIN CONFIGURATION (Top View)
2. BLOCK DIAGRAM
3. PIN FUNCTIONS
- 3.1 Port Pins
- 3.2 Non-port Pins
- 3.3 Pin Input/Output Circuits
- 3.4 Recommended Connections for Unused Pins
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
- 4.1 Difference between Mk I Mode and Mk II Mode
- 4.2 Setting Method of Stack Bank Select Register (SBS)
5. MEMORY CONFIGURATION
6. PERIPHERAL HARDWARE FUNCTION
- 6.1 Digital I/O Port
- 6.2 Clock Generator
- 6.3 Subsystem Clock Oscillator Control Functions
- 6.4 Clock Output Circuit
- 6.5 Basic Interval Timer/Watchdog Timer
- 6.6 Watch Timer
- 6.7 Timer/Event Counter
- 6.8 Serial Interface
- 6.9 LCD Controller/Driver
- 6.10 Bit Sequential Buffer
7. INTERRUPT FUNCTION AND TEST FUNCTION
8. STANDBY FUNCTION
9. RESET FUNCTION
10. MASK OPTION
11. INSTRUCTION SET
12. ELECTRICAL SPECIFICATIONS
13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
14. PACKAGE DRAWINGS
15. RECOMMENDED SOLDERING
APPENDIX A. uPD75308B, 753108 AND 75P3116 FUNCTIONAL LIST
APPENDIX B. DEVELOPMENT TOOLS
APPENDIX C. RELATED DOCUMENTS

4-BIT SINGLE-CHIP MICROCONTROLLER

The

PD753108 is one of the 75XL Series 4-bit single-chip microcontroller chips and has a data processing

capability comparable to that of an 8-bit microcontroller.

The existing 75X Series containing an LCD controller/driver supplies an 80-pin package.

The

PD753108 supplies a 64-pin package (12 x 12 mm), which is suitable for small-scale systems.

It features expanded CPU functions and can provide high-speed operation at a low supply voltage of 1.8 V

compared with the existing

PD75308B.

For detailed function descriptions, refer to the following user's manual. Be sure to read the document

before designing.

PD753108 User's Manual: U10890E

Features

Low voltage operation: V

= 1.8 to 5.5 V

· Can be driven by two 1.5-V batteries

On-chip memory

· Program memory (ROM):

4096 x 8 bits (

PD753104)

6144 x 8 bits (

PD753106)

8192 x 8 bits (

PD753108)

· Data memory (RAM):

512 x 4 bits

Capable of high-speed operation and variable instruction execution time for power saving

· 0.95, 1.91, 3.81, 15.3

s (@ 4.19 MHz with main system clock)

· 0.67, 1.33, 2.67, 10.7

s (@ 6.0 MHz with main system clock)

· 122

s (@ 32.768 kHz with subsystem clock)

Internal programmable LCD controller/driver

Small package:

64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

One-time PROM version:

PD75P3116

Application

Remote controllers, cameras, hemadynamometers, electronic scale, gas meters, etc.

Unless otherwise indicated, references in this data sheet to the

PD753108 mean the

PD753104 and

PD753106.

MOS INTEGRATED CIRCUIT

PD753104, 753106, 753108

1995

DATA SHEET

The mark shows major revised points.

Document No.

U10086EJ3V0DS00 (3rd edition)

Date Published April 1997 N
Printed in Japan

The information in this document is subject to change without notice.

PD753104, 753106, 753108

Functional Outline

Parameter

Function

Instruction execution time

· 0.95, 1.91, 3.81, 15.3

s (@ 4.19 MHz with main system clock)

· 0.67, 1.33, 2.67, 10.7

s (@ 6.0 MHz with main system clock)

· 122

s (@ 32.768 kHz with subsystem clock)

On-chip memory

ROM

4096 x 8 bits (

PD753104)

6144 x 8 bits (

PD753106)

8192 x 8 bits (

PD753108)

RAM

512 x 4 bits

General-purpose register

· 4-bit operation: 8 x 4 banks

· 8-bit operation: 4 x 4 banks

Input/

CMOS input

On-chip pull-up resistors which can be specified by software: 7

output

CMOS input/output

On-chip pull-up resistors which can be specified by software: 12

port

Also used for segment pins: 8

N-ch open-drain

On-chip pull-up resistors which can be specified by mask option, 13-V withstand

input/output pins

voltage

Total

LCD controller/driver

· Segment selection:

16/20/24 segments (can be changed to CMOS input/

output port in 4 time-unit; max. 8)

· Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias),

1/3 duty (1/3 bias), 1/4 duty (1/3 bias)

· On-chip split resistor for LCD drive can be specified by mask option

Timer

5 channels

· 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator,

timer with gate)

· Basic interval timer/watchdog timer: 1 channel

· Watch timer: 1 channel

Serial interface

· 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

· 2-wire serial I/O mode

· SBI mode

Bit sequential buffer (BSB)

16 bits

Clock output (PCL)

, 524, 262, 65.5 kHz (@ 4.19 MHz with main system clock)

, 750, 375, 93.8 kHz (@ 6.0 MHz with main system clock)

Buzzer output (BUZ)

· 2, 4, 32 kHz

(@ 4.19 MHz with main system clock or

@ 32.768 kHz with subsystem clock)

· 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)

Vectored interrupt

External: 3, Internal: 5

Test input

External: 1, Internal: 1

System clock oscillator

· Ceramic or crystal oscillator for main system clock oscillation

· Crystal oscillator for subsystem clock oscillation

Standby function

STOP/HALT mode

Supply voltage

= 1.8 to 5.5 V

Package

· 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)

· 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

PD753104, 753106, 753108

CONTENTS

PIN CONFIGURATION (Top View) ...................................................................................................... 6

BLOCK DIAGRAM ................................................................................................................................ 8

PIN FUNCTIONS ...................................................................................................................................9

3.1

Port Pins ...................................................................................................................................... 9

3.2

Non-port Pins ............................................................................................................................ 11

3.3

Pin Input/Output Circuits ......................................................................................................... 13

3.4

Recommended Connections for Unused Pins ....................................................................... 15

SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 16

4.1

Difference between Mk I Mode and Mk II Mode ......................................................................16

4.2

Setting Method of Stack Bank Select Register (SBS) ........................................................... 17

MEMORY CONFIGURATION ............................................................................................................. 18

PERIPHERAL HARDWARE FUNCTION ........................................................................................... 23

6.1

Digital I/O Port ........................................................................................................................... 23

6.2

Clock Generator ........................................................................................................................23

6.3

Subsystem Clock Oscillator Control Functions .................................................................... 25

6.4

Clock Output Circuit .................................................................................................................26

6.5

Basic Interval Timer/Watchdog Timer ..................................................................................... 27

6.6

Watch Timer .............................................................................................................................. 28

6.7

Timer/Event Counter .................................................................................................................29

6.8

Serial Interface ..........................................................................................................................33

6.9

LCD Controller/Driver ...............................................................................................................35

6.10 Bit Sequential Buffer ................................................................................................................ 37

INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 38

STANDBY FUNCTION ........................................................................................................................40

RESET FUNCTION ............................................................................................................................. 41

10. MASK OPTION ...................................................................................................................................44

11. INSTRUCTION SET ............................................................................................................................ 45

12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 59

13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ............................................................... 75

14. PACKAGE DRAWINGS ..................................................................................................................... 78

15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 80

PD753104, 753106, 753108

1. PIN CONFIGURATION (Top View)

· 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)

PD753104GC-xxx-AB8,

PD753106GC-xxx-AB8,

PD753108GC-xxx-AB8

· 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

PD753104GK-xxx-8A8,

PD753106GK-xxx-8A8,

PD753108GK-xxx-8A8

Note

Connect the IC (Internally Connected) pin directly to V

BIAS

LC0

LC1

LC2

P30/LCDCL

P31/SYNC

P32

P33

P50

P51

P52

P53

P60/KR0

P61/KR1

P62/KR2

S12

S13

S14

S15

S16/P93

S17/P92

S18/P91

S19/P90

S20/P83

S21/P82

S22/P81

S23/P80

P23/BUZ

P22/PCL/PTO2

P21/PTO1

P20/PTO0

COM3

COM2

COM1

COM0

S10

S11

P63/KR3

RESET

XT1

XT2

Note

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P10/INT0

P11/INT1

P12/INT2/TI1/TI2

P13/TI0

PD753104, 753106, 753108

Pin Identification

P00 to P03

: Port 0

LC0

to V

LC2

: LCD Power Supply 0 to 2

P10 to P13

: Port 1

BIAS

: LCD Power Supply Bias Control

P20 to P23

: Port 2

LCDCL

: LCD Clock

P30 to P33

: Port 3

SYNC

: LCD Synchronization

P50 to P53

: Port 5

TI0 to TI2

: Timer Input 0 to 2

P60 to P63

: Port 6

PTO0 to PTO2

: Programmable Timer Output 0 to 2

P80 to P83

: Port 8

BUZ

: Buzzer Clock

P90 to P93

: Port 9

PCL

: Programmable Clock

KR0 to KR3

: Key Return 0 to 3

INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4

SCK

: Serial Clock

INT2

: External Test Input 2

: Serial Input

X1, X2

: Main System Clock Oscillation 1, 2

: Serial Output

XT1, XT2

: Subsystem Clock Oscillation 1, 2

SB0, SB1

: Serial Data Bus 0, 1

: Positive Power Supply

RESET

: Reset

: Ground

S0 to S23

: Segment Output 0 to 23

: Internally Connected

COM0 to COM3 : Common Output 0 to 3

PD753104, 753106, 753108

2. BLOCK DIAGRAM

Note

The ROM capacity depends on the product.

WATCH

TIMER

INTW

LCD

BASIC

INTERVAL

TIMER/

WATCHDOG

TIMER

INTBT

8-BIT

TIMER/EVENT

COUNTER #0

INTT0

TOUT0

8-BIT

TIMER/EVENT

COUNTER #1

8-BIT

TIMER/EVENT

COUNTER #2

CASCADED

16-BIT

TIMER/

EVENT

COUNTER

INTT2

CLOCKED

SERIAL

INTERFACE

INTCSI

TOUT0

INT1

INTERRUPT

CONTROL

BIT SEQ.

BUFFER (16)

INT0/P10

INT1/P11

INT4/P00

INT2/P12/TI1/TI2

KR0/P60 to

KR3/P63

SI/SB1/P03

SO/SB0/P02

SCK/P01

TI1/TI2/P12/INT2

PTO1/P21

PTO2/PCL/P22

INTT1

TI0/P13

PTO0/P20

BUZ/P23

PROGRAM

COUNTER

PROGRAM

MEMORY

Note

(ROM)

ALU

DECODE

AND

CONTROL

SP(8)

SBS

BANK

GENERAL REG.

DATA MEMORY

(RAM)

512 x 4 BITS

CLOCK

OUTPUT

CONTROL

CLOCK

DIVIDER

SYSTEM CLOCK

GENERATOR

MAIN

SUB

STAND BY

CONTROL

CPU

CLOCK

PCL/PTO2/P22

XT1

XT2

RESET

LCD

PORT0

P00 to P03

PORT1

P10 to P13

PORT2

P20 to P23

PORT3

P30 to P33

PORT5

P50 to P53

PORT6

P60 to P63

PORT8

P80 to P83

PORT9

P90 to P93

LCD

CONTROLLER/

DRIVER

S0 to S15

S16/P93 to

S19/P90

S20/P83 to

S23/P80

COM0 to COM3

BIAS

LC0

LC1

LC2

SYNC/P31

LCDCL/P30

TOUT0

PD753104, 753106, 753108

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin Name

Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function

I/O

TYPE

Note 1

P00

Input

INT4

Input

(B)

P01

Input/Output

SCK

(F)-A

P02

Input/Output

SO/SB0

(F)-B

P03

Input/Output

SI/SB1

(M)-C

P10

Input

INT0

Input

(B)-C

P11

INT1

P12

TI1/TI2/INT2

P13

TI0

P20

Input/Output

PTO0

Input

E-B

P21

PTO1

P22

PCL/PTO2

P23

BUZ

P30

Input/Output

LCDCL

Input

E-B

P31

SYNC

P32

P33

P50-P53

Note 2

Input/Output

M-D

Notes 1.

Characters in parentheses indicate the Schmitt trigger input.

If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),

low-level input leakage current increases when input or bit manipulation instruction is executed.

4-bit input port (PORT0).

For P01 to P03, connection of on-chip pull-

up resistors can be specified by software in

3-bit units.

4-bit input port (PORT1).

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

P10/INT0 can select noise elimination

circuit.

4-bit input/output port (PORT2).

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

Programmable 4-bit input/output port

(PORT3).

This port can be specified for input/output

bit-wise.

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units.

N-ch open-drain 4-bit input/output port

(PORT5).

A pull-up resistor can be contained bit-wise

(mask option).

Withstand voltage is 13 V in open-drain mode.

High level
(when pull-
up resistors
are provided)
or high-
impedance

PD753104, 753106, 753108

3.1 Port Pins (2/2)

Pin Name

Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function

I/O

TYPE

Note 1

P60

Input/Output

KR0

Input

(F)-A

P61

KR1

P62

KR2

P63

KR3

P80

Input/Output

S23

Yes

Input

P81

S22

P82

S21

P83

S20

P90

Input/Output

S19

Input

P91

S18

P92

S17

P93

S16

Notes 1.

Characters in parentheses indicate the Schmitt trigger input.

When these pins are used as segment signal output pins, do not connect the on-chip pull-up resistor

by software.

Programmable 4-bit input/output port
(PORT6).
This port can be specified for input/output
bit-wise.
Connection of on-chip pull-up resistors can
be specified by software in 4-bit units.

4-bit input/output port (PORT8).

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units

Note 2

4-bit input/output port (PORT9).

Connection of on-chip pull-up resistors can

be specified by software in 4-bit units

Note 2

PD753104, 753106, 753108

3.2 Non-port Pins (1/2)

Pin Name

Input/Output

Alternate

Function

After Reset

I/O Circuit

Function

TYPE

Note 1

TI0

Input

P13

Inputs external event pulses to the timer/event

Input

(B)-C

TI1

P12/INT2/TI2

counter.

TI2

P12/INT2/TI1

PTO0

Output

P20

Timer/event counter output

Input

E-B

PTO1

P21

PTO2

P22/PCL

PCL

P22/PTO2

Clock output

BUZ

P23

Optional frequency output (for buzzer output or

system clock trimming)

SCK

Input/Output

P01

Serial clock input/output

Input

(F)-A

SO/SB0

P02

Serial data output

(F)-B

Serial data bus input/output

SI/SB1

P03

Serial data input

(M)-C

Serial data bus input/output

INT4

Input

P00

Edge detection vectored interrupt input (both

Input

(B)

rising edge and falling edge detection)

INT0

Input

P10

Input

(B)-C

INT1

P11

INT2

P12/TI1/TI2

KR0-KR3

Input

P60-P63

Falling edge detection testable input

Input

(F)-A

S0-S15

Output

Segment signal output

Note 2

G-A

S16-S19

Output

P93-P90

Segment signal output

Input

S20-S23

Output

P83-P80

Segment signal output

Input

COM0-COM3

Output

Common signal output

Note 2

G-B

LC0

-V

LC2

LCD drive power

On-chip split resistor is enabled (mask option).

BIAS

Output

Output for external split resistor disconnect

Note 3

LCDCL

Note 4

Output

P30

Clock output for externally expanded driver

Input

E-B

SYNC

Note 4

Output

P31

Clock output for externally expanded driver

Input

E-B

synchronization

Notes 1.

Characters in parentheses indicate the Schmitt trigger input.

Each display output selects the following V

LCX

as input source.

S0-S15: V

LC1

, COM0-COM2: V

LC2

, COM3: V

LC0

When a split resistor is contained ........ Low level

When no split resistor is contained ...... High-impedance

These pins are provided for future system expansion.

At present, these pins are used only as pins P30 and P31.

Edge detection vectored

Noise elimination circuit/

interrupt input (detection

asynchronous selection

edge can be selected).

INT0/P10 can select noise

elimination circuit.

Rising edge detection

Asynchronous

testable input

Asynchronous

PD753104, 753106, 753108

(2/2)

TYPE F-B

TYPE H

TYPE G-A

TYPE M-C

TYPE M-D

P.U.R
enable

P.U.R.

P-ch

N-ch

output

disable

(P)

data

output

disable

output

disable

(N)

IN/OUT

P.U.R. : Pull-Up Resistor

data

output

disable

P.U.R.

enable

P.U.R.

P-ch

IN/OUT

N-ch

P.U.R. : Pull-Up Resistor

TYPE G-B

SEG

data

output

disable

TYPE G-A

TYPE E-B

IN/OUT

N-ch

LC0

LC1

SEG

data

LC2

OUT

P-ch
N-ch

N-ch

P-ch

LC0

LC1

P-ch

N-ch

OUT

N-ch

LC2

N-ch

COM

data

P-ch

P-ch
N-ch

IN/OUT

P.U.R.
(Mask Option)

data

output

disable

N-ch

P-ch

input

instruction

(+13 V withstand
voltage)

The pull-up resistor operates only when an input
instruction is executed (current flows from V

the pin when the pin is low).

P.U.R.

Voltage limitation

circuit

Note

(+13 V
withstand
voltage)

Note

PD753104, 753106, 753108

3.4 Recommended Connections for Unused Pins

Table 3-1. List of Recommended Connections for Unused Pins

Recommended Connection

P00/INT4

Connect to V

or V

P01/SCK

Connect to V

or V

via a resistor individually

P02/SO/SB0

P03/SI/SB1

Connect to V

P10/INT0, P11/INT1

Connect to V

or V

P12/TI1/TI2/INT2

P13/TI0

P20/PTO0

Input state:

Connect to V

or V

via a resistor

P21/PTO1

individually

P22/PCL/PTO2

Output state: Leave open

P23/BUZ

P30/LCDCL

P31/SYNC

P32

P33

P50-P53

Input state:

Connect to V

Output state: Connect to V

(do not connect a

pull-up resistor of mask option)

P60/KR0-P63/KR3

Input state:

Connect to V

or V

via a resistor

individually

Output state: Leave open

S0-S15

Leave open

COM0-COM3

S16/P93-S19/P90

Input state:

Connect to V

or V

via a resistor

individually

S20/P83-S23/P80

Output state: Leave open

LC0

-V

LC2

Connect to V

BIAS

Only if all of V

LC0

to V

LC2

are unused, connect to V

In other cases, leave open.

XT1

Note

Connect to V

XT2

Note

Leave open

Connect

directly to V

Note

When the subsystem clock is not used, specify SOS.0 = 1 (so as not

to use the on-chip feedback resistor).

PD753104, 753106, 753108

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Difference between Mk I Mode and Mk II Mode

The CPU of the

PD753108 has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by bit 3 of the stack bank select register (SBS).

· Mk I mode:

Upward compatible with the

PD75308B. Can be used in the 75XL CPU with a ROM capacity

of up to 16 Kbytes.

· Mk II mode: Incompatible with the

PD75308B. Can be used in all the 75XL CPU's including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I mode

Mk II mode

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

CALL !addr instruction

3 machine cycles

4 machine cycles

CALLF !faddr instruction

2 machine cycles

3 machine cycles

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL

Series. Therefore, this mode is effective for enhancing software compatibility with

products exceeding 16 Kbytes.

When the Mk II mode is selected, the number of stack bytes used during execution of

subroutine call instructions increases by one byte per stack compared to the Mk I mode.

When the CALL !addr and CALLF !faddr instructions are used, the machine cycle

becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM

efficiency and processing performance are more important than software compatibility.

PD753104, 753106, 753108

Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk

I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the

Mk II mode.

4.2 Setting Method of Stack Bank Select Register (SBS)

Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure

4-1 shows the format.

The SBS is set by a 4-bit memory manipulation instruction.

When using the Mk I mode, the SBS must be initialized to 100xB

Note

at the beginning of a program. When using

the Mk II mode, it must be initialized to 000xB

Note

Set the desired value in the x position.

Figure 4-1. Stack Bank Select Register Format

SBS3

SBS2

SBS1

SBS0

Symbol

SBS

Address

F84H

Memory bank 0

Memory bank 1

Other than above setting prohibited

0 must be set in the bit 2 position.

Stack area specification

Mk II mode

Mk I mode

Mode switching specification

PD753104, 753106, 753108

5. MEMORY CONFIGURATION

Program Memory (ROM) .... 4096 x 8 bits (

PD753104)

.... 6144 x 8 bits (

PD753106)

.... 8192 x 8 bits (

PD753108)

Addresses 0000H and 0001H

Vector table wherein the program start address and the values set for the RBE and MBE at the time a

RESET signal is generated are written. Reset start is possible from any address.

Addresses 0002H to 000DH

Vector table wherein the program start address and the values set for the RBE and MBE by each vectored

interrupt are written. Interrupt processing can start from any address.

Addresses 0020H to 007FH

Table area referenced by the GETI instruction

Note

The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte

instruction, or two 1-byte instructions. It is used to decrease the number of program steps.

Data Memory (RAM)

Data area ... 512 words x 4 bits (000H to 1FFH)

Peripheral hardware area ... 128 words x 4 bits (F80H to FFFH)

PD753104, 753106, 753108

Figure 5-1. Program Memory Map (1/3)

(a)

PD753104

Note

Can be used in Mk II mode only.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

0 0 0 H

Address

MBE RBE

Internal reset start address

(high-order 4 bits)

0 0 2 H MBE RBE

INTBT/INT4

(high-order 4 bits)

start address

0 0 4 H MBE RBE

INT0

(high-order 4 bits)

start address

0 0 6 H MBE RBE

INT1

(high-order 4 bits)

start address

0 0 8 H MBE RBE

INTCSI

(high-order 4 bits)

start address

0 0 A H MBE RBE

INTT0

(high-order 4 bits)

start address

0 0 C H MBE RBE

INTT1/INTT2

(high-order 4 bits)

start address

0 2 0 H

0 7 F H

0 8 0 H

7 F F H

8 0 0 H

F F F H

GETI instruction reference table

(low-order 8 bits)

CALLF
!faddr
instruction
entry
address

BRCB !caddr
instruction
branch
address

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

Internal reset start address

INTBT/INT4

start address

INT0

start address

INT1

start address

INTCSI

start address

INTT0

start address

INTT1/INTT2

start address

Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1

Note

CALLA !addr1

Note

instruction

CALL !addr
instruction
subroutine entry
address

BR $addr
instruction relative
branch address

15 to 1,
+2 to +16

PD753104, 753106, 753108

Figure 5-1. Program Memory Map (2/3)

(b)

PD753106

Note

Can be used in Mk II mode only.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

0 0 0 0 H

Address

0 0 0 2 H MBE RBE

INTBT/INT4

(high-order 5 bits)

start address

0 0 0 4 H MBE RBE

INT0

(high-order 5 bits)

start address

0 0 0 6 H MBE RBE

INT1

(high-order 5 bits)

start address

0 0 0 8 H MBE RBE

INTCSI

(high-order 5 bits)

start address

0 0 0 A H MBE RBE

INTT0

(high-order 5 bits)

start address

0 0 2 0 H

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

MBE RBE

Internal reset start address

(high-order 5 bits)

0 F F F H

1 0 0 0 H

1 7 F F H

GETI instruction reference table

0 0 0 C H MBE RBE

INTT1/INTT2

(high-order 5 bits)

start address

(low-order 8 bits)

CALLF
!faddr
instruction
entry
address

BRCB !caddr
instruction
branch
address

Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1

Note

CALLA !addr1

Note

instruction

CALL !addr
instruction
subroutine entry
address

BR $addr
instruction relative
branch address

15 to 1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB !caddr
instruction
branch
address

Internal reset start address

INTBT/INT4

INT0

INT1

INTCSI

INTT0

INTT1/INTT2

start address

PD753104, 753106, 753108

Figure 5-1. Program Memory Map (3/3)

(c)

PD753108

Note

Can be used in Mk II mode only.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

0 0 0 0 H

Address

0 0 0 2 H MBE RBE

INTBT/INT4

(high-order 5 bits)

start address

0 0 0 4 H MBE RBE

INT0

(high-order 5 bits)

start address

0 0 0 6 H MBE RBE

INT1

(high-order 5 bits)

start address

0 0 0 8 H MBE RBE

INTCSI

(high-order 5 bits)

start address

0 0 0 A H MBE RBE

INTT0

(high-order 5 bits)

start address

0 0 2 0 H

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

MBE RBE

Internal reset start address

(high-order 5 bits)

0 F F F H

1 0 0 0 H

1 F F F H

GETI instruction reference table

0 0 0 C H MBE RBE

INTT1/INTT2

(high-order 5 bits)

start address

(low-order 8 bits)

CALLF
!faddr
instruction
entry
address

BRCB !caddr
instruction
branch
address

Branch address
of BR BCXA, BR
BCDE, BR !addr,
BRA !addr1

Note

CALLA !addr1

Note

instruction

CALL !addr
instruction
subroutine entry
address

BR $addr
instruction relative
branch address

15 to 1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB !caddr
instruction
branch
address

Internal reset start address

INTBT/INT4

INT0

INT1

INTCSI

INTT0

INTT1/INTT2

start address

PD753104, 753106, 753108

6. PERIPHERAL HARDWARE FUNCTION

6.1 Digital I/O Port

There are three kinds of I/O port.

· CMOS input ports (PORT 0, 1)

: 8

· CMOS input/output ports (PORT 2, 3, 6, 8, 9) : 20

· N-ch open-drain input/output ports (PORT 5)

: 4

Total

Table 6-1. Types and Features of Digital Ports

Port name

Function

Operation and features

Remarks

PORT0

4-bit input

When the serial interface function is used, the dual

Also used for the INT4, SCK,

function pins function as output ports depending on the

SO/SB0, SI/SB1 pins.

operation mode.

PORT1

4-bit input only port.

Also used for the INT0-INT2/
TI1/TI2, TI0 pins.

PORT2

4-bit input/

Can be set to input mode or output mode in 4-bit units.

Also used for the PTO0-

output

PTO2/PCL, BUZ pins.

PORT3

Can be set to input mode or output mode bit-wise.

Also used for the LCDCL,
SYNC pins.

PORT5

4-bit input/

Can be set to input mode or output mode in 4-bit units.

output

On-chip pull-up resistor can be specified bit-wise

(N-ch open-

by mask option.

drain, 13 V
withstand
voltage)

PORT6

4-bit input/

Can be set to input mode or output mode bit-wise.

Also used for the KR0-KR3 pins.

PORT8

output

Can be set to input

Ports 8 and 9 are paired

Also used for the S20-S23 pins.

PORT9

mode or output mode

and data can be input/

Also used for the S16-S19 pins.

in 4-bit units.

output in 8-bit units.

6.2 Clock Generator

The clock generator is a device that generates the clock which is supplied to peripheral hardware on the CPU

and is configured as shown in Figure 6-1.

The clock generator operates according to how the processor clock control register (PCC) and system clock

control register (SCC) are set.

There are two kinds of clocks, main system clock and subsystem clock.

The instruction execution time can also be changed.

· 0.95, 1.91, 3.81, 15.3

s (main system clock: in 4.19-MHz operation)

· 0.67, 1.33, 2.67, 10.7

s (main system clock: in 6.0-MHz operation)

· 122

s (subsystem clock: in 32.768-kHz operation)

PD753104, 753106, 753108

Figure 6-1. Clock Generator Block Diagram

Note Instruction execution

Remarks 1.

= Main system clock frequency

= Subsystem clock frequency

= CPU clock

PCC: Processor Clock Control Register

SCC: System Clock Control Register

One clock cycle (t

) of the CPU clock is equal to one machine cycle of the instruction.

XT1

XT2

Subsystem
clock oscillator

Main system
clock oscillator

HALT

Note

STOP

Note

WM.3

SCC

SCC3

SCC0

PCC0

PCC1

PCC2

PCC3

PCC2,

PCC3

Clear

STOP F/F

Oscillation
stop

HALT F/F

Wait release signal from BT

RESET signal

Standby release signal from
interrupt control circuit

· CPU
· INT0 noise
elimination circuit
· Clock output circuit

1/4

Divider

1/1 to 1/4096

Divider

1/2 1/4 1/16

· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· INT0 noise elimination circuit
· Clock output circuit

LCD controller/driver

Watch timer

PCC

Selector

Internal bus

PD753104, 753106, 753108

6.3 Subsystem Clock Oscillator Control Functions

The

PD753108 subsystem clock oscillator has the following two control functions.

· Selects by software whether an on-chip feedback resistor is to be used or not

Note

· Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage

is high (V

2.7 V).

Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the on-chip feedback resistor) by

software, connect XT1 to V

or V

, and open XT2. This makes it possible to reduce the current

consumption in the subsystem clock oscillator.

The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See

Figure 6-2.)

Figure 6-2. Subsystem Clock Oscillator

Feedback resistor

SOS.0

SOS.1

XT1

XT2

Inverter

PD753104, 753106, 753108

6.6 Watch Timer

The

PD753108 has one watch timer channel which has the following functions.

Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by the IRQW.

0.5-second interval can be created by both the main system clock (4.194304 MHz) and subsystem clock

(32.768 kHz).

Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the

fast feed mode.

Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ pin, usable for buzzer and trimming of

system clock oscillation frequencies.

Clears the frequency divider to make the watch start with zero seconds.

Figure 6-5. Watch Timer Block Diagram

Remark The values enclosed in parentheses are applied when f

= 4.194304 MHz and f

= 32.768 kHz.

From

clock

generator

Selector

128

(32.768 kHz)

Divider

4 kHz 2 kHz

Clear

Selector

(512 Hz : 1.95 ms)

(256 Hz : 3.91 ms)

Selector

2 Hz

0.5 sec

IRQW
set signal

INTW

LCD

Output buffer

Bit 2 of PMGB

PORT2.3

WM7

WM5

WM4

WM3

WM2

WM1

WM0

P23
output latch

Port 2 input/
output mode

Internal bus

Bit test instruction

P23/BUZ

PD753104, 753106, 753108

6.7 Timer/Event Counter

The

PD753108 has three channels of timer/event counters. Its configuration is shown in Figures 6-6 to 6-8.

The timer/event counter has the following functions.

Programmable interval timer operation

Square wave output of any frequency to the PTOn pin (n = 0 to 2)

Event counter operation

Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided

frequency to the PTOn pin (frequency divider operation).

Supplies the serial shift clock to the serial interface circuit.

Reads the count value.

The timer/event counter operates in the following four modes as set by the mode register.

Table 6-2. Operation Modes of Timer/Event Counter

Channel

Channel 0

Channel 1

Channel 2

Mode

8-bit timer/event counter mode

Yes

Gate control function

Note

Yes

PWM pulse generator mode

Yes

16-bit timer/event counter mode

Yes

Gate control function

Note

Yes

Carrier generator mode

Yes

Note Used for gate control signal generation

PD753104, 753106, 753108

Figure 6-7. Timer/Event Counter (Channel 1) Block Diagram

PORT1.2

Input buffer

TI1/TI2/P12/INT2

Timer/event counter

(channel 2) output

From clock

generator

MPX

TM16

TM15

TM14

TM13

TM12

TM11

TM10

TM1

SET1

Note

Decoder

16-bit timer/event counter mode

Timer operation start

Selector

Clear

Modulo register (8)

Comparator (8)

Count register (8)

Timer/event counter (channel 2) match signal

(When 16-bit timer/event counter mode)

Timer/event counter (channel 2) comparator

(When 16-bit timer/event counter mode)

Timer/event counter (channel 2) reload signal

TMOD1

Match

TOUT

F/F

Reset

enable flag

P21

output latch

Port 2

input/output

mode

INTT1

IRQT1

set signal

IRQT1 clear signal

RESET

TOE1

PORT2.1

Bit 2 of PMGB

P21/PTO1

Output buffer

Internal bus

Note

Instruction execution

PD753104, 753106, 753108

Figure 6-8. Timer/Event Counter (Channel 2) Block Diagram

PORT1.2

Input buffer

TI1/TI2/P12/INT2

From clock

generator

MPX

TM25

TM26

TM24

TM23

TM22

TM21

TM20

TM2

SET1

Note

TC2

Decoder

High-level period setting

modulo register (8)

Modulo register (8)

TGCE

TOE2

REMC

NRZB

NRZ

Reload

MPX (8)

Comparator (8)

Count register (8)

Clear

16-bit timer/event counter mode

Timer operation start

Timer/event counter

(channel 1) match signal

(When 16-bit timer/event

counter mode)

Timer/event counter

(channel 1) clear signal

(When 16-bit timer/event

counter mode)

Timer/event counter

(channel 1) match signal

(When carrier generator mode)

Match

Overflow

Carrier generator mode

PORT2.2

Bit 2 of PMGB

P22

output latch

Output buffer

P22/PCL/PTO2

Timer/event counter

(channel 1) clock input

INTT2

IRQT2

set signal

IRQT2 clear signal

RESET

TMOD2

TMOD2H

Internal bus

Timer event counter

(channel 0) TOUT F/F

Reset

Selector

Port 2

input/output

TOUT

F/F

From clock output circuit

Note

Instruction execution

PD753104, 753106, 753108

6.9 LCD Controller/Driver

The

PD753108 incorporates a display controller which generates segment and common signals according to

the display data memory contents and incorporates segment and common drivers which can drive the LCD panel

directly.

The

PD753108 LCD controller/driver has the following functions:

Display data memory is read automatically by DMA operation and segment and common signals are

generated.

Display mode can be selected from among the following five:

<1> Static

<2> 1/2 duty (time multiplexing by 2), 1/2 bias

<3> 1/3 duty (time multiplexing by 3), 1/2 bias

<4> 1/3 duty (time multiplexing by 3), 1/3 bias

<5> 1/4 duty (time multiplexing by 4), 1/3 bias

A frame frequency can be selected from among four in each display mode.

A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to

COM3).

The segment signal output pins (S0 to S23) can be changed to the I/O ports (PORT8 and PORT9).

Split resistor can be incorporated to supply LCD drive power (mask option).

· Various bias methods and LCD drive voltages are applicable.

· When display is off, current flowing through the split resistor is cut.

Display data memory not used for display can be used for normal data memory.

It can also operate by using the subsystem clock.

PD753104, 753106, 753108

7. INTERRUPT FUNCTION AND TEST FUNCTION

The

PD753108 has eight types of interrupt sources and two types of test sources. Of these test sources, INT2

has two types of edge detection testable inputs.

The interrupt control circuit of the

PD753108 has the following functions.

(1) Interrupt function

· Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the

interrupt enable flag (IExxx) and interrupt master enable flag (IME).

· Can set any interrupt start address.

· Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS).

· Test function of interrupt request flag (IRQxxx). An interrupt generation can be checked by software.

· Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag.

(2) Test function

· Test request flag (IRQxxx) generation can be checked by software.

· Release the standby mode. The test source to be released can be selected by the test enable flag.

PD753104, 753106, 753108

8. STANDBY FUNCTION

In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the

PD753108.

Table 8-1. Operation Status in Standby Mode

Item

Mode

STOP mode

HALT mode

Set instruction

STOP instruction

HALT instruction

System clock when set

Settable only when the main system

Settable both by the main system clock

clock is used.

and subsystem clock.

Operation

Clock generator

Main system clock stops oscillation.

Only the CPU clock

halts (oscillation

status

continues).

Basic interval timer/

Operation stops.

Operable only when the main system

watchdog timer

clock is oscillated.

BT mode : IRQBT is set in the

reference time interval

WT mode : Reset signal is generated

by BT overflow

Serial interface

Operable only when an external SCK

Operable only when an external SCK input

input is selected as the serial clock.

is selected as the serial clock or when the

main system clock is oscillated.

Timer/event counter

Operable only when a signal input to the

TI0 to TI2 pins is specified as the count

clock.

clock or when the main system clock is

oscillated.

Watch timer

Operable when f

is selected as the

Operable.

count clock.

LCD controller/driver

Operable only when f

is selected as the Operable.

LCDCL.

External interrupt

The INT1, 2, and 4 are operable.

Only the INT0 is not operated

Note

CPU

The operation stops.

Release signal

Interrupt request signal sent from the operable hardware enabled by the interrupt

enable flag or RESET signal input.

Note

Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection

mode register (IM0).

PD753104, 753106, 753108

Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing

chart of the reset operation.

Figure 9-2. Reset Operation by RESET Signal Generation

Note

The following two times can be selected by the mask option.

(21.8 ms: @ 6.00-MHz operation, 31.3 ms: @ 4.19-MHz operation)

(5.46 ms: @ 6.00-MHz operation, 7.81 ms: @ 4.19-MHz operation)

9. RESET FUNCTION

There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/

watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 9-

1 shows the configuration of the above two inputs.

Figure 9-1. Configuration of Reset Function

RESET

Internal reset signal

Reset signal sent from the
basic interval timer/watchdog timer

WDTM

Internal bus

Operation mode or

standby mode

Wait

Note

RESET

signal

generated

Operation mode

HALT mode

Internal reset operation

PD753104, 753106, 753108

Table 9-1. Status of Each Hardware After Reset (1/2)

Hardware

RESET signal generation

in the standby mode

in operation

Program counter (PC)

PD753104

Sets the low-order 4 bits of

program memory's address

0000H to the PC11-PC8 and the

contents of address 0001H to

the PC7-PC0.

PD753106,

Sets the low-order 5 bits of

PD753108

program memory's address

0000H to the PC12-PC8 and the

contents of address 0001H to

the PC7-PC0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0 to SK2)

Interrupt status flag (IST0, IST1)

Bank enable flag (MBE, RBE)

Sets the bit 6 of program

memory's address 0000H to the

RBE and bit 7 to the MBE.

Stack pointer (SP)

Undefined

Stack bank select register (SBS)

1000B

Data memory (RAM)

Held

Undefined

General-purpose register (X, A, H, L, D, E, B, C)

Held

Undefined

Bank select register (MBS, RBS)

0, 0

Basic interval

Counter (BT)

Undefined

timer/watchdog

Mode register (BTM)

timer

Watchdog timer enable flag (WDTM)

Timer/event

Counter (T0)

counter (T0)

Modulo register (TMOD0)

FFH

Mode register (TM0)

TOE0, TOUT F/F

0, 0

Timer/event

Counter (T1)

counter (T1)

Modulo register (TMOD1)

FFH

Mode register (TM1)

TOE1, TOUT F/F

0, 0

Timer/event

Counter (T2)

counter (T2)

Modulo register (TMOD2)

FFH

High-level period setting modulo

FFH

Mode register (TM2)

TOE2, TOUT F/F

0, 0

REMC, NRZ, NRZB

0, 0, 0

TGCE

Watch timer

Mode register (WM)

PD753104, 753106, 753108

Table 9-1. Status of Each Hardware After Reset (2/2)

Hardware

RESET signal generation

in the standby mode

in operation

Serial interface

Shift register (SIO)

Held

Undefined

Operation mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

Held

Undefined

Clock generator,

Processor clock control register (PCC)

clock output

System clock control register (SCC)

circuit

Clock output mode register (CLOM)

Sub-oscillator control register (SOS)

LCD controller/

Display mode register (LCDM)

driver

Display control register (LCDC)

LCD/port selection register (LPS)

Interrupt

Interrupt request flag (IRQxxx)

Reset (0)

function

Interrupt enable flag (IExxx)

Interrupt priority selection register (IPS)

INT0, 1, 2 mode registers (IM0, IM1, IM2)

0, 0, 0

Digital port

Output buffer

Off

Output latch

Cleared (0)

I/O mode registers (PMGA, B, C)

Pull-up resistor setting register (POGA, B)

Bit sequential buffer (BSB0 to BSB3)

Held

Undefined

PD753104, 753106, 753108

10. MASK OPTION

The

PD753108 has the following mask options.

P50-P53 mask options

Selects whether or not to internally connect a pull-up resistor.

<1> Connect pull-up resistor internally bit-wise.

<2> Do not connect pull-up resistor internally.

LC0

-V

LC2

pins, BIAS pin mask option

Selects whether or not to internally connect LCD-driving split resistors.

<1> Do not connect split resistor internally.

<2> Connect four 10-k

(typ.) split resistors simultaneously internally.

<3> Connect four 100-k

(typ.) split resistors simultaneously internally.

Standby function mask option

Selects the wait time with the RESET signal.

<1> 2

/fx (21.8 ms: When fx = 6.0 MHz, 31.3 ms: When fx = 4.19 MHz)

<2> 2

/fx (5.46 ms: When fx = 6.0 MHz, 7.81 ms: When fx = 4.19 MHz)

Subsystem clock mask option

Selects whether or not to use an internal feedback resistor.

<1> Use internal feedback resistor.

(Switch internal feedback resistor ON/OFF by software)

<2> Do not use internal feedback resistor.

(Disconnect internal feedback resistor by hardware)

PD753104, 753106, 753108

11. INSTRUCTION SET

(1) Expression formats and description methods of operands

The operand is described in the operand column of each instruction in accordance with the description

method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER

PACKAGE USERS' MANUAL----LANGUAGE (EEU-1363)". If there are several elements, one of them

is selected. Capital letters and the + and symbols are key words and are described as they are.

For immediate data, appropriate numbers and labels are described.

Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described.

However, there are restrictions in the labels that can be described for fmem and pmem. For details, see

User's Manual.

Expression

Description method

format

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label

Note

bit

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

pmem

FC0H-FFFH immediate data or label

addr

0000H-0FFFH immediate data or label (

PD753104)

0000H-17FFH immediate data or label (

PD753106)

0000H-1FFFH immediate data or label (

PD753108)

addr1

0000H-0FFFH immediate data or label (

PD753104)

(Mk II mode only)

0000H-17FFH immediate data or label (

PD753106)

0000H-1FFFH immediate data or label (

PD753108)

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H-7FH immediate data (where bit0 = 0) or label

PORTn

PORT0-PORT3, PORT5, PORT6, PORT8, PORT9

IExxx

IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW

RBn

RB0-RB3

MBn

MB0, MB1, MB15

Note mem can be only used for even address in 8-bit data processing.

PD753104, 753106, 753108

(2) Legend in explanation of operation

: A register, 4-bit accumulator

: B register

: C register

: D register

: E register

: H register

: L register

: X register

: XA register pair; 8-bit accumulator

: BC register pair

: DE register pair

: HL register pair

XA'

: XA' expanded register pair

BC'

: BC' expanded register pair

DE'

: DE' expanded register pair

HL'

: HL' expanded register pair

: Program counter

: Stack pointer

: Carry flag, bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn

: Port n (n = 0 to 3, 5, 6, 8, 9)

IME

: Interrupt master enable flag

IPS

: Interrupt priority selection register

IExxx

: Interrupt enable flag

RBS

: Register bank selection register

MBS

: Memory bank selection register

PCC

: Processor clock control register

: Separation between address and bit

(xx)

: The contents addressed by xx

xxH

: Hexadecimal data

PD753104, 753106, 753108

(3) Explanation of symbols under addressing area column

MB = MBE·MBS

(MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (000H to 07FH)

MB = 15 (F80H to FFFH)

Data memory addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H to FBFH, FF0H to FFFH

MB = 15, pmem = FC0H to FFFH

PD753104

addr = 000H to FFFH

PD753106

addr = 0000H to 17FFH

PD753108

addr = 0000H to 1FFFH

addr

= (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

addr1 = (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

PD753104

caddr = 000H to FFFH

PD753106

caddr = 0000H to 0FFFH (PC

= 0) or

Program memory addressing

1000H to 17FFH (PC

= 1)

PD753108

caddr = 0000H to 0FFFH (PC

= 0) or

1000H to 1FFFH (PC

= 1)

faddr = 0000H to 07FFH

*10

taddr = 0020H to 007FH

*11

PD753104

addr1 = 000H to FFFH

PD753106

addr1 = 0000H to 17FFH

PD753108

addr1 = 0000H to 1FFFH

Remarks 1.

MB indicates memory bank that can be accessed.

In *2, MB = 0 independently of how MBE and MBS are set.

In *4 and *5, MB = 15 independently of how MBE and MBS are set.

*6 to *11 indicate the areas that can be addressed.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Transfer

MOV

A, #n4

A <- n4

String effect A

reg1, #n4

reg1 <- n4

XA, #n8

XA <- n8

String effect A

HL, #n8

HL <- n8

String effect B

rp2, #n8

rp2 <- n8

A, @HL

A <- (HL)

A, @HL+

2+S

A <- (HL), then L <- L+1

L = 0

A, @HL

2+S

A <- (HL), then L <- L1

L = FH

A, @rpa1

A <- (rpa1)

XA, @HL

XA <- (HL)

@HL, A

(HL) <- A

@HL, XA

(HL) <- XA

A, mem

A <- (mem)

XA, mem

XA <- (mem)

mem, A

(mem) <- A

mem, XA

(mem) <- XA

A, reg

A <- reg

XA, rp'

XA <- rp'

reg1, A

reg1 <- A

rp'1, XA

rp'1 <- XA

XCH

A, @HL

A <-> (HL)

A, @HL+

2+S

A <-> (HL), then L <- L+1

L = 0

A, @HL

2+S

A <-> (HL), then L <- L1

L = FH

A, @rpa1

A <-> (rpa1)

XA, @HL

XA <-> (HL)

A, mem

A <-> (mem)

XA, mem

XA <-> (mem)

A, reg1

A <-> reg1

XA, rp'

XA <-> rp'

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Table

MOVT

XA, @PCDE

PD753104

reference

XA <- (PC

118

+DE)

ROM

PD753106, 753108

XA <- (PC

128

+DE)

ROM

XA, @PCXA

PD753104

XA <- (PC

118

+XA)

ROM

PD753106, 753108

XA <- (PC

128

+XA)

ROM

XA, @BCDE

XA <- (BCDE)

ROM

Note

XA, @BCXA

XA <- (BCXA)

ROM

Note

Bit transfer

MOV1

CY, fmem.bit

CY <- (fmem.bit)

CY, pmem.@L

CY <- (pmem

.bit(L

))

CY, @H+mem.bit

CY <- (H+mem

.bit)

fmem.bit, CY

(fmem.bit) <- CY

pmem.@L, CY

(pmem

.bit(L

)) <- CY

@H+mem.bit, CY

(H+mem

.bit) <- CY

Operation

ADDS

A, #n4

1+S

A <- A+n4

carry

XA, #n8

2+S

XA <- XA+n8

carry

A, @HL

1+S

A <- A+(HL)

carry

XA, rp'

2+S

XA <- XA+rp'

carry

rp'1, XA

2+S

rp'1 <- rp'1+XA

carry

ADDC

A, @HL

A, CY <- A+(HL)+CY

XA, rp'

XA, CY <- XA+rp'+CY

rp'1, XA

rp'1, CY <- rp'1+XA+CY

SUBS

A, @HL

1+S

A <- A(HL)

borrow

XA, rp'

2+S

XA <- XArp'

borrow

rp'1, XA

2+S

rp'1 <- rp'1XA

borrow

SUBC

A, @HL

A, CY <- A(HL)CY

XA, rp'

XA, CY <- XArp'CY

rp'1, XA

rp'1, CY <- rp'1XACY

Note

Set "0" in B register if the

PD753104 is used. Only low-order one bit of B register will be valid if the

PD753106 or 753108 is used.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Operation

AND

A, #n4

A <- A

A, @HL

A <- A

(HL)

XA, rp'

XA <- XA

rp'

rp'1, XA

rp'1 <- rp'1

A, #n4

A <- A

A, @HL

A <- A

(HL)

XA, rp'

XA <- XA

rp'

rp'1, XA

rp'1 <- rp'1

XOR

A, #n4

A <- A v n4

A, @HL

A <- A v (HL)

XA, rp'

XA <- XA v rp'

rp'1, XA

rp'1 <- rp'1 v XA

Accumulator

RORC

CY <- A

, A

<- CY, A

<- A

manipulation

NOT

A <- A

Increment

INCS

reg

1+S

reg <- reg+1

reg = 0

and
decrement

rp1

1+S

rp1 <- rp1+1

rp1 = 00H

@HL

2+S

(HL) <- (HL)+1

(HL) = 0

mem

2+S

(mem) <- (mem)+1

(mem) = 0

DECS

reg

1+S

reg <- reg1

reg = FH

rp'

2+S

rp' <- rp'1

rp' = FFH

Comparison

SKE

reg, #n4

2+S

Skip if reg = n4

reg = n4

@HL, #n4

2+S

Skip if (HL) = n4

(HL) = n4

A, @HL

1+S

Skip if A = (HL)

A = (HL)

XA, @HL

2+S

Skip if XA = (HL)

XA = (HL)

A, reg

2+S

Skip if A = reg

A = reg

XA, rp'

2+S

Skip if XA = rp'

XA = rp'

Carry flag

SET1

CY <- 1

manipulation

CLR1

CY <- 0

SKT

1+S

Skip if CY = 1

CY = 1

NOT1

CY <- CY

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Memory bit

SET1

mem.bit

(mem.bit) <- 1

manipulation

fmem.bit

(fmem.bit) <- 1

pmem.@L

(pmem

.bit(L

)) <- 1

@H+mem.bit

(H+mem

.bit) <- 1

CLR1

mem.bit

(mem.bit) <- 0

fmem.bit

(fmem.bit) <- 0

pmem.@L

(pmem

.bit(L

)) <- 0

@H+mem.bit

(H+mem

.bit) <- 0

SKT

mem.bit

2+S

Skip if (mem.bit) = 1

(mem.bit) = 1

fmem.bit

2+S

Skip if (fmem.bit) = 1

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

.bit(L

)) = 1

(pmem.@L) = 1

@H+mem.bit

2+S

Skip if (H+mem

.bit) = 1

(@H+mem.bit) = 1

SKF

mem.bit

2+S

Skip if (mem.bit) = 0

(mem.bit) = 0

fmem.bit

2+S

Skip if (fmem.bit) = 0

(fmem.bit) = 0

pmem.@L

2+S

Skip if (pmem

.bit(L

)) = 0

(pmem.@L) = 0

@H+mem.bit

2+S

Skip if (H+mem

.bit) = 0

(@H+mem.bit) = 0

SKTCLR

fmem.bit

2+S

Skip if (fmem.bit) = 1 and clear

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

.bit(L

)) = 1 and clear

(pmem.@L) = 1

@H+mem.bit

2+S

Skip if (H+mem

.bit) = 1 and clear

(@H+mem.bit) = 1

AND1

CY, fmem.bit

CY <- CY

(fmem.bit)

CY, pmem.@L

CY <- CY

(pmem

.bit(L

))

CY, @H+mem.bit

CY <- CY

(H+mem

.bit)

OR1

CY, fmem.bit

CY <- CY

(fmem.bit)

CY, pmem.@L

CY <- CY

(pmem

.bit(L

))

CY, @H+mem.bit

CY <- CY

(H+mem

.bit)

XOR1

CY, fmem.bit

CY <- CY v (fmem.bit)

CY, pmem.@L

CY <- CY v (pmem

.bit(L

))

CY, @H+mem.bit

CY <- CY v (H+mem

.bit)

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Branch

Note

addr

PD753104

110

<- addr

Select appropriate instruction from among
BR !addr, BRCB !caddr and BR $addr
according to the assembler being used.

PD753106, 753108

120

<- addr

Select appropriate instruction from
among BR !addr, BRCB !caddr and BR
$addr according to the assembler
being used.

addr1

PD753104

*11

11-0

<- addr1

Select appropriate instruction from
among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.

PD753106, 753108

120

<- addr1

Select appropriate instruction from
among BR !addr, BRA !addr1, BRCB
!caddr and BR $addr1 according to the
assembler being used.

!addr

PD753104

110

<- addr

PD753106, 753108

120

<- addr

$addr

PD753104

110

<- addr

PD753106, 753108

120

<- addr

$addr1

PD753104

110

<- addr1

PD753106, 753108

120

<- addr1

Note

The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Branch

PCDE

PD753104

110

<- PC

11-8

+DE

PD753106, 753108

120

<- PC

12-8

+DE

PCXA

PD753104

110

<- PC

11-8

+XA

PD753106, 753108

120

<- PC

12-8

+XA

BCDE

PD753104

110

<- BCDE

Note 1

PD753106, 753108

120

<- BCDE

Note 2

BCXA

PD753104

110

<- BCXA

Note 1

PD753106, 753108

120

<- BCXA

Note 2

BRA

Note 3

!addr1

PD753104

*11

110

<- addr1

PD753106, 753108

120

<- addr1

BRCB

!caddr

PD753104

110

<- caddr

110

PD753106, 753108

120

<- PC

+caddr

110

Subroutine

CALLA

Note 3

!addr1

PD753104

*11

stack control

(SP2) <- x, x, MBE, RBE
(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, 0
PC

110

<- addr1, SP <- SP6

PD753106, 753108

(SP2) <- x, x, MBE, RBE
(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, PC

120

<- addr1, SP <- SP6

Notes 1.

"0" must be set to B register.

Only low-order one bit is valid in B register.

The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

CALL

Note

!addr

PD753104

stack control

(SP3) <- MBE, RBE, 0, 0
(SP4) (SP1) (SP2) <- PC

110

<- addr, SP <- SP4

PD753106, 753108

(SP3) <- MBE, RBE, 0, PC

(SP4) (SP1) (SP2) <- PC

110

120

<- addr, SP <- SP4

PD753104

(SP2) <- x, x, MBE, RBE
(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, 0
PC

110

<- addr, SP <- SP6

PD753106, 753108

(SP2) <- x, x, MBE, RBE
(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, PC

120

<- addr, SP <- SP6

CALLF

Note

!faddr

PD753104

(SP3) <-

MBE, RBE, 0, 0

(SP4) (SP1) (SP2) <- PC

110

<- 0+faddr, SP <- SP4

PD753106, 753108

(SP3) <- MBE, RBE, 0, PC

(SP4) (SP1) (SP2) <- PC

110

120

<- 00+faddr, SP <- SP4

PD753104

(SP2) <- x, x, MBE, RBE
(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, 0
PC

110

<- 0+faddr, SP <- SP6

PD753106, 753108

(SP2) <- x, x, MBE, RBE
(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, PC

120

<- 00+faddr, SP <- SP6

Note

The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

RET

Note

PD753104

stack control

110

<- (SP) (SP+3) (SP+2)

MBE, RBE, 0, 0 <- (SP+1), SP <- SP+4

PD753106, 753108

110

<- (SP) (SP+3) (SP+2)

MBE, RBE, 0, PC

<- (SP+1), SP <- SP+4

PD753104

x, x, MBE, RBE <- (SP+4)
0, 0, 0, 0, <- (SP+1)
PC

110

<- (SP) (SP+3) (SP+2), SP <- SP+6

PD753106, 753108

x, x, MBE, RBE <- (SP+4)
MBE, 0, 0, PC

<- (SP+1)

110

<- (SP) (SP+3) (SP+2), SP <- SP+6

RETS

Note

3+S

PD753104

Unconditional

MBE, RBE, 0, 0 <- (SP+1)
PC

110

<- (SP) (SP+3) (SP+2)

SP <- SP+4
then skip unconditionally

PD753106, 753108

MBE, RBE, 0, PC

<- (SP+1)

110

<- (SP) (SP+3) (SP+2)

SP <- SP+4
then skip unconditionally

PD753104

0, 0, 0, 0 <- (SP+1)
PC

110

<- (SP) (SP+3) (SP+2)

x, x, MBE, RBE <- (SP+4)
SP <- SP+6
then skip unconditionally

PD753106, 753108

0, 0, 0, PC

<- (SP+1)

110

<- (SP) (SP+3) (SP+2)

x, x, MBE, RBE <- (SP+4)
SP <- SP+4
then skip unconditionally

Note

The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

RETI

Note 1

PD753104

stack control

MBE, RBE, 0, 0 <- (SP+1)
PC

110

<- (SP) (SP+3) (SP+2)

PSW <- (SP+4) (SP+5), SP <- SP+6

PD753106, 753108

MBE, RBE, 0, PC

<- (SP+1)

110

<- (SP) (SP+3) (SP+2)

PSW <- (SP+4) (SP+5), SP <- SP+6

PD753104

0, 0, 0, 0 <- (SP+1)
PC

110

<- (SP) (SP+3) (SP+2)

PSW <- (SP+4) (SP+5), SP <- SP+6

PD753106, 753108

0, 0, 0, PC

<- (SP+1)

110

<- (SP) (SP+3) (SP+2)

PSW <- (SP+4) (SP+5), SP <- SP+6

PUSH

(SP1) (SP2) <- rp, SP <- SP2

(SP1) <- MBS, (SP2) <- RBS, SP <- SP2

POP

rp <- (SP+1) (SP), SP <- SP+2

MBS <-

(SP+1), RBS <-

(SP), SP <- SP+2

Interrupt

IME (IPS.3) <- 1

control

IExxx

IExxx <- 1

IME (IPS.3) <- 0

IExxx

IExxx <- 0

Input/output

Note 2

A, PORTn

A <- PORTn

(n = 0-3, 5, 6, 8, 9)

XA, PORTn

XA <- PORTn+1, PORTn

(n = 8)

OUT

Note 2

PORTn, A

PORTn <- A

(n = 3, 5, 6, 8, 9)

PORTn, XA

PORTn+1, PORTn <- XA

(n = 8)

CPU control

HALT

Set HALT Mode (PCC.2 <- 1)

STOP

Set STOP Mode (PCC.3 <- 1)

NOP

No Operation

Special

SEL

RBn

RBS <- n

(n = 0-3)

MBn

MBS <- n

(n = 0, 1, 15)

Notes 1.

The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and

MBS must be set to 15.

PD753104, 753106, 753108

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Special

GETI

Note 1, 2

taddr

PD753104

*10

· When TBR instruction

110

<- (taddr)

+ (taddr+1)

· When TCALL instruction

(SP4) (SP1) (SP2) <- PC

110

(SP3) <- MBE, RBE, 0, 0
PC

110

<- (taddr)

+ (taddr+1)

SP <- SP4

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

PD753106, 753108

· When TBR instruction

120

<- (taddr)

+ (taddr+1)

· When TCALL instruction

(SP4) (SP1) (SP2) <- PC

110

(SP3) <- MBE, RBE, 0, PC

120

<- (taddr)

+ (taddr+1)

SP <- SP4

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

PD753104

*10

· When TBR instruction

110

<- (taddr)

+ (taddr+1)

· When TCALL instruction

(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, 0
(SP2) <- x, x, MBE, RBE
PC

110

<- (taddr)

+ (taddr+1)

SP <- SP6

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

PD753106, 753108

· When TBR instruction

120

<- (taddr)

+ (taddr+1)

· When TCALL instruction

(SP6) (SP3) (SP4) <- PC

110

(SP5) <- 0, 0, 0, PC

(SP2) <- x, x, MBE, RBE
PC

120

<- (taddr)

+ (taddr+1)

SP <- SP6

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

Notes 1.

The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

PD753104, 753106, 753108

12. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25 °C)

Parameter

Symbol

Test Conditions

Rating

Unit

Supply voltage

0.3 to +7.0

Input voltage

Except port 5

0.3 to V

+ 0.3

Port 5

On-chip pull-up resistor

0.3 to V

+ 0.3

When N-ch open-drain

0.3 to +14

Output voltage

0.3 to V

+ 0.3

Output current high

Per pin

Total of all pins

Output current low

Per pin

Total of all pins

220

Operating ambient

40 to +85

Note

°C

temperature

Storage temperature

stg

65 to +150

°C

Note

When LCD is driven in normal mode: T

= 10 to +85 °C

Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding

the ratings could cause parmanent damage. The parameters apply independently. The device

should be operated within the limits specified under DC and AC Characteristics.

CAPACITANCE (T

= 25 °C, V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

OUT

Unmeasured pins returned to 0 V.

I/O capacitance

PD753104, 753106, 753108

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Resonator

Recommended constant

Parameter

Test conditions

MIN.

TYP.

MAX.

Unit

Ceramic

Oscillation

1.0

6.0

Note 2

MHz

resonator

frequency (fx)

Note 1

Oscillation

After V

reaches oscil-

stabilization time

Note 3

lation voltage range MIN.

Crystal

Oscillation

1.0

6.0

Note 2

MHz

resonator

frequency (fx)

Note 1

Oscillation

= 4.5 to 5.5 V

stabilization time

Note 3

External

X1 input

1.0

6.0

Note 2

MHz

clock

frequency (fx)

Note 1

X1 input

83.3

500

high/low-level width

, t

)

Notes 1.

The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For

the instruction execution time, refer to the AC characteristics.

When the oscillation frequency is 4.19 MHz < fx

6.0 MHz at 1.8 V

< 2.7 V, setting the processor

clock control register (PCC) to 0011 results in 1 machine cycle time being less than the required 0.95

s. Therefore, set PCC to a value other than 0011.

The oscillation stabilization time is necessary for oscillation to stabilize after applying V

or releasing

the STOP mode.

Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line in the

above figure should be carried out as follows to avoid an adverse effect from wiring capacitance.

· Wiring should be as short as possible.

· Wiring should not cross other signal lines.

· Wiring should not be placed close to a varying high current.

· The potential of the oscillator capacitor ground should be the same as V

· Do not ground to the ground pattern in which a high current flows.

· Do not fetch a signal from the oscillator.

PD753104, 753106, 753108

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Resonator

Recommended constant

Parameter

Test conditions

MIN.

TYP.

MAX.

Unit

Crystal

Oscillation

32.768

kHz

resonator

frequency (f

)

Note 1

Oscillation

= 4.5 to 5.5 V

1.0

stabilization time

Note 2

External

XT1 input frequency

100

kHz

clock

)

Note 1

X1 input high/low-level

width (t

XTH

, t

XTL

)

Notes 1.

Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

The oscillation stabilization time is necessary for oscillation to stabilize after applying V

Caution

When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line in the

above figure should be carried out as follows to avoid an adverse effect from wiring capacitance.

· Wiring should be as short as possible.

· Wiring should not cross other signal lines.

· Wiring should not be placed close to a varying high current.

· The potential of the oscillator capacitor ground should be the same as V

· Do not ground to the ground pattern in which a high current flows.

· Do not fetch a signal from the oscillator.

The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption

current, causing misoperation by noise more frequently than the main system clock oscillator.

Special care should therefore be taken for wiring method when the subsystem clock is used.

XT2

XT1

XT2

PD753104, 753106, 753108

RECOMMENDED OSCILLATOR CONSTANT

Ceramic Resonator (T

= 20 to +85 °C)

Manufacturer

Product name

Frequency

Oscillator

Oscillation

Remarks

constant (pF)

voltage range (V

)

(MHz)

MIN.

MAX.

Kyocera

KBR-1000F/Y

1.0

100

1.8

5.5

Corporation

KBR-2.0MS

2.0

2.2

KBR-4.19MSA

4.19

1.8

KBR-4.19MKS

On-chip capacitor

product

PBRC 4.19A

PBRC 4.19B

On-chip capacitor

product

KBR-6.0MSA

6.0

KBR-6.0MKS

On-chip capacitor

product

PBRC 6.00A

PBRC 6.00B

On-chip capacitor

product

Ceramic Resonator (T

= 40 to +85 °C)

Manufacturer

Product name

Frequency

Oscillator

Oscillation

Remarks

constant (pF)

voltage range (V

)

(MHz)

MIN.

MAX.

TDK

CCR1000K2

1.0

150

2.3

5.5

CCR2.0MC33

2.0

On-chip capacitor

FCR4.19MC5

4.19

product

CCR4.19MC3

FCR6.0MC5

6.0

2.2

CCR6.0MC3

PD753104, 753106, 753108

Ceramic Resonator (T

= 20 to +80 °C)

Manufacturer

Product name

Frequency

Oscillator

Oscillation

Remarks

constant (pF)

voltage range (V

)

(MHz)

MIN.

MAX.

Murata Mfg.

CSB1000J

1.0

100

2.4

5.5

Rd = 5.6 k

Note

Co., Ltd.

CSA2.00MG

2.0

1.8

CST2.00MGW

On-chip capacitor product

CSA3.00MG

3.0

CST3.00MGW

On-chip capacitor product

CSA4.19MG

4.19

CST4.19MGW

On-chip capacitor product

CSA5.00MG

5.0

2.2

CSA5.00MGU

1.8

CST5.00MGW

2.2

On-chip capacitor product

CST5.00MGWU

1.8

CSA6.00MG

6.0

2.5

CSA6.00MGU

1.8

CST6.00MGW

2.5

On-chip capacitor product

CST6.00MGWU

1.8

Note

If using the CSB1000J (1.0-MHz) ceramic resonator manufactured by Murata Mfg. Co., Ltd., a limiting

resistor (Rd = 5.6 k

) is required (see figure below). A limiting resistor is not required if using the other

recommended resonators.

Recommended Main System Clock Circuit Example (using Murata Mfg. Co., Ltd. CSB1000J)

CSB1000J

PD753104, 753106, 753108

DC CHARACTERISTICS (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Output current low

Per pin

Total of all pins

150

Input voltage high

IH1

Ports 2, 3, 8, 9

2.7

5.5 V

0.7V

1.8

< 2.7 V

0.9V

IH2

Ports 0, 1, 6, RESET

2.7

5.5 V

0.8V

1.8

< 2.7 V

0.9V

IH3

Port 5

On-chip pull-up

2.7

5.5 V

0.7V

resistor

1.8

< 2.7 V

0.9V

When N-ch

2.7

5.5 V

0.7V

open-drain

1.8

< 2.7 V

0.9V

IH4

X1, XT1

0.1

Input voltage low

IL1

Ports 2, 3, 5, 8, 9

2.7

5.5 V

0.3V

1.8

< 2.7 V

0.1V

IL2

Ports 0, 1, 6, RESET

2.7

5.5 V

0.2V

1.8

< 2.7 V

0.1V

IL3

X1, XT1

0.1

Output voltage high

SCK, SO, ports 2, 3, 6, 8, 9 I

= 1.0 mA

0.5

Output voltage low

OL1

SCK, SO, ports 2, 3, 5, 6, 8, 9

= 15 mA,

0.2

2.0

= 4.5 to 5.5 V

= 1.6 mA

0.4

OL2

SB0, SB1

N-ch open-drain

0.2V

pull-up resistor

1 k

Input leakage

LIH1

= V

Pins other than X1, XT1

current high

LIH2

X1, XT1

LIH3

= 13 V

Port 5 (When N-ch open-drain)

Input leakage

LIL1

= 0 V

Pins other than X1, XT1, port 5

current low

LIL2

X1, XT1

LIL3

Port 5 (When N-ch open-drain)

When input instruction is not executed

Port 5 (When N-ch

open-drain) When input V

= 5.0 V

instruction is executed

= 3.0 V

Output leakage

LOH1

OUT

= V

SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9,

current high

port 5 (When N-ch open-drain)

LOH2

OUT

= 13 V

Port 5 (When N-ch open-drain)

Output leakage

LOL

OUT

= 0 V

current low

On-chip pull-up resistor

= 0 V

Ports 0 to 3, 6, 8, 9

100

200

(Excluding P00 pin)

Port 5 (mask option)

PD753104, 753106, 753108

DC CHARACTERISTICS (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

LCD drive voltage

LCD

VAC0 = 0

TA = 40 to +85

2.7

TA = 10 to +85

2.2

VAC0 = 1

1.8

VAC current

Note 1

VAC

VAC0 = 1, V

= 2.0 V

10%

LCD split resistor

Note 2

LCD1

100

200

LCD2

LCD output voltage

ODC

1.0

LCD0

= V

LCD

0.2

deviation

Note 3

(common)

LCD1

= V

LCD

x 2/3

LCD2

= V

LCD

x 1/3

1.8 V

LCD

5.0

LCD0

= V

LCD

0.2

LCD1

= V

LCD

x 2/3

LCD2

= V

LCD

x 1/3

2.2 V

LCD

LCD output voltage

ODS

0.5

LCD0

= V

LCD

0.2

deviation

Note 3

(segment)

LCD1

= V

LCD

x 2/3

LCD2

= V

LCD

x 1/3

1.8 V

LCD

1.0

LCD0

= V

LCD

0.2

LCD1

= V

LCD

x 2/3

LCD2

= V

LCD

x 1/3

2.2 V

LCD

Supply current

Note 4

DD1

6.0 MHz

Note 5

= 5.0 V

10%

Note 6

1.9

6.0

Crystal oscillation V

= 3.0 V

10%

Note 7

0.4

1.3

DD2

C1 = C2 = 22 pF

HALT mode V

= 5.0 V

10%

0.72

2.1

= 3.0 V

10%

0.27

0.8

DD1

4.19 MHz

Note 5

= 5.0 V

10%

Note 6

1.5

4.0

Crystal oscillation V

= 3.0 V

10%

Note 7

0.25

0.75

DD2

C1 = C2 = 22 pF

HALT mode V

= 5.0 V

10%

0.7

2.0

= 3.0 V

10%

0.23

0.7

DD3

32.768 kHz

Note 8

Low-voltage V

= 3.0 V

10%

35.0

Crystal oscillation mode

Note 9

= 2.0 V

10%

4.5

12.0

= 3.0 V, T

= 25 °C

24.0

Low current consump- V

= 3.0 V

10%

6.0

18.0

tion mode

Note 10

= 3.0 V, T

= 25 °C

6.0

12.0

DD4

HALT mode Low-

= 3.0 V

10%

8.5

voltage

= 2.0 V

10%

3.0

9.0

mode

Note 9

= 3.0 V, T

= 25 °C

8.5

= 3.0 V

10%

3.5

= 3.0 V, T

= 25 °C

3.5

7.0

DD5

XT1 = 0 V

Note 11

= 5.0 V

10%

0.05

STOP mode

= 3.0 V

0.02

5.0

10%

= 25 °C

0.02

3.0

Low current
consumption
mode

Note 10

PD753104, 753106, 753108

Notes 1.

Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the

current increases by about 1

Either R

LCD1

or R

LCD2

can be selected by the mask option.

The voltage deviation is the difference from the output voltage corresponding to the ideal value of the

segment and common outputs (V

LCDn

; n = 0, 1, 2).

Not including currents flowing in on-chip pull-up resistors or LCD split resistors.

Including oscillation of the subsystem clock.

When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-

speed mode.

When PCC is set to 0000 and the device is operated in the low-speed mode.

When the system clock control register (SCC) is set to 1001 and the device is operated on the

subsystem clock, with main system clock oscillation stopped.

When the sub-oscillator control register (SOS) is set to 0000.

10.

When the SOS is set to 0010.

11.

When the SOS is set to 00x1, and the sub-oscillator feedback resistor is not used (x : don't care).

PD753104, 753106, 753108

AC CHARACTERISTICS (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle

Operating on

= 2.7 to 5.5 V

0.67

time

Note 1

main system clock

0.95

(minimum instruction execution

Operating on subsystem clock

114

122

125

time = 1 machine cycle)

TI0, TI1, TI2 input

= 2.7 to 5.5 V

1.0

MHz

frequency

275

kHz

TI0, TI1, TI2 input

TIH

, t

TIL

= 2.7 to 5.5 V

0.48

high/low-level width

1.8

Interrupt input high/

INTH

, t

INTL

INT0

IM02 = 0

Note 2

low-level width

IM02 = 1

INT1, 2, 4

KR0-KR3

RESET low-level width

RSL

Notes 1.

The cycle time (minimum instruction

execution time) of the CPU clock

(

) is determined by the oscillation

frequency of the connected

resonator (and external clock), the

system clock control register (SCC)

and the processor clock control

right indicates the cycle time t

versus supply voltage V

characteristic with the main system

clock operating.

or 128/fx is set by setting the

interrupt mode register (IM0).

0.5

Supply Voltage V

[V]

vs V

(At main system clock operation)

Cycle Time t

[

Operation Guaranteed
Range

PD753104, 753106, 753108

SERIAL TRANSFER OPERATION

2-Wire and 3-Wire Serial I/O Modes (SCK...Internal clock output): (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY1

= 2.7 to 5.5 V

1300

3800

SCK high/low-level

KL1

, t

KH1

= 2.7 to 5.5 V

KCY1

/250

width

KCY1

/2150

Note 1

setup time

SIK1

= 2.7 to 5.5 V

150

(to SCK

)

500

Note 1

hold time

KSI1

= 2.7 to 5.5 V

400

(from SCK

)

600

Note 1

output delay time

KSO1

= 1 k

Note 2

= 2.7 to 5.5 V

250

from SCK

= 100 pF

1000

Notes 1.

Read as SB0 or SB1 when using the 2-wire serial I/O mode.

and C

are the load resistance and load capacitance of the SO output line.

2-Wire and 3-Wire Serial I/O Modes (SCK...External clock input): (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY2

= 2.7 to 5.5 V

800

3200

SCK high/low-level

KL2

, t

KH2

= 2.7 to 5.5 V

400

width

1600

Note 1

setup time

SIK2

= 2.7 to 5.5 V

100

(to SCK

)

150

Note 1

hold time

KSI2

= 2.7 to 5.5 V

400

(from SCK

)

600

Note 1

output delay time

KSO2

= 1 k

Note 2

= 2.7 to 5.5 V

300

from SCK

= 100 pF

1000

Notes 1.

Read as SB0 or SB1 when using the 2-wire serial I/O mode.

and C

are the load resistance and load capacitance of the SO output line.

PD753104, 753106, 753108

SBI Mode (SCK...Internal clock output (master)): (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY3

= 2.7 to 5.5 V

1300

3800

SCK high/low-level

KL3

, t

KH3

= 2.7 to 5.5 V

KCY3

/250

width

KCY3

/2150

SB0, 1 setup time

SIK3

= 2.7 to 5.5 V

150

(to SCK

)

500

SB0, 1 hold time (from SCK

)

KSI3

KCY3

SB0, 1 output delay

KSO3

= 1 k

Note

= 2.7 to 5.5 V

250

time from SCK

= 100 pF

1000

SB0, 1

from SCK

KSB

KCY3

SCK

from SB0, 1

SBK

KCY3

SB0, 1 low-level width

SBL

KCY3

SB0, 1 high-level width

SBH

KCY3

Note

and C

are the load resistance and load capacitance of the SB0, 1 output line.

SBI Mode (SCK...External clock input (slave)): (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY4

= 2.7 to 5.5 V

800

3200

SCK high/low-level

KL4

, t

KH4

= 2.7 to 5.5 V

400

width

1600

SB0, 1 setup time

SIK4

= 2.7 to 5.5 V

100

(to SCK

)

150

SB0, 1 hold time (from SCK

)

KSI4

KCY4

SB0, 1 output delay

KSO4

= 1 k

Note

= 2.7 to 5.5 V

300

time from SCK

= 100 pF

1000

SB0, 1

from SCK

KSB

KCY4

SCK

from SB0, 1

SBK

KCY4

SB0, 1 low-level width

SBL

KCY4

SB0, 1 high-level width

SBH

KCY4

Note

and C

are the load resistance and load capacitance of the SB0, 1 output line.

PD753104, 753106, 753108

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

= 40 to +85 °C)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Release signal set time

SREL

Oscillation stabilization

WAIT

Release by RESET

Note 2

wait time

Note 1

Release by interrupt request

Note 3

Notes 1.

The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent

unstable operation at the oscillation start.

Either 2

or 2

can be selected by the mask option.

Depends on the basic interval timer mode register (BTM) settings (see the table below).

BTM3

BTM2

BTM1

BTM0

Wait time

fx = at 4.19 MHz

fx = at 6.0 MHz

/fx (approx. 250 ms)

/fx (approx. 175 ms)

/fx (approx. 31.3 ms)

/fx (approx. 21.8 ms)

/fx (approx. 7.81 ms)

/fx (approx. 5.46 ms)

/fx (approx. 1.95 ms)

/fx (approx. 1.37 ms)

Data Retention Timing (STOP Mode Release by RESET)

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

RESET

STOP Instruction Execution

STOP Mode

Data Retention Mode

Internal Reset Operation

HALT Mode

Operating Mode

SREL

WAIT

SREL

WAIT

STOP Instruction Execution

STOP Mode

Data Retention Mode

HALT Mode

Operating Mode

Standby Release Signal
(Interrupt Request)

PD753104, 753106, 753108

15. RECOMMENDED SOLDERING CONDITIONS

The

PD753108 should be soldered and mounted under the conditions recommended in the table below.

For details of recommended soldering conditions, refer to the information document "Semiconductor Device

Mounting Technology Manual" (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 15-1. Surface Mounting Type Soldering Conditions

(1)

PD753104GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)

PD753106GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)

PD753108GC-xxx-AB8 : 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)

Soldering

Soldering Conditions

Symbol

Method

Infrared reflow

Peak package's surface temperature: 235 °C, Reflow time: 30 seconds or less

IR35-00-3

(at 210 °C or higher), Number of reflow processes: 3 max.

VPS

Peak package's surface temperature: 215 °C, Reflow time: 40 seconds or less

VP15-00-3

(at 200 °C or higher), Number of reflow processes: 3 max.

Wave soldering

Solder temperature: 260 °C or below, Flow time: 10 seconds or less, Number of

WS60-00-1

flow processes: 1, Preheating temperature: 120 °C or below (package surface

temperature)

Partial heating

Pin temperature: 300 °C or below, Time: 3 seconds or less (per device side)

Caution

Use of more than one soldering method should be avoided (except for partial heating).

(2)

PD753104GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

PD753106GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

PD753108GK-xxx-8A8 : 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

Soldering

Soldering Conditions

Symbol

Method

Infrared reflow

Peak package's surface temperature: 235 °C, Reflow time: 30 seconds or less

IR35-00-2

(at 210 °C or higher), Number of reflow processes: 2 max.

VPS

Peak package's surface temperature: 215 °C, Reflow time: 40 seconds or less

VP15-00-2

(at 200 °C or higher), Number of reflow processes: 2 max.

Wave soldering

Solder temperature: 260 °C or below, Flow time: 10 seconds or less, Number of

WS60-00-1

flow processes: 1, Preheating temperature: 120 °C or below (package surface

temperature)

Partial heating

Pin temperature: 300 °C or below, Time: 3 seconds or less (per device side)

Caution Use of more than one soldering method should be avoided (except for partial heating).

PD753104, 753106, 753108

APPENDIX A.

PD75308B, 753108 AND 75P3116 FUNCTIONAL LIST

Parameter

PD75308B

PD753108

PD75P3116

Program memory

Mask ROM

One-time PROM

0000H to 1F7FH

0000H to 1FFFH

0000H to 3FFFH

(8064 x 8 bits)

(8192 x 8 bits)

(16384 x 8 bits)

Data memory

000H to 1FFH
(512 x 4 bits)

CPU

75X Standard

75XL CPU

Instruction

When main system clock is

0.95, 1.91, 15.3

· 0.95, 1.91, 3.81, 15.3

s (during 4.19-MHz operation)

execution

selected

(during 4.19-MHz operation)

· 0.67, 1.33, 2.67, 10.7

s (during 6.0-MHz operation)

time

When subsystem clock is

122

s (32.768-kHz operation)

selected

Stack

SBS register

None

SBS.3 = 1: Mk I mode selection
SBS.3 = 0: Mk II mode selection

Stack area

000H to 0FFH

000H to 1FFH

Subroutine call instruction

2-byte stack

When Mk I mode: 2-byte stack

stack operation

When Mk II mode: 3-byte stack

Instruction

BRA !addr1

Unavailable

When Mk I mode: unavailable

CALLA !addr1

When Mk II mode: available

MOVT XA, @BCDE

Available

MOVT XA, @BCXA
BR BCDE
BR BCXA

CALL !addr

3 machine cycles

Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles

CALLF !faddr

2 machine cycles

Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles

I/O port

CMOS input

CMOS input/output

Bit port output

N-ch open-drain input/output

Total

LCD controller/driver

Segment selection: 24/28/32

Segment selection: 16/20/24 segments

segments

(can be changed to CMOS input/output port in 4 time-unit;

(can be changed to CMOS

max. 8)

input/output port in 4 time-
unit; max. 8)

Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),

1/4 duty (1/3 bias)

On-chip split resistor for LCD driver can be specified by using

No on-chip split resistor for

mask option.

LCD driver

Timer

3 channels

5 channels

· Basic interval timer:

· Basic interval timer/watchdog timer: 1 channel

1 channel

· 8-bit timer/event counter: 3 channels

· 8-bit timer/event counter:

(can be used as 16-bit timer/event counter)

1 channel

· Watch timer: 1 channel

PD753104, 753106, 753108

Parameter

PD75308B

PD753108

PD75P3116

Clock output (PCL)

, 524, 262, 65.5 kHz

(Main system clock:

(Main system clock: during 4.19-MHz operation)

during 4.19-MHz operation)

, 750, 375, 93.8 kHz

(Main system clock: during 6.0-MHz operation)

BUZ output (BUZ)

· 2 kHz

· 2, 4, 32 kHz

(Main system clock:

(Main system clock: during 4.19-MHz operation or

during 4.19-MHz operation)

subsystem clock: during 32.768-kHz operation)

· 2.93, 5.86, 46.9 kHz

(Main system clock: 6.0-MHz operation)

Serial interface

3 modes are available
· 3-wire serial I/O mode ... MSB/LSB can be selected for transfer first bit
· 2-wire serial I/O mode
· SBI mode

SOS

Feedback resistor cut flag

None

Contained

(SOS.0)

Sub-oscillator current cut flag

None

Contained

(SOS.1)

None

Yes

Standby release by INT0

Unavailable

Available

Vectored interrupt

External: 3, internal: 3

External: 3, internal: 5

Supply voltage

= 2.0 to 6.0 V

= 1.8 to 5.5 V

Operating ambient temperature

= 40 to +85 °C

Package

· 80-pin plastic QFP

· 64-pin plastic QFP (14 x 14 mm, 0.8-mm pitch)

(14 x 20 mm)

· 64-pin plastic QFP (12 x 12 mm, 0.65-mm pitch)

· 80-pin plastic QFP

(14 x 14 mm)

· 80-pin plastic TQFP

(Fine pitch) (12 x 12 mm)

PD753104, 753106, 753108

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are provided for system development using the

PD753108.

In the 75XL Series, the relocatable assembler which is common to the series is used in combination with the

device file of each product.

Language processor

RA75X relocatable assembler

Host machine

Part number

Supply media

(product name)

PC-9800 Series

MS-DOSTM

3.5-inch 2HD

S5A13RA75X

Ver. 3.30 to

5-inch 2HD

S5A10RA75X

Ver. 6.2

Note

IBM PC/ATTM and

Refer to

3.5-inch 2HC

S7B13RA75X

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10RA75X

Device file

Host machine

Part number

Supply media

(product name)

PC-9800 Series

MS-DOS

3.5-inch 2HD

S5A13DF753108

Ver. 3.30 to

5-inch 2HD

S5A10DF753108

Ver. 6.2

Note

IBM PC/AT and

Refer to

3.5-inch 2HC

S7B13DF753108

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10DF753108

Note

Ver. 5.00 and later have the task swap function, but it cannot be used for this software.

Remark Operation of the assembler and the device file is guaranteed only on the above host machines and OSs.

PD753104, 753106, 753108

PROM write tools

Hardware

PG-1500

PG-1500 is a PROM programmer which enables you to program single-chip microcontrollers

including PROM by stand-alone or host machine operation by connecting an attached board

and optional programmer adapter to PG-1500. It also enables you to program typical PROM

devices of 256K bits to 4M bits.

PA-75P3116GC

PROM programmer adapter for the

PD75P3116GC. Connect the programmer adapter to

PG-1500 for use.

PA-75P3116GK

PROM programmer adapter for the

PD75P3116GK. Connect the programmer adapter to

PG-1500 for use.

Software

PG-1500 controller

PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500

is controlled on the host machine.

Host machine

Part number

Supply media

(product name)

PC-9800 Series

MS-DOS

3.5-inch 2HD

S5A13PG1500

Ver. 3.30 to

5-inch 2HD

S5A10PG1500

Ver. 6.2

Note

IBM PC/AT and

Refer to

3.5-inch 2HD

S7B13PG1500

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10PG1500

Note

Ver. 5.00 and later have the task swap function, but it cannot be used for this software.

Remark Operation of the PG-1500 controller is guaranteed only on the above host machines and OSs.

PD753104, 753106, 753108

Debugging tool

The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the

PD753108.

The system configurations are described as follows.

Hardware

IE-75000-R

Note 1

In-circuit emulator for debugging the hardware and software when developing the application

systems that use the 75X Series and 75XL Series. When developing a

PD753108

Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R

or EP-753108GK-R) that are sold separately must be used with the IE-75000-R.

By connecting with the host machine and the PROM programmer, efficient debugging can

be made.

It contains the emulation board (IE-75000-R-EM) which is connected.

IE-75001-R

In-circuit emulator for debugging the hardware and software when developing the application

systems that use the 75X Series and 75XL Series. When developing a

PD753108

Subseries, the emulation board (IE-75300-R-EM) and emulation probe (EP-753108GC-R

or EP-753108GK-R) that are sold separately must be used with the IE-75001-R.

It can debug the system efficiently by connecting the host machine and PROM programmer.

IE-75300-R-EM

Emulation board for evaluating the application systems that use a

PD753108 Subseries.

It must be used with the IE-75000-R or IE-75001-R.

EP-753108GC-R

Emulation probe for the

PD753108GC.

It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 64-pin conversion socket EV-9200GC-64 which facilitates

EV-9200GC-64

connection to a target system.

EP-753108GK-R

Emulation probe for the

PD753108GK.

It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 64-pin conversion adapter TGK-064SBW which facilitates

TGK-064SBW

Note 2

connection to a target system.

Software

IE control program

Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronics interface

and controls the IE-75000-R or IE-75001-R on a host machine.

Host machine

Part No.

Supply media

(product name)

PC-9800 Series

MS-DOS

3.5-inch 2HD

S5A13IE75X

Ver. 3.30 to

5-inch 2HD

S5A10IE75X

Ver. 6.2

Note 3

IBM PC/AT and

Refer to

3.5-inch 2HC

S7B13IE75X

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10IE75X

Notes 1.

Maintenance product.

This is a product of TOKYO ELETECH CORPORATION (Tokyo 03-5295-1661). For purchasing,

contact an NEC sales representative.

Ver. 5.00 and later have the task swap function, but it cannot be used for this software.

Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.

2. The

PD753104, 753106, 753108 and 75P3116 are commonly referred to as the

PD753108

Subseries.

PD753104, 753106, 753108

APPENDIX C. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Device Related Documents

Document Name

Document No.

English

Japanese

PD753104, 753106, 753108 Data Sheet

U10086E (This document)

U10086J

PD75P3116 Data Sheet

U11369E

U11369J

PD753108 User's Manual

U10890E

U10890J

PD753108 Instruction Application Table

IEM-5600

75XL Series Selection Guide

U10453E

U10453J

Development Tool Related Documents

Document Name

Document No.

English

Japanese

Hardware

IE-75000-R/IE-75001-R User's Manual

EEU-1416

EEU-846

IE-75300-R-EM User's Manual

U11354E

U11354J

EP-753108GC/GK-R User's Manual

EEU-1495

EEU-968

PG-1500 User's Manual

EEU-1335

U11940J

Software

RA75X Assembler Package

Operation

EEU-1346

EEU-731

User's Manual

Language

EEU-1363

EEU-730

PG-1500 Controller User's Manual

PC-9800 Series

EEU-1291

EEU-704

(MS-DOS) base

IBM PC Series

U10540E

EEU-5008

(PC DOS) base

Other Related Documents

Document Name

Document No.

English

Japanese

IC Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535E

C10535J

Quality Grades on NEC Semiconductor Devices

C11531E

C11531J

NEC Semiconductor Device Reliability/Quality Control System

C10983E

C10983J

Electrostatic Discharge (ESD) Test

MEM-539

Guide to Quality Assurance for Semiconductor Devices

MEI-1202

C11893J

Microcomputer Product Series Guide

U11416J

Caution

The above related documents are subject to change without notice. For design purpose, etc.,

be sure to use the latest documents.

PD753104, 753106, 753108

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry.

Each unused pin should be connected to V

or GND with a resistor, if it is

considered to have a possibility of being an output pin. All handling related

to the unused pins must be judged device by device and related specifications

governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immediately

after power-on for devices having reset function.

PD753104, 753106, 753108

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

PD753104, 753106, 753108

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/

or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5

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