Document Outline

1. PIN CONFIGURATION(TOP VIEW)
2. BLOCK DIAGRAM
3. PIN FUNCTION
- 3.1 Port Pins
- 3.2 Non-Port Pins
- 3.3 Pin Input/Output Circuits
- 3.4 Recommended Connections for Unused Pins
4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
- 4.1 Difference Between Mk I and Mk II Modes
- 4.2 Setting Method of Stack Bank Select Register(SBS)
5. MEMORY CONFIGURATION
6. PERIPHERAL HARDWARE FUNCTION
- 6.1 Digital I/O Port
- 6.2 Clock Generator
- 6.3 Clock Output Circuit
- 6.4 Basic Interval Timer/Watchdog Timer
- 6.5 Watch Timer
- 6.6 Timer/Event Counter
- 6.7 Serial Interface
- 6.8 LCD Controller/Driver
- 6.9 Bit Sequential Buffer
7. INTERRUPT FUNCTION AND TEST FUNCTION
8. STANDBY FUNCTION
9. RESET FUNCTION
10. MASK OPTION
11. INSTRUCTION SET
12. ELECTRICAL SPECIFICATIONS
13.CHARACTERISTIC CURVES (REFERENCE VALUES)
14. PACKAGE DRAWINGS
15. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A uPD753108, 753208, AND 75P3216 FUNCTIONAL LIST
APPENDIX B DEVELOPMENT TOOLS
APPENDIX C RELATED DOCUMENTS

1996

DATA SHEET

4-BIT SINGLE-CHIP MICROCONTROLLERS

The

PD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing

capability comparable to that of an 8-bit microcontroller.

The

PD753208 has an on-chip LCD controller/driver and is based on the

PD75308B of the 75X Series.

However, the

PD75308B is supplied in an 80-pin package, whereas the

PD753208 is supplied in a 48-

pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In

addition, the

PD753208 features expanded CPU functions and performs high-speed operations at a low

voltage of 1.8 V.

Detailed information about functions can be found in the following user's manual. Be sure to read it

before designing.

PD753208 User's Manual: U10158E

Document No. U10166EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan

MOS INTEGRATED CIRCUIT

PD753204, 753206, 753208

The information in this document is subject to change without notice.

The mark shows major revised points.

Features

Low-voltage operation: V

= 1.8 to 5.5 V

Can be driven by two 1.5-V batteries

Internal memory

Program memory (ROM):

4096

8 bits (

PD753204)

6144

8 bits (

PD753206)

8192

8 bits (

PD753208)

Data memory (RAM):

512

4 bits

Variable instruction execution time for high-speed

operation and power saving operation

0.95, 1.91, 3.81, 15.3

s (@ 4.19-MHz operation)

0.67, 1.33, 2.67, 10.7

s (@ 6.0-MHz operation)

Internal programmable LCD controller/driver

Small package:

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

One-time PROM version:

PD75P3216

Applications

Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems,

gas meters, etc.

Ordering Information

Part number

Package

ROM (

8 bits)

PD753204GT-

×××

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

4096

PD753206GT-

×××

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

6144

PD753208GT-

×××

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

8192

Remark

×××

indicates ROM code suffix.

Unless otherwise specified, references in this data sheet to the

PD753208 mean the

PD753204 and the

PD753206.

PD753204, 753206, 753208

Function Outline

Parameter

Function

Instruction execution time

· 0.95, 1.91, 3.81, 15.3

s (@ 4.19-MHz operation with system clock)

· 0.67, 1.33, 2.67, 10.7

s (@ 6.0-MHz operation with system clock)

Internal memory

ROM

4096

8 bits (

PD753204)

6144

8 bits (

PD753206)

8192

8 bits (

PD753208)

RAM

512

4 bits

General-purpose register

· 4-bit operation: 8

4 banks

· 8-bit operation: 4

4 banks

Input/

CMOS input

Connecting on-chip pull-up resistors can be specified by software: 5

output

CMOS input/output

Connecting on-chip pull-up resistors can be specified by software: 20

port

Also used for segment pins: 8

N-ch open-drain

On-chip pull-up resistors can be specified by mask option

input/output

13-V withstand voltage

Total

LCD controller/driver

· Segment selection:

4/8/12 segments (can be changed to CMOS input/

output port in 4-time units; max. 8)

· Display mode selection:

Static

1/2 duty (1/2 bias)

1/3 duty (1/2 bias)

1/3 duty (1/3 bias)

1/4 duty (1/3 bias)

· On-chip split resistor for LCD drive can be specified by mask option

Timer

5 channels

· 8-bit timer/event counter: 1 channel

· 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier

generator, and timer with gate)

· Basic interval timer/watchdog timer: 1 channel

· Watch timer: 1 channel

Serial interface

· 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

· 2-wire serial I/O mode

· SBI mode

Bit sequential buffer (BSB)

16 bits

Clock output (PCL)

, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)

, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)

Buzzer output (BUZ)

· 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)

· 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)

Vectored interrupts

External: 2, Internal: 5

Test input

External: 1, Internal: 1

System clock oscillator

Ceramic or crystal oscillator for system clock oscillation

Standby function

STOP/HALT mode

Power supply voltage

= 1.8 to 5.5 V

Package

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

PD753204, 753206, 753208

CONTENTS

PIN CONFIGURATION (TOP VIEW) .................................................................................................... 5

BLOCK DIAGRAM ................................................................................................................................ 6

3. PIN FUNCTIONS .................................................................................................................................... 7

3.1

Port Pins ...................................................................................................................................... 7

3.2

Non-Port Pins .............................................................................................................................. 9

3.3

Pin Input/Output Circuits ......................................................................................................... 11

3.4

Recommended Connections for Unused Pins ....................................................................... 13

SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................ 14

4.1

Difference Between Mk I and Mk II Modes .............................................................................. 14

4.2

Setting Method of Stack Bank Select Register (SBS) ........................................................... 15

MEMORY CONFIGURATION ............................................................................................................. 16

PERIPHERAL HARDWARE FUNCTION ........................................................................................... 21

6.1

Digital I/O Port ........................................................................................................................... 21

6.2

Clock Generator ........................................................................................................................ 22

6.3

Clock Output Circuit ................................................................................................................. 23

6.4

Basic Interval Timer/Watchdog Timer ..................................................................................... 24

6.5

Watch Timer .............................................................................................................................. 25

6.6

Timer/Event Counter ................................................................................................................. 26

6.7

Serial Interface .......................................................................................................................... 30

6.8

LCD Controller/Driver ............................................................................................................... 32

6.9

Bit Sequential Buffer ................................................................................................................ 34

INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 35

STANDBY FUNCTION ........................................................................................................................ 37

RESET FUNCTION ............................................................................................................................. 38

10. MASK OPTION ................................................................................................................................... 41

11. INSTRUCTION SET ............................................................................................................................ 42

12. ELECTRICAL SPECIFICATIONS ....................................................................................................... 56

13. CHARACTERISTIC CURVES (REFERENCE VALUES) ................................................................... 68

14. PACKAGE DRAWINGS ..................................................................................................................... 70

15. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 71

PD753204, 753206, 753208

1. PIN CONFIGURATION (TOP VIEW)

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

PD753204GT-

×××

PD753206GT-

×××

PD753208GT-

×××

Note Connect IC (Internally Connected) pin directly to V

Pin Identification

P00 to P03

: Port0

S12 to S23

: Segment Output 12 to 23

P10, P13

: Port1

LC0

to V

LC2

: LCD Power Supply 0 to 2

P20 to P23

: Port2

BIAS

: LCD Power Supply Bias Control

P30 to P33

: Port3

LCDCL

: LCD Clock

P50 to P53

: Port5

SYNC

: LCD Synchronization

P60 to P63

: Port6

TI0

: Timer Input 0

P80 to P83

: Port8

PTO0 to PTO2 : Programmable Timer Output 0 to 2

P90 to P93

: Port9

BUZ

: Buzzer Clock

KR0 to KR3

: Key Return 0 to 3

PCL

: Programmable Clock

COM0 to COM3 : Common Output 0 to 3

INT0, INT4

: External Vectored Interrupt 0, 4

SCK

: Serial Clock

X1, X2

: System Clock Oscillation 1, 2

: Serial Input

RESET

: Reset

: Serial Output

: Internally Connected

SB0, SB1

: Serial Data Bus 0, 1

: Positive Power Supply

: Ground

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

COM0
COM1
COM2
COM3

BIAS

LC0

LC1

LC2

P30/LCDCL

P31/SYNC

P32
P33

P50
P51
P52
P53

P60/KR0
P61/KR1
P62/KR2
P63/KR3

X1
X2

S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
IC

Note

PD753204, 753206, 753208

2. BLOCK DIAGRAM

Note The ROM capacity depends on the product.

PORT0

PORT1

PORT2

PORT3

PORT5

PORT6

PORT8

PORT9

P00 to P03

P10,P13

P20 to P23

P30 to P33

P50 to P53

P60 to P63

P80 to P83

P90 to P93

S12 to S15

S16/P93 to
S19/P90

S20/P83 to
S23/P80

COM0 to COM3

LC0

LC1

LC2

BIAS
LCDCL/P30

SYNC/P31

LCD

LCD
CONTROLLER/
DRIVER

INT0/P10

INTW

CPU CLOCK

RESET

STANDBY
CONTROL

SYSTEM
CLOCK
GENERATOR

X1 X2

CLOCK
DIVIDER

CLOCK
OUTPUT
CONTROL

PCL/PTO2/P22

INTERRUPT
CONTROL

BIT SEQ
BUFFER (16)

INTCSI TOUT

INTT2

CLOCKED
SERIAL
INTERFACE

8-BIT
TIMER
COUNTER #1

8-BIT
TIMER
COUNTER #2

CASCADED
16-BIT
TIMER
COUNTER

PTO1/P21

TOUT

PTO2/PCL/P22

SP (8)

SBS

BANK

GENERAL REG.

DATA
MEMORY
(RAM)
512

4 BITS

ALU

PROGRAM
COUNTER

PROGRAM
MEMORY

Note

(ROM)

LCD

WATCH
TIMER

BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER

BUZ/P23

TI0/P13

TPO0/P20

8-BIT
TIMER/EVENT
COUNTER #0

INTT1

INTT0 TOUT

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT4/P00

KR0/P60 to
KR3/P63

DECODE
AND
CONTROL

INTBT

PD753204, 753206, 753208

3. PIN FUNCTION

3.1 Port Pins (1/2)

Pin Name

Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function

I/O

TYPE

Note 1

P00

Input

INT4

Input

(B)

P01

Input/Output

SCK

(F)-A

P02

Input/Output

SO/SB0

(F)-B

P03

Input/Output

SI/SB1

(M)-C

P10

Input

INT0

Input

(B)-C

P13

TI0

P20

Input/Output

PTO0

Input

E-B

P21

PTO1

P22

PCL/PTO2

P23

BUZ

P30

Input/Output

LCDCL

Input

E-B

P31

SYNC

P32

P33

P50 to

Input/Output

M-D

P53

Note 2

Notes 1. Characters in parentheses indicate the Schmitt-trigger input.

2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),

low level input leakage current increases when input or bit manipulation instruction is executed.

4-bit input port (PORT0).

For P01 to P03, on-chip pull-up resistors can

be specified by software in 3-bit units.

High level
(when pull-
up resistors
are
provided) or
high-
impedance

Input port in 1 bit unit (PORT1).

On-chip pull-up resistors can be specified by

software in 2-bit units.

Noise elimination circuit can be specified with

P10/INT0.

4-bit input/output port (PORT2).

On-chip pull-up resistors can be specified by

software in 4-bit units.

Programmable 4-bit input/output port (PORT3).

This port can be specified input/output bit-

wise. On-chip pull-up resistor can be speci-

fied by software in 4-bit units.

N-ch open-drain 4-bit input/output port (PORT5).

A pull-up resistor can be contained bit-wise

(mask option).

Withstand voltage is 13 V in open-drain mode.

PD753204, 753206, 753208

3.1 Port Pins (2/2)

Pin Name

Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function

I/O

TYPE

Note 1

P60

Input/Output

KR0

Input

(F)-A

P61

KR1

P62

KR2

P63

KR3

P80

Input/Output

S23

Yes

Input

P81

S22

P82

S21

P83

S20

P90

Input/Output

S19

Input

P91

S18

P92

S17

P93

S16

Notes 1. Characters in parentheses indicate the Schmitt-trigger input.

2. Do not connect on-chip pull-up resistors specified by software when using as segment signal output

pins.

Programmable 4-bit input/output port (PORT6).

This port can be specified for input/output bit-

wise.

On-chip pull-up resistors can be specified by

software in 4-bit units.

4-bit input/output port (PORT8).

On-chip pull-up resistors can be specified by

software in 4-bit units.

Note 2

4-bit input/output port (PORT9).

On-chip pull-up resistors can be specified by

software in 4-bit units.

Note 2

PD753204, 753206, 753208

3.2 Non-Port Pins (1/2)

Pin Name

Input/Output

Alternate

Function

After Reset

I/O Circuit

Function

TYPE

Note 1

TI0

Input

P13

Inputs external event pulses to the timer/event

Input

(B)-C

counter.

PTO0

Output

P20

Timer/event counter output

Input

E-B

PTO1

P21

Timer counter output

PTO2

P22/PCL

PCL

P22/PTO2

Clock output

BUZ

P23

Optional frequency output (for buzzer output

or system clock trimming)

SCK

Input/Output

P01

Serial clock input/output

Input

(F)-A

SO/SB0

P02

Serial data output

(F)-B

Serial data bus input/output

SI/SB1

P03

Serial data input

(M)-C

Serial data bus input/output

INT4

Input

P00

Edge detection vectored interrupt input (both

Input

(B)

rising edge and falling edge detection)

INT0

Input

P10

Input

(B)-C

KR0 to KR3

Input/Output

P60 to P63

Falling edge detection testable input

Input

(F)-A

S12 to S15

Output

Segment signal output

Note 2

G-A

S16 to S19

Output

P93 to P90

Segment signal output

Input

S20 to S23

Output

P83 to P80

Segment signal output

Input

COM0 to COM3

Output

Common signal output

Note 2

G-B

LC0

to V

LC2

LCD drive power

On-chip split resistor is enable (mask option).

BIAS

Output

Output for external split resistor disconnect

Note 3

LCDCL

Note 4

Input/Output

P30

Clock output for externally expanded driver

Input

E-B

SYNC

Note 4

Input/Output

P31

Clock output for externally expanded driver sync

Input

E-B

Notes 1. Characters in parentheses indicate the Schmitt trigger input.

2. Each display output selects the following VLCX as input source.

S12 to S15: V

LC1

, COM0 to COM2: V

LC2

, COM3: V

LC0

3. When a split resistor is contained ....... Low level

When no split resistor is contained ...... High-impedance

4. These pins are provided for future system expansion.

At present, these pins are used only as pins P30 and P31.

Edge detection vectored

With clock elimination

interrupt input (detection

circuit/asynchronous

edge can be selected).

selectable

Noise elimination circuit

can be specified.

PD753204, 753206, 753208

TYPE F-B

TYPE H

TYPE G-A

TYPE M-D

TYPE M-C

P.U.R
enable

P.U.R

P-ch

N-ch

output

disable

(P)

data

output

disable

output

disable

(N)

IN/OUT

P.U.R : Pull-Up Resistor

data

output

disable

P.U.R.

enable

P.U.R

P-ch

IN/OUT

N-ch

P.U.R : Pull-Up Resistor

LC1

P-ch

N-ch

OUT

N-ch

LC2

N-ch

COM

data

P-ch

IN/OUT

N-ch
(+13-V
withstand)

data

output

disable

P.U.R.
(Mask Option)

P.U.R. : Pull-Up Resistor

Voltage
control
circuit

Pull-up resistor that only operates upon the execution
of an input instruction when the pull-up resistor is not
connected via the mask option (it is available during
low-voltage).

Note

P-ch

P.U.R.

Note

input

instruction

TYPE G-B

LC0

LC1

SEG

data

LC2

N-ch

SEG

data

output

disable

TYPE G-A

TYPE E-B

IN/OUT

(2/2)

P-ch
N-ch

LC0

P-ch
N-ch

P-ch

N-ch

OUT

N-ch

P-ch
N-ch

PD753204, 753206, 753208

3.4 Recommended Connections for Unused Pins

Table 3-1. List of Recommended Connections for Unused Pins

Recommended Connection

P00/INT4

Connect to V

or V

P01/SCK

Connect individually to V

or V

via a resistor

P02/SO/SB0

P03/SI/SB1

Connect to V

P10/INT0

Connect to V

or V

P13/TI0

P20/PTO0

Input state: Connect individually to V

or V

via a resistor

P21/PTO1

Output state: No connection

P22/PCL/PTO2

P23/BUZ

P30/LCDCL

P31/SYNC

P32

P33

P50 to P53

Input state

: Connect to V

Output state : Connect to V

(Do not connect pull-up

resistor in the mask option)

P60/KR0 to P63/KR3

Input state

: Connect individually to V

or V

via a

resistor

Output state : No connection

S0 to S15

No connection

COM0 to COM3

S16/P93 to S19/P90

Input state: Connect individually to V

or V

via a resistor

S20/P83 to S23/P80

Output state: No connection

LC0

to V

LC2

Connect to V

BIAS

Only if all of V

LC0

to V

LC2

are unused, connect to V

In other cases, no connection.

Connect to V

directly

PD753204, 753206, 753208

SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Difference Between Mk I and Mk II Modes

The CPU of the

PD753208 has the following two modes: Mk I and Mk II, either of which can be selected.

The mode can be switched by bit 3 of the Stack Bank Select register (SBS).

Mk I mode:

Upward compatible with the

PD75308B. Can be used in the 75XL CPU with a ROM

capacity of up to 16 Kbytes.

Mk II mode:

Incompatible with

PD75308B. Can be used in all the 75XL CPU including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I mode

Mk II mode

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA ! addr1 instruction

Not available

Available

CALLA ! addr1 instruction

CALL ! addr instruction

3 machine cycles

4 machine cycles

CALLF ! faddr instruction

2 machine cycles

3 machine cycles

Caution

The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.

Software compatibility with products whose program memory exceeds 16 Kbytes can be raised

by using this mode.

When the MkII mode is selected, the number of stack bytes increases by one byte per stack

during subroutine call instruction execution compared with the MkI mode. When the !faddr

instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore,

if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI

mode is recommended.

PD753204, 753206, 753208

Caution

Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode.

When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode.

4.2 Setting Method of Stack Bank Select Register (SBS)

Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.

The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be

initialized to 100

Note

at the beginning of a program. When using the Mk II mode, it must be initialized to 000

Note

Note The desired numbers must be set in the

positions.

Figure 4-1. Stack Bank Select Register Format

SBS3

SBS2

SBS1

SBS0

Symbol

SBS

Address

F84H

Memory bank 0

Memory bank 1

Other than
above

0 must be set in the bit 2 position.

Stack area specification

Mk II mode

Mk I mode

Mode switching specification

Setting prohibited

PD753204, 753206, 753208

5. MEMORY CONFIGURATION

Program Memory (ROM)

.... 4096

8 bits (

PD753204)

.... 6144

8 bits (

PD753206)

.... 8192

8 bits (

PD753208)

Addresses 0000H and 0001H

Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET

signal is generated are written. Reset and start are possible at an arbitrary address.

Addresses 0002H to 000DH

Vector table wherein the program start address and values set for the RBE and MBE by the vectored

interrupts are written. Interrupt execution can be started at an arbitrary address.

Addresses 0020H to 007FH

Table area referenced by the GETI instruction

Note

Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte

instruction, or two 1-byte instructions. It is used to decrease the program steps.

Data Memory (RAM)

Data area ... 512 words

4 bits (000H to 1FFH)

Peripheral hardware area ... 128 words

4 bits (F80H to FFFH)

PD753204, 753206, 753208

Figure 5-1. Program Memory Map (1/3)

(a)

PD753204

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

0 0 0 H

Address

MBE RBE

Internal reset start address

(high-order 4 bits)

0 0 2 H MBE RBE

INTBT/INT4

(high-order 4 bits)

start address

0 0 4 H MBE RBE

INT0

(high-order 4 bits)

start address

0 0 6 H

0 0 8 H MBE RBE

INTCSI

(high-order 4 bits)

start address

0 0 A H MBE RBE

INTT0

(high-order 4 bits)

start address

0 0 C H MBE RBE

INTT1/INTT2

(high-order 4 bits)

start address

0 2 0 H

0 7 F H

0 8 0 H

7 F F H

8 0 0 H

F F F H

GETI instruction reference table

(low-order 8 bits)

BRCB
! caddr instruction
branch address

CALL !addr instruction
subroutine entry address

BR $addr instruction
relative branch address

15 to 1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

Internal reset start address

INTBT/INT4

start address

INT0

start address

INTCSI

start address

INTT0

start address

INTT1/INTT2

start address

Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1

Note

CALLA !addr1

Note

instructions

CALLF
! faddr
instruction
entry
address

PD753204, 753206, 753208

Figure 5-1. Program Memory Map (2/3)

(b)

PD753206

0 0 0 0 H

Address

0 0 0 2 H MBE RBE

INTBT/INT4

(high-order 5 bits)

start address

0 0 0 4 H MBE RBE

INT0

(high-order 5 bits)

start address

0 0 0 6 H

0 0 0 8 H MBE RBE

INTCSI

(high-order 5 bits)

start address

0 0 0 A H MBE RBE

INTT0

(high-order 5 bits)

start address

0 0 2 0 H

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

MBE RBE

Internal reset start address

(high-order 5 bits)

0 F F F H

1 0 0 0 H

1 7 F F H

GETI instruction reference table

0 0 0 C H MBE RBE

INTT1/INTT2

(high-order 5 bits)

start address

(low-order 8 bits)

CALLF
! faddr
instruction
entry
address

BRCB ! caddr
instruction
branch
address

Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1

Note

CALLA ! addr1

Note

instructions

CALL ! addr
instruction
subroutine entry
address

BR $ addr
instruction relative
branch address

15 to 1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB ! caddr
instruction
branch
address

Internal reset start address

INTBT/INT4

INT0

INTCSI

INTT0

INTT1/INTT2

start address

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

PD753204, 753206, 753208

Figure 5-1. Program Memory Map (3/3)

(c)

PD753208

0 0 0 0 H

Address

0 0 0 2 H MBE RBE

INTBT/INT4

(high-order 5 bits)

start address

0 0 0 4 H MBE RBE

INT0

(high-order 5 bits)

start address

0 0 0 6 H

0 0 0 8 H MBE RBE

INTCSI

(high-order 5 bits)

start address

0 0 0 A H MBE RBE

INTT0

(high-order 5 bits)

start address

0 0 2 0 H

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

MBE RBE

Internal reset start address

(high-order 5 bits)

0 F F F H

1 0 0 0 H

1 F F F H

GETI instruction reference table

0 0 0 C H MBE RBE

INTT1/INTT2

(high-order 5 bits)

start address

(low-order 8 bits)

CALLF
! faddr
instruction
entry
address

BRCB ! caddr
instruction
branch
address

Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1

Note

CALLA ! addr1

Note

instructions

CALL ! addr
instruction
subroutine entry
address

BR $ addr
instruction relative
branch address

15 to 1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB ! caddr
instruction
branch
address

Internal reset start address

INTBT/INT4

INT0

INTCSI

INTT0

INTT1/INTT2

start address

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

PD753204, 753206, 753208

6. PERIPHERAL HARDWARE FUNCTION

6.1 Digital I/O Port

There are three kinds of I/O ports.

CMOS input ports (Ports 0, 1)

: 6

CMOS input/output ports (Ports 2, 3, 6, 8, 9)

: 20

N-ch open-drain input/output ports (Port 5)

: 4

Total

Table 6-1. Types and Features of Digital Ports

Port

Function

Operation and features

Remarks

PORT0

4-bit input

The alternate function pins have an output function

Also used for the INT4, SCK,

with operation mode when using the serial interface

SO/SB0, and SI/SB1 pins.

function.

PORT1

1-bit input

2-bit input dedicated port

Also used for the INT0 and
TI0.

PORT2

4-bit I/O

Can be set to input mode or output mode in 4-bit

Also used for the PTO0 to

units.

PTO2, PCL, and BUZ pins.

PORT3

Can be set to input mode or output mode bit-wise.

Also used for the LCDCL
and SYNC pins.

PORT5

4-bit I/O (N-

Can be set to input mode or output mode in 4-bit

channel open-

units. On-chip pull-up resistor can be specified

drain, 13-V

by mask option bit-wise.

withstand)

PORT6

4-bit I/O

Can be set to input mode or output mode bit-wise.

Also used for the KR0 to
KR3 pins.

PORT8

Can be set to input mode

Ports 8 and 9 are paired

Also used for the S20 to

or output mode in 4-bit

and data can be input/

S23 pins.

units.

output in 8-bit units.

PORT9

Also used for the S16 to
S19 pins.

PD753204, 753206, 753208

6.2 Clock Generator

The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is

shown in Figure 6-1.

The operation of the clock generator is determined by the Processor Clock Control Register (PCC).

The instruction execution time can also be changed.

0.95, 1.91, 3.81, 15.3

s (system clock: @ 4.19-MHz operation)

0.67, 1.33, 2.67, 10.7

s (system clock: @ 6.0-MHz operation)

Figure 6-1. Clock Generator Block Diagram

Note Instruction execution

Oscillation stop

System clock
oscillator

1/2 1/4 1/16

1/1 to 1/4096
Divider

Selector

Divider

1/4

· CPU
· INT0 noise eliminator
· Clock output circuit

HALT

F/F

Wait release signal from BT

RESET Signal

Standby release signal from
interrupt control circuit

F/F

STOP

PCC2,
PCC3
Clear

STOP

Note

PCC2

PCC3

PCC1

PCC0

PCC

HALT

Note

Internal bus

· Basic interval timer (BT)
· Timer/event counter 0
· Timer counter 1, 2
· Watch timer
· LCD controller/driver
· Serial interface
· INT0 noise eliminator
· Clock output circuit

PD753204, 753206, 753208

From clock

generator

Selector

CLOM3

CLOM1 CLOM0

CLOM

P22
output latch

Port 2 I/O mode
specification bit

PORT2.2

Bit 2 of PMGB

Internal bus

Output buffer

PCL/PTO2/P22

From timer counter
(channel 2)

Selector

Remarks

1. f

= System clock frequency

= CPU clock

3. PCC: Processor Clock Control Register

4. One clock cycle (t

) of the CPU clock is equal to one machine cycle of the instruction.

6.3 Clock Output Circuit

The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2)

to the remote control wave outputs and peripheral LSIs.

Clock Output (PCL)

, 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation)

, 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation)

Figure 6-2. Clock Output Circuit Block Diagram

Remark Special care has been taken in designing the chip so that small-width pulses may not be output when

switching clock output enable/disable.

PD753204, 753206, 753208

From clock
generator

MPX

BTM3 BTM2 BTM1 BTM0 BTM

SET1

Note

Internal bus

Basic interval timer

(8-bit frequency divider)

Clear

Wait release signal
when standby is
released.

Set

Clear

WDTM

SET1

Note

Internal reset
signal

Vectored
interrupt
request signal

BT
interrupt
request flag

IRQBT

6.4 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has the following functions.

Interval timer operation to generate a reference time interrupt

Watchdog timer operation to detect program runaway and reset the CPU

Selects and counts the wait time when the standby mode is released

Reads the contents of counting

Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram

Note Instruction execution

PD753204, 753206, 753208

6.5 Watch Timer

The

PD753208 has one watch timer channel, whose functions are as follows.

Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW.

0.5 sec interval can be created with the system clock (4.194304 MHz)

Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the

fast feed mode.

Outputs a frequency (2.048, 4.096, or 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming

of system clock frequencies.

Clears the frequency divider to make the clock start with zero seconds.

Figure 6-4. Watch Timer Block Diagram

From

clock

generator

Selector

128

(32.768 kHz)

Divider

4 kHz 2 kHz

Clear

Selector

(512 Hz : 1.95 ms)

(256 Hz : 3.91 ms)

Selector

2 Hz

0.5 sec

IRQW
set signal

INTW

LCD

Output buffer

PMGB bit 2

PORT2.3

WM7

WM5

WM4

WM3

WM2

WM1

WM0

P23
output-latch

Port 2 input/
output mode

Internal bus

P23/BUZ

Note 2

Note 1

Notes 1. WM3 is undefined while reading data.

2. Be sure to set WM0 to 0.

Remark The values enclosed in parentheses are applied when f

= 4.194304 MHz.

PD753204, 753206, 753208

6.6 Timer/Event Counter

The

PD753208 provides one channel for timer/event counters and two channels for timer counters. Figures

6-5 to 6-7 show the block diagrams. Timer/event counter functions are as follows.

Programmable interval timer operation

Square wave output of any frequency to the PTO0 pin (n = 0 to 2).

Event counter operation (Channel 0 only)

Divides the frequency of signal input via the TI0 pin to 1-nth of the original signal and outputs the divided

frequency to the PTO0 pin (frequency divider operation).

Supplies the shift clock to the serial interface circuit.

Reads the counting status.

The timer/event counter operates in the following four modes as set by the mode register.

Table 6-2. Operation Modes of Timer/Event Counter

Channel

Channel 0

Channel 1

Channel 2

Mode

8-bit timer/event counter mode

Note 1

Gate control function

N/A

Note 2

N/A

PWM pulse generator mode

N/A

16-bit timer counter mode

N/A

Gate control function

N/A

Note 2

Carrier generator mode

N/A

Notes 1. Channel 0 only. 8-bit timer counter mode for channel 1 and channel 2

2. Used for gate control signal generation

Remark A:

Available

N/A:

Not available

PD753204, 753206, 753208

Figure 6-6. Timer/Event Counter Block Diagram (channel 1)

Note

Execution of instruction

From clock

generator

MPX

TM16

TM15

TM14

TM13

TM12

TM11

TM10

TM1

Decoder

16 bit timer counter mode

Timer operation start

Selector

Clear

Modulo register (8)

Comparator (8)

Count register (8)

Timer counter match signal (channel 2)

(During 16-bit timer counter mode)

Timer counter comparator (channel 2)

(During 16-bit timer counter mode)

Timer counter reload signal (channel 2)

TMOD1

Match

TOUT

F/F

Reset

enable flag

P21

output latch

Port 2

input/output

mode

INTT1

IRQT1

set signal

IRQT1 clear signal

RESET

TOE1

PORT2.1

PMGB bit 2

P21/PTO1

Output buffer

Internal bus

Timer counter

(channel 2) output

SET1

Note

PD753204, 753206, 753208

Figure 6-7. Timer Counter Block Diagram (channel 2)

Note

Execution of instruction

TM25

TM26

TM24

TM23

TM22

TM21

TM20

TM2

TC2

Decoder

High-level period setting

modulo register (8)

Modulo register (8)

TGCE

TOE2

REMC

NRZB

NRZ

Reload

MPX (8)

Comparator (8)

Count register (8)

Clear

16-bit timer counter mode

Timer operation start

Timer counter match signal (channel 1) (During 16-bit timer counter mode)

Timer counter clear signal (channel 1) (During 16-bit timer counter mode)

Timer counter match signal (channel 1) (When carrier generator mode)

Match

Overflow

Carrier generator mode

PORT2.2

PMGB bit 2

P22

output latch

Output buffer

P22/PCL/PTO2

Timer clock

input (channel 1)

INTT2

IRQT2

set signal

IRQT2 clear signal

RESET

TMOD2

TMOD2H

Internal bus

Timer event counter

TOUT F/F (channel 0)

Reset

Selector

Port 2

input/output

TOUT

F/F

From clock

generator

MPX

Selector

From clock generator

SET1

Note

PD753204, 753206, 753208

6.8 LCD Controller/Driver

The

PD753208 incorporates a display controller which generates segment and common signals according

to the display data memory contents and incorporates segment and common drivers which can drive the panel

directly.

The

PD753208 LCD controller/driver functions are as follows:

Display data memory is read automatically by DMA operation and segment and common signals are

generated.

Display mode can be selected from among the following five:

<1>

Static

<2>

1/2 duty (time multiplexing by 2), 1/2 bias

<3>

1/3 duty (time multiplexing by 3), 1/2 bias

<4>

1/3 duty (time multiplexing by 3), 1/3 bias

<5>

1/4 duty (time multiplexing by 4), 1/3 bias

A frame frequency can be selected from among four in each display mode.

A maximum of 12 segment signal output pins (S12 to S23) and four common signal output pins (COM0 to

COM3).

The segment signal output pins (S16 to S23) can be changed to the I/O ports (PORT8 and PORT9).

Split-resistor can be incorporated to supply LCD drive power. (Mask option)

Various bias methods and LCD drive voltages can be applicable.

When display is off, current flowing through the split resistor is cut.

Display data memory not used for display can be used for normal data memory.

PD753204, 753206, 753208

7. INTERRUPT FUNCTION AND TEST FUNCTION

There are seven interrupt sources and two test sources in the

PD753208.

The interrupt control circuit of the

PD753208 has the following functions.

(1) Interrupt function

Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the

interrupt enable flag (IE

×××

) and interrupt master enable flag (IME).

Can set any interrupt start address.

Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register

(IPS).

Test function of interrupt request flag (IRQ

×××

). An interrupt generated can be checked by software.

Release the standby mode. A release interrupt can be selected by the interrupt enable flag.

(2) Test function

Test request flag (IRQ

×××

) generation can be checked by software.

Release the standby mode. The test source to be released can be selected by the test enable flag.

PD753204, 753206, 753208

8. STANDBY FUNCTION

In order to save power dissipation while a program is in standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the

PD753208.

Table 8-1. Operation Status in Standby Mode

Item

Mode

STOP mode

HALT mode

Set instruction

STOP instruction

HALT instruction

Operation

Clock generator

The system clock stops oscillation.

Only the CPU clock

halts (oscillation

status

continues).

Basic interval timer/

Operation stops.

Operable only when the system clock

Watchdog timer

is oscillated. (The IRQBT is set in the

reference interval).

Serial interface

Operable only when an external SCK

Operable

input is selected as the serial clock.

Timer/event counter

Operable only when a signal input to

Operable

the TI0 pin is specified as the count

clock.

Watch timer

Operation stops.

Operable

LCD controller/driver

Operation stops.

Operable

External interrupt

The INT4 is operable.

Only the INT0 is not operated

Note

CPU

Operation stops.

Release signal

Interrupt request signal sent from the operable hardware enabled by the

interrupt enable flag or RESET signal input.

Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register

(IM0).

PD753204, 753206, 753208

RESET

Internal RESET signal

RESET signal sent from the
basic interval timer/watchdog timer

WDTM

Internal bus

Operation mode or

standby mode

Wait

Note

RESET

signal

generated

Operation mode

HALT mode

Internal reset operation

9. RESET FUNCTION

There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/

watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure

9-1 shows the circuit diagram of the above two inputs.

Figure 9-1. Configuration of Reset Function

Each hardware is initialized by the RESET signal generation as listed in Table 9-1. Figure 9-2 shows the

timing chart of the reset operation.

Figure 9-2. Reset Operation by RESET Signal Generation

Note The following two times can be selected by the mask option.

(21.8 ms: @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation)

(5.46 ms: @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation)

PD753204, 753206, 753208

Table 9-1. Status of Each Device After Reset (1/2)

Hardware

RESET signal generation

in the standby mode

during operation

Program counter (PC)

PD753204

Sets the low-order 4 bits of

program memory's address

0000H to PC11 to PC8 and

the contents of address 0001H

to PC7 to PC0.

PD753206, Sets the low-order 5 bits of

Sets the low-order 5 bits of

PD753208

program memory's address

0000H to PC12 to PC8 and

the contents of address 0001H

to PC7 to PC0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0-SK2)

Interrupt status flag (IST0, IST1)

Bank enable flag (MBE, RBE)

Sets bit 6 of program memory's

address 0000H to RBE and bit

7 to MBE.

Stack pointer (SP)

Undefined

Stack bank select register (SBS)

1000B

Data memory (RAM)

Held

Undefined

General-purpose register (X, A, H, L, D, E, B, C)

Held

Undefined

Bank select register (MBS, RBS)

0, 0

Basic interval

Counter (BT)

Undefined

timer/watchdog

Mode register (BTM)

timer

Watchdog timer enable flag (WDTM)

Timer/event

Counter (T0)

counter (T0)

Modulo register (TMOD0)

FFH

Mode register (TM0)

TOE0, TOUT F/F

0, 0

Timer

Counter (T1)

counter (T1)

Modulo register (TMOD1)

FFH

Mode register (TM1)

TOE1, TOUT F/F

0, 0

Timer

Counter (T2)

counter (T2)

Modulo register (TMOD2)

FFH

High-level period setting modulo

FFH

Mode register (TM2)

TOE2, TOUT F/F

0, 0

REMC, NRZ, NRZB

0, 0, 0

TGCE

Watch timer

Mode register (WM)

PD753204, 753206, 753208

Table 9-1. Status of Each Device After Reset (2/2)

Hardware

RESET signal generation

in the standby mode

during operation

Serial interface

Shift register (SIO)

Held

Undefined

Operation mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

Held

Undefined

Clock generator,

Processor clock control register (PCC)

clock output circuit

Clock output mode register (CLOM)

LCD controller/

Display mode register (LCDM)

driver

Display control register (LCDC)

LCD/port selection register (LPS)

Interrupt

Interrupt request flag (IRQ

×××

)

Reset (0)

function

Interrupt enable flag (IE

×××

)

Interrupt priority selection register (IPS)

INT0, 2 mode registers (IM0, IM2)

0, 0

Digital port

Output buffer

Off

Output latch

Cleared (0)

I/O mode registers (PMGA, B, C)

Pull-up resistor setting register (POGA, B)

Bit sequential buffer (BSB0 to BSB3)

Held

Undefined

PD753204, 753206, 753208

11. INSTRUCTION SET

(1) Expression formats and description methods of operands

The operand is described in the operand column of each instruction in accordance with the description

method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER

PACKAGE USERS' MANUAL--LANGUAGE (EEU-1363)". If there are several elements, one of them

is selected. Capital letters and the + and symbols are key words and are described as they are.

For immediate data, appropriate numbers and labels are described.

Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described.

However, there are restrictions in the labels that can be described for fmem and pmem. For details, see

the user's manual.

Representation

Description method

format

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label

Note

bit

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

pmem

FC0H-FFFH immediate data or label

addr

000H-FFFH immediate data or label (

PD753204)

0000H-17FFH immediate data or label (

PD753206)

0000H-1FFFH immediate data or label (

PD753208)

addr1

000H-FFFH immediate data or label (

PD753204)

(Only in the

0000H-17FFH immediate data or label (

PD753206)

MKII mode)

0000H-1FFFH immediate data or label (

PD753208)

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H-7FH immediate data (where bit 0 = 0) or label

PORTn

PORT0-PORT3, PORT5, PORT6, PORT8, PORT9

×××

IEBT, IET0-IET2, IE0, IE2, IE4, IECSI, IEW

RBn

RB0-RB3

MBn

MB0, MB1, MB15

Note mem can be only used for even address in 8-bit data processing.

PD753204, 753206, 753208

(2) Legend in explanation of operation

: A register, 4-bit accumulator

: B register

: C register

: D register

: E register

: H register

: L register

: X register

: XA register pair; 8-bit accumulator

: BC register pair

: DE register pair

: HL register pair

XA'

: XA' expanded register pair

BC'

: BC' expanded register pair

DE'

: DE' expanded register pair

HL'

: HL' expanded register pair

: Program counter

: Stack pointer

: Carry flag, bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn

: Port n (n = 0 to 3, 5, 6, 8, 9)

IME

: Interrupt master enable flag

IPS

: Interrupt priority selection register

×××

: Interrupt enable flag

RBS

: Register bank selection register

MBS

: Memory bank selection register

PCC

: Processor clock control register

: Separation between address and bit

(

××

)

: Contents addressed by

××

: Hexadecimal data

PD753204, 753206, 753208

(3) Explanation of symbols under addressing area column

MB = MBE·MBS

(MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH)

Data memory addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

PD753204

addr = 000H-FFFH

PD753206

addr = 0000H-17FFH

PD753208

addr = 0000H-1FFFH

addr, addr1 = (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

PD753204

caddr = 000H-FFFH

PD753206

caddr = 0000H-0FFFH(PC

= 0) or

Program memory addressing

1000H-17FFH(PC

= 1)

PD753208

caddr = 0000H-0FFFH(PC

= 0) or

1000H-1FFFH(PC

= 1)

faddr = 0000H-07FFH

*10

taddr = 0020H-007FH

*11

PD753204

addr1 = 000H-FFFH

PD753206

addr1 = 0000H-17FFH

PD753208

addr1 = 0000H-1FFFH

Remarks

1. MB indicates memory bank that can be accessed.

2. In *2, MB = 0 independently of how MBE and MBS are set.

3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.

4. *6 to *11 indicate the areas that can be addressed.

(4) Explanation of number of machine cycles column

S denotes the number of machine cycles required by skip operation when a skip instruction is executed.

The value of S varies as follows.

When no skip is made: S = 0

When the skipped instruction is a 1- or 2-byte instruction: S = 1

When the skipped instruction is a 3-byte instruction

Note

: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle of CPU clock (= t

); time can be selected from among four types

by setting PCC.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Transfer

MOV

A, #n4

String effect A

instruction

reg1, #n4

reg1

XA, #n8

String effect A

HL, #n8

String effect B

rp2, #n8

rp2

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A, mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg

reg

XA, rp'

rp'

reg1, A

reg1

rp'1, XA

rp'1

XCH

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

A, mem

(mem)

XA, mem

(mem)

A, reg1

reg1

XA, rp'

rp'

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Table

MOVT

XA, @PCDE

PD753204

reference

(PC

118

+DE)

ROM

PD753206, 753208

(PC

128

+DE)

ROM

XA, @PCXA

PD753204

(PC

118

+XA)

ROM

PD753206, 753208

(PC

128

+XA)

ROM

XA, @BCDE

(BCDE)

ROM

Note

XA, @BCXA

(BCXA)

ROM

Note

Bit transfer

MOV1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

fmem.bit, CY

(fmem.bit)

pmem.@L, CY

(pmem

.bit(L

))

@H+mem.bit, CY

(H+mem

.bit)

Operation

ADDS

A, #n4

1+S

A+n4

carry

XA, #n8

2+S

XA+n8

carry

A, @HL

1+S

A+(HL)

carry

XA, rp'

2+S

XA+rp'

carry

rp'1, XA

2+S

rp'1

rp'1+XA

carry

ADDC

A, @HL

A, CY

A+(HL)+CY

XA, rp'

XA, CY

XA+rp'+CY

rp'1, XA

rp'1, CY

rp'1+XA+CY

SUBS

A, @HL

1+S

A(HL)

borrow

XA, rp'

2+S

XArp'

borrow

rp'1, XA

2+S

rp'1

rp'1XA

borrow

SUBC

A, @HL

A, CY

A(HL)CY

XA, rp'

XA, CY

XArp'CY

rp'1, XA

rp'1, CY

rp'1XACY

Note Set "0" to register B if the

PD753204 is used. Only the low-order one bit of register B will be valid if the

PD753206 or 753208 is used.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Operation

AND

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

XOR

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

Accumulator

RORC

, A

CY, A

manipulation
instructions

NOT

Increment

INCS

reg

1+S

reg

reg+1

reg=0

and
Decrement

rp1

1+S

rp1

rp1+1

rp1=00H

instructions

@HL

2+S

(HL)

(HL)+1

(HL)=0

mem

2+S

(mem)

(mem)+1

(mem)=0

DECS

reg

1+S

reg

reg1

reg=FH

rp'

2+S

rp'

rp'1

rp'=FFH

Comparison

SKE

reg, #n4

2+S

Skip if reg = n4

reg=n4

instruction

@HL, #n4

2+S

Skip if (HL) = n4

(HL) = n4

A, @HL

1+S

Skip if A = (HL)

A = (HL)

XA, @HL

2+S

Skip if XA = (HL)

XA = (HL)

A, reg

2+S

Skip if A = reg

A=reg

XA, rp'

2+S

Skip if XA = rp'

XA=rp'

Carry flag

SET1

manipulation
instruction

CLR1

SKT

1+S

Skip if CY = 1

CY=1

NOT1

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Memory bit

SET1

mem.bit

(mem.bit)

manipulation
instructions

fmem.bit

(fmem.bit)

pmem.@L

(pmem

.bit(L

))

@H+mem.bit

(H+mem

.bit)

CLR1

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

.bit(L

))

@H+mem.bit

(H+mem

.bit)

SKT

mem.bit

2+S

Skip if (mem.bit)=1

(mem.bit)=1

fmem.bit

2+S

Skip if (fmem.bit)=1

(fmem.bit)=1

pmem.@L

2+S

Skip if (pmem

.bit(L

))=1

(pmem.@L)=1

@H+mem.bit

2+S

Skip if (H+mem

.bit)=1

(@H+mem.bit)=1

SKF

mem.bit

2+S

Skip if (mem.bit)=0

(mem.bit)=0

fmem.bit

2+S

Skip if (fmem.bit)=0

(fmem.bit)=0

pmem.@L

2+S

Skip if (pmem

.bit(L

))=0

(pmem.@L)=0

@H+mem.bit

2+S

Skip if (H+mem

.bit)=0

(@H+mem.bit)=0

SKTCLR

fmem.bit

2+S

Skip if (fmem.bit)=1 and clear

(fmem.bit)=1

pmem.@L

2+S

Skip if (pmem

.bit(L

))=1 and clear

(pmem.@L)=1

@H+mem.bit

2+S

Skip if (H+mem

.bit)=1 and clear

(@H+mem.bit)=1

AND1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

OR1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

XOR1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Branch

Note

addr

PD753204

instructions

110

addr

Select the most appropriate instruction from
among BR !addr, BRCB !caddr and BR $addr
according to the assembler being used.

PD753206, 753208

120

addr

Select the most appropriate instruction
from among BR !addr, BRCB !caddr
and BR $addr according to the
assembler being used.

addr1

PD753204

*11

11-0

addr1

Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.

PD753206, 753208

120

addr1

Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.

! addr

PD753204

110

addr

PD753206, 753208

120

addr

$addr

PD753204

110

addr

PD753206, 753208

120

addr

$addr1

PD753204

110

addr1

PD753206, 753208

120

addr1

Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Branch

PCDE

PD753204

instruction

110

11-8

+DE

PD753206, 753208

120

12-8

+DE

PCXA

PD753204

110

11-8

+XA

PD753206, 753208

120

12-8

+XA

BCDE

PD753204

110

BCDE

Note 1

PD753206, 753208

120

BCDE

Note 2

BCXA

PD753204

110

BCXA

Note 1

PD753206, 753208

120

BCXA

Note 2

BRA

Note 3

!addr1

PD753204

110

addr1

PD753206, 753208

120

addr1

BRCB

!caddr

PD753204

110

caddr

110

PD753206, 753208

120

+caddr

110

Subroutine

CALLA

Note 3

!addr1

PD753204

*11

stack control

(SP2)

, MBE, RBE

instructions

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

110

addr1, SP

SP6

PD753206, 753208

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, PC

120

addr1, SP

SP6

Notes 1. "0" must be set to the B register.

2. Only the low-order one bit is valid in the B register.

3. The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

CALL

Note

!addr

PD753204

stack control

(SP3)

MBE, RBE, 0, 0

instructions

(SP4) (SP1) (SP2)

110

addr, SP

SP4

PD753206, 753208

(SP3)

MBE, RBE, 0, PC

(SP4) (SP1) (SP2)

110

120

addr, SP

SP4

PD753204

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

110

addr, SP

SP6

PD753206, 753208

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, PC

120

addr, SP

SP6

CALLF

Note

!faddr

PD753204

(SP3)

MBE, RBE, 0, 0

(SP4) (SP1) (SP2)

110

0+faddr, SP

SP4

PD753206, 753208

(SP3)

MBE, RBE, 0, PC

(SP4) (SP1) (SP2)

110

120

00+faddr, SP

SP4

PD753204

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

110

0+faddr, SP

SP6

PD753206, 753208

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, PC

120

00+faddr, SP

SP6

Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

RET

Note

PD753204

stack control

110

(SP) (SP+3) (SP+2)

instructions

MBE, RBE, 0, 0

(SP+1), SP

SP+4

PD753206, 753208

110

(SP) (SP+3) (SP+2)

MBE, RBE, 0, PC

(SP+1), SP

SP+4

PD753204

, MBE, RBE

(SP+4)

0, 0, 0, 0,

(SP+1)

110

(SP) (SP+3) (SP+2), SP

SP+6

PD753206, 753208

, MBE, RBE

(SP+4)

MBE, 0, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2), SP

SP+6

RETS

Note

3+S

PD753204

Unconditional

MBE, RBE, 0, 0

(SP+1)

110

(SP) (SP+3) (SP+2)

SP+4

then skip unconditionally

PD753206, 753208

MBE, RBE, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

SP+4

then skip unconditionally

PD753204

0, 0, 0, 0

(SP+1)

110

(SP) (SP+3) (SP+2)

, MBE, RBE

(SP+4)

SP+6

then skip unconditionally

PD753206, 753208

0, 0, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

, MBE, RBE

(SP+4)

SP+4

then skip unconditionally

Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

RETI

Note 1

PD753204

stack control

MBE, RBE, 0, 0

(SP+1)

instructions

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

PD753206, 753208

MBE, RBE, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

PD753204

0, 0, 0, 0

(SP+1)

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

PD753206, 753208

0, 0, 0, PC

(SP+1)

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

PUSH

(SP1)(SP2)

rp, SP

SP2

(SP1)

MBS, (SP2)

RBS, SP

SP2

POP

(SP+1) (SP), SP

SP+2

MBS

(SP+1), RBS

(SP), SP

SP+2

Interrupt

IME (IPS.3)

control

instructions

×××

IME (IPS.3)

×××

Input/output

Note 2

A, PORTn

PORTn

(n = 0-3, 5, 6, 8, 9)

instructions

XA, PORTn

PORTn+1, PORTn

(n = 8)

OUT

Note 2

PORTn, A

PORTn

(n = 3, 5, 6, 8, 9)

PORTn, XA

PORTn+1, PORTn

(n = 8)

CPU control

HALT

Set HALT Mode (PCC.2

instructions

STOP

Set STOP Mode (PCC.3

NOP

No Operation

Special

SEL

RBn

RBS

(n = 0-3)

instructions

MBn

MBS

(n = 0, 1, 15)

Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and

MBS must be set to 15.

PD753204, 753206, 753208

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Special

GET

Notes 1, 2

taddr

PD753204

*10

instructions

· When TBR instruction

110

(taddr)

+ (taddr+1)

· When TCALL instruction

(SP4) (SP1) (SP2)

110

(SP3)

MBE, RBE, 0, 0

110

(taddr)

+ (taddr+1)

SP4

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

PD753206, 753208

· When TBR instruction

120

(taddr)

+ (taddr+1)

· When TCALL instruction

(SP4) (SP1) (SP2)

110

(SP3)

MBE, RBE, 0, PC

120

(taddr)

+ (taddr+1)

SP4

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

PD753204

*10

· When TBR instruction

110

(taddr)

+ (taddr+1)

· When TCALL instruction

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

(SP2)

, MBE, RBE

110

(taddr)

+ (taddr+1)

SP6

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

2. The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

PD753204, 753206, 753208

12. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25°C)

Parameter

Symbol

Test Conditions

Rating

Unit

Supply voltage

0.3 to +7.0

Input voltage

Except port 5

0.3 to V

+ 0.3

Port 5

On-chip pull-up resistor

0.3 to V

+ 0.3

When N-ch open-drain

0.3 to +14

Output voltage

0.3 to V

+ 0.3

Output current high

Per pin

Total for all pins

Output current low

Per pin

Total for all pins

220

Operating ambient

40 to +85

Note

°C

temperature

Storage temperature

stg

65 to +150

°C

Note When LCD is driven in normal mode: T

= 10 to +85°C

Caution

Product quality may suffer if the absolute maximum rating is exceeded for even a single

parameter or even momentarily. That is, the absolute ratings are rated values at which the

product is on the verge of suffering physical damage, and therefore the product must be used

under conditions which ensure that the absolute maximum ratings are not exceeded.

CAPACITANCE (T

= 25°C, V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

OUT

Unmeasured pins returned to 0 V.

I/O capacitance

PD753204, 753206, 753208

SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Resonator

Recommended constant

Parameter

Test conditions

MIN.

TYP.

MAX.

Unit

Ceramic

Oscillator

1.0

6.0

Note 2

MHz

resonator

frequency (f

)

Note 1

Oscillation

After V

reaches oscil-

stabilization time

Note 3

lation voltage range MIN.

Crystal

Oscillator

1.0

6.0

Note 2

MHz

resonator

frequency (f

)

Note 1

Oscillation

= 4.5 to 5.5 V

stabilization time

Note 3

External

X1 input

1.0

6.0

Note 2

MHz

clock

frequency (f

)

Note 1

X1 input

83.3

500

high/low level width

, t

)

Notes 1. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the

instruction execution time, refer to the AC characteristics.

2. When the oscillator frequency is 4.19 MHz < fx

6.0 MHz, setting the processor clock control register

(PCC) to 0011 results in 1 machine cycle being less than the required 0.95

s. Therefore, set PCC

to a value other than 0011.

3. The oscillation stabilization time is necessary for oscillation to stabilize after applying V

or releasing

the STOP mode.

Caution

When using the system clock oscillator, wiring in the area enclosed with the dotted line should

be carried out as follows to avoid an adverse effect from wiring capacitance.

· Wiring should be as short as possible.

· Wiring should not cross other signal lines.

· Wiring should not be placed close to a varying high current.

· The potential of the oscillator capacitor ground should be the same as V

· Do not ground it to the ground pattern in which a high current flows.

· Do not fetch a signal from the oscillator.

PD753204, 753206, 753208

DC CHARACTERISTICS (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Output voltage low

Per pin

Sum of the all pins

150

Input voltage high

IH1

Ports 2, 3, 8, and 9

2.7

5.5 V

0.7V

1.8

< 2.7 V

0.9V

IH2

Ports 0, 1, 6, RESET

2.7

5.5 V

0.8V

1.8

< 2.7 V

0.9V

IH3

Port 5

When a pull-up register

2.7

5.5 V

0.7V

is incorporated

1.8

< 2.7 V

0.9V

When N-ch open-drain

2.7

5.5 V

0.7V

1.8

< 2.7 V

0.9V

IH4

0.1

Input voltage low

Ports 2, 3, 5, 8, and 9

2.7

5.5 V

0.3V

1.8

< 2.7 V

0.1V

IL2

Ports 0, 1, 6, RESET

2.7

5.5 V

0.2V

1.8

< 2.7 V

0.1V

IL3

0.1

Output voltage high

SCK, SO, ports 2, 3, 6, 8, and 9 I

= 1.0 mA

0.5

Output voltage low

OL1

SCK, SO, ports 2, 3, 5, 6, 8,

= 15 mA,

0.2

2.0

and 9

= 4.5 to 5.5 V

= 1.6 mA

0.4

OL2

SB0, SB1

N-ch open-drain

0.2V

pull-up resistor

1 k

Input leakage

LIH1

= V

Other pins than X1

current high

LIH2

LIH3

= 13 V

Port 5 (When N-ch open-drain)

Input leakage

LIL1

= 0 V

Other pins than port 5 and X1

current low

LIL2

LIL3

Port 5 (When N-ch open drain)

Other than when an input instruction

is executed

Port 5 (When N-ch open-drain)

When an input instruction

= 5.0 V

is executed

= 3.0 V

Output leakage

LOH1

OUT

= V

SCK, SO/SB0, SB1, ports 2, 3, 6, 8

current high

and 9

Port 5 (When a pull-up resistor

is incorporated.)

LOH2

OUT

= 13 V

Port 5 (When N-ch open-drain)

Output leakage

LOL

OUT

= 0 V

current low

On-chip pull-up resistor

= 0 V

Ports 0 to 3, 6, 8, and 9

100

200

(Excluding P00 pin)

Port 5 (Mask option)

PD753204, 753206, 753208

DC CHARACTERISTICS (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

LCD drive voltage

LCD

VAC0 = 0

= 40 to +85°C

2.7

= 10 to +85°C

2.2

VAC0 = 1

1.8

VAC current

Note 1

VAC

VAC0 = 1, V

= 2.0 V

10%

LCD split resistor

Note 2

LCD1

100

200

LCD2

LCD output voltage

ODC

1.0

LCD0

= V

LCD

0.2

deviation

Note 3

(common)

LCD1

= V

LCD

2/3

LCD output voltage

ODS

0.5

LCD2

= V

LCD

1/3

0.2

deviation

Note 3

(segment)

1.8 V

LCD

Supply current

Note 4

DD1

6.0 MHz

= 5.0 V

10%

Note 5

1.9

6.0

Crystal oscillation

= 3.0 V

10%

Note 6

0.4

1.3

DD2

C1 = C2 = 22 pF

HALT mode V

= 5.0 V

10%

0.72

2.1

= 3.0 V

10%

0.27

0.8

DD1

4.19 MHz

= 5.0 V

10%

Note 5

1.5

4.0

Crystal oscillation

= 3.0 V

10%

Note 6

0.25

0.75

DD2

C1 = C2 = 22 pF

HALT mode V

= 5.0 V

10%

0.7

2.0

= 3.0 V

10%

0.23

0.7

DD3

STOP mode

= 5.0 V

10%

0.05

= 3.0 V

0.02

10%

= 25°C

0.02

Notes 1. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1

2. Either R

LCD1

or R

LCD2

can be selected by the mask option.

3. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the

segment and common outputs (V

LCDn

; n = 0, 1, 2).

4. Not including currents flowing in on-chip pull-up resistors or LCD split resistors.

5. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-

speed mode.

6. When PCC is set to 0000 and the device is operated in the low-speed mode.

PD753204, 753206, 753208

AC CHARACTERISTICS (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle

= 2.7 to 5.5 V

0.67

time

Note 1

0.95

TI0 input frequency

= 2.7 to 5.5 V

1.0

MHz

275

kHz

TI0 input

TIH

, t

TIL

= 2.7 to 5.5 V

0.48

high/low-level width

1.8

Interrupt input high/

INTH

INT0

IM02 = 0

Note 2

low-level width

INTL

IM02 = 1

INT4

KR0 to KR3

RESET low level width

RSL

Notes 1. The cycle time (minimum instruc-

tion execution time) of the CPU

clock (

) is determined by the

oscillation frequency of the con-

nected resonator (and external

clock) and the processor clock

control register (PCC). The figure

at the right indicates the cycle

time t

versus supply voltage

characteristic.

2. 2t

or 128/f

is set by setting the

interrupt mode register (IM0).

0.5

Supply Voltage V

[V]

vs V

Cycle Time t

[ s]

Guaranteed Operation
Range

PD753204, 753206, 753208

SERIAL TRANSFER OPERATION

2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY1

= 2.7 to 5.5 V

1300

3800

SCK high/low-level

KL1

, t

KH1

= 2.7 to 5.5 V

KCY1

/2 50

width

KCY1

/2 150

Note 1

setup time

SIK1

= 2.7 to 5.5 V

150

(to SCK

)

500

Note 1

hold time

KSI1

= 2.7 to 5.5 V

400

(from SCK

)

600

Note 1

output delay

KSO1

= 1 k

Note 2

= 2.7 to 5.5 V

250

time from SCK

= 100 pF

1000

Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.

2. R

and C

are the load resistance and load capacitance of the SO output lines.

2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY2

= 2.7 to 5.5 V

800

3200

SCK high/low-level

KL2

, t

KH2

= 2.7 to 5.5 V

400

width

1600

Note 1

setup time

SIK2

= 2.7 to 5.5 V

100

(to SCK

)

150

Note 1

hold time

KSI2

= 2.7 to 5.5 V

400

(from SCK

)

600

Note 1

output delay

KSO2

= 1 k

Note 2

= 2.7 to 5.5 V

300

time from SCK

= 100 pF

1000

Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.

2. R

and C

are the load resistance and load capacitance of the SO output lines.

PD753204, 753206, 753208

SBI Mode (SCK...Internal clock output (master)): (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY3

= 2.7 to 5.5 V

1300

3800

SCK high/low-level

KL3

, t

KH3

= 2.7 to 5.5 V

KCY3

/2 50

width

KCY3

/2 150

SB0, 1 setup time

SIK3

= 2.7 to 5.5 V

150

(to SCK

)

500

SB0, 1 hold time

KSI3

= 2.7 to 5.5 V

KCY3

(from SCK

)

SB0, 1 output delay

KSO3

= 1 k

Note

= 2.7 to 5.5 V

250

time from SCK

= 100 pF

1000

SB0, 1

from SCK

KSB

KCY3

SCK

from SB0, 1

SBK

KCY3

SB0, 1 low-level width

SBL

KCY3

SB0, 1 high-level width

SBH

KCY3

Note R

and C

are the load resistance and load capacitance of the SB0 and SB1 output lines.

SBI Mode (SCK...External clock input (slave)): (T

= 40 to +85 °C, V

= 1.8 to 5.5 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY4

= 2.7 to 5.5 V

800

3200

SCK high/low-level

KL4

, t

KH4

= 2.7 to 5.5 V

400

width

1600

SB0, 1 setup time

SIK4

= 2.7 to 5.5 V

100

(to SCK

)

150

SB0, 1 hold time

KSI4

= 2.7 to 5.5 V

KCY4

(from SCK

)

SB0, 1 output delay

KSO4

= 1 k

Note

= 2.7 to 5.5 V

300

time from SCK

= 100 pF

1000

SB0, 1

from SCK

KSB

KCY4

SCK

from SB0, 1

SBK

KCY4

SB0, 1 low-level width

SBL

KCY4

SB0, 1 high-level width

SBH

KCY4

Note R

and C

are the load resistance and load capacitance of the SB0 and SB1 output lines.

PD753204, 753206, 753208

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

= 40 to +85°C)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Release signal set time

SREL

Oscillation stabilization

WAIT

Release by RESET

Note 2

wait time

Note 1

Release by interrupt

Note 3

Notes 1. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent

unstable operation at the oscillation start.

2. Either 2

or 2

can be selected by the mask option.

3. Depends on the basic interval timer mode register (BTM) settings (See the table below).

BTM3

BTM2

BTM1

BTM0

Wait time

When fx = 4.19-MHz operation When fx = 6.0-MHz operation

(approx. 250 ms)

(approx. 175 ms)

(approx. 31.3 ms)

(approx. 21.8 ms)

(approx. 7.81 ms)

(approx. 5.46 ms)

(approx. 1.95 ms)

(approx. 1.37 ms)

Data Retention Timing (STOP Mode Release by RESET)

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

RESET

STOP Instruction Execution

STOP Mode

Data Retention Mode

Internal Reset Operation

Halt mode

Operating Mode

SREL

WAIT

SREL

WAIT

STOP Instruction Execution

STOP Mode

Data Retention Mode

Halt mode

Operating Mode

Standby Release Signal
(Interrupt Request)

PD753204, 753206, 753208

15. RECOMMENDED SOLDERING CONDITIONS

The

PD753208 should be soldered and mounted under the conditions recommended in the table below.

For details of recommended soldering conditions, refer to the information document "Semiconductor Device

Mounting Technology Manual" (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 15-1. Surface Mounting Type Soldering Conditions

PD753204GT-xxx

: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

PD753206GT-xxx

: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

PD753208GT-xxx

: 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

Soldering

Soldering Conditions

Symbol

Method

Infrared rays

Peak package's surface temperature: 235°C, Reflow time: 30 seconds or less

IR35-00-2

reflow

(at 210°C or higher), Number of reflow processes: Twice max.

VPS

Peak package's surface temperature: 215°C, Reflow time: 40 seconds or less

VP15-00-2

(at 200°C or higher), Number of reflow processes: Twice max.

Wave soldering

Solder temperature: 260°C or below, Flow time: 10 seconds or less, Number of

WS60-00-1

flow process: 1, Preheating temperature: 120°C or below (Package surface

temperature)

Partial heating

Pin temperature: 300°C or below, Time: 3 seconds or less (per device side)

Caution

Use of more than one soldering method should be avoided (except for partial heating).

PD753204, 753206, 753208

APPENDIX A

PD753108, 753208, AND 75P3216 FUNCTIONAL LIST

Parameter

PD753108

PD753208

PD75P3216

Program memory

Mask ROM

One-time PROM

0000H-1FFFH

0000H-3FFFH

(8192

8 bits)

(16384

8 bits)

Data memory

000H-1FFH

(512

4 bits)

CPU

75XL CPU

Instruction

When main system

· 0.95, 1.91, 3.81, 15.3

s (@ 4.19-MHz operation)

execution

clock is selected

· 0.67, 1.33, 2.67, 10.7

s (@ 6.0-MHz operation)

time

When subsystem

122

s (@ 32.768-kHz

None

clock is selected

operation)

I/O port

CMOS input

8 (on-chip pull-up resistors can

6 (on-chip pull-up resistors can be specified by software: 5)

be specified by software: 7)

CMOS input/output

20 (on-chip pull-up resistors can be specified by software)

N-ch open drain

4 (on-chip pull-up resistors can be specified by software,

4 (no mask option, withstand

input/output

withstand voltage is 13 V)

voltage is 13 V)

Total

LCD controller/driver

Segment selection: 16/20/24

Segment selection: 4/8/12 segments

(can be changed to CMOS

(can be changed to CMOS input/output port in 4 time-unit;

input/output port in 4 time-

max. 8)

unit; max. 8)

Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)

On-chip split resistor for LCD driver can be specified by

No on-chip split resistor for

using mask option.

LCD driver

Timer

5 channels

· 8-bit timer/event

· 8-bit timer counter: 2 channels (can be used as the 16-bit

counter: 3 channels

timer counter, carrier generator, and timer with gate)

· Basic interval timer/

· 8-bit timer/event counter: 1 channel

watchdog timer: 1 channel

· Basic interval timer/watchdog timer: 1 channel

· Watch timer: 1 channel

Clock output (PCL)

, 524, 262, 65.5 kHz

(Main system clock: @ 4.19-MHz operation)

, 750, 375, 93.8 kHz

(Main system clock: @ 6.0-MHz operation)

Buzzer output (BUZ)

· 2, 4, 32 kHz

(Main system clock: @

(Main system clock: @ 4.19-MHz operation)

4.19-MHz operation or sub-

· 2.93, 5.86, 46.9 kHz

system clock: @ 32.768-kHz

(Main system clock: @ 6.0-MHz operation)

operation)

· 2.86, 5.72, 45.8 kHz

(Main system clock: @
6.0-MHz operation)

Serial interface

3 modes are available
· 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
· 2-wire serial I/O mode
· SBI mode

SCC register

Contained

None

SOS register

Vectored interrupt

External: 3, internal: 5

External: 2, internal: 5

PD753204, 753206, 753208

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for system development using the

PD753208.

In 75XL series, the relocatable assembler which is common to the

PD753208 Subseries is used in combination

with the device file of each product.

Language processor

RA75X relocatable assembler

Host machine

Part number

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13RA75X

Ver. 3.30 to

5-inch 2HD

S5A10RA75X

Ver. 6.2

Note

IBM PC/AT

and

Refer to section

3.5-inch 2HC

S7B13RA75X

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10RA75X

Device file

Host machine

Part number

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13DF753208

Ver. 3.30 to

5-inch 2HD

S5A10DF753208

Ver. 6.2

Note

IBM PC/AT and

Refer to section

3.5-inch 2HC

S7B13DF753208

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10DF753208

PROM write tools

Hardware

PG-1500

PG-1500 is a PROM programmer which enables you to program single chip microcomputers

including PROM by stand-alone or host machine operation by connecting an attached board

and optional programmer adapter to PG-1500. It also enables you to program typical PROM

devices of 256 Kbits to 4 Mbits.

PA-75P3216GT

PROM programmer adapter for the

PD75P3216GT. Connect the programmer adapter to

PG-1500 for use.

Software

PG-1500 controller

PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500

is controlled on the host machine.

Host machine

Part number

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13PG1500

Ver. 3.30 to

5-inch 2HD

S5A10PG1500

Ver. 6.2

Note

IBM PC/AT and

Refer to section

3.5-inch 2HD

S7B13PG1500

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10PG1500

Note Ver. 5.00 or later have the task swap function, but it cannot be used for this software.

Remarks

1. Operation of the assembler and device file is guaranteed only on the above host machine and OSs.

2. Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.

PD753204, 753206, 753208

Debugging tool

The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the

PD753208.

The system configurations are described as follows.

Hardware

IE-75000-R

Note 1

In-circuit emulator for debugging the hardware and software when developing the

application systems that use the 75X series and 75XL series. When developing a

PD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP-

753208GT-R that are sold separately must be used with the IE-75000-R.

By connecting with the host machine and the PROM programmer, efficient debugging

can be made.

It contains the emulation board IE-75000-R-EM which is connected.

IE-75001-R

In-circuit emulator for debugging the hardware and software when developing the

application systems that use the 75X series and 75XL series. When developing a

PD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP-

753208GT-R which are sold separately must be used with the IE-75001-R.

It can debug the system efficiently by connecting the host machine and PROM

programmer.

IE-75300-R-EM

Emulation board for evaluating the application systems that use a

PD753208

subseries.

It must be used with the IE-75000-R or IE-75001-R.

EP-753208GT-R

Emulation probe for the

PD753208GT.

It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the 48-pin conversion adapter EV-9500GF-48 which facilitates

EV-9500GF-48

connection to a target system.

Software

IE control program

Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix

I/F and controls the above hardware on a host machine.

Host machine

Part No.

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13IE75X

Ver. 3.30 to

5-inch 2HD

S5A10IE75X

Ver. 6.2

Note 2

IBM PC/AT and its

Refer to section

3.5-inch 2HC

S7B13IE75X

compatible machine

"OS for IBM PC"

5-inch 2HC

S7B10IE75X

Notes 1. Maintenance parts.

2. Ver. 5.00 or later have the task swap function, but it cannot be used for this software.

Remarks

1. Operation of the IE control program is guaranteed only on the above host machines and OSs.

2. The

PD753204, 753206, 753208, and 75P3216 are commonly referred to as the

PD753208

Subseries.

PD753204, 753206, 753208

APPENDIX C RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents related to device

Document No.

Document Name

Japanese

English

PD753204, 753206, 753208 Data Sheet

U10166J

This manual

PD75P3216 Data Sheet

U10241J

U10241E

PD753208 User's Manual

U10158J

U10158E

75XL Series Selection Guide

U10453J

U10453E

Documents related to development tool

Document No.

Document Name

Japanese

English

Hardware

IE-75000-R/IE-75001-R User`s Manual

EEU-846

EEU-1416

IE-75300-R-EM User's Manual

U11354J

U11354E

EP-753208GT-R User's Manual

U10739J

U10739E

PG-1500 User's Manual

U11940J

EEU-1335

Software

RA75X Assembler Package User's Manual

Operation

EEU-731

EEU-1346

Language

EEU-730

EEU-1363

PG-1500 Controller User's Manual

PC-9800 Series

EEU-704

EEU-1291

(MS-DOS) Base

IBM PC Series

EEU-5008

U10540E

(PC DOS) Base

Other related documents

Document No.

Document Name

Japanese

English

Semiconductor Device Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

Quality Grades on NEC Semiconductor Devices

C11531J

C11531E

NEC Semiconductor Device Reliability/Quality Control System

C10983J

C10983E

Electrostatic Discharge (ESD) Test

MEM-539

IEI-1201

Guide to Quality Assurance for Semiconductor Devices

C11893J

MEI-1202

Microcontroller Related Product Guide Third Party Products

C11416J

Caution

The contents of the documents listed above are subject to change without prior notice to users.

Make sure to use the latest edition when starting design.

PD753204, 753206, 753208

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry.

Each unused pin should be connected to V

or GND with a resistor, if it is

considered to have a possibility of being an output pin. All handling related

to the unused pins must be judged device by device and related specifications

governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immediately

after power-on for devices having reset function.

PD753204, 753206, 753208

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

PD753204, 753206, 753208

MS-DOS is a trademark of Microsoft Corporation.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be

prohibited without governmental license, the need for which must be judged by the customer. The export or re-

export of this product from a country other than Japan may also be prohibited without a license from that country.

Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

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