Printed in Japan

MOS INTEGRATED CIRCUIT

DATA SHEET

PD75402A(A)

4 BIT SINGLE-CHIP MICROCOMPUTER

The

PD75402A(A) is a CMOS single-chip microcomputer which uses the 75X series architecture. It operates

at high speed with a minimum instruction execution time of 0.95

The

PD75P402 is also available for system development evaluation. It contains one-time PROM instead

of mask ROM used in the

PD75402A(A).

The following user's manual describes the details of the functions of the

PD75402A(A). Be sure to read

it before designing an application system.

PD75402A User's Manual: IEU-644

FEATURES

More reliable than the

PD75402A

High-speed operation with a minimum instruction execution time of 0.95

s (when the microcomputer

operates at 4.19 MHz)

Low voltage and low-speed instruction execution time of 15.3

s (when the microcomputer operates at

4.19 MHz)

Memory mapping by on-chip peripheral hardware

NEC standard serial bus interface (SBI)

8-bit basic interval timer (watchdog timer applicable)

Interrupt function

Three vectored interrupts (one external and two internal interrupts)

One external test input

Clock output function (remote controller output applicable)

Capable of specifying the incorporation of 16 pull-up resistors by software

APPLICATIONS

Electronic units for automobiles, and suchlike

ORDERING INFORMATION

Part number

Package

Quality grade

PD75402AC(A)-

×××

28-pin plastic DIP (600 mil)

Special

PD75402ACT(A)-

×××

28-pin plastic shrink DIP (400 mil)

Special

PD75402AGB(A)-

×××

-3B4

44-pin plastic QFP (10

10 mm)

Special

Remark

×××

indicates the ROM code number.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

Major changes in this revision are indicated by stars (

) in the margins.

Document No.

IC-2841B

(O.D.No.

IC-8273B)

Date Published November 1993 P

1990

NEC CORPORATION 1991

PD75402A(A)

DIFFERENCES BETWEEN THE

PD75402A(A) AND

PD75402A

FUNCTIONAL OVERVIEW

Special

Standard

Item

Quality grade

Product

PD75402A(A)

PD75402A

Function

0.95, 1.91, or 15.3

s (when operating at 4.19 MHz)

Switchable among three speeds

1920

8 bits

4 bits

4 or 8 bits

2 (memory mapping)

CMOS input ports

6 lines

CMOS I/O ports

: 12 lines (8 lines can drive the LED directly.)

N-ch open-drain I/O ports :

4 lines (All lines can drive the LED directly.)

Capable of controlling the incorporation of 16 pull-up resistors by software

Capable of controlling the incorporation of 4 pull-up resistors by mask option

1.05 MHz, 524 kHz, or 65.5 kHz (when operating at 4.19 MHz)

Applicable to remote controller output

8-bit basic interval timer (watchdog timer applicable)

8 bits

Two transfer modes (three-wire synchronous mode and SBI mode)

One external and two internal interrupts

One external input (See Chapter 6 for details.)

STOP/HALT mode

Bit manipulation instructions (set, clear, test, and Boolean operation)

1-byte relative branch instructions

4-bit operation instructions (add, Boolean operation, and compare)

4- and 8-bit transfer instructions

28-pin plastic DIP (600 mil)

28-pin plastic shrink DIP (400 mil)

44-pin plastic QFP (10

10 mm)

Item

Number of basic

instructions

Minimum instruction

execution time

ROM

RAM

General register

I/O line

Pull-up resistor

Clock output

Timer/counter

Serial interface

Vectored interrupt

Test input

Standby

Instruction set

Package

Built-in

memory

PD75402A(A)

CONTENTS

PIN CONFIGURATION (TOP VIEW) ......................................................................................

BLOCK DIAGRAM ......................................................................................................................

PIN FUNCTIONS .......................................................................................................................

3.1

PORT PINS .....................................................................................................................................

3.2

NON-PORT PINS ...........................................................................................................................

3.3

PIN INPUT/OUTPUT CIRCUITS ..................................................................................................

3.4

SELECTION OF A MASK OPTION ...........................................................................................

3.5

HANDLING UNUSED PINS .........................................................................................................

3.6

NOTES ON USING THE P00 AND RESET PINS .................................................................

MEMORY CONFIGURATION ...................................................................................................

PERIPHERAL HARDWARE FUNCTIONS ................................................................................

5.1

PORTS ..............................................................................................................................................

5.2

CLOCK GENERATOR ....................................................................................................................

5.3

CLOCK OUTPUT CIRCUIT ...........................................................................................................

5.4

BASIC INTERVAL TIMER ............................................................................................................

5.5

SERIAL INTERFACE ......................................................................................................................

INTERRUPT FUNCTION ...........................................................................................................

STANDBY FUNCTION ..............................................................................................................

RESET FUNCTION ....................................................................................................................

INSTRUCTION SET ...................................................................................................................

10. ELECTRICAL CHARACTERISTICS ...........................................................................................

11. PACKAGE DIMENSIONS ..........................................................................................................

12. RECOMMENDED SOLDERING CONDITIONS .........................................................................

APPENDIX A DIFFERENCES BETWEEN THE

PD75402A(A) AND

PD75P402 ...................

APPENDIX B DEVELOPMENT TOOLS .........................................................................................

APPENDIX C

RELATED DOCUMENTS ........................................................................................

PD75402A(A)

1. PIN CONFIGURATION (TOP VIEW)

28-pin plastic DIP (600 mil), 28-pin plastic shrink DIP (400 mil)

Note

RESET

P00

P01/SCK

P12 /INT2

P02/SO/SB0

P10/INT0

P03/SI

P23

P50

P22 /PCL

P51

P21

P52

P20

P53

P63

P30

P62

P31

P61

P32

P60

P33

PD75402AC(A)/CT(A)-

×××

P00 - P03

: Port 0

SCK

: Serial clock I/O

P10 and P12: Port 1

SO/SB0

: Serial output/input-output

P20 - P23

: Port 2

: Serial input

P30 - P33

: Port 3

PCL

: Clock output

P50 - P53

: Port 5

INT0

: External vectored interrupt input

P60 - P63

: Port 6

INT2

: External test input

X1 and X2 : Oscillating pins

RESET

: Reset input

: Power supply

: Ground

: No connection

Note When the

PD75402A(A) shares the printed circuit board with the

PD75P402, connect the NC pin

directly to the V

pin.

PD75402A(A)

3. PIN FUNCTIONS

3.1 PORT PINS

Remarks 1. The

PD75402A(A) cannot perform 8-bit I/O with two ports as a pair.

2. See Chapter 8 for each pin status during resetting.

P00

P01

P02

P03

P10

P12

P20

P21

P22

P23

P30 - P33

P50 - P53

P60 - P63

I /O

Input

I/O

Input

I/O

Dual-

function pin

SCK

SO/SB0

INT0

INT2

PCL

Function

4-bit input port (port 0)

P01 to P03 allow the connection of built-in pull-up resistors to be

specified in units of three bits by software.

2-bit input port (port 1)

P10 connects with the built-in noise eliminator using a sampling clock.

P12 connects with the built-in noise eliminator using an analog delay.

P12 allows the connection of built-in pull-up resistor to be specified by

software.

4-bit I/O port (port 2)

Allow I/O specification in units of four bits.

Allow the connection of built-in pull-up resistors to be specified in

units of four bits by software.

Programmable 4-bit I/O port (port 3)

Allow I/O specification bit by bit.

Allow the connection of built-in pull-up resistors to be specified in

units of four bits by software.

Can directly drive LED.

4-bit N-ch open-drain I/O port (port 5)

Allow I/O specification in units of four bits.

Allow the connection of built-in pull-up resistors to be specified bit by

bit by mask option.

Can directly drive LED.

4-bit I/O port (port 6)

Allow I/O specification in units of four bits.

Allow the connection of built-in pull-up resistors to be specified in

units of four bits by software.

Can directly drive LED.

PD75402A(A)

3.2 NON-PORT PINS

Remark See Chapter 8 for each pin status during resetting.

Note Connect the NC pin directly to the V

pin when the

PD75402A(A) shares the printed circuit board

with the

PD75P402 in emulation.

3.3 PIN INPUT/OUTPUT CIRCUITS

The I/O circuits of the

PD75402A(A) are roughly shown on the next and subsequent pages.

Table 1-1 I/O Circuit Type of Pin

Remark The types in circles have a Schmitt-triggered input.

INT0

INT2

SCK

SB0

PCL

X1, X2

RESET

Note

I /O

Input

I/O

Input

Dual-

function pin

P10

P12

P03

P02/SB0

P01

P02/SO

P22

Function

Edge detection vectored interrupt request input pin (A detected edge

can be selected by the mode register.)

Connects with the built-in noise eliminator using a sampling clock.

Edge detection external test input pin (A rising edge is detected.)

Serial data input pin

Serial data output pin

Serial clock I/O pin

Serial bus I/O pin

Clock output pin

Pin for connection to a crystal/ceramic resonator for system clock

generation. An external clock is applied to X1, and its reverse phase to

X2.

System reset input pin, which connects with the built-in noise elimina-

tor using an analog delay.

Positive power supply pin

Ground potential pin

No connection

P00

P01 /SCK

P02 / SO / SB0

P03 / SI

P10 / INT0

P12 /INT2

P20, P21, and P23

P22 /PCL

P30 - P33

P50 - P53

P60 - P63

RESET

I/O type

E-B

I /O type

-A

-B

-C

PD75402A(A)

3.5 HANDLING UNUSED PINS

Recommended connection method

Connected to the V

When a pull-up resistor is contained

Connected to the V

When a pull-up resistor is not contained

Connected to the V

or V

When a pull-up resistor is contained

Input mode

: Connected to the V

Output mode : Open

When a pull-up resistor is not contained

Input mode

: Connected to the V

or V

Output mode : Open

Open or directly connected to the V

Note

P00

P01 - P03

P10, P12

P20 - P23

P30 - P33

P50 - P53

P60 - P63

Connect a capacitor between the pin and V

Note When the

PD75402A(A) shares the printed circuit board with the

PD75P402, connect the NC pin

directly to V

pin.

3.6 NOTES ON USING THE P00 AND RESET PINS

The P00 and RESET pins have the test mode selecting function for testing the internal operation of the

PD75402A(A) (IC test), besides the functions shown in Sections 3.1 and 3.2.

Applying a voltage exceeding V

to the P00 and/or RESET pin causes the

PD75402A(A) to enter the test

mode. When noise exceeding V

comes in during normal operation, the device is switched to the test mode.

For example, when the wiring from the P00 or RESET pin is too long, noise voltage induced on the wiring

is applied to the pin, driving the voltage at the pin above V

, which may cause malfunction.

When installing the wiring, lay the wiring in such a way that noise is suppressed as much as possible. If

noise yet arises, use an external part to suppress it as shown below.

Connect a diode with low V

(0.3 V or lower)

between the pin and V

P00, RESET

Diode with
low V

PD75402A(A)

4. MEMORY CONFIGURATION

Program memory (ROM): 1920

8 bits (000H to 77FH)

· 000H and 001H : Vector table which contains the program start address after reset

· 002H to 009H

: Vector table which contains the program start addresses when interrupts occur

Data memory

· Data area

: 64

4 bits (000H to 03FH)

· Peripheral hardware area: 128

4 bits (F80H to FFFH)

Fig. 4-1 Program Memory Map

Reset start address
(three high-order bits)

INTBT start address
(three high-order bits)

INT0 start address
(three high-order bits)

Reset start address (eight low-order bits)

INTBT start address (eight low-order bits)

INT0 start address (eight low-order bits)

INTCSI start address
(three high-order bits)

INTCSI start address (eight low-order bits)

Address

000H

001H

002H

003H

004H

005H

008H

009H

77FH

Entry address specified in
CALLF !faddr instruction

Branch address specified in
BRCB !caddr instruction

Relative branch address specified in
BR $addr instruction

15 to 1,
+2 to +16

PD75402A(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORTS

The

PD75402A(A) has the following three types of I/O port:

· 6 CMOS input pins (PORT0 and PORT1)

· 12 CMOS I/O pins (PORT2, PORT3, and PORT6)

· 4 N-ch open-drain I/O pins (PORT5)

Total: 22 pins

Table 5-1 Functions of Ports

Note PORT3, PORT5, and PORT6 can directly drive the LED.

Port name

PORT0

PORT1

PORT3

Note

PORT2

PORT6

Note

PORT5

Note

Function

4-bit Input

4-bit I/O

4-bit I/O (N-ch

open-drain I/O

with a withstand

voltage of 10 V)

Remarks

Also used for SO/SB0, SI, SCK, INT0, and

INT2.

Port 2 is also used for PCL.

This port can incorporate a pull-up

resistor as a mask option bit by bit.

Operation and feature

Allows read and test at any

time regardless of the operation

modes of dual function pins.

Allows input or output mode

setting bit by bit.

Allows input or output mode

setting in units of 4 bits.

Allows input or output mode

setting in units of 4 bits.

PD75402A(A)

5.2 CLOCK GENERATOR

Operation of the clock generator is specified by the processor clock control register (PCC).

The instruction execution time is variable.

· 0.95

s, 1.91

s, 15.3

s (when f

is 4.19 MHz.)

Fig. 5-1 Block Diagram of the Clock Generator

System
clock
oscillator

or f

Oscillation
stops.

1/16 to 1/512

Frequency divider

1/2 1/16

Selector

Frequency
divider

HALT flip-
flop

RESET input rising edge
detection signal

RESET input falling
edge detection signal

Standby release signal
from interrupt control circuit

STOP flip-
flop

All bits are
cleared.

PCC2 is
cleared.

HALT*

STOP*

PCC0

PCC1

PCC2

PCC3

Internal bus

PCC

Basic interval timer (BT)

Clock output circuit

Serial interface

1/4

INT0 noise eliminator

· CPU

INT0 noise

eliminator

Clock output

circuit

Remarks 1. f

= Crystal/ceramic oscillated frequency

2. f

= External clock frequency

= CPU clock

4. An asterisk (*) indicates instruction execution.

5. PCC: Processor clock control register

6. One clock cycle (t

) of

is equal to one machine cycle of an instruction. See AC

characteristics of Chapter 10 for details of t

PD75402A(A)

5.3 CLOCK OUTPUT CIRCUIT

The clock output circuit, which outputs clock pulses from pin P22/PCL, is used for supplying clock pulses

for peripheral LSIs or for remote control output.

· Clock output (PCL): 1.05 MHz, 524 kHz, 65.5 kHz (when f

is 4.19 MHz).

Fig. 5-2 shows the configuration of the clock output circuit.

Fig. 5-2 Configuration of the Clock Output Circuit

From the clock
generator

CLOM3 0

Selector

Output
buffer

Port 2 input/
output mode
specification bit

P22 output
latch

P22/PCL

Internal bus

PORT2.2

Bit 2 of PMGB

CLOM1 CLOM0 CLOM

Remark The clock output circuit is designed not to output high-frequency pulses when clock output is

switched between the enable and disable states.

PD75402A(A)

6. INTERRUPT FUNCTION

The

PD75402A(A) has three interrupt sources and each of them has the interrupt vector table.

The

PD75402A(A) is also provided with one edge-sensitive testable input signal.

When a vectored interrupt request is issued, the PC and PSW are saved in the stack, and the contents of

the vector table which corresponds to the issued vectored interrupt are set in the PC as a start address. The

program branches to the interrupt service routine. These operations are performed automatically by the

hardware.

The flag is set by detecting the edge of the testable input signal, but a vectored interrupt request is not

issued.

During execution of the interrupt service routine, the

PD75402A(A) does not accept the other interrupt

requests. Unlike the other 75X series, the

PD75402A(A) cannot handle multiple interrupts.

The interrupt control circuit of the

PD75402A(A) has the following functions.

· Vectored interrupt function under hardware control which can determine whether to accept an interrupt

by an interrupt enable flag (IE

×××

) and an interrupt master enable flag (IME).

· Any interrupt start address can be set.

· Test function of an interrupt request flag (IRQ

×××

) (Software can confirm that an interrupt occurs.)

· Release of the standby (HALT) mode (An interrupt to be released by an interrupt enable flag can be selected

from interrupts other than INT0.)

PD75402A(A)

7. STANDBY FUNCTION

To reduce the power consumption when the program is in the wait state, the

PD75402A(A) has two standby

modes, STOP and HALT.

Table 7-1 Operation Statuses in the Standby Mode

Instruction to be used to

set mode

Clock generator

Basic interval

timer

Serial interface

Clock output

circuit

External

interrupt

CPU

Release signal

HALT mode

HALT instruction

Only the CPU clock (

) stops, but

oscillation continues.

Operates. (IRQBT is set at every refer-

ence time interval.)

Operable

Clocks other than CPU clock (

) can be

output.

INT2 pin is usable.

INT0 pin cannot be used.

RESET input or interrupt request signals

enabled by the interrupt enable flags

STOP mode

STOP instruction

Oscillation of the system clock stops.

Operation stops.

Operable only when the external SCK

input is selected for the serial clock.

Operation stops.

INT2 pin is usable.

INT0 pin cannot be used.

Operation stops.

RESET input

Opera-

tion

status

PD75402A(A)

8. RESET FUNCTION

When a low level signal is input to the RESET input pin, the state changes to the system reset. Table 8-1

shows the statuses of the hardware.

When the RESET signal rises from the low level to the high level, the reset state is released. The three low-

order bits of the reset vector table whose address is 000H is set in bits 10 to 8 of the program counter (PC)

and the contents of the reset vector table whose address is 001H is set in bits 7 to 0 of the PC. The program

branches to that address and starts execution, i.e., the reset start address is programmable.

Initialize contents of registers in a program if necessary.

The RESET pin connects to the Schmitt-trigger circuit whose threshold level has hysteresis in the chip. This

pin is also connected to the noise eliminator using an analog delay to eliminate narrow noise and prevent

errors caused by noise. (See Fig. 8-1.)

For the power-on reset operation, be sure to allow sufficient time for oscillation to settle between power

on and acceptance of the reset signal (see Fig. 8-2).

Fig. 8-1 Acceptance of the Reset Signal

RESET

Analog
delay

Content of the reset
vector table is set
to the PC
(the initialization of the PC).

The instruction which
is stored at the reset
branch address is executed.

Elimination
as noise.

This low level
signal is accepted
as the reset signal.

The reset is
released.

Fig. 8-2 Power-On Reset Operation

RESET

Oscillation
settling time

Analog
delay

The reset
is released.

Content of the reset vector
table is set to the PC
(the initialization of the PC).

The instruction which is stored
at the reset branch address is
executed.

PD75402A(A)

Table 8-1 Hardware Statuses after Reset Operations

Hardware

Program counter (PC)

PSW

Carry flag (CY)

Skip flag (SK0 - SK2)

Interrupt status flag (IST0)

Stack pointer (SP)

Data memory (RAM)

General register (X, A, H, L)

RESET input during operations

Set the three low-order bits of

address 000H in program

memory in PC bits 10 to 8 and

set the contents of address

001H in PC bits 7 to 0.

Undefined

Reset (0)

Off

Cleared (0)

Used as inputs

High level when pull-up

resistor is built in

High impedance when

open drain is used in the

internal circuit

RESET input in standby mode

Set the three low-order bits of

address 000H in program

memory in PC

bits 10 to 8 and

set the contents of address

001H in PC bits 7 to 0.

Retained

Undefined

Retained

Note

Retained

Undefined

Retained

Reset (0)

Off

Cleared (0)

Used as inputs

High level when pull-up

resistor is built in

High impedance when

open drain is used in the

internal circuit

Counter (BT)

Mode register (BTM)

Shift register (SIO)

Operation mode register (CSIM)

SBI control register (SBIC)

Slave address register (SVA)

Processor clock control register

(PCC)

Clock output mode register

(CLOM)

Interrupt request flag (IRQ

×××

)

Interrupt enable flag (IE

×××

)

Interrupt master enable flag

(IME)

INT0 mode register (IM0)

Output buffer

Output latch

I /O mode register

(PMGA, PMGB)

Pull-up resistor specification

P00 - P03, P10, P12, P20 - P23,

P30 - P33, P60 - P63

P50 - P53

Basic interval

timer

Serial

interface

Clock genera-

tor and clock

output circuit

Interrupt

Digital I/O

port

States of pins

Note Data in the data memory whose addresses are 38H to 3DH is not defined when the standby mode

is released by the RESET input signal.

PD75402A(A)

9. INSTRUCTION SET

(1) Representation format and description method of operands

An operand is described in the operand field of each instruction according to the description method

corresponding to the operand representation format of the instruction refer to "RA75X Assembler Package

User's Manual, Language" (EEU-1363) for details. When two or more elements are described in the

description method field, select one of them. Upper-case letters, a number sign (#), and at mark (@), an

exclamation mark (!), and a dollar sign ($) are keywords, so they can be used without alteration.

Specify an appropriate numeric value or label for immediate data.

The symbols of registers and flags can be used as labels instead of mem, fmem, and bit (refer to the

PD75402A User's Manual" (IEU-644) for details). Some labels, however, cannot be specified in fmem.

Note Only an even address can be written in mem when 8-bit data is processed.

(2) Legend

: A register, 4-bit accumulator

: H register

: L register

: X register

: Register pair (XA), 8-bit accumulator

: Register pair (HL)

: Program counter

: Stack pointer

: Carry flag, bit accumulator

PSW

: Program status word

PORTn: Port n (n = 0 to 3, 5, 6)

IME

: Interrupt master enable flag

×××

: Interrupt enable flag

PCC

: Processor clock control register

: Address/bit delimiter

(

××

)

: Contents addressed by

××

: Hexadecimal data

Representation format

reg

reg1

mem

bit

fmem

addr

caddr

faddr

PORTn

×××

Description method

X, A, H, L

X, H, L

XA, HL

4-bit immediate data or label

8-bit immediate data or label

Note

2-bit immediate data or label

FB0H - FBFH/FF0H - FFFH immediate data or label

11-bit immediate data or label

PORT0 - PORT3, PORT5, PORT6

IEBT, IECSI, IE0, IE2

PD75402A(A)

(3) Explanation of the symbols in the addressing area field

Remarks 1. MB indicates an accessible memory bank.

2. *4 to *7 indicate each addressable area.

(4) Explanation of the machine cycle field

S indicates the number of machine cycles required for a skip instruction to perform skipping. The following

shows the values of S.

When the next instruction is not skipped, S is 0.

When the next instruction is skipped, S is 1.

A machine cycle is equal to one cycle (= t

) of CPU clock

. A PCC setting determines the machine cycle.

It can be set to one of three different periods.

MB = 0

MB = 0 (00H - 3FH)
MB = 15 (80H - FFH)

MB = 15, fmem = FB0H - FBFH or
FF0H - FFFH

addr = 000H - 77FH

addr = (Current PC) 15 to (Current PC) 1 or
(Current PC) + 16 to (Current PC) + 2

caddr = 000H - 77FH

faddr = 000H - 77FH

Data memory
addressing

Program memory
addressing

PD75402A(A)

Instruc-

tion

group

Transfer

instruc-

tion

Arithme-

tic/

logical

instruc-

tion

Accumu-

lator

manipu-

lation

instruc-

tion

Incre-

ment/

decre-

ment

instruc-

tion

Compari-

son

instruc-

tion

Carry flag

manipu-

lation

instruc-

tion

Mne-

monic

MOV

XCH

MOVT

ADDS

ADDC

AND

XOR

RORC

NOT

INCS

DECS

SKE

SET1

CLR1

SKT

NOT1

Operand

A, #n4

XA, #n8

HL, #n8

A, @HL

@HL, A

A, mem

XA, mem

mem, A

mem, XA

A, @HL

A, mem

XA, mem

A, reg1

XA, @PCXA

A, #n4

A, @HL

reg

mem

reg

reg, #n4

A, @HL

Number

bytes

Skip

condition

String A

String B

carry

reg = 0

(mem) = 0

reg = FH

reg = n4

A = (HL)

CY = 1

Address-

ing area

Operation

(HL)

(mem)

(HL)

(mem)

reg1

(PC

10-8

+ XA)

ROM

A + n4

A + (HL)

A, CY

A + (HL) + CY

(HL)

, A

CY, A

reg

reg + 1

(mem)

(mem) + 1

reg

reg 1

Skip if reg = n4

Skip if A = (HL)

Skip if CY = 1

Ma-

chine

cycle

1 + S

2 + S

1 + S

2 + S

1 + S

PD75402A(A)

Instruc-

tion

group

Memory

bit

manipu-

lation

instruc-

tion

Branch

instruc-

tion

Subrou-

tine

stack

control

instruc-

tion

Interrupt

control

instruc-

tion

Input/

output

instruc-

tion

CPU

control

instruction

Mne-

monic

SET1

CLR1

SKT

SKF

SKTCLR

AND1

OR1

XOR1

BRCB

CALLF

RET

RETS

RETI

PUSH

POP

OUT

HALT

STOP

NOP

Number

bytes

Skip

condition

(mem.bit) = 1

(fmem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

(fmem.bit) = 1

Uncondition-

ally

Address-

ing area

Ma-

chine

cycle

2 + S

3 + S

Operand

mem.bit

fmem.bit

mem.bit

fmem.bit

mem.bit

fmem.bit

mem.bit

fmem.bit

CY, fmem.bit

addr

$addr

!caddr

!faddr

×××

A, PORTn

PORTn, A

Operation

(mem.bit)

(fmem.bit)

(mem.bit)

(fmem.bit)

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (fmem.bit) = 1 and clear

(fmem.bit)

10-0

addr

(The assembler selects an

appropriate instruction from the

BRCB !caddr and BR $addr

instructions.)

10-0

addr

10-0

caddr

(SP 4)(SP 1)(SP 2)

0, PC

10-0

(SP 3)

0000

10-0

faddr, SP

SP 4

, PC

10-0

(SP)(SP + 3)(SP + 2)

SP + 4

, PC

10-0

(SP)(SP + 3)(SP + 2)

SP + 4, then skip unconditionally

, PC

10-0

(SP)(SP + 3)(SP + 2)

PSW

(SP + 4)(SP + 5), SP

SP + 6

(SP 1)(SP 2)

rp, SP

SP 2

(SP + 1)(SP), SP

SP + 2

IME (IPS.3)

×××

IME (IPS.3)

×××

PORTn (n = 0 - 3, 5, 6)

PORT n

A (n = 2, 3, 5, 6)

Set HALT mode (PCC.2

Set STOP mode (PCC.3

No operation

PD75402A(A)

10. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T

= 25 °C)

Parameter

Supply voltage

Input voltage

Output voltage

High-level output

current

Low-level output

current

Operating

temperature

Storage tempera-

ture

Unit

°C

Rated value

0.3 to +7.0

0.3 to V

+ 0.3

0.3 to V

+ 0.3

0.3 to +11.0

0.3 to V

+ 0.3

100

40 to +85

65 to +150

Symbol

Note

opt

stg

Conditions

Ports other than port 5

Port 5

Built-in pull-up resistor

Open drain

Each pin

Total of all output pins

One pin of port 0, 3, 5, or 6

One pin of port 2

Total of all pins of ports 0, 3,

and 5 (excl. P33)

Total of all pins of ports 2, 6,

and P33

Peak value

rms

Peak value

rms

Peak value

rms

Peak value

rms

Note Calculate rms with [rms] = [peak value]

duty.

Caution Absolute maximum ratings are rated values beyond which some physical damages may be

caused to the product; if any of the parameters in the table above exceeds its rated value even

for a moment, the quality of the product may deteriorate. Be sure to use the product within the

rated values.

PD75402A(A)

Resonator

Ceramic

resonator

Crystal

External

clock

Recommended

constant

Parameter

Oscillator

frequency

)

Note 1

Oscillation

settling time

Note 2

Oscillator

frequency

)

Note 1

Oscillation

settling time

Note 2

X1 input

frequency

)

Note 1

X1 input

high/low

level width

, t

)

CHARACTERISTICS OF THE OSCILLATION CIRCUIT (T

= 40 to +85 °C, V

= 2.7 to 6.0 V)

Notes 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. See

the item of AC characteristics for the instruction execution time.

2. The oscillation settling time means the time required for the oscillation to settle after V

is applied

or after the STOP mode is released.

3. When 4.19 MHz < f

5.0 MHz, do not select PCC = 0011 as the instruction execution time. When

PCC = 0011, one machine cycle falls short of 0.95

s, the minimum value for the standard.

Caution When the clock oscillator is used, conform to the following guidelines when wiring at the

portions surrounded by dotted lines in the figures above to eliminate the influence of the wiring

capacity.

· The wiring must be as short as possible.

· Other signal lines must not run in these areas.

· Any line carrying a high fluctuating current must be kept away as far as possible.

· The grounding point of the capacitor of the oscillator must have the same potential as that

of V

. It must not be grounded to ground patterns carrying a large current.

· No signal must be taken from the oscillator.

CAPACITANCE (T

= 25 °C, V

= 0 V)

Unit

MHz

Min.

2.0

100

Typ.

4.19

Max.

5.0

Note 3

5.0

Note 3

5.0

Note 3

250

Conditions

= oscillation

voltage range

After V

reaches

MIN. of the oscilla-

tion voltage range

= 4.5 to 6.0 V

PD74HCU04

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

OUT

Min.

Typ.

Max.

Unit

Conditions

f = 1 MHz

0 V for pins other than pins to be

measured

PD75402A(A)

= 4.5 to 6.0 V, I

= 1 mA

= 100

= 4.5 to 6.0 V, I

= 15 mA

= 4.5 to 6.0 V, I

= 1.6 mA

= 400

Pull-up resistor : 1 k

more V

= 4.5 to 6.0 V

Other than X1 and X2

X1 and X2

Port 5 (open drain)

Other than X1 and X2

X1 and X2

Other than port 5

Port 5 (open drain)

DC CHARACTERISTICS (T

= 40 to +85 °C, V

= 2.7 to 6.0 V)

Notes 1. This current excludes the current which flows through the built-in pull-up resistors.

2. Value when the processor clock control resistor (PCC) is set to 0011 and the

PD75402A(A) is

operated in the high-speed mode

3. Value when the PCC is set to 0000 and the

PD75402A(A) is operated in the low-speed mode

Parameter

High-level input

voltage

Low-level input

voltage

High-level output

voltage

Low-level output

voltage

High-level input

leakage current

Low-level input

leakage current

High-level output

leakage current

Low-level output

leakage current

Built-in pull-up

resistor

Power supply

current

Note 1

Symbol

IH1

IH2

IH3

IH4

IL1

IL2

IL3

LIH1

LIH2

LIH3

LIL1

LIL2

LOH1

LOH2

LOL

DD1

DD2

DD3

Conditions

Ports 2, 3, and 6

Ports 0 and 1, and RESET

Port 5

Built-in pull-up resistor

Open drain

X1 and X2

Ports 2, 3, 5, and 6

Ports 0 and 1, and RESET

X1 and X2

Ports 0, 2,

3, and 6

Ports 3, 5,

and 6

Ports 0, 2,

3, 5, and 6

SB0 (Open

drain)

= V

= 10 V

= 0 V

OUT

= V

OUT

= 10 V

OUT

= 0 V

Ports 0, 1, 2, 3, and

6 (excl. P00 and

P10) V

= 0 V

Port 5

OUT

= V

2.0 V

4.19 MHz

crystal

resonance

C1 = C2 =

22 pF

STOP

mode

HALT

mode

= 25 °C

= 5.0 V

10 %

Note 2

= 3.0 V

10 %

Note 3

= 5.0 V

10 %

= 3.0 V

10 %

= 5.0 V

10 %

3.0 V

10 %

= 5.0 V

10 %

= 3.0 V

10 %

= 5.0 V

10 %

= 3.0 V

10 %

Typ.

0.6

2.5

0.5

500

150

0.5

0.1

Max.

0.3V

0.2V

0.4

2.0

0.4

0.5

0.2V

300

1.5

1500

450

Unit

Min.

0.7V

0.8V

0.7V

0.5

1.0

0.5

PD75402A(A)

Typ.

Max.

Min.

0.95

3.8

Unit

Note 2

AC CHARACTERISTICS (T

= 40 to +85 °C, V

= 2.7 to 6.0 V, V

= 0 V)

Notes 1. The cycle time of the CPU clock (

)

(minimum instruction execution time)

depends on the connected resonator

frequency and the setting of the proc-

essor clock control register (PCC).

The figure on the right side shows

the cycle time t

characteristics for

the supply voltage V

2. This value is 2t

or 128/f

according

to the setting of the interrupt mode

Symbol

INTH

, t

INTL

RSL

Parameter

CPU clock cycle time

Note 1

(minimum instruction execu-

tion time = one machine cycle)

Interrupt input high/low level

width

RESET low-level width

Conditions

= 4.5 to 6.0 V

INT0

INT2

Guaranteed operating
range

0.5

Supply voltage V

[V]

Cycle time t

[ s]

vs. V

PD75402A(A)

Serial transfer operation

Three-wire serial I /O mode (SCK ··· Internal clock output):

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

Three-wire serial I/O mode (SCK ··· External clock input):

Parameter

SCK cycle time

SCK high/low level

width

SI setup time

(referred to SCK

)

SI hold time

(referred to SCK

)

Delay from SCK

SO output

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

Parameter

SCK cycle time

SCK high/low level

width

SI setup time

(referred to SCK

)

SI hold time

(referred to SCK

)

Delay from SCK

SO output

Symbol

KCY2

KL2

KH2

SIK2

KSI2

KSO2

= 4.5 to 6.0 V

Conditions

= 4.5 to 6.0 V

= 1 k

= 100 pF

Note

Typ.

Max.

250

1000

Unit

Min.

1600

3800

KCY1

/2 50

KCY1

/2 150

150

400

Symbol

KCY1

KL1

KH1

SIK1

KSI1

KSO1

Min.

800

3200

400

1600

100

400

Typ.

Max.

300

1000

Unit

Conditions

= 4.5 to 6.0 V

= 1 k

= 100 pF

Note

= 4.5 to 6.0 V

PD75402A(A)

SBI mode (SCK ··· Internal clock output (master)):

SBI mode (SCK ··· External clock input (slave)):

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

Min.

1600

3800

KCY3

/2 50

KCY3

/2 150

150

KCY3

Parameter

SCK cycle time

SCK high/low level

width

SB0 setup time

(referred to SCK

)

SB0 hold time

(referred to SCK

)

Delay from SCK

SB0 output

Delay from SCK

to SB0

Delay from SB0

to SCK

SB0 low-level width

SB0 high-level width

Symbol

KCY4

KL4

KH4

SIK4

KSI4

KSO4

KSB

SBK

SBL

SBH

Symbol

KCY3

KL3

KH3

SIK3

KSI3

KSO3

KSB

SBK

SBL

SBH

Parameter

SCK cycle time

SCK high/low level

width

SB0 setup time

(referred to SCK

)

SB0 hold time

(referred to SCK

)

Delay from SCK

SB0 output

Delay from SCK

to SB0

Delay from SB0

to SCK

SB0 low-level width

SB0 high-level width

Typ.

Max.

250

1000

Unit

Conditions

= 4.5 to 6.0 V

Conditions

= 4.5 to 6.0 V

= 1 k

= 100 pF

Note

= 4.5 to 6.0 V

Min.

800

3200

400

1600

100

KCY4

Typ.

Max.

300

1000

Unit

PD75402A(A)

Data Hold Timing (STOP Mode Release by RESET)

RESET

DDDR

SRS

STOP instruction execution

STOP mode

Data hold mode

HALT mode

Operating mode

DATA HOLD CHARACTERISTICS AT LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE

= 40 to +85 °C)

Parameter

Data hold supply

voltage

Data hold supply

current

RESET setup time

Oscillation settling

time

Symbol

DDDR

SRS

Min.

2.0

Typ.

0.1

Max.

6.0

Unit

Conditions

DDDR

= 2.0 V

After V

reaches the oscillation

voltage range when the ceramic

resonator is connected

After V

reaches the oscillation

voltage range when the crystal is

connected

PD75402A(A)

11. PACKAGE DIMENSIONS

28 PIN PLASTIC DIP (600 mil)

ITEM

MILLIMETERS

INCHES

38.10 MAX.

2.54 (T.P.)

3.6±0.3

0.51 MIN.

4.31 MAX.

2.54 MAX.

0.25

15.24 (T.P.)

5.72 MAX.

13.2

1.2 MIN.

1.500 MAX.

0.100 MAX.

0.047 MIN.

0.142±0.012

0.020 MIN.

0.170 MAX.

0.226 MAX.

0.600 (T.P.)

0.520

0.01

0.100 (T.P.)

P28C-100-600A1-1

0.50±0.10

0.020

0.25

0.010

+0.10

0.05

+0.004

0.005

+0.004

0.003

NOTES

Each lead centerline is located within 0.25 mm (0.01 inch)
of its true position (T.P.) at maximum material condition.

Item "K" to center of leads when formed parallel.

PD75402A(A)

28PIN PLASTIC SHRINK DIP (400 mil)

ITEM MILLIMETERS

INCHES

NOTES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

0.17

0.007

28.46 MAX.

1.121 MAX.

2.67 MAX.

0.106 MAX.

0.9 MIN.

0.035 MIN.

3.2±0.3

0.126±0.012

5.08 MAX.

0.200 MAX.

10.16 (T.P.)

0.400 (T.P.)

1.778 (T.P.)

0.070 (T.P.)

0.50±0.10

0.020 +0.004

0.005

0.51 MIN.

0.020 MIN.

4.31 MAX.

0.170 MAX.

8.6

0.339

0.25

0.010 +0.004

0.003

+0.10

0.05

P28C-70-400A-1

0~15

2) ltem "K" to center of leads when formed parallel.

PD75402A(A)

44 PIN PLASTIC QFP ( 10)

NOTE

Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.

P44GB-80-3B4-3

ITEM

MILLIMETERS

INCHES

13.6±0.4

10.0±0.2

0.535

0.394

13.6±0.4

0.535

1.0

0.039

1.0

0.039

0.35±0.10

0.014

0.15

0.006

0.8 (T.P.)

0.031 (T.P)

1.8±0.2

0.071

0.8±0.2

0.031

0.15

0.006

0.10

0.004

2.7

0.106

0.1±0.1

0.004±0.004

5°±5°

3.0 MAX.

0.119 MAX.

+0.017

0.016

+0.008

0.009

+0.008

0.009

+0.017

0.016

+0.004

0.005

+0.008

0.009

+0.009

0.008

+0.004

0.003

detail of lead end

+0.10

0.05

PD75402A(A)

12. RECOMMENDED SOLDERING CONDITIONS

The following conditions shall be met when soldering the

PD75402A(A).

For details of the recommended soldering conditions, refer to our document "SMD Surface Mount

Technology Manual" (IEI-1207).

Please consult with our sales offices in case other soldering process is used, or in case soldering is done

under different conditions.

Table 12-1 Soldering Conditions for Surface-Mount Devices

PD75402AGB(A)-

×××

-3B4: 44-pin plastic QFP (10

10 mm)

Caution Do not apply more than a single process at once, except for "Partial heating method."

Table 12-2 Soldering Conditions for Insertion-Mount Devices

PD75402AC(A)-

×××

: 28-pin plastic DIP (600 mil)

PD75402ACT(A)-

×××

: 28-pin plastic shrink DIP (400 mil)

Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does

not come in contact with the main body of the package.

Solder temperature: 260 °C or less

Flow time: 10 seconds or less

Terminal temperature: 260 °C or less

Flow time: 10 seconds or less

Wave soldering

(Only for leads)

Partial heating method

Soldering process

Soldering conditions

Peak package's surface temperature: 230 °C

Reflow time: 30 seconds or less (210 °C or more)

Number of reflow processes: 1

Peak package's surface temperature: 215 °C

Reflow time: 40 seconds or less (200 °C or more)

Number of reflow processes: 1

Solder temperature: 260 °C or less

Flow time: 10 seconds or less

Number of flow processes: 1

Preheating temperature: 120 °C max. (measured on the package

surface)

Terminal temperature: 300 °C or less

Flow time: 3 seconds or less (for each side of device)

Soldering process

Infrared ray reflow

VPS

Wave soldering

Partial heating method

Symbol

IR30-00-1

VP15-00-1

WS60-00-1

Soldering conditions

Notice

Other versions of the products are available. For these versions, the recommended reflow

soldering conditions have been mitigated as follows:

Higher peak temperature (235

C), two-stage, and longer exposure limit.

Contact an NEC representative for details.

PD75402A(A)

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for developing systems including the

PD75402A(A)

In-circuit emulator for the 75X series

Emulation board for the IE-75000-R and IE-75001-R

Emulation probe for the

PD75402AC(A) and

PD75402ACT(A)

Emulation probe for the

PD75402AGB(A). A 44-pin conversion socket, the EV-9200G-44,

is attached to the probe.

PROM programmer

PROM programmer adapter for the

PD75P402C and

PD75P402CT. Connected to the

PG-1500.

PROM programmer adapter for the

PD75P402GB. Connected to the PG-1500.

IE-75000-R

Note 1

IE-75001-R

IE-75000-R-EM

Note 2

EP-75402C-R

EP-75402GB-R

PG-1500

PA-75P402CT

PA-75P402GB

EV-9200G-44

IE control program

PG-1500 controller

RA75X relocatable

assembler

Host machine

· PC-9800 series (MS-DOS

Ver. 3.30 to Ver. 5.00A

Note 3

)

· IBM PC/AT

(PC DOS

Ver. 3.1)

Software

Notes 1. Maintenance service only

2. Not contained in the IE-75001-R

3. These software cannot use the task swap function, which is available in MS-DOS Ver. 5.00 and

Ver. 5.00A.

Remark

Refer to "75X Series Selection Guide" (IF-1027) for development tools manufactured by third parties.

Hardware

PD75402A(A)

APPENDIX C RELATED DOCUMENTS

Documents related to the device

User's manual

Application note

75X series selection guide

Document name

Document No.

IEU-644

IEA-638

IF-1027

IE-75000-R/IE-75001-R User's Manual

IE-75000-R-EM User's Manual

EP-75402C-R User's Manual

EP-75402GB-R User's Manual

PG-1500 User's Manual

Document name

Document No.

EEU-1416

EEU-1294

EEU-701

EEU-702

EEU-1335

EEU-1346

RA75X Assembler Package User's Manual

Operation

Language

EEU-1363

EEU-1291

PG-1500 Controller User's Manual

Other related documents

Package Manual

SMD Surface Mount Technology Manual

Quality Grades on NEC Semiconductor Devices

NEC Semiconductor Device Reliability/Quality Control System

Electrostatic Discharge (ESD) Test

Guide to Quality Assurance for Semiconductor Devices

Document name

Document No.

IEI-1213

IEI-1207

IEI-1209

IEI-1203

IEI-1201

MEI-1202

Caution The above documents may be revised without notice. Use the latest versions when you design

an application system.

Hardware

Software

Documents related to development tools

PD75402A(A)

Cautions on CMOS Devices

Countermeasures against static electricity for all MOSs

Caution

When handling MOS devices, take care so that they are not electrostatically charged.

Strong static electricity may cause dielectric breakdown in gates. When transporting

or storing MOS devices, use conductive trays, magazine cases, shock absorbers, or

metal cases that NEC uses for packaging and shipping. Be sure to ground MOS

devices during assembling. Do not allow MOS devices to stand on plastic plates or

do not touch pins.

Also handle boards on which MOS devices are mounted in the same way.

CMOS-specific handling of unused input pins

Caution

Hold CMOS devices at a fixed input level.

Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an

intermediate-level input may be caused by noise. This allows current to flow in the

CMOS device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold

a fixed input level. Since unused pins may function as output pins at unexpected

times, each unused pin should be separately connected to the V

or GND pin

through a resistor.

If handling of unused pins is documented, follow the instructions in the document.

Statuses of all MOS devices at initialization

Caution

The initial status of a MOS device is unpredictable when power is turned on.

Since characteristics of a MOS device are determined by the amount of ions im-

planted in molecules, the initial status cannot be determined in the manufacture

process. NEC has no responsibility for the output statuses of pins, input and output

settings, and the contents of registers at power on. However, NEC assures operation

after reset and items for mode setting if they are defined.

When you turn on a device having a reset function, be sure to reset the device first.

PD75402A(A)

MS-DOS

is a trademark of Microsoft Corporation.

PC/AT and PC DOS

are trademarks of IBM Corporation.

[MEMO]

No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Ma-

chine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special:

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.

M4 92. 6

Document Outline

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