Document Outline

COVER
DESCRIPTION
FEATURES
APPLICATIONS
ORDERING INFORMATION
Functional Outline
1. PIN CONFIGURATION (TOP VIEW)
2. BLOCK DIAGRAM
3. PIN FUNCTION
- 3.1 Port Pins
- 3.2 Non-port Pins
- 3.3 Pin Input/Output Circuits
- 3.4 Recommended Connection of Unused Pins
4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE
- 4.1 Difference between Mk I and Mk II Modes
- 4.2 Setting Method of Stack Bank Select Register (SBS)
5. MEMORY CONFIGURATION
6. EEPROM
7. PERIPHERAL HARDWARE FUNCTIONS
- 7.1 Digital Input/Output Ports
- 7.2 Clock Generator
- 7.3 Basic Interval Timer/Watchdog Timer
- 7.4 Timer Counter
- 7.5 Programmable Threshold Port (Analog Input Port)
- 7.6 Bit Sequential Buffer ....... 16 Bits
8. INTERRUPT FUNCTION AND TEST FUNCTION
9. STANDBY FUNCTION
10. RESET FUNCTION
- 10.1 Configuration and Operation Status of RESET Function
- 10.2 Watchdog Flag (WDF), Key Return Flag (KRF)
11. MASK OPTION
12. INSTRUCTION SETS
13. ELECTRICAL SPECIFICATIONS
- 13.1 uPD754144
- 13.2 uPD754244
14. CHARACTERISTICS CURVES (REFERENCE VALUES)
- 14.1 uPD754144
- 14.2 uPD754244
15. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUES)
16. PACKAGE DRAWINGS
17. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. COMPARISON OF FUNCTIONS AMONG uPD754144, 754244, AND 75F4264
APPENDIX B. DEVELOPMENT TOOLS
APPENDIX C. RELATED DOCUMENTS

DESCRIPTION

The

PD754244 is a 4-bit single-chip microcontroller which incorporates the EEPROM

for key-less entry

application.

It incorporates a 16

8-bit EEPROM, a 4-Kbyte mask ROM to store software, a 128

4-bit RAM to store the

processing data, a processing CPU, and a carrier generator which easily outputs waveforms for infrared remote

controller.

The details of functions are described in the following user's manual. Be sure to read it before designing.

PD754144, 754244 User's Manual: U10676E

FEATURES

On-chip EEPROM: 16

8 bits (mapped to the data memory)

On-chip key return reset function for key-less entry

System clock oscillation circuit

PD754144: RC oscillator (external resistor and capacitor)

PD754244: Crystal/ceramic oscillator

Low-voltage operation: V

= 1.8 to 6.0 V

Timer function (4 channels)

· Basic interval timer/watchdog timer: 1 channel

· 8-bit timer counter

: 3 channels

On-chip memory

· Program memory (ROM)

4096

8 bits

· Data memory (static RAM)

128

4 bits

Instruction execution time variable function suited for power saving.

PD754144:

4, 8, 16, 64

s (at fcc = 1.0-MHz operation)

PD754244:

0.95, 1.91, 3.81, 15.3

s (at fx = 4.19-MHz operation)

0.67, 1.33, 2.67, 10.7

s (at fx = 6.0-MHz operation)

APPLICATIONS

Automotive appliances such as key-less entry, compact data carrier, etc.

Unless contextually excluded, references in this data sheet to the

PD754244 (crystal/ceramic oscillation: f

)

mean the

PD754144.

The

PD754144 and

PD754244 differ in the notation of their RC oscillation: whenever f

(RC oscillation notation

for

PD754244) is described, f

should be substituted for the

PD754144.

Document No. U10040EJ2V0DS00
Date Published July 1998 N CP(K)
Printed in Japan

The information in this document is subject to change without notice.

4-BIT SINGLE-CHIP MICROCONTROLLERS

PD754144, 754244

MOS INTEGRATED CIRCUIT

1995

DATA SHEET

The mark

shows major revised points.

PD754144, 754244

Functional Outline

Parameter

PD754144

PD754244

Instruction execution time

· 4, 8, 16, 64

· 0.95, 1.91, 3.81, 15.3

(at fcc = 1.0-MHz operation)

(at fx = 4.19-MHz operation)

· 0.67, 1.33, 2.67, 10.7

(at fx = 6.0-MHz operation)

On-chip

Mask ROM

4096

8 bits (0000H-0FFFH)

memory

RAM

128

4 bits (000H-07FH)

EEPROM

8 bits (400H-41FH)

System clock oscillator

RC oscillator

Crystal/ceramic oscillator

(External resistor and capacitor)

General-purpose register

· 4-bit operation: 8

4 banks

· 8-bit operation: 4

4 banks

Input/output

CMOS input

On-chip pull-up resistor can be specified by mask option.

port

CMOS input/output

On-chip pull-up resistor connection can be specified by means of software.

Total

Start-up time after reset

56/fcc

/fx, 2

/fx (selected by mask option)

Stand-by mode release time

/fcc

/fx, 2

/fx

(selected by the setting of BTM)

Timer

4 channels

· 8-bit timer counter

(can be used as 16-bit timer counter)

: 3 channels

· Basic interval/watchdog timer

: 1 channel

Bit sequential buffer

16 bits

Vectored interrupt

External: 1, Internal: 5

Test input

External: 1 (key return reset function available)

Standby function

STOP/HALT mode

Operating ambient temperature

= 40 to +85

Operating supply voltage

= 1.8 to 6.0 V

Package

· 20-pin plastic SOP (300 mil, 1.27-mm pitch)

· 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)

PD754144, 754244

CONTENTS

PIN CONFIGURATION (TOP VIEW) .................................................................................................... 6

BLOCK DIAGRAM ................................................................................................................................ 8

PIN FUNCTION ..................................................................................................................................... 9

3.1

Port Pins ...................................................................................................................................... 9

3.2

Non-port Pins ............................................................................................................................ 10

3.3

Pin Input/Output Circuits ......................................................................................................... 11

3.4

Recommended Connection of Unused Pins .......................................................................... 12

SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE ............................................... 13

4.1

Difference between Mk I and Mk II Modes .............................................................................. 13

4.2

Setting Method of Stack Bank Select Register (SBS) ........................................................... 14

MEMORY CONFIGURATION ............................................................................................................. 15

EEPROM .............................................................................................................................................18

PERIPHERAL HARDWARE FUNCTIONS ......................................................................................... 19

7.1

Digital Input/Output Ports ........................................................................................................ 19

7.2

Clock Generator ........................................................................................................................ 19

7.3

Basic Interval Timer/Watchdog Timer ..................................................................................... 22

7.4

Timer Counter ........................................................................................................................... 23

7.5

Programmable Threshold Port (Analog Input Port) ............................................................... 27

7.6

Bit Sequential Buffer ....... 16 Bits ............................................................................................ 28

INTERRUPT FUNCTION AND TEST FUNCTION .............................................................................. 29

STANDBY FUNCTION ........................................................................................................................ 31

10. RESET FUNCTION ............................................................................................................................. 32

10.1 Configuration and Operation Status of RESET Function ..................................................... 32

10.2 Watchdog Flag (WDF), Key Return Flag (KRF) ...................................................................... 36

11. MASK OPTION ................................................................................................................................... 38

12. INSTRUCTION SETS .......................................................................................................................... 39

13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48

13.1

PD754144 ................................................................................................................................. 48

13.2

PD754244 ................................................................................................................................. 56

14. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................. 67

14.1

PD754144 ................................................................................................................................. 67

14.2

PD754244 ................................................................................................................................. 69

PD754144, 754244

PD754244

· 20-pin Plastic SOP (300 mil, 1.27-mm pitch)

PD754244GS-

×××

-BA5

· 20-pin Plastic Shrink SOP (300 mil, 0.65-mm pitch)

PD754244GS-

×××

-GJG

IC: Internally Connected (Connect to V

directly)

Pin Identification

REF

: Analog reference

P70 to P73

: Port 7

CL1 and CL2

: System clock (RC)

P80

: Port 8

: Internally connected

PTH00 and PTH01

: Programmable threshold port analog inputs 0 and 1

INT0

: External vectored interrupt 0

PTO0 to PTO2

: Programmable timer outputs 0 to 2

KR4 to KR7

: Key returns 4 to 7

RESET

: Reset

KRREN

: Key return reset enable

: Positive power supply

P30 to P33

: Port 3

: Ground

P60 to P63

: Port 6

X1 and X2

: System clock (crystal/ceramic)

RESET

P60/AV

REF

P61/INT0

P62/PTH00

P63/PTH01

KRREN

P80

P30/PTO0

P31/PTO1

P32/PTO2

P33

P70/KR4

P71/KR5

P72/KR6

P73/KR7

PD754144, 754244

3. PIN FUNCTION

3.1 Port Pins

Pin Name

Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function

I/O

TYPE

Note 1

P30

Input/Output

PTO0

Input

E-B

P31

PTO1

P32

PTO2

P33

P60

Input/Output

REF

Input

F -A

P61

INT0

P62

PTH00

P63

PTH01

P70

Input

KR4

Input

B -A

P71

KR5

P72

KR6

P73

KR7

P80

Input/Output

Input

F -A

Notes 1.

Circled characters indicate the Schmitt-trigger input.

Do not specify an on-chip pull-up resistor connection when using the programmable threshold port.

Programmable 4-bit input/output port

(PORT3).

This port can be specified input/output bit-

wise.

On-chip pull-up resistor connection can be

specified by software in 4-bit units.

Programmable 4-bit input/output port (PORT6).

This port can be specified input/output bit-

wise.

On-chip pull-up resistor can be specified by

software in 4-bit units

Note2

Noise eliminator can be selected with P61/INT0.

4-bit input port (PORT7).

On-chip pull-up resistor can be specified by

software bit-wise.

1-bit input/output port (PORT8).

On-chip pull-up resistor connection can be

specified by software.

PD754144, 754244

3.2 Non-port Pins

Pin Name

Input/Output

Alternate

Function

After Reset

I/O Circuit

Function

TYPE

Note

PTO0

Output

P30

Timer counter output pins

Input

E-B

PTO1

P31

PTO2

P32

INT0

Input

P61

Edge detection vectored

Noise elimination

Input

F -A

interrupt input pin

circuit can be

(detected edge can be

selected.

selected)

Asynchronous

Noise elimination circuit

input

can be selected.

KR4 to KR7

Input

P70 to P73

Falling edge detection testable input pins

Input

B -A

PTH00

Input

P62

Threshold voltage-variable 2-bit analog input pins

Input

F -A

PTH01

P63

KRREN

Input

Key return reset enable pin

Input

The reset signal is generated at the falling edge

of KRn while KRREN is high in STOP mode.

REF

Input

P60

Reference voltage input pin

Input

F -A

CL1

Incorporated in the

PD754144 only

RC (for system clock oscillation) connection pin

CL2

External clock cannot be input.

Input

Incorporated in the

PD754244 only

Crystal/ceramic resonator (for system clock

oscillation) connection pin

When inputting the external clock, input the external

clock to pin X1 and input the inverted phase of the

external clock to pin X2.

RESET

Input

System reset input pin (low-level active)

B -A

Pull-up resistor can be incorporated (mask option).

Internally Connected Connect directly to V

Positive supply pin

Ground potential

Note

Circled characters indicate the Schmitt-trigger input.

PD754144, 754244

4. SWITCHING FUNCTION BETWEEN MK I MODE AND MK II MODE

4.1 Difference between Mk I and Mk II Modes

The

PD754244 75XL CPU has the following two modes: Mk I and Mk II, either of which can be selected. The

mode can be switched by the bit 3 of the Stack Bank Select register (SBS).

· Mk I mode:

Instructions are compatible with the 75X series. Can be used in the 75XL CPU with a ROM

capacity of up to 16 Kbytes.

· Mk II mode:

Incompatible with 75X series. Can be used in all the 75XL CPU's including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I Mode

Mk II Mode

Number of stack bytes

2 bytes

3 bytes

for subroutine instructions

BRA !addr1 instruction

Not available

Available

CALLA !addr1 instruction

CALL !addr instruction

3 machine cycles

4 machine cycles

CALLF !faddr instruction

2 machine cycles

3 machine cycles

Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.

Therefore, this mode is effective for enhancing software compatibility with products that

have a program area of more than 16 Kbytes.

With regard to the number of stack bytes during execution of subroutine call instructions,

the usable area increases by 1 byte per stack compared to the Mk I mode when the Mk II

mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle

becomes longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use

efficiency and processing performance than on software compatibility, the Mk I mode

should be used.

PD754144, 754244

5. MEMORY CONFIGURATION

· Program memory (ROM)

· · ·

4096 x 8 bits

Addresses 0000H and 0001H

Vector table wherein the program start address and the values set for the RBE and MBE at the time a

RESET signal is generated are written. Reset and start are possible at an arbitrary address.

Addresses 0002H to 000FH

Vector table wherein the program start address and values set for the RBE and MBE by the vectored

interrupts are written. Interrupt service can be started at an arbitrary address.

Addresses 0020H to 007FH

Table area referenced by the GETI instruction

Note

The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte

instruction, or two 1-byte instructions. It is used to decrease the program steps.

· Data memory

Data area

Static RAM

· · ·

128 words x 4 bits (000H to 07FH)

EEPROM

· · ·

16 words x 8 bits (400H to 41FH)

Peripheral hardware area

· · ·

128 words x 4 bits (F80H to FFFH)

PD754144, 754244

Figure 5-1. Program Memory Map

Note Can be used in the MkII mode only.

Remark In addition to the above, a branch can be made to an address with the low-order 8-bits only of the

PC changed by means of a BR PCDE or BR PCXA instruction.

MBE

RBE

Internal reset start address

(high-order 4 bits)

Internal reset start address

(low-order 8 bits)

MBE

RBE

INTBT start address

(high-order 4 bits)

INTBT start address

(low-order 8 bits)

MBE

RBE

INT0 start address

(high-order 4 bits)

INT0 start address

(low-order 8 bits)

MBE

RBE

INTT0 start address

(high-order 4 bits)

INTT0 start address

(low-order 8 bits)

MBE

RBE

INTT1/INTT2 start address

(high-order 4 bits)

INTT1/INTT2 start address

(low-order 8 bits)

MBE

RBE

INTEE start address

(high-order 4 bits)

INTEE start address

(low-order 8 bits)

GET instruction reference table

0000H

0001H

0002H

0003H

0004H

0005H

0006H

0007H

0008H

0009H

000AH

000BH

000CH

000DH

000EH

000FH

0020H

007FH

0080H

07FFH

0800H

0FFFH

CALLF !faddr instruction

entry address

Branch address of

BR !addr

BRCB !caddr

BR BCDE
BR BCXA

BRA !addr

Note

CALL !addr

CALLA !addr

Note

instructions

GETI Branch/call

Addresses

BR $addr instruction

relative branch address

(15 to 1, +2 to +16)

Address

PD754144, 754244

7. PERIPHERAL HARDWARE FUNCTIONS

7.1 Digital Input/Output Ports

The following two types of I/O ports are provided.

CMOS input (Port 7)

CMOS I/O (Ports 3, 6, 8)

Total

: 13

Table 7-1. Types and Features of Digital Ports

Port Name

Function

Operation and Features

Remarks

PORT3

4-bit I/O

Can be set to input or output mode bit-wise.

Also used as PTO0 to PTO2 pins.

PORT6

Also used as AV

REF

, INT0, PTH00,

and PTH01 pins.

PORT7

4-bit input

4-bit input only port

Also used as KR4 to KR7 pins.

On-chip pull-up resistor connection can be specified

by mask option bit-wise.

PORT8

1-bit I/O

Can be set to input or output mode bit wise.

7.2 Clock Generator

The clock generator provides the clock signals to the CPU and peripheral hardware. Its configuration is shown

in Figures 7-1 and 7-2.

The operation of the clock generator is set with the processor clock control register (PCC).

The instruction execution time can be changed.

PD754144

4, 8, 16, 64

s (when the system clock f

operates at 1.0 MHz)

PD754244

0.95, 1.91, 3.81, 15.3

s (when the system clock f

operates at 4.19 MHz)

0.67, 1.33, 2.67, 10.7

s (when the system clock f

operates at 6.0 MHz)

PD754144, 754244

7.3 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has the following functions.

(a) Interval timer operation to generate a reference time interrupt

(b) Watchdog timer operation to detect a runaway of program and reset the CPU

PD754244 only)

Note 1

(d) Reads the contents of counting

Figure 7-3. Basic Interval Timer/Watchdog Timer Block Diagram

Notes 1.

In the

PD754144 (RC oscillation), the wait time cannot be specified when the standby mode

is released. The oscillation stabilization wait time is negligible in the

PD754144 and this device

returns to the normal operation mode after counting 2

(512

s: @ f

= 1.0-MHz operation).

In the

PD754244 (crystal/ceramic oscillation), on the other hand, the wait time can be specified

when the standby mode is released.

Instruction execution.

From clock
generator

MPX

BTM3 BTM2 BTM1 BTM0 BTM

SET1

Note 2

Internal bus

Basic interval timer

(8-bit frequency divider)

Clear

Wait release signal
when standby is
released

Note 1

Set

Clear

WDTM

SET1

Note 2

Internal reset
signal

Vectored
interrupt
request signal

BT
interrupt
request flag

IRQBT

PD754144, 754244

Figure 7-6. Timer Counter (Channel 2) Block Diagram

Note Instruction execution

Caution When setting data to TC2, be sure to set bit 7 to 0.

Internal bus

TM25 TM24 TM23 TM22 TM21 TM20

TM26

MPX

Decoder

From clock
generator

16-bit timer counter mode

Timer operation start

Count register (8)

Comparator (8)

MPX (8)

Match

TOUT
F/F

High-level period

setting modulo register (8)

Modulo register (8)

Reset

TOE2 REMC NRZB NRZ

TMOD2

TMODH

TC2

Reload

Overflow

Carrier generator mode

PORT3.2

PMGA bit 2

Output
latch

Port 3
input/output
mode

Output buffer

P32/PTO2

Timer counter (channel 1)
clock input

INTT2

IRQT2
set signal

RESET

IRQT2 clear signal

Timer counter (channel 1) match signal
(When 16-bit timer counter mode)

Timer counter (channel 1) clear
signal (When 16-bit timer mode)

Timer counter (channel 1) match signal
(When Carrier generator mode)

TM2

Clear

Selector

SET

Note

PD754144, 754244

8. INTERRUPT FUNCTION AND TEST FUNCTION

Figure 8-1 shows the interrupt control circuit. Each hardware device is mapped in the data memory

space.

The interrupt control circuit of the

PD754244 has the following functions.

(1) Interrupt function

· Vectored interrupt function for hardware control, enabling/disabling the interrupt acknowledgement by

the interrupt enable flag (IE

×××

) and interrupt master enable flag (IME).

· Can set any interrupt start address.

· Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register

(IPS).

· Test function of interrupt request flag (IRQ

×××

). An interrupt generated can be checked by software.

· Release the standby mode. A release interrupt can be selected by the interrupt enable flag.

(2) Test function

· Test request flag (IRQ2) generation can be checked by software.

· Release the standby mode. The test source to be released can be selected by the test enable flag.

PD754144, 754244

9. STANDBY FUNCTION

In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the

PD754244.

Table 9-1. Operation Status in Standby Mode

Item

Mode

STOP Mode

HALT Mode

Set instruction

STOP instruction

HALT instruction

Operation

Clock generator

Operation stops.

Only the CPU clock

halts (oscillation

status

continues).

Basic interval timer/

Operation stops.

Operable

watchdog timer

BT mode: The IRQBT is set in the basic

time interval.

WT mode: Reset is generated by the

BT overflow.

Timer

Operation stops.

Operable.

External interrupt

INT0 is not operable.

Note

INT2 is operable during KRn falling period only.

CPU

The operation stops.

Release signal

· Reset signal

· Interrupt request signal sent from

interrupt enabled peripheral hardware

· System reset signal (key return reset)

generated by KRn falling edge when the

KRREN pin = 1

Note

Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode

PD754144, 754244

Table 10-1. Hardware Status After Reset (1/3)

Hardware

RESET signal generation

in the standby mode

in operation

Program counter (PC)

Sets the low-order 4 bits of

program memory's address

0000H to the PC11-PC8 and the

contents of address 0001H to

the PC7-PC0.

PSW

Carry flag (CY)

Held

Undefined

Skip flag (SK0 to SK2)

Interrupt status flag (IST0, IST1)

Bank enable flag (MBE, RBE)

Sets the bit 6 of program

memory's address 0000H to

the RBE and bit 7 to the MBE.

Stack pointer (SP)

Undefined

Stack bank select register (SBS)

1000B

Data memory (RAM)

Held

Undefined

Data memory (EEPROM)

Held

Note 1

Held

Note 2

EEPROM write control register (EWC)

General-purpose register (X, A, H, L, D, E, B, C)

Held

Undefined

Bank select register (MBS, RBS)

0, 0

Basic interval

Counter (BT)

Undefined

timer/watchdog

Mode register (BTM)

timer

Watchdog timer enable flag (WDTM)

Timer counter

Counter (T0)

(channel 0)

Modulo register (TMOD0)

FFH

Mode register (TM0)

TOE0, TOUT F/F

0, 0

Timer counter

Counter (T1)

(channel 1)

Modulo register (TMOD1)

FFH

Mode register (TM1)

TOE1, TOUT F/F

0, 0

Timer counter

Counter (T2)

(channel 2)

Modulo register (TMOD2)

FFH

High-level period setting modulo

FFH

Mode register (TM2)

TOE2, TOUT F/F

0, 0

REMC, NRZ, NRZB

0, 0, 0

Notes 1.

Undefined if STOP mode is entered during an EEPROM write operation. Also undefined if HALT mode

is entered during a write operation and a RESET signal is input during a write operation.

If a RESET signal is input during an EEPROM write operation, the data at that address is undefined.

PD754144, 754244

Table 10-1. Hardware Status After Reset (2/3)

Hardware

RESET signal generation

in the standby mode

in operation

Programmable threshold port mode register (PTHM)

00H

Clock generator

Processor clock control register (PCC)

Interrupt

Interrupt request flag (IRQ

×××

)

Reset (0)

function

Interrupt enable flag (IE

×××

)

Interrupt priority selection register (IPS)

INT0, 2 mode registers (IM0, IM2)

0, 0

Digital port

Output buffer

Off

Output latch

Cleared (0)

I/O mode registers (PMGA, C)

Pull-up resistor setting register (POGA, B)

Bit sequential buffer (BSB0-BSB3)

Held

Undefined

Table 10-1. Hardware Status After Reset (3/3)

RESET signal

Hardware

generation by key

generation in the

generation by WDT

generation during

return reset

standby mode

during operation

operation

Watchdog flag (WDF)

Hold the previous status

Key return flag (KRF)

Hold the previous status

PD754144, 754244

10.2 Watchdog Flag (WDF), Key Return Flag (KRF)

The WDF is cleared by a watchdog timer overflow signal, and the KRF is set by a reset signal generated by

the KRn pins. As a result, by checking the contents of WDF and KRF, it is possible to know what kind of reset

signal is generated.

As the WDF and KRF are cleared only by external signal or instruction execution, if once these flags are set,

they are not cleared until an external signal is generated or a clear instruction is executed. Check and clear the

contents of WDF and KRF after reset start operation by executing SKTCLR instruction and so on.

Table 10-2 lists the contents of WDF and KRF corresponding to each signal. Figure 10-3 shows the WDF

operation in generating each signal, and Figure 10-4 shows the KRF operation in generating each signal.

Table 10-2. WDF and KRF Contents Correspond to Each Signal

External RESET

Reset signal

WDF clear

KRF clear

Hardware

signal generation

generation by watch-

generation by the

instruction

dog timer overflow

KRn input

execution

Watchdog flag (WDF)

Hold

Key return flag (KRF)

Hold

Figure 10-3. WDF Operation in Generating Each Signal

External RESET

WDF

Operation mode

Reset signal generation by

watchdog timer overflow

External RESET

signal generation

WDF clear

instruction

execution

Operation mode

HALT
mode

Operation

mode

HALT
mode

Operation

mode

HALT
mode

Operation mode

Internal reset operation

Reset signal generation by

watchdog timer overflow

PD754144, 754244

11. MASK OPTION

The

PD754244 has the following mask options:

· Mask option of P70/KR4 to P73/KR7

On-chip pull-up resistor connection can be specified for these pins.

(1) Do not connect an on-chip pull-up resistor

(2) Connect the 100-k

(typ.) pull-up resistor bit-wise

· Mask option of RESET pin

On-chip pull-up resistor connection can be specified for this pin.

(1) Do not connect an on-chip pull-up resistor

(2) Connect the 100-k

(typ.) pull-up resistor

· Standby function mask option (

PD754244 only)

Note

The wait time when the RESET signal is input can be selected.

(1) 2

/fX (21.8 ms: @ f

= 6.0-MHz operation, 31.3 ms: @ f

= 4.19-MHz operation)

(2) 2

/fX (5.46 ms: @ f

= 6.0-MHz operation, 7.81 ms: @ f

= 4.19-MHz operation)

Note This mask option is not provided for the

PD754144, and its wait time is fixed to

56/f

(56

s: @ f

= 1.0-MHz operation).

PD754144, 754244

12. INSTRUCTION SETS

(1) Expression formats and description methods of operands

The operand is described in the operand column of each instruction in accordance with the description

method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER

PACKAGE USERS' MANUAL -- LANGUAGE (EEU-1367)". If there are several elements, one of them

is selected. Capital letters and the + and symbols are key words and are described as they are.

For immediate data, appropriate numbers and labels are described.

Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described.

However, there are restrictions in the labels that can be described for fmem and pmem. For details, refer

to "

PD754144, 754244 user's manual (U10676E)".

Expression

Description method

format

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label

Note

bit

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

pmem

FC0H-FFFH immediate data or label

addr

000H-FFFH immediate data or label

addr1

000H-FFFH immediate data or label

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H-7FH immediate data (where bit 0 = 0) or label

PORTn

PORT3, 6, 7, 8

×××

IEBT, IET0-IET2, IE0, IE2, IEEE

RBn

RB0-RB3

MBn

MB0, MB4, MB15

Note mem can be only used for even address in 8-bit data processing.

PD754144, 754244

(2) Legend in explanation of operation

: A register, 4-bit accumulator

: B register

: C register

: D register

: E register

: H register

: L register

: X register

: XA register pair; 8-bit accumulator

: BC register pair

: DE register pair

: HL register pair

XA'

: XA' extended register pair

BC'

: BC' extended register pair

DE'

: DE' extended register pair

HL'

: HL' extended register pair

: Program counter

: Stack pointer

: Carry flag, bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn

: Port n (n = 3, 6, 7, 8)

IME

: Interrupt master enable flag

IPS

: Interrupt priority selection register

×××

: Interrupt enable flag

RBS

: Register bank selection register

MBS

: Memory bank selection register

PCC

: Processor clock control register

: Separation between address and bit

(

××

)

: The contents addressed by

××

: Hexadecimal data

PD754144, 754244

(3) Explanation of symbols under addressing area column

MB = MBE·MBS

(MBS = 0, 4, 15)

MB = 0

MBE = 0 : MB = 0 (000H to 07FH)

MB = 15 (F80H to FFFH)

Data memory addressing

MBE = 1 : MB = MBS (MBS = 0, 4, 15)

MB = 15, fmem = FB0H to FBFH, FF0H to FFFH

MB = 15, pmem = FC0H to FFFH

addr = 000H to FFFH

addr

= (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

addr1 = (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

Program memory addressing

caddr = 000H to FFFH

faddr = 0000H to 07FFH

*10

taddr = 0020H to 007FH

*11

addr1 = 000H to FFFH

Remarks 1.

MB indicates memory bank that can be accessed.

In *2, MB = 0 independently of how MBE and MBS are set.

In *4 and *5, MB = 15 independently of how MBE and MBS are set.

*6 to *11 indicate the areas that can be addressed.

(4) Explanation of number of machine cycles column

S denotes the number of machine cycles required by skip operation when a skip instruction is executed.

The value of S varies as follows.

· When no skip is made: S = 0

· When the skipped instruction is a 1- or 2-byte instruction: S = 1

· When the skipped instruction is a 3-byte instruction

Note

: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, or CALLA !addr1 instruction

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle of CPU clock (= t

); time can be selected from among four types

by setting PCC.

PD754144, 754244

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Transfer

MOV

A, #n4

String effect A

instruction

reg1, #n4

reg1

XA, #n8

String effect A

HL, #n8

String effect B

rp2, #n8

rp2

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A, mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg

reg

XA, rp'

rp'

reg1, A

reg1

rp'1, XA

rp'1

XCH

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

A, mem

(mem)

XA, mem

(mem)

A, reg1

reg1

XA, rp'

rp'

Table

MOVT

XA, @PCDE

(PC

118

+DE)

ROM

reference
instructions

XA, @PCXA

(PC

118

+XA)

ROM

XA, @BCDE

(BCDE)

ROM

Note

XA, @BCXA

(BCXA)

ROM

Note

Set "0" in register B.

PD754144, 754244

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Bit transfer

MOV1

CY, fmem.bit

(fmem.bit)

instructions

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

fmem.bit, CY

(fmem.bit)

pmem.@L, CY

(pmem

.bit(L

))

@H+mem.bit, CY

(H+mem

.bit)

Operation

ADDS

A, #n4

1+S

A+n4

carry

instructions

XA, #n8

2+S

XA+n8

carry

A, @HL

1+S

A+(HL)

carry

XA, rp'

2+S

XA+rp'

carry

rp'1, XA

2+S

rp'1

rp'1+XA

carry

ADDC

A, @HL

A, CY

A+(HL)+CY

XA, rp'

XA, CY

XA+rp'+CY

rp'1, XA

rp'1, CY

rp'1+XA+CY

SUBS

A, @HL

1+S

A(HL)

borrow

XA, rp'

2+S

XArp'

borrow

rp'1, XA

2+S

rp'1

rp'1XA

borrow

SUBC

A, @HL

A, CY

A(HL)CY

XA, rp'

XA, CY

XArp'CY

rp'1, XA

rp'1, CY

rp'1XACY

AND

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

A, #n4

A, @HL

(HL)

XA, rp'

rp'

rp'1, XA

rp'1

XOR

A, #n4

A v n4

A, @HL

A v (HL)

XA, rp'

XA v rp'

rp'1, XA

rp'1

rp'1 v XA

Accumulator

RORC

, A

CY, A

manipulation
instructions

NOT

PD754144, 754244

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Increment

INCS

reg

1+S

reg

reg+1

reg=0

and
Decrement

rp1

1+S

rp1

rp1+1

rp1=00H

instructions

@HL

2+S

(HL)

(HL)+1

(HL)=0

mem

2+S

(mem)

(mem)+1

(mem)=0

DECS

reg

1+S

reg

reg1

reg=FH

rp'

2+S

rp'

rp'1

rp'=FFH

Comparison

SKE

reg, #n4

2+S

Skip if reg = n4

reg=n4

instruction

@HL, #n4

2+S

Skip if (HL) = n4

(HL) = n4

A, @HL

1+S

Skip if A = (HL)

A = (HL)

XA, @HL

2+S

Skip if XA = (HL)

XA = (HL)

A, reg

2+S

Skip if A = reg

A=reg

XA, rp'

2+S

Skip if XA = rp'

XA=rp'

Carry flag

SET1

manipulation
instruction

CLR1

SKT

1+S

Skip if CY = 1

CY=1

NOT1

Memory bit

SET1

mem.bit

(mem.bit)

manipulation
instructions

fmem.bit

(fmem.bit) 1

pmem.@L

(pmem

.bit(L

))

@H+mem.bit

(H+mem

.bit) 1

CLR1

mem.bit

(mem.bit) 0

fmem.bit

(fmem.bit) 0

pmem.@L

(pmem

.bit(L

))

@H+mem.bit

SKT

mem.bit

2+S

Skip if (mem.bit)=1

(mem.bit)=1

fmem.bit

2+S

Skip if (fmem.bit)=1

(fmem.bit)=1

pmem.@L

2+S

Skip if (pmem

.bit(L

))=1

(pmem.@L)=1

@H+mem.bit

2+S

Skip if (H+mem

.bit)=1

(@H+mem.bit)=1

SKF

mem.bit

2+S

Skip if (mem.bit)=0

(mem.bit)=0

fmem.bit

2+S

Skip if (fmem.bit)=0

(fmem.bit)=0

pmem.@L

2+S

Skip if (pmem

.bit(L

))=0

(pmem.@L)=0

@H+mem.bit

2+S

Skip if (H+mem

.bit)=0

(@H+mem.bit)=0

(H+mem

.bit)

PD754144, 754244

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Memory bit

SKTCLR

fmem.bit

2+S

Skip if (fmem.bit)=1 and clear

(fmem.bit)=1

manipulation
instructions

pmem.@L

2+S

Skip if (pmem

.bit(L

))=1 and clear

(pmem.@L)=1

@H+mem.bit

2+S

Skip if (H+mem

.bit)=1 and clear

(@H+mem.bit)=1

AND1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

OR1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

.bit(L

))

CY, @H+mem.bit

(H+mem

.bit)

XOR1

CY, fmem.bit

CY v (fmem.bit)

CY, pmem.@L

CY v (pmem

.bit(L

))

CY, @H+mem.bit

CY v (H+mem

.bit)

Branch

Note 1

addr

110

addr

instructions

Select appropriate instruction among
BR !addr BRCB !caddr, and BR $addr
according to the assembler being used.

addr1

11-0

addr

*11

Select appropriate instruction among
BR !addr BRA !addr1, BRCB !caddr and
BR $addr1 according to the assembler
being used.

! addr

110

addr

$addr

110

addr

$addr1

110

addr1

PCDE

110

11-8

+DE

PCXA

110

11-8

+XA

BCDE

110

BCDE

Note 2

BCXA

110

BCXA

Note 2

BRA

Note 1

!addr1

110

addr1

*11

BRCB

!caddr

110

caddr

110

Notes 1.

The above operations in the double boxes can be performed only in the Mk II mode.

"0" must be set to B register.

PD754144, 754244

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Subroutine

CALLA

Note

!addr1

(SP2)

, MBE, RBE

*11

stack control

(SP6) (SP3) (SP4)

110

instructions

(SP5)

0, 0, 0, 0

110

addr1, SP

SP6

CALL

Note

!addr

(SP3)

MBE, RBE, 0, 0

(SP4) (SP1) (SP2)

110

addr, SP

SP4

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

110

addr, SP

SP6

CALLF

Note

!faddr

(SP3)

MBE, RBE, 0, 0

(SP4) (SP1) (SP2)

110

0+faddr, SP

SP4

(SP2)

, MBE, RBE

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

110

0+faddr, SP

SP6

RET

Note

110

(SP) (SP+3) (SP+2)

MBE, RBE, 0, 0

(SP+1), SP

SP+4

, MBE, RBE

(SP+4)

0, 0, 0, 0,

(SP+1)

110

(SP) (SP+3) (SP+2), SP

SP+6

RETS

Note

3+S

MBE, RBE, 0, 0

(SP+1)

Unconditional

110

(SP) (SP+3) (SP+2)

SP+4

then skip unconditionally

0, 0, 0, 0

(SP+1)

110

(SP) (SP+3) (SP+2)

, MBE, RBE

(SP+4)

SP+6

then skip unconditionally

RETI

Note

MBE, RBE, 0, 0

(SP+1)

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

0, 0, 0, 0

(SP+1)

110

(SP) (SP+3) (SP+2)

PSW

(SP+4) (SP+5), SP

SP+6

PUSH

(SP1) (SP2)

rp, SP

SP2

(SP1)

MBS, (SP2)

RBS, SP

SP2

POP

(SP+1) (SP), SP

SP+2

MBS

(SP+1), RBS

(SP), SP

SP+2

Note

The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

PD754144, 754244

Instruction

Number

Addressing

Mnemonic

Operand

of machine

Operation

Skip condition

group

of bytes

cycles

area

Interrupt

IME (IPS.3)

control
instructions

×××

IME (IPS.3)

×××

Input/output

Note 1

A, PORTn

PORTn

(n = 3, 6, 7, 8)

instructions

OUT

Note 1

PORTn, A

PORTn

(n = 3, 6, 8)

CPU control

HALT

Set HALT Mode (PCC.2

instructions

STOP

Set STOP Mode (PCC.3

NOP

No Operation

Special

SEL

RBn

RBS

(n = 0-3)

instructions

MBn

MBS

(n = 0, 4, 15)

GETI

Notes 2, 3

taddr

· When TBR instruction

*10

110

(taddr)

+ (taddr+1)

· When TCALL instruction

(SP4) (SP1) (SP2)

110

(SP3)

MBE, RBE, 0, 0

110

(taddr)

+ (taddr+1)

SP4

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

· When TBR instruction

*10

110

(taddr)

+ (taddr+1)

· When TCALL instruction

(SP6) (SP3) (SP4)

110

(SP5)

0, 0, 0, 0

(SP2)

, MBE, RBE

110

(taddr)

+ (taddr+1)

SP6

· When instruction other than TBR and

Depending on

TCALL instructions

the reference

(taddr) (taddr+1) instruction is executed.

instruction

Notes 1.

While the IN instruction and OUT instruction are being executed, MBE must be set to 0, or MBE must

be set to 1 and MBS must be set to 15.

The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

PD754144, 754244

13. ELECTRICAL SPECIFICATIONS

13.1

PD754144

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Test Conditions

Ratings

Unit

Power supply voltage

0.3 to +7.0

Input voltage

0.3 to V

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current, high

Per pin

P30, P31, P33, P60 to P63, P80

P32

For all pins

Output current, low

Per pin

For all pins

Operating ambient

40 to +85

temperature

Storage temperature

stg

65 to +150

Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality

of the product may be impaired. The absolute maximum ratings are values that may physically

damage the products. Be sure to use the products within the ratings.

Capacitance (T

= 25

C, V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

OUT

Unmeasured pins returned to 0 V

I/O capacitance

PD754144, 754244

PD754144

System Clock Oscillator Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Resonator

Recommended Constant

Parameter

Testing Conditions

MIN.

TYP.

MAX.

Unit

Oscillation

0.4

2.0

MHz

oscillator

frequency (f

)

Note

Note Only the oscillator characteristics are shown. For the instruction execution time and oscillation frequency

characteristics, refer to AC Characteristics.

Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines

in the figures as follows to avoid adverse influences on the wiring capacitance:

· Keep the wire length as short as possible.

· Do not cross other signal lines.

· Do not route the wiring in the vicinity of lines though which a high fluctuating current flows.

· Always keep the ground point of the capacitor of the oscillation circuit as the same potential

as V

· Do not connect the power source pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

CL1 CL2

PD754144, 754244

PD754144

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

High-level output

Per pin

P30, P31, P33,

current

P60 to P63, P80

P32, V

= 3.0 V,

= V

2.0 V

Total of all pins

Low-level output

Per pin

current

Total of all pins

High-level input

IH1

Port 3

2.7 V

6.0 V

0.7V

voltage

1.8 V

< 2.7 V

0.9V

IH2

Ports 6 to 8,

2.7 V

6.0 V

0.8V

KRREN, RESET

1.8 V

< 2.7 V

0.9V

Low-level input

IL1

Port 3

2.7 V

6.0 V

0.3V

voltage

1.8 V

< 2.7 V

0.1V

IL2

Ports 6 to 8,

2.7 V

6.0 V

0.2V

KRREN, RESET

1.8 V

< 2.7 V

0.1V

High-level

= 4.5 to 6.0 V, I

= 1.0 mA

1.0

output voltage

= 1.8 to 6.0 V, I

= 100

0.5

Low-level

= 4.5 to 6.0 V

Port 3, I

= 15 mA

0.6

2.0

output voltage

Ports 6, 8,

0.4

= 1.6 mA

= 1.8 to 6.0 V, I

= 400

0.5

High-level input

LIH

VIN = V

3.0

leakage current

Low-level input

LIL

= 0 V

3.0

leakage current

High-level output

LOH

OUT

= V

3.0

leakage current

Low-level output

LOL

OUT

= 0 V

3.0

leakage current

On-chip pull-up

= 0 V

Ports 3, 6, 8

100

200

resistance

Port 7, RESET

100

200

(mask option)

PD754144, 754244

PD754144

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power supply

DD1

1.0-MHz

= 5.0 V

10%

Note 2

0.7

2.1

current

Note 1

RC oscillation

= 3.0 V

10%

Note 3

0.3

1.0

DD2

R = 22 k

HALT

= 5.0 V

10%

0.5

1.8

C = 22 pF

mode

= 3.0 V

10%

0.25

0.9

DD1

1.0-MHz

= 5.0 V

10%

Note 2

1.15

3.5

RC oscillation

= 3.0 V

10%

Note 3

0.55

1.6

DD2

R = 5.1 k

HALT

= 5.0 V

10%

0.95

2.8

C = 120 pF

mode

= 3.0 V

10%

0.5

1.5

DD3

STOP

= 1.8 to 6.0 V

mode

= 25

= 3.0 V

10%

0.1

= 40 to +40

0.1

Notes 1.

The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and

the current when the program threshold port (PTH) is operating are not included.

When the device is operated in the high-speed mode by setting the processor clock control register

(PCC) to 0011H.

When the device is operated in the low-speed mode by setting PCC to 0000H.

PD754144, 754244

PD754144

AC Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle time

Note1

2.0

4.0

128

(Minimum instruction execution

time = 1 machine cycle)

RC oscillation frequency

R = 22 k

= 3.6 to 6.0 V

0.9

1.0

Note 2

1.2

MHz

C = 22 pF

= 2.2 to 3.6 V

0.75

1.0

Note 2

1.15

MHz

= 1.8 to 3.6 V

0.5

1.0

Note 2

1.15

MHz

= 1.8 to 6.0 V

0.5

1.0

Note 2

1.2

MHz

R = 5.1 k

= 3.6 to 6.0 V

0.91

1.0

Note 2

1.1

MHz

C = 120 pF

= 2.2 to 3.6 V

0.76

1.0

Note 2

1.05

MHz

= 1.8 to 3.6 V

0.51

1.0

Note 2

1.05

MHz

= 1.8 to 6.0 V

0.51

1.0

Note 2

1.1

MHz

Interrupt input high- and

INTH

, t

INTL

INT0

IM02 = 0

Note 3

low-level width

IM02 = 1

KR4 to KR7

RESET low-level width

RSL

Notes 1.

The CPU clock (

) cycle time (minimum

instruction execution time) is determined

by the time constants of the connected

resistor (R) and capacitor (d) and the pro-

cessor clock control register (PCC). The

figure on the right shows the cycle time t

characteristics against the supply voltage

when the system clock is used.

This is the typical value when V

= 3.6 V.

or 128/f

depending on the setting of

the interrupt mode register (IM0).

0.5

Supply voltage V

(V)

1.8

128

(During system clock operation)

vs. V

Operation guranteed range

Cycle time t

( s)

PD754144, 754244

PD754144

EEPROM Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

EEPROM

EEW

1.0 MHz,

= 5.0 V

10%

4.0

write current

RC oscillation

= 3.0 V

10%

2.0

EEPROM

EEW

1.0 MHz, RC oscillation

Note

3.8

4.6

10.0

write time

EEPROM

EEWT

= 40 to +70

100000

times/byte

write times

= 40 to +85

80000

times/byte

Note

Set EWTC 4 to 6 so as to be 18 x 2

(4.6 ms: @ f

= 1.0-MHz operation), considering the variation

of the RC oscillation.

Comparator Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Comparison accuracy

ACOMP

100

Threshold voltage

Note

PTH input voltage

IPTH

REF

input voltage

IAVREF

1.8

Comparator circuit

DD5

When bit 7 of PTHM is set to 1

current consumption

Note

The threshold voltage becomes as follows by settings bits 0 to 3 of PTHM.
V

= V

IAVREF

x (n + 0.5)/16 (n = 0 to 15)

PD754144, 754244

13.2

PD754244

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Test Conditions

Ratings

Unit

Power supply voltage

0.3 to +7.0

Input voltage

0.3 to V

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current, high

Per pin

P30, P31, P33, P60 to P63, P80

P32

For all pins

Output current, low

Note

Per pin

For all pins

Operating ambient

40 to +85

temperature

Storage temperature

stg

65 to +150

Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality

of the product may be impaired. The absolute maximum ratings are values that may physically

damage the products. Be sure to use the products within the ratings.

Capacitance (T

= 25

C, V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

OUT

Unmeasured pins returned to 0 V

I/O capacitance

PD754144, 754244

PD754244

System Clock Oscillator Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Resonator

Recommended Constant

Parameter

Testing Conditions

MIN.

TYP.

MAX.

Unit

Ceramic

Oscillation

1.0

6.0

Notes2, 3, 4

MHz

resonator

frequency (f

)

Note1

Oscillation

After V

reaches MIN.

stabilization

value of oscillation

time

Note 5

voltage range

Crystal

Oscillation

1.0

6.0

Notes2, 3, 4

MHz

resonator

frequency(f

)

Note1

Oscillation

= 4.5 to 6.0 V

stabilization time

Note3

External

X1 input

1.0

6.0

Notes2, 3, 4

MHz

clock

frequency (f

)

Note1

X1 input high- and

83.3

500

low-level widths

, t

)

Notes 1.

Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Charac-

teristics.

If the oscillation frequency is 2.1 MHz < f

4.19 MHz at 1.8 V

< 2.0 V, set the processor control

of 1.9

s is not satisfied.

If the oscillation frequency is 4.19 MHz < f

6.0 MHz at 1.8 V

< 2.0 V, set the processor control

cycle time of 1.9

s is not satisfied.

If the oscillation frequency is 4.19 MHz < f

6.0 MHz at 2.0 V

< 2.7 V, set the processor control

0.95

s is not satisfied.

Oscillation stabilization time is a time required for oscillation to stabilize after application of V

or after the STOP mode has been released.

Caution When using the oscillation circuit of the system clock, wire the portion enclosed in dotted lines

in the figures as follows to avoid adverse influences on the wiring capacitance:

· Keep the wire length as short as possible.

· Do not cross other signal lines.

· Do not route the wiring in the vicinity of lines though which a high fluctuating current flows.

· Always keep the ground point of the capacitor of the oscillation circuit as the same potential

as V

· Do not connect the power source pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

PD754144, 754244

PD754244

Recommended Oscillator Constants

Ceramic resonator (T

= 20 to +80

Manufacturer

Part Number

Frequency

Recommended Circuit

Oscillation Voltage

Remark

Constant (pF)

Range (V

)

(MHz)

MN. (V)

MAX. (V)

Kyocera

KBR-1000F/Y

1.0

100

1.8

6.0

KBR-2.0MS

2.0

KBR-4.19MSB

4.19

KBR-4.19MKC

Model with capacitor

PBRC4.19A

PBRC4.19B

Model with capacitor

KBR-6.0MSB

6.0

KBR-6.0MKC

Model with capacitor

PBRC6.00A

PBRC6.00B

Model with capacitor

Ceramic resonator (T

= 40 to +80

Manufacturer

Part Number

Frequency

Recommended Circuit

Oscillation Voltage

Remark

Constant (pF)

Range (V

)

(MHz)

MIN. (V)

MAX. (V)

Murata Mfg.

CSB1000J

Note

1.0

100

2.0

6.0

Rd = 2.2 k

Co., Ltd.

CSA2.00MG040

2.0

CST2.00MG040

Model with capacitor

CSA4.19MG

4.19

1.9

CST4.19MGW

Model with capacitor

CSA4.19MGU

1.8

CST4.19MGWU

Model with capacitor

CSA6.00MG

6.0

2.5

CST6.00MGW

Model with capacitor

CSA6.00MGU

1.8

CST6.00MGWU

Model with capacitor

TDK

CCR1000K2

1.0

100

2.0

CCR4.19MC3

4.19

Model with capacitor

FCR4.19MC5

CCR6.0MC3

6.0

FCR6.0MC5

PD754144, 754244

PD754244

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

High-level output

Per pin

P30, P31, P33,

current

P60 to P63, P80

P32, V

= 3.0 V,

= V

2.0 V

Total of all pins

Low-level output

Per pin

current

Total of all pins

High-level input

IH1

Port 3

2.7 V

6.0 V

0.7V

voltage

1.8 V

< 2.7 V

0.9V

IH2

Ports 6 to 8,

2.7 V

6.0 V

0.8V

KRREN, RESET

1.8 V

< 2.7 V

0.9V

IH3

0.1

Low-level input

IL1

Port 3

2.7 V

6.0 V

0.3V

voltage

1.8 V

< 2.7 V

0.1V

IL2

Ports 6 to 8,

2.7 V

6.0 V

0.2V

KRREN, RESET

1.8 V

< 2.7 V

0.1V

IH3

0.1

High-level

= 4.5 to 6.0 V, I

= 1.0 mA

1.0

output voltage

= 1.8 to 6.0 V, I

= 100

0.5

Low-level

= 4.5 to 6.0 V

Port 3, I

= 15 mA

0.6

2.0

output voltage

Ports 6, 8,

0.4

= 1.6 mA

= 1.8 to 6.0 V, I

= 400

0.5

High-level input

LIH1

= V

Pins other than X1

3.0

leakage current

LIH2

Low-level input

LIL1

= 0 V

Pins other than X1

3.0

leakage current

LIH2

High-level output

LOH

OUT

= V

3.0

leakage current

Low-level output

LOL

OUT

= 0 V

3.0

leakage current

On-chip pull-up

= 0 V

Port 3, 6, 8

100

200

resistance

Port 7, RESET

100

200

(mask option)

PD754144, 754244

PD754244

DC Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power supply

DD1

4.19-MHz

= 5.0 V

10%

Note 2

1.5

5.0

current

Note 1

crystal

= 3.0 V

10%

Note 3

0.23

1.0

DD2

oscillation

HALT

= 5.0 V

10%

0.64

3.0

C1 = C2 = 22 pF mode

= 3.0 V

10%

0.20

0.9

DD3

X1 = 0 V

= 1.8 to 6.0 V

STOP mode

= 25

= 3.0 V

10%

0.1

= 40 to +40

0.1

Notes 1.

The current flowing through the on-chip pull-up resistor, the current during EEPROM writing time, and

the current during the program threshold port (PTH) operation are not included.

When the device is operated in the high-speed mode by setting the processor clock control register

(PCC) to 0011H

When the device is operated in the low-speed mode by setting PCC to 0000H

PD754144, 754244

PD754244

AC Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle time

Note 1

= 1.8 to 2.0 V

1.9

64.0

(Minimum instruction execution

= 2.0 to 2.7 V

0.95

64.0

time = 1 machine cycle)

= 2.7 to 6.0 V

0.67

64.0

Interrupt input high- and

INTH

, t

INTL

INT0

IM02 = 0

Note 2

low-level width

IM02 = 1

KR4 to KR7

RESET low-level width

RSL

Notes 1.

The CPU clock (

) cycle time (minimum

instruction execution time) is determined

by the oscillation frequency of the con-

nected resonator (or external clock) and

the processor clock control register (PCC).

The figure on the right shows the cycle

time t

characteristics against the supply

voltage V

when the system clock is used.

or 128/f

depending on the setting of

the interrupt mode register (IM0).

0.5

Supply voltage V

(V)

1.9

0.95

0.67

2.7

(During system clock operation)

vs. V

Operation guranteed range

1.8

Cycle time t

( s)

PD754144, 754244

PD754244

EEPROM Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

EEPROM

EEW

4.19 MHz,

= 5.0 V

10%

4.5

write current

crystal oscillation

= 3.0 V

10%

2.0

EEPROM

EEW

3.8

10.0

write time

EEPROM

EEWT

= 40 to +70

100000

times/byte

write times

= 40 to +85

80000

times/byte

Comparator Characteristics (T

= 40 to +85

C, V

= 1.8 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Comparison accuracy

ACOMP

100

Threshold voltage

Note

PTH input voltage

IPTH

REF

input voltage

IAVREF

1.8

Comparator circuit

DD5

When bit 7 of PTHM is set to 1

current consumption

Note

The threshold voltage becomes as follows by settings bits 0 to 3 of PTHM.
V

= V

IAVREF

x (n + 0.5)/16 (n = 0 to 15)

PD754144, 754244

PD754244

Interrupt Input Timing

RESET Input Timing

Data Memory STOP Mode Low-Supply Voltage Data Retention Characteristics (T

= 40 to +85

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Release signal set time

SREL

Oscillation stabilization

WAIT

Release by RESET

Note 2

wait time

Note 1

Release by interrupt request

Note 3

Notes 1.

The oscillation stabilization wait time is the time during which the CPU operation is stopped to

avoid unstable operation at oscillation start.

/fx and 2

/fx can be selected with mask option.

Depends on setting of basic interval timer mode register (BTM) (see table below).

BTM3

BTM2

BTM1

BTM0

Wait Time

When f

= 4.19 MHz

When f

= 6.0 MHz

(Approx. 250 ms)

(Approx. 175 ms)

(Approx. 31.3 ms)

(Approx. 21.8 ms)

(Approx. 7.81 ms)

(Approx. 5.46 ms)

(Approx. 1.95 ms)

(Approx. 1.37 ms)

RESET

RSL

INT0, KR4 to KR7

INTL

INTH

PD754144, 754244

17. RECOMMENDED SOLDERING CONDITIONS

Solder the

PD754244 under the following recommended conditions.

For the details on the recommended soldering conditions, refer to Information Document "Semiconductor

Device Mounting Technology Manual (C10535E)".

For the soldering method and conditions other than those recommended, consult an NEC representative.

Table 17-1. Soldering Conditions of Surface Mount Type (1/2)

(1)

PD754244GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)

Soldering Method

Soldering Conditions

Symbol

Infrared ray reflow

Package peak temperature: 235

C, Reflow time: 30 seconds max. (210

C min.),

IR35-00-2

Number of reflow process: 2 max.

VPS

Package peak temperature: 215

C, Reflow time: 40 seconds max. (200

C min.),

VP15-00-2

Number of reflow process: 2 max.

Wave soldering

Solder bath temperature: 260

C max., Flow time: 10 seconds max.,

WS60-00-1

Number of flow process: 1

Preheating temperature: 120

C max. (package surface temperature)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per side of device)

Caution

Do not use different soldering methods together (except for partial heating).

(2)

PD754144GS-xxx-GJG: 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)

Soldering Method

Soldering Conditions

Symbol

Infrared ray reflow

Package peak temperature: 235

C, Reflow time: 30 seconds max. (210

C min.),

IR35-00-3

Number of reflow process: 3 max.

VPS

Package peak temperature: 215

C, Reflow time: 40 seconds max. (200

C min.),

VP15-00-3

Number of reflow process: 3 max.

Wave soldering

Solder bath temperature: 260

C max., Flow time: 10 seconds max.,

WS60-00-1

Number of flow process: 1

Preheating temperature: 120

C max. (package surface temperature)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per side of device)

Caution

Do not use different soldering methods together (except for partial heating).

PD754144, 754244

Table 17-1. Soldering Conditions of Surface Mount Type (2/2)

(3)

PD754144GS-xxx-BA5: 20-pin plastic SOP (300 mil, 1.27-mm pitch)

PD754244GS-xxx-BA5: 20-pin plastic SOP (300 mil, 1.27-mm pitch)

Soldering Method

Soldering Conditions

Symbol

Infrared ray reflow

Package peak temperature: 235

C, Reflow time: 30 seconds max. (210

C min.),

IR35-107-2

Number of reflow process: 2 max.

Exposure limit: 7 days

Note

(afterward, 10-hour pre-baking at 125

C is required)

VPS

Package peak temperature: 215

C, Reflow time: 40 seconds max. (200

C min.),

VP15-107-2

Number of reflow process: 2 max.

Exposure limit: 7 days

Note

(afterward, 10-hour pre-baking at 125

C is required)

Wave soldering

Solder bath temperature: 260

C max., Flow time: 10 seconds max.,

WS60-107-1

Number of flow process: 1

Preheating temperature: 120

C max. (package surface temperature)

Exposure limit: 7 days

Note

(afterward, 10-hour pre-baking at 125

C is required)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per side of device)

Note

Maximum number of days during which the product can be stored at a temperature of 25

C and a relative

humidity of 65% or less after dry-pack package is opened.

Caution

Do not use different soldering methods together (except for partial heating).

PD754144, 754244

APPENDIX A. COMPARISON OF FUNCTIONS AMONG

PD754144, 754244, AND 75F4264

Item

PD754144

PD754244

PD75F4264

Note

Program memory

Mask ROM

Flash memory

0000H to 0FFFH

(4096 x 8 bits)

Data

Static RAM

000H to 07FH

memory

(128 x 4 bits)

EEPROM

400H to 41FH

400H to 43FH

(16 x 8 bits)

(32 x 8 bits)

CPU

75XL CPU

General-purpose register

(4 bits x 8 or 8 bits x 4) x 4 banks

Instruction execution time

· 4, 8, 16, 64

· 0.67, 1.33, 2.67, 10.7

(@ f

= 1.0-MHz

(@ f

= 6.0-MHz operation)

operation)

· 0.95, 1.91, 3.81, 15.3

(@ f

= 4.19-MHz operation)

I/O port

CMOS input

4 (on-chip pull-up resistor can be connected by mask option)

CMOS I/O

9 (on-chip pull-up resistor connection can be specified by means of software)

Total

System clock oscillator

RC oscillator

Ceramic/crystal oscillator

(resistor and capacitor are

connected externally)

Start-up time after reset

56/f

, 2

(can be

selected by mask option)

Standby mode release time

, 2

(can be selected by the setting of BTM)

Timer

4 channels

· 8-bit timer counter: 3 channels (can be used as 16-bit timer counter)

· Basic interval timer/watchdog timer: 1 channel

A/D converter

None

· 8-bit resolution x 2

channels (successive

approximation, hardware

control)

· Can be operated

from V

= 1.8 V

Programmable threshold port

2 channels

Vectored interrupt

External: 1, internal: 5

Test input

External: 1 (key return reset function available)

Power supply voltage

= 1.8 to 6.0 V

Operating ambient temperature

= 40 to +85

Package

· 20-pin plastic SOP (300 mil, 1.27-mm pitch)

· 20-pin plastic SOP

· 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch)

(300 mil, 1.27-mm pitch)

Note

Under development

PD754144, 754244

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for system development using the

PD754244.

In the 75XL series, the relocatable assembler which is common to the series is used in combination with the

device file of each product.

Language processor

RA75X relocatable assembler

Host machine

Part number

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13RA75X

Ver. 3.30 to

5-inch 2HD

S5A10RA75X

Ver. 6.2

Note

IBM PC/AT

and

Refer to

3.5-inch 2HC

S7B13RA75X

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10RA75X

Device file

Host machine

Part number

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13DF754244

Ver. 3.30 to

5-inch 2HD

S5A10DF754244

Ver. 6,2

Note

IBM PC/AT and

Refer to

3.5-inch 2HC

S7B13DF754244

compatible machines

"OS for IBM PC"

5-inch 2HC

S7B10DF754244

Note

Ver.5.00 or later have the task swap function, but it cannot be used for this software.

Remark Operation of the assembler and device file are guaranteed only on the above host machine and OSs.

PD754144, 754244

Debugging tool

The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the

PD754244.

The system configurations are described as follows.

Hardware

IE-75000-R

Note 1

In-circuit emulator for debugging the hardware and software when developing applica-

tion systems that use the 75X series and 75XL series. When developing the

PD754244, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R

that are sold separately must be used with the IE-75000-R.

By connecting with the host machine, efficient debugging can be made.

It contains the emulation board IE-75000-R-EM which is connected.

IE-75001-R

In-circuit emulator for debugging the hardware and software when developing applica-

tion systems that use the 75X series and 75XL series. When developing the

PD754244, the emulation board IE-75300-R-EM and emulation probe EP-754144GS-R

which are sold separately must be used with the IE-75001-R.

By connecting the host machine, efficient debugging can be made.

IE-75300-R-EM

Emulation board for evaluating the application systems that use the

PD754244.

It must be used with the IE-75000-R or IE-75001-R.

EP-754144GS-R

Emulation probe for the

PD754244GS.

It must be connected to IE-75000-R (or IE-75001-R) and IE-75300-R-EM.

It is supplied with the flexible boards EV-9500GS-20 (supporting 20-pin plastic shrink

EV-9500GS-20

SOPs) and EV-9501GS-20 (supporting 20-pin plastic SOPs) which facillitate connection

EV-950IGS-20

to a target system.

Software

IE control program

Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix

I/F and controls the above hardware on a host machine.

Host machine

Part No.

Distribution media

(product name)

PC-9800 series

MS-DOS

3.5-inch 2HD

S5A13IE75X

Ver. 3.30 to

5-inch 2HD

S5A10IE75X

Ver. 6.2

Note 2

IBM PC/AT and its

Refer to

3.5-inch 2HC

S7B13IE75X

compatible machine

"OS for IBM PC"

5-inch 2HC

S7B10IE75X

Notes 1.

Maintenance parts

Ver.5.00 or later have the task swap function, but it cannot be used for this software.

Remark Operation of the IE control program is guaranteed only on the above host machines and OSs.

PD754144, 754244

APPENDIX C. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Device related documents

Document Name

Document Number

Japanese

English

PD754144, 754244 Data Sheet

U10040J

This document

PD754144, 754244 User's Manual

U10676J

U10676E

75XL Series Selection Guide

U10453J

U10453E

Development tool related documents

Document Name

Document Number

Japanese

English

Hardware

IE-75000-R/IE-75001-R User's Manual

EEU-846

EEU-1416

IE-75300-R-EM User's Manual

U11354J

U11354E

EP-754144GS-R User's Manual

U10695J

U10695E

Software

RA75X Assembler Package User's Manual

Operation

EEU-731

EEU-1346

Language

EEU-730

EEU-1363

Other related documents

Document Name

Document Number

Japanese

English

IC Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

Quality Grades on NEC Semiconductor Devices

C11531J

C11531E

NEC Semiconductor Device Reliability/Quality Control System

C10983J

C10983E

Static Electricity Discharge (ESD) Test

MEM-539

Guide to Quality Assurance for Semiconductor Devices

C11893J

MEI-1202

Microcomputer Related Product Guide - Other Manufacturers

U11416J

Caution These documents are subject to change without notice. Be sure to read the latest documents.

PD754144, 754244

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools includ-

ing work bench and floor should be grounded. The operator should be

grounded using wrist strap. Semiconductor devices must not be touched with

bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry.

Each unused pin should be connected to V

or GND with a resistor, if it is

considered to have a possibility of being an output pin. All handling related

to the unused pins must be judged device by device and related specifications

governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immedi-

ately after power-on for devices having reset function.

PD754144, 754244

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J98. 2

PD754144, 754244

[MEMO]

EEPROM is a trademark of NEC Corporation.

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in

the United States and/or other countries.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines

Corporation.

The

PD754244 is manufactured and sold based on a licence contract with CP8 Transac regarding the

EEPROM microcomputer patent.

This product cannot be used for an IC card (SMART CARD).

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

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