The mark 5 shows major revised points.

DESCRIPTION

The

PD75512(A) is a 4-bit single-chip microcomputer which employs 75X series architecture, and its

performance is comparable to that of an 8-bit microcomputer.

In addition to its high-speed processing capabilities, the

PD75512(A) is also capable of processing data in

units of 1, 4, or in 8-bits. With its internally provided A/D converter and serial interface, the

PD75512(A) provides

the highest performance in its class.

Detailed functions are described in the following user`s manual. Be sure to read it for designing.

PD75516 User`s Maual: IEM-5049

FEATURES

Higher reliability than

PD75512

Adequate I/O lines: 64

(can be provided with pull-up/pull-down resistors: 47)

Built-in 8-bit serial interface: 2-ch

NEC standard serial bus interface (SBI) internally provided

Built-in 8-bit A/D converter: 8-ch

Variable instruction execution time function which is convenient for high-speed operation and power saving

· 0.95

s/1.95

s/15.3

s (at 4.19 MHz operation),

· 122

s (at 32.768 kHz operation)

Program memory (ROM) size: 12,160

8 bits

Data memory (RAM) size: 512

4 bits

High-performance timer function: 4-ch

· 8-bit timer/event counter

· Watch timer

· 8-bit basic interval timer

· Timer/pulse generator: Capable of outputting 14-bit PWM

Clock operation for reduced power consumption possible

A TYP. at 3 V operation)

PROM version (

PD75P516) available

APPLICATIONS

Switable for automotive and transportation equipments, etc.

NEC Corporation 1991

Document No.

IC-2815A

(O. D. No.

IC-8265A)

Date Published

January 1994 P

Printed in Japan

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75512(A)

The information in this document is subject to change without notice.

4-BIT SINGLE-CHIP MICROCOMPUTER

PD75512(A)

PD75512(A) FUNCTIONS

Item

Function

Internal

ROM

12160

8 bits

Memory
Size

RAM

512

4 bits

Genearl-Purpose Register

(4 bits

8 or 8 bits

4 banks

Instruction Cycle

· 0.95

s/1.91

s/15.3

s (Main system clock: at 4.19 MHz)

· 122

s (Subsystem clock: at 32.768 kHz)

Total

64 lines

CMOS Inputs

16 lines (also serve as INT, SIO, PPO, analog input; can be pulled up by software: 7
lines)

Input/
Output

CMOS

28 lines

Ports

Input/Outputs

· Can be pulled up by software: 16 lines
· Can be pulled down by mask option: 4 lines

N-ch Open-Drain

20 lines (10 V withstand voltage; pins that can be pulled up by mask option: 20)

Input/Outputs

A/D Converter

8-bit resolution

8 channels (successive approxmation type)

· Operation voltage: V

= 3.5 to 6.0 V

· Timer/event counter
· Basic interval timer
· Timer/pulse generator (capable of outputting 14-bit PWM)
· Watch timer

· NEC standard serial bus interface (SBI)/3-line SIO: 1 channel
· Normal clock synchronized serial interface (3-line SIO): 1 channel

Vector Interrupt

External: 3, Internal: 4

Test Input

External: 1, Internal: 1

· Bit data set/reset/test/boolean operation instruction

Instruction Set

· 4-bit data transfer/operation/increment/decrement /compare instructions
· 8-bit data transfer/operation/increment/decrement /compare instructions

· Ceramic/crystal oscillator for main system clock: 4.19 MHz
· Crystal oscillator for subsystem clock: 32.768 kHz

Operation Voltage

= 2.7 V to 6.0 V

Package

80-pin plastic QFP (14

20mm)

System Clock Generator

Timer/Counter

4 channels

Serial Interface

2 channels

PD75512(A)

CONTENTS

PIN CONFIGURATION .....................................................................................................................

INTERNAL BLOCK DIAGRAM .........................................................................................................

PIN FUNCTIONS ..............................................................................................................................

3.1

PORT PINS .............................................................................................................................................

3.2

NON-PORT PINS ...................................................................................................................................

3.3

PIN INPUT/OUTPUT CIRCUITS ............................................................................................................

3.4

RECOMMENDED CONDITIONS FOR UNUSED PINS ..........................................................................

3.5

MASK OPTION SELECTION .................................................................................................................

MEMORY CONFIGURATION ..........................................................................................................

PERIPHERAL HARDWARE FUNCTIONS ........................................................................................

5.1

PORT ......................................................................................................................................................

5.2

CLOCK GENERATOR CIRCUIT .............................................................................................................

5.3

CLOCK OUTPUT CIRCUIT .....................................................................................................................

5.4

BASIC INTERVAL TIMER ......................................................................................................................

5.5

WATCH TIMER ......................................................................................................................................

5.6

TIMER/EVENT COUNTER .....................................................................................................................

5.7

TIMER/PULSE GENERATOR .................................................................................................................

5.8

SERIAL INTERFACE ...............................................................................................................................

5.9

A/D CONVERTER ...................................................................................................................................

5.10

BIT SEQUENTIAL BUFFER ...................................................................................................................

INTERRUPT FUNCTIONS ................................................................................................................

STANDBY FUNCTIONS ...................................................................................................................

RESET FUNCTIONS .........................................................................................................................

INSTRUCTION SET ..........................................................................................................................

10. ELECTRICAL SPECIFICATIONS .......................................................................................................

11. PACKAGE DRAWINGS ....................................................................................................................

12. RECOMMENDED SOLDERING CONDITIONS ................................................................................

PD75512(A)

PIN CONFIGURATION

IC: Internally Connected (Connect directly to V

)

*: Power must be supplied to both V

pins.

AN0

PD75512GF(A)

3B9

×××

AN4/P150

P120

AN1

25 26

P93

27 28 29 30 31 32 33 34 35 36 37 38 39 40

AN2

AN3

AN5/P151

AN6/P152

AN7/P153

P121

P122

P123

P130

P131

P132

P133

REF

P113

P112

P111

P110

P103

P102

P101

P100

P92

P91

P90

SI1/P83

SO1/P82

SCK1/P81

PPO/P80

KR7/P73

KR6/P72

KR5/P71

KR4/P70

KR3/P63

KR2/P62

KR1/P61

KR0/P60

P53

P52

P51

P50

P43

P42

P41

P40

P33

P32

P31

P140

P141

P142

P143

RESET

XT2

XT1

P00/INT4

P01/SCK0

P02/SO0/SB0

P03/SI0/SB1

P10/INT0

P11/INT1

P12/INT2

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

PD75512(A)

INTERNAL BLOCK DIAGRAM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 8

PORT 9

PORT10

PORT11

PORT12

PORT13

PORT14

PORT15

P10-P13

P00-P03

P20-P23

P30-P33

P40-P43*

P50-P53*

P60-P63

P70-P73

P80-P83

P90-P93

P100-P103

P110-P113

P120-P123*

P130-P133*

P140-P143*

P150-P153

SP (8)

BANK

GENERAL REG.

ALU

PROGRAM

COUNTER (14)

ROM

PROGRAM

MEMORY

12160

8 BITS

DECODE

AND

CONTROL

RAM

DATA MEMORY

512 x 4 BITS

TI0/P13

TIMER/EVENT

COUNTER

INTT0

PTO0/P20

BUZ/P23

WATCH
TIMER

INTW

INTCSI

SERIAL

INTERFACE0

SI0/SB1/P03

SO0/SB0/P02

SCK0/P01

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0/P60

KR7/P73

INTERRUPT

CONTROL

BIT SEQ.

BUFFER (16)

BASIC
INTERVAL
TIMER

INTBT

PPO/P80

TIMER/PULSE
GENERATOR

INTTPG

SERIAL

INTERFACE1

SI1/P83

SO1/P82

SCK1/P81

A/D

CONVERTER

REF

AN0-AN3

AN4/P150-AN7/P15

f /2

RESET

PCL/P22

XT1

XT2 X1

SUB

MAIN

CLOCK
OUTPUT
CONTROL

CLOCK
DIVIDER

CLOCK
GENERATOR

STAND BY
CONTROL

CPU CLOCK

*: PORTs 4, 5, and 12 to 14 are 10 V middle voltage, N-ch open-drain input/output ports.

PD75512(A)

3. PIN FUNCTIONS

3.1 PORT PINS (1/2)

Input/

Shared

Function

8-bit

When Reset

Output

Name

Output

I/O

Circuit
Type*

P00

INT4

4-bit input port (PORT0).

For P01 to P03, built-in pull-up

P01

SCK0

resistors can be specified in 3-bit

F -A

Input

units by software.

Input

P02

SO0/SB0

F -B

P03

SI0/SB1

M -C

P10

INT0

With noise
elimination function

P11

INT1

Input

4-bit input port (PORT1).

Input

B -C

P12

INT2

Built-in pull-up resistors can be
specified by software in 4-bit units.

P13

TI0

P20

PTO0

4-bit input/output port (PORT2).

P21

Input/

Built-in pull-up resistors can be

output

specified by software in 4-bit units.

Input

E-B

P22

PCL

P23

BUZ

P30

Programmable 4-bit input/output
port (PORT3).

P31

Input/

Input/output can be specified in

output

bit units.

Input

E-C

P32

Built-in pull-up resistors can be
specified by software in 4-bit unit.

P33

N-ch open-drain 4-bit input/output

High level

port (PORT4).

(when pull-up

P40 to

Input/

A pull-up resistor can be provided

resistor is

P43

output

in bit units (mask option).

provided) or

10V withstanding voltage in the

high impedance

open-drain mode.

N-ch open-drain 4-bit input/output

High level

port (PORT5).

(when pull-up

P50 to

Input/

A pull-up resistor can be provided

resistor is

P53

output

in bit units (mask option).

provided) or

10V withstanding voltage in the

high impedance

open-drain mode.

P60

KR0

Programmable 4-bit input/ output
port (PORT6).

P61

Input/

KR1

Input/output can be specified in

output

bit units.

Input

F -C

P62

KR2

Built-in pull-up resistors can be
specified by software in 4-bit units.

P63

KR3

*: The number enclosed with a circle indicates Schmitt trigger input.

PD75512(A)

3.1 PORT PINS (2/2)

Input/

Shared

Function

8-bit

When Reset

Output

Name

Output

I/O

Circuit
Type*

P70

KR4

4-bit input/output port (PORT7).

P71

Input/

KR5

Built-in pull-up resistor can be

output

specified in 4-bit units by software.

Input

F -A

P72

KR6

P73

KR7

P80

PPO

P81

SCK1

Input

4-bit input port (PORT8).

Input

P82

SO1

P83

SI1

Low level

4-bit input/output port (PORT9).

(when pull-

P90 to

Input/

Built-in pull-up resistors can be

down resistor

P93

output

specified in bit units by mask

is provided)

option.

or high
impedance

P100 to

Input/

4-bit input/output port (PORT10).

Input

P103

output

P110 to

Input/

4-bit input/output port (PORT11).

Input

P113

output

N-ch open-drain 4-bit input/output

High level

port (PORT12).

(when pull-up

P120 to

Input/

A pull-up resistor can be provided

resistor is

P123

output

in bit units (mask option).

provided) or

10V withstanding voltage in the

high impedance

open-drain mode.

N-ch open-drain 4-bit input/output

High level

port (PORT13).

(when pull-up

P130 to

Input/

A pull-up resistor can be provided

resistor is

P133

output

in bit units (mask option).

provided) or

10V withstanding voltage in the

high impedance

open-drain mode.

N-ch open-drain 4-bit input/output

High level

port (PORT14).

(when pull-up

P140 to

Input/

A pull-up resistor can be provided

resistor is

P143

output

in bit units (mask option).

provided) or

10V withstanding voltage in the

high impedance

open-drain mode.

P150 to

Input

AN4 to AN7

4-bit input port (PORT15).

Input

Y-A

P153

*: The number enclosed with a circle indicates Schmitt trigger input.

PD75512(A)

3.2 NON-PORT PINS

Input/

Shared

Function

When Reset

Output

Name

Output

Circuit
Type*

TI0

Input

P13

The external event pulse input for the timer/event

B -C

counter.

PTO0

Output

P20

Timer/event counter output

Input

E-B

PCL

Output

P22

Clock output

Input

E-B

BUZ

Output

P23

Fixed frequency output (for buzzer output or

Input

E-B

system clock trimming)

SCK0

Input/

P01

Serial clock input/output

Input

F -A

output

SO0/SB0

Input/

P02

Serial data output

Input

F -B

output

Serial bus input/output

SI0/SB1

Input/

P03

Serial data input

Input

M -C

output

Serial bus input/output

INT4

Input

P00

Edge detection vector interrupt input (both rising

edge and falling edge detection)

INT0

P10

Edge detection vector

Synchronized

interrupt input

with clock

Input

(detection edge selectable)

B -C

INT1

P11

Asynchronous

INT2

Input

P12

Edge detection testable input

Asynchronous

B -C

(rising edge detection)

KR0-KR3

Input

P60-P63

Parallel falling edge detection testable input

Input

F -C

KR4-KR7

Input

P70-P73

Parallel falling edge detection testable input

Input

F -A

SCK1

Input/

P81

Serial clock input/output

Input

output

SO1

Output

P82

Serial data output

Input

SI1

Input

P83

Serial data input

Input

AN0-AN3

Input

A/D converter analog input

AN4-AN7

P150-P153

Y-A

REF

Input

A/C converter reference voltage input

A/D converter reference ground

Pins for connecting the crystal ceramic oscillator
to the main system clock generator. When

X1, X2

Input

inputting the external clock, input the external

clock to pin X1, and the reverse phase of the
external clock to pin X2.

XT1

Input

Pins for connecting the crystal oscillator to the

subsystem clock generator. When the external

clock is used, inputs the external clock to pin
XT1. In this case, pin XT2 must be left open.

RESET

Input

System reset input

PPO

Output

P80

Timer/pulse generator pulse output

Input

Internally Connected. Connect directly to V

Positive power supply

GND

*: The number enclosed with a circle indicates Schmidt trigger input.

XT2

PD75512(A)

3.3

PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the

PD75512(A).

TYPE A

TYPE D

TYPE B

TYPE E

Input buffer of CMOS standard

data

output
disable

OUT

Pch

Nch

Push-pull output that can be set in a output
high-impedance state (both P-ch and N-ch are off)

Schmitt trigger input with hysteresis characteristics

data

output
disable

Type D

Type A

IN/OUT

This input/output circuit consists of D-type push-pull
outputs and Type A input buffers.

P.U.R.
enable

P.U.R.

Pch

TYPE BC

TYPE E

data

output
disable

Type D

Type A

P.U.R.
enable

P.U.R.

Pch

IN/OUT

Schmitt trigger input with hysteresis characteristics

P.U.R. : Pull-Up Resistor

Pch

Nch

Fig. 3-1 Pin Input/Output Circuits (1/3)

PD75512(A)

Type E-C

data

output
disable

Type D

Type A

P.U.R.
enable

P.U.R.

Pch

IN/OUT

Type F-B

data

output
disable

P.U.R.
enable

P.U.R.

Pch

N-ch

P-ch

output
disable

(P-ch)

output
disable

(N-ch)

IN/OUT

Type B

Type F

Type F-C

data

output
disable

Type D

Type B

P.U.R.
enable

P.U.R.

Pch

IN/OUT

data

output
disable

Type D

Type B

IN/OUT

This input/output circuit consists of D-type push-pull
outputs and Type B Schmitt trigger inputs.

Type F-A

Type M

data

output
disable

P.U.R.

IN/OUT

N-ch

Middle-voltage input buffer
(can withstand up to +10 V)

data

output
disable

Type D

Type B

P.U.R.
enable

P.U.R.

Pch

IN/OUT

(can withstand
up to +10 V)

P.U.R. : Pull-Up Resistor

(Mask Option)

Fig. 3-1 Pin Input/Output Circuits (2/3)

PD75512(A)

3.5 MASK OPTION SELECTION

The following mask options are provided with the pins.

(1)

Pull-up/pull-down resistor selection

Table 3-2 Pull-up/Pull-down Resistor Selection

Pins

Mask Option

P40-P43

(1) With pull-up resistor

(2) Without pull-up resistor

P50-P53

(Can be specified in bit units)

P120-P123

P130-P133

P140-P143

P90-P93

(1) With pull-down resistor

(2) Without pull-down resistor

(Can be specified in bit units)

(2)

Feedback resistor selection for the subsystem clock oscillation

Table 3-3 Feedback Resistor Selection

Pins

Mask Option

XT1, XT2

(1) With feedback resistor

(2) Without feedback resistor

(When the subsystem clock

is used)

is not used)

Note:

The operation is not affected if the feedback resistor is selected when the subsystem

clock is not used. However, the supply current I

is increased.

PD75512(A)

MBE

Internal reset start address (upper 6 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 6 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 6 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 6 bits)

INT1 start address (lower 8 bits)

INTCSIO0 start address (upper 6 bits)

INTCSIO0 start address (lower 8 bits)

INTT0 start address (upper 6 bits)

INTT0 start address (lower 8 bits)

0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH
0080H

007FH
0800H

0FFFH
1000H

1FFFH

GETI instruction reference table

CALLF

!faddr

instruction

entry

address

Address

2000H

2F7FH

BRCB

!caddr

instruction

branch

address

BRCB

!caddr

instruction

branch

address

RBE

MBE

INTTPG start address (upper 6 bits)

000CH

RBE

INTTPG start address (lower 8 bits)

BR !addr

instruction

branch address

CALL !addr

instruction
subroutine

entry address

BR $addr

instruction

relational

branch address

(15 to 1,
+2 to +16)

Branch destination

address and

subroutine entry

address for

GETI instruction

BRCB

!caddr

instruction

branch

address

Remarks:

In addition to the above, branching to an address, for which only the lower 8 bits of the PC are

modified, is possible by the BR PCDE and BR PCXA instructions.

Fig. 4-1 Program Memory Map

PD75512(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORT

I/O ports are classified into following kinds:

CMOS input (PORTS 0, 1, 8, 15)

: 16

CMOS input/output (PORTS 2, 3, 6, 7, 9, 10, 11)

: 28

N-ch open-drain input/output (PORTS 4, 5, 12, 13, 14)

: 20

Total

: 64

Table 5-1 Port Functions

Port

Function

Operation/Feature

Remarks

(Pin Name)

Also serves as the INT4, SCK0 ,

Can be read or tested regardless of the operation

SO0/SB0, and SI0/SB1 pins

4-bit input

mode of the shared pin.

Also serves as INT0 to 2, and
TIO pins

Can be specified for I/O in 4-bit units

Also serves as PTO0, PCL and

4-bit I/O

BUZ pins.

Can be specified for I/O in 1/4-bit units.

4-bit I/O

Whether or not the internal

(N-ch

Can be specifiedfor

pull-up resistor is provided

open-drain,

I/O in 4-bit units

can be specified for each bit

can sustain

by mask option

with 10V)

Can be specified
for I/O in 1/4-bit units

Ports 6 and 7 can

Also serves as KR0-3.

4-bit I/O

be paired to I/O

Can be specified

data in 8-bit units

I/O in 4-bit

Also serves as KR4-7.

units

4-bit

Can be read or tested regardless of the operation

Also serves as PPO, SCK1,

input

mode of the shared pin.

SO1, and SI1 pins.

Whether or not the internal
pull-up resistor is provided
can be specified for each bit
by mask option.

PORT10

4-bit I/O

Can be specified for I/O in 4-bit units.

PORT11

PORT12

4-bit I/O

Whether or not the internal

(N-ch

pull-up resistor is provided

PORT13

open-drain,

Can be specified for I/O in 4-bit units.

can be specified for each

can sustain

bit by mask option.

PORT14

with 10V)

PORT15

4-bit

Can be read or tested regardless of the operation

Also serves as AN4-7 pins.

Input

mode of the shared pins

PORT9

4-bit I/O

Can be specified for I/O in 4-bit units.

PORT8

PORT0

PORT1

PORT2

PORT4

PORT3

PORT5

PORT7

PORT6

Ports 4 and 5 can
be paired to I/O
data in 8-bit units

PD75512(A)

6.2

CLOCK GENERATOR CIRCUIT

The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and

system clock control register (SCC).

This circuit can generate two types of clocks: main system clock and subsystem clock.

In addition, it can also change the instruction execution time.

0.95

s, 1.91

s, 15.3

s (main system clock: 4.19 MHz)

122

s (subsystem clock: 32.768 kHz)

*: instruction execution.

Remarks 1: f

= Main system clock frequency

2: f

= Subsystem clock frequency

CPU clock

4: PCC: Processor clock control register

5: SCC: System clock control register

6: One clock cycle (t

) of

is one machine cycle of an instruction. For t

, refer to AC

characteristics in 10. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

XT1

XT2

Watch timer

Subsystem

clock

oscillator

Main system

clock

oscillator

1/2 1/16

1/8 to 1/4096

Frequency divider

· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· Clock output circuit
· A/D converter
· INT0 noise rejecter circuit

Internal bus

WM.3

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

HALT*

STOP*

PCC2, PCC3

clear signal

STOP F/F

HALT F/F

Oscillator

disable

signal

Frequency

divider

1/4

Selector

· CPU
· Clock output
circuit
· INT0 noise
rejecter circuit

Wait release
signal from BT

RESET signal

Standby release
signal from interrupt
control circuit

Timer/pulse
generator

Selector

PD75512(A)

5.5

WATCH TIMER

The

PD75512(A) has a built-in 1-ch watch timer. The watch timer has these functions.

Sets the test flag (IRQW) with 0.5 sec interval.

The standby mode can be released by IRQW.

0.5 second interval can be generated either from the main system clock or subsystem clock.

Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient

for program debugging, test, etc.

Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock

frequency trimming.

The frequency divider circuit can be cleared so that zero second watch start is possible.

WM7

WM2 WM1 WM0

Selector

Frequency divider

(256 Hz: 3.91 ms)

INTW
(IRQW
set signal)

(2 Hz
0.5 sec)

Selector

(32.768
kHz)

(2.048
kHz)

Clear

128
(32.768 kHz)

(32.768 kHz)

From the
clock
generator

PORT2.3

Bit 2 of PMGB

Output buffer

P23/BUZ

P23
output
latch

Port 2
input/output
mode

Bit test
instruction

Internal bus

Remarks: ( ) is for f

= 4.194304 MHz, f

= 32.768 kHz.

Fig. 5-4 Watch Timer Block Diagram

5.6

TIMER/EVENT COUNTER

The

PD75512(A) has a built-in 1-ch timer/event counter. The timer/event counter has these functions:

Programmable interval timer operation

Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.

Event counter operation

Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).

Supplies serial shift clock to the serial interface circuit.

Count condition read out function

PD75512(A)

5.7 TIMER/PULSE GENERATOR

The

PD75512(A) contains a timer/pulse generator, that can be used as the timer or the pulse generator. Timer/

pulse generator has the following functions.

(a)

Function, when used in the timer mode

· 8-bit interval timer operation (IRQTPG generation), for which the clock source can be changed in 5

steps.

· Square waveform output to the PPO pin

(b)

Function, when used in the PWM pulse generation mode

· 14-bit accuracy PWM pulse output to PPO pin (can be used as a D/A converter for electronics tuning).

· Fixed time interval interrupt generation (2

= 7.81ms: f

= 4.19 MHz)

When no pulse output is required, the PPO pin can be used as 1-bit output port.

Note:

When setting the STOP mode, if the timer pulse generator is in operating mode, erroneous operation

may occur. Therefore, the timer/pulse generator must be set in no-operation state by the mode

Internal bus

TPGM3
(Set to 1 )

MODH

Modulo register L (8)

Modulo register H (8)

Frequency
divider

1/2

TPGM1

Prescaler select latch (5)

Clear

Count register (8)

Comparator (8)

T F/F

Set

Coincidence

Modulo latch H (8)

TPGM4 TPGM5 TPGM7

PPO

Output buffer

INTTPG
(IRQTPG
set signal)

Selector

MODL

Fig. 5-6 Timer/Pulse Generator Block Diagram (Timer Mode)

PD75512(A)

Internal bus

Modulo register H (8)

MODL

MODH

Modulo register L (8)

TPGM3

TPGM1

1/2

Frequency divider

MODH(8)

MODL (6)

7-2

Modulo latch (14)

PWM pulse generator

IRQTPG set signal

( = 7.8 ms: f at 4.19MHz)

INTTPG

TPGM5

TPGM7

Selector

Output buffer

PPO

Fig. 5-7 Timer/Pulse Generator Block Diagram (PWM Pulse Generation Mode)

5.8 SERIAL INTERFACE

The

PD75512(A) is provided with two serial interface channels. Table 5-2 indicates differences between channel

0 and channel 1.

Table 5-2 Differences Between Channel 0 and Channel 1

Serial Transfer Mode, Funciton

Channel 0

Channel 1

Clock Selection

, f

, TOUT F/F, external clock

, f

external clock

3-Line

Transfer Method

MSB first/LSB first selectable

MSB first

Serial I/O

Transfer Completion

Serial transfer completion interrupt

Serial transfer completion flag (EOT)

Flag

request flag (IRQCSI0)

2-Line Serial I/O

Usable

Unprovided

Serial Bus Interface (SBI)

(1)

Serial interface function (Channel 0)

The

PD75512(A) is equipped with the following four modes:

· Operation stop mode

· Three-line serial I/O mode

· Two-line serial I/O mode

· SBI mode (serial bus interface mode)

PD75512(A)

Address bit

Symbol

L register

L = F

L = C L = B

L = 8 L = 7

L = 4 L = 3

L = 0

BSB3

BSB2

BSB1

BSB0

DECS L

INCS L

FC3H

FC2H

FC1H

FC0H

5.10

BIT SEQUENTIAL BUFFER ..... 16 BITS

The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,

addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this

buffer is very useful for processing long data in bit units.

Remarks: For the pmem.@L addressing, the specification bit is shifted according to the L register.

Fig. 5-11 Bit Sequential Buffer Format

6. INTERRUPT FUNCTIONS

The

PD75512(A) has 7 different interrupt sources and multiplexed interrupt with priority order.

In addition to that, the

PD75512 is also provided with two types of test sources, of which INT2 has two types

of edge detection testable inputs.

The interrupt control circuit of the

PD75512(A) has these functions:

Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by

using the interrupt flag (IExxx) and interrupt master enable flag (IME).

The interrupt start address can be arbitrarily set.

Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of

software).

Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).

PD75512(A)

Can operate only when the external
SCK0 input is selected as the serial
clock

Instruction for Setting

STOP instrtuction

HALT instruction

Can be set only when operating on
the main system clock

Can be set when operating either on
the main system clock or the subsys-
tem clock

Item

Mode

STOP Mode

HALT Mode

Clock Oscillator

Only the main system clock can stop
its operation.

Only the CPU clock

stops its

operation. (oscillation continues)

Basic Interval
Timer

Does not operate

Operates (Sets IRQBT with the

reference time interval)

System Clock at the Time of
Setting

Serial Interface
(Channel 0)

Operates when the timer system
clock is operating or external SCK0 is
selected

Serial Interface
(Channel 1)

Can operate only when the external
SCK1 input is selected as the serial
clock

Operates only when the main system
clock is operating

Timer/Event
Counter

Can only operate when the TI0 pin
input is selected as system clock

Operates only when the main system
clock is operating

Clock Timer

Operates when f

is selected as the

count clock

Can operate

A/D Converter

Does not operate

Timer/Pulse
Generator

Operates only when the main system
clock is operating

Does not operate

Operates only when the main system
clock is operating

Release Signal

CPU

Does not operate

Timer/Pulse
Generator

INT1, INT2, and INT4 can operate, but INT0 cannot operate

An interrupt request signal from a piece of hardware, whose operation is
enabled by the interrupt enable flag, or the RESET signal input

Operation
Status

7. STANDBY FUNCTIONS

In order to fully exploit the

PD75512(A) low power dissipation, CPU operation can be stopped by setting the unit

to the standby mode, thus, further reducing power dissipation. The

PD75512(A) features two standby modes, a

STOP mode and a HALT mode.

Table 7-1 Status in Standby Mode

PD75512(A)

8. RESET FUNCTIONS

When the RESET signal is input, the

PD75512(A) is reset and each hardware is initialized as indicated in

Table 8-1. Fig. 8-1 shows the reset operation timing.

RESET input

Wait

(31.3ms/4.19MHz)

Operation mode
or standby mode

HALT mode

Operation mode

Internal reset operation

Fig. 8-1 Reset Operation by RESET Input

Table 8-1 Status of Each Hardware after Reset (1/2)

Hardware

RESET Input in Standby Mode

RESET Input during Operation

Program Counter (PC)

The contents of the lower 6 bits
of address 0000H of the program
memory are set to PC13-8, and
the contents of address 0001H
are set to PC7-0.

Same as left

PSW

Carry Flag (CY)

Retained

Undefined

Skip Flag (SK0-2)

Interrupt Status Flag (IST0, 1)

Bank Enable Flag (MBE, RBE)

The contents of bit 6 of address
0000H of the program memory
are set to RBE and those of bit 7
are set to MBE.

Same as left

Stack Pointer (SP)

Undefined

Data Memory (RAM)

Retained *

Undefined

General-Purpose Register
(X, A, H, L, D, E, B, C)

Retained

Undefined

Bank Selection Register (MBS, RBS)

0, 0

Basic Interval
Timer

Counter (BT)

Undefined

Timer/Event
Counter

Counter (T0)

Modulo Register
(TMOD0)

FFH

Mode Register (TM0)

TOE0, TOUT F/F

0, 0

Mode Register (BTM)

Timer/Pulse
Generator

Modulo Register

Mode Register

Mode Register (WM)

Watch Timer

Retained

*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.

PD75512(A)

Shift Register (SIO0)

Retained

Undefined

Operation Mode

SBI Control Register

(SBIC)

Slave Address Register

Retained

Undefined

(SVA)

P01/SCK0 Output

Latch

A/D Converter Mode Regiseter (ADM),

04H (EOC = 1)

EOC

SA Register

7FH

Clock

Processor Clock Control

Generator,

Clock Output

System Clock Control

Circuit

Clock Output Mode

Serial

Shift Register

Retained

Undefined

Interface

(SIO1)

(Channel 1)

Operation Mode

Serial Transfer End

Flag (EOT)

Interrupt

Interrupt Request Flag

Reset (0)

Function

(IRQxxx)

Interrupt Enable Flag

(IExxx)

Interrupt Master Enable

Flag (IME)

INT0, INT1, INT2 Mode

0, 0, 0

Registers (IM0, 1, 2)

Digital Port

Output Buffer

Off

Output Latch

Clear (0)

Input/Output Mode

Pull-Up Resistor

Specification Register
(POGA)

Bit Sequential Buffer (BSB0-3)

Retained

Undefined

Hardware

RESET Input during Operation

RESET Input in Standby Mode

Table 8-1 Status of Each Hardware after Reset (2/2)

Serial
Interface
(Channel 0)

PD75512(A)

INSTRUCTION SET

(1)

Operand representation and description

Describe one or more operands in the operand field of each instruction according to the operand

representation and description methods of the instruction (for details, refer to RA75X Assembler Package

User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from

several operands. The uppercase characters, +, and are keywords and must be described as is.

Describe an appropriate numeric value or label as immediate data.

Representation

Description

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label*

bit

2-bit immediate data or label

fmem

FB0H to FBFH,FF0H to FFFH immediate data or label

pmem

FC0H to FFFH immediate data or label

addr

0000H to 2F7FH immediate data or label

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H to 7FH immediate data (where bit0 = 0) or label

PORTn

PORT0 to PORT15

IExxx

IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG

RBn

RB0-RB3

MBn

MB0, MB1, MB15

*: Only even addresses can be described in mem when processing

8-bit data.

PD75512(A)

(2)

Legend of operation field

: A register; 4-bit accumulator

: B register; 4-bit accumulator

: C register; 4-bit accumulator

: D register; 4-bit accumulator

: E register; 4-bit accumulator

: H register; 4-bit accumulator

: L register; 4-bit accumulator

: X register; 4-bit accumulator

: Register pair (XA); 8-bit accumulator

: Register pair (BC); 8-bit accumulator

: Register pair (DE); 8-bit accumulator

: Register pair (HL); 8-bit accumulator

XA'

: Expanded register pair (XA')

BC'

: Expanded register pair (BC')

DE'

: Expanded register pair (DE')

HL'

: Expanded register pair (HL')

: Program counter

: Stack pointer

: Carry flag; or bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn : Port n (n = 0 to 15)

IME

: Interrupt mask enable flag

IPS

: Interrupt priority selector register

IExxx

: Interrupt enable flag

RBS

: Memory bank selector register

MBS

: Memory bank selector register

PCC

: Processor clock control register

: Delimiter of address and bit

(xx)

: Contents addressed by xx

xxH

: Hexadecimal data

PD75512(A)

(3)

Symbols in addressing area field

MB = MBE . MBS
(MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (00H-7FH)

Data memory

MB = 15 (80H-FFH)

addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H-FBFH,

FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr = 0000H-2F7FH

addr = (Current PC) 15 to (Current PC) 1

(Current PC) + 2 to (Current PC) + 16

Program

caddr = 0000H-0FFFH (PC

13, 12

= 00B) or

memory

1000H-1F7FH (PC

13, 12

= 01B) or

addressing

2000H-2F7FH (PC

13, 12

= 10B)

faddr = 0000H-07FFH

*10

taddr = 0020H-007FH

Remarks 1:

MB indicates memory bank that can be accessed.

In *2, MB = 0 regardless of MBE and MBS.

In *4 and *5, MB = 15 regardless of MBE and MBS.

*6 to *10 indicate areas that can be addressed.

(4)

Machine cycle field

In this field, S indicates the number of machine cycles required when an instruction having a skip

function skips. The value of S varies as follows:

When no instruction is skipped ·····························································

S = 0

When 1-byte or 2-byte instruction is skipped ······································

S = 1

When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ·······

S = 2

Note : The GETI instruction is skipped in one machine cycle.

One machine cycle equals to one cycle of the CPU clock

, (=t

), and can be changed in three steps

depending on the setting of the processor clock control register (PCC).

PD75512(A)

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

Transfer MOV

A, #n4

String effect A

reg1, #n4

reg1

XA, #n8

String effect A

HL, #n8

String effect B

rp2, #n8

rp2

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A,mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg

reg

XA, rp'

rp'

reg1, A

reg1

rp'1, XA

rp'1

XCH

A, @HL

(HL)

A, @HL+

2+S

(HL), then L

L+1

L = 0

A, @HL

2+S

(HL), then L

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

A, mem

(mem)

XA, mem

(mem)

A, reg1

reg1

XA, rp'

rp'

Table

MOVT

XA, @PCDE

(PC

13-8

+DE)

ROM

Reference

XA, @PCXA

(PC

13-8

+XA)

ROM

PD75512(A)

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

MOV1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

7-2

3-2

.bit(L

1-0

))

CY, @H+mem.

(H+mem

3-0

.bit)

bit

fmem.bit, CY

(fmem.bit)

pmem.@L, CY

(pmem

7-2

3-2

.bit(L

1-0

))

@H+mem.bit,

(H+mem

3-0

.bit)

ADDS

A,#n4

1+S

A+n4

carry

XA,#n8

2+S

XA+n8

carry

A,@HL

1+S

A+(HL)

carry

XA,rp'

2+S

XA+rp'

carry

rp'1,XA

2+S

rp'1

rp'1+XA

carry

ADDC

A,@HL

A,CY

A+(HL)+CY

XA,rp'

XA,CY

XA+rp'+CY

rp'1,XA

rp'1,CY

rp'1+XA+CY

SUBS

A,@HL

1+S

A-(HL)

borrow

XA,rp'

2+S

XA-rp'

borrow

rp'1,XA

2+S

rp'1

rp'1-XA

borrow

SUBC

A,@HL

A,CY

A-(HL)-CY

XA,rp'

XA,CY

XA-rp'-CY

rp'1,XA

rp'1,CY

rp'1-XA-CY

AND

A,#n4

A,@HL

(HL)

XA,rp'

XA-rp'

rp'1,XA

rp'1

A,#n4

A,@HL

(HL)

XA,rp'

rp'

rp'1,XA

rp'1

XOR

A,#n4

A,@HL

(HL)

XA,rp'

rp'

rp'1,XA

rp'1

Bit

Transfer

Arithme-

tic

Opera-

tion

PD75512(A)

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

RORC

, A

CY, A

n-1

NOT

Incre-

INCS

reg

1+S

reg

reg+1

reg = 0

ment/

rp1

1+S

rp1

rp1+1

rp1 = 00H

Decre-

@HL

2+S

(HL)

(HL)+1

(HL) = 0

ment

mem

2+S

(mem)

(mem)+1

(mem) = 0

DECS

reg

1+S

reg

reg-1

reg = FH

rp'

2+S

rp'

rp'-1

rp' = FFH

Compari- SKE

reg,#n4

2+S

Skip if reg = n4

reg = n4

son

@HL,#n4

2+S

Skip if (HL) = n4

(HL) = n4

A,@HL

1+S

Skip if A = (HL)

A = (HL)

XA,@HL

2+S

Skip if XA = (HL)

XA = (HL)

A,reg

2+S

Skip if A = reg

A = reg

XA,rp'

2+S

Skip if XA = rp'

XA = rp'

SET1

CLR1

SKT

1+S

Skip if CY = 1

CY = 1

NOT1

Carry

Flag

Manipu-

lation

Accumu-

lator

Manipu-

lation

PD75512(A)

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

Memory/ SET1

mem.bit

(mem.bit)

Bit

fmem.bit

(fmem.bit)

Manipu-

pmem.@L

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

lation

@H+mem.bit

(H + mem

3-0

.bit)

CLR1

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

7-2

+ L

3-2

.bit(L

1-0

))

@H+mem.bit

(H+mem

3-0

.bit)

SKT

mem.bit

2+S

Skip if (mem.bit) = 1

(mem.bit) = 1

fmem.bit

2+S

Skip if (fmem.bit) = 1

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit (L

1-0

)) = 1

(pmem.@L) = 1

@H+mem.bit

2+S

Skip if (H + mem

3-0

.bit) = 1

(@H+mem.bit) = 1

SKF

mem.bit

2+S

Skip if (mem.bit) = 0

(mem.bit) = 0

fmem.bit

2+S

Skip if (fmem.bit) = 0

(fmem.bit) = 0

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit (L

1-0

)) = 0

(pmem.@L) = 0

@H+mem.bit

2+S

Skip if (H + mem

3-0

.bit) = 0

(@H+mem.bit) = 0

SKTCLR fmem.bit

2+S

Skip if (fmem.bit) = 1 and clear

(fmem.bit) = 1

pmem.@L

2+S

Skip if (pmem

7-2

3-2

.bit

(pmem.@L) = 1

1-0

)) = 1 and clear

@H+mem.bit

2+S

Skip if (H+mem

3-0

.bit) = 1 and clear

(@H+mem.bit) = 1

AND1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

bit(L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

OR1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

.bit (L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

XOR1

CY,fmem.bit

(fmem.bit)

CY,pmem.@L

(pmem

7-2

3-2

.bit (L

1-0

))

CY,@H+mem.bit

(H+mem

3-0

.bit)

Branch

addr

13-0

addr

(The most suitable instruction
is selectable from among BR
!addr, BRCB !caddr, and BR
$addr depending on the
assembler.)

!addr

13-0

addr

$addr

13-0

addr

BRCB

!caddr

13-0

13,12

+caddr

11-0

PCDE

13-0

13-8

+DE

PCXA

13-0

13-8

+XA

PD75512(A)

Ma-

Ad-

Instruc-

Mne-

Operand

Bytes

chine

Operation

dress-

Skip

tions

monics

Cyc-

ing

Conditions

les

Area

CALL

!addr

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, PC

13,12

13-0

addr, SP

SP-4

CALLF

!faddr

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, PC

13,12

13-0

00, faddr, SP

SP-4

RET

MBE, RBE, PC

13,12

(SP+1)

11-0

(SP)(SP+3)(SP+2)

SP+4

RETS

3+S

MBE, RBE, PC

13,12

(SP+1)

Undefined

11-0

(SP)(SP+3)(SP+2)

SP+4, then skip unconditionally

RETI

13,12

(SP+1)

11-0

(SP)(SP+3)(SP+2)

PSW

(SP+4)(SP+5), SP

SP+6

PUSH

(SP-1)(SP-2)

rp, SP

SP-2

(SP-1)

MBS, (SP-2)

RBS, SP

SP-2

POP

(SP+1)(SP), SP

SP+2

MBS

(SP+1), RBS

(SP), SP

SP+2

Inter-

IME (IPS.3)

rupt

IExxx

Control

IME (IPS.3)

IExxx

I/O

A,PORTn

PORT

(n = 0-15)

XA,PORTn

PORT

n+1

,PORT

(n = 4, 6)

OUT *

PORTn,A

PORT

(n = 2-7, 9-14)

PORTn,XA

PORT

n+1

,PORT

(n = 4, 6)

CPU

HALT

Set HALT Mode (PCC.2

Control

STOP

Set STOP Mode (PCC.3

NOP

No Operation

Special

SEL

RBn

RBS

(n = 0-3)

MBn

MBS

(n = 0, 1, 15)

GETI *

taddr

. Where TBR instruction,

*10

13-0

(taddr)

4-0

+(taddr+1)

. Where TCALL instruction,

(SP-4)(SP-1)(SP-2)

11-0

(SP-3)

MBE, RBE, PC

13,12

13-0

(taddr)

5-0

+(taddr+1)

SP-4

. Except for TBR and TCALL

Depends on

instructions,

referenced

Instruction execution of

instruction

(taddr)(taddr+1)

*1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.

*2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of

GETI instruction.

Subrou-

tine/
Stack

Control

.........................................................

.............................

.........................................................

.............................

PD75512(A)

10. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply Voltage

-0.3 to +7.0

Other than ports 4, 5, 12-14

-0.3 to V

+0.3

Input Voltage

Ports 4, 5, 12-14

w/pull-up

-0.3 to V

+0.3

resistor

Open drain

-0.3 to +11

Output Voltage

-0.3 to V

+0.3

High-Level Output

1 pin

Peak

-10

Current

rms

-5

All pins

Peak

-30

rms

-15

Low-Level Output

1 pin

Peak

Current

rms

Total of ports 0, 2, 3, 4

Peak

100

rms

Total of ports 5-11

Peak

100

rms

Total of ports 12-14

Peak

rms

Operating Temperature

opt

-40 to +85

Storage Temperature

stg

-65 to +150

*: rms = Peak value x

Duty

OPERATING SUPPLY VOLTAGE

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

A/D Converter

Supply voltage

3.5

6.0

Ambient temperature

-40

+85

Timer/Pulse

Supply voltage

4.5

6.0

Generator

Ambient temperatuare

-40

+85

Other Circuits

Supply voltage

2.7

6.0

Ambient temperatuare

-40

+85

CAPACITANCE (T

= 25

C, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Capacitance

f = 1 MHz

Output Capacitance

Pins other than thosemeasured are at 0 V

Input/Output

Capacitance

PD75512(A)

MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

= -40 to +85

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation

= osccillation

1.0

5.0

MHz

frequency(f

voltage range

Oscillation stabiliza- After V

came to

tion time*

MIN. value of
oscillation voltage

range

Crystal

Oscillation

1.0

4.19

5.0

MHz

frequency (f

Oscillation stabiliza- V

= 4.5 to 6.0 V

tion time*

External Clock

X1 input frequency

1.0

5.0

MHz

X1 input high-,
low-level widths
(t

, t

)

100

500

SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

= -40 to +85

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Crystal

Oscillation*

32.768

kHz

frequency (f

)

Oscillation stabiliza- V

= 4.5 to 6.0 V

1.0

tion time*

External Clock

XT1 input frequency

100

kHz

XT1 input high-,
low-level widths

XTH

, t

XTL

)

*1: Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to AC

Characteristics.

2: Time required for oscillation to stabilize after V

reaches the minimum value of the oscillation voltage

range or the STOP mode has been released.

3: When the oscillation frequency is 4.19 MHz

5.0 MHz, do not select PCC = 0011 as the instruction

execution time: otherwise, one machine cycle is set to less than 0.95

s, falling short of the rated

minimum value of 0.95

PD74HCU04

XT1

XT2

XT1

XT2

Open

PD75512(A)

Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion

enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity:

· Keep the wiring length as short as possible.

· Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines

through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillator circuit at the same potential as V

Do not connect the ground pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the

current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more

easily than the main system clock oscillation circuit. When using the subsystem clock, therefore,

exercise utmost care in wiring the circuit.

PD75512(A)

DC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

High-Level Input

IH1

Ports 2, 3, 9-11, P80, P82

0.7V

Voltage

IH2

Ports 0, 1, 6, 7, 15, P81, P83, RESET

0.8V

IH3

Ports 4, 5, 12-14

w/pull-up resistor

0.7V

Open-drain

0.7V

IH4

X1, X2, XT1

-0.5

Low-level Input

IL1

Ports 2-5, 9-14, P80, P82

0.3V

Voltage

IL2

Ports 0, 1, 6, 7, 15, P81, P83, RESET

0.2V

IL3

X1, X2, XT1

0.4

High-Level Output

= 4.5 to 6.0 V, I

= -1 mA

-1.0

Voltage

= -100

-0.5

Low-Level Output

Ports 3, 4, and 5

= 4.5 to 6.0 V,

0.2

1.0

Voltage

= 5 mA

= 4.5 to 6.0 V, I

= 1.6 mA

0.4

= 400

0.5

SB0, 1

Open-drain Pull-up

0.2V

resistor

1 k

High-Level Input

LIH1

= V

Other than below

Leakage Current

LIH2

X1, X2, XT1

LIH3

= 9 V

Ports 4, 5, 12-14

(open-drain)

Low-Level Input

LIL1

= 0 V

Other than below

-3

Leakage Current

LIL2

X1, X2, XT1

-20

High-Level Output

LOH1

= V

Other than below

Leakage Current

LOH2

= 9 V

Ports 4, 5, 12-14

(open-drain)

Low-Level Output

LOL

= 0 V

-3

Leakage Current

Internal Pull-Up Resistor

Ports 0, 1, 2, 3, 6, 7

= 5.0 V

10%

(except P00) V

= 0V

= 3.0 V

10%

300

Ports 4, 5, 12-14

= 5.0 V

10%

= V

-2.0 V

= 3.0 V

10%

Internal Pull-Down

= 2 V

Port 9

140

Resistor

PD75512(A)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply Current *

DD1

4.19 MHz*

crystal

Ooperation

= 5 V

10%*

oscillator

mode

= 3 V

10%*

0.55

1.5

DD2

C1 = C2 = 22pF

HALT mode

= 5 V

10%

600

1800

= 3 V

10%

200

600

DD3

32.768 kHz*

crystal Operation

= 3 V

10%

120

oscillator

mode

DD4

HALT mode

= 3 V

10%

DD5

XT1 = 0 V

= 5 V

10%

0.5

STOP mode

= 3 V

10%

0.3

= 25

*1: Currents for the built-in pull-up resistor are not included.

2: Including when the subsystem clock is operated.

3: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.

4: When operated in the low-speed mode with the PCC set to 0000.

5: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001 to

stop the main system clock operation.

PD75512(A)

AC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

(1)

Basic Operation

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

w/main system clock

= 4.5 to 6.0 V

0.95

3.8

w/sub-system clock

114

122

125

TI0 Input Frequency

= 4.5 to 6.0 V

MHz

275

kHz

TI0 Input High-,

TIH

= 4.5 to 6.0 V

0.48

Low-Level Widths

TIL

1.8

Interrupt Input High-,

INTH

INT0

Low-Level Widths

INTL

INT1, 2, 4

KR0-7

RESET Low-Level Width

RSL

*1: The CPU clock (

) cycle time is

determined by the oscillation frequency

of the connected oscillator, system clock

control register (SCC), and processor

clock control register (PCC). The figure

on the right is cycle time t

vs. supply

voltage V

characteristics at the main

system clock.

2: 2t

or 128/f

depending on the setting

of the interrupt mode register (IM0).

0.5

Supply voltage V

[V]

Cycle time t

[ s]

vs V

(with main system clock)

Guaranteed operating range

CPU Clock Cycle Time*

(Minimum Instruction
Execution Time
= 1 Machine Cycle)

PD75512(A)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY1

= 4.5 to 6.0 V

1600

3800

SCK High-, Low-Level

KL1

= 4.5 to 6.0 V

KCY1

/2)-50

Widths

KH1

KCY1

/2)-150

SI Set-Up Time (vs. SCK

) t

SIK1

150

SI Hold Time (vs. SCK

) t

KSI1

400

SCK

SO Output

KSO1

= 1 k

= 4.5 to 6.0 V

250

Delay Time

= 100 pF*

1000

*: R

and C

are load resistance and load capacitance of the SO output line.

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY2

= 4.5 to 6.0 V

800

3200

SCK High-, Low-Level

KL2

= 4.5 to 6.0 V

400

Widths

KH2

1600

SI Set-Up Time (vs. SCK

) t

SIK2

100

SI Hold Time (vs. SCK

)

KSI2

400

SCK

SO Output

KSO2

= 1 k

, C

= 100 pF*

= 4.5 to 6.0 V

300

Delay Time

1000

*: R

and C

are load resistance and load capacitance of the SO output line.

(2)

Serial Transfer Operation

(a)

Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)

(b)

Two-Line and Three-Line Serial I/O Modes (SCK: external clock input)

PD75512(A)

(c)

SBI Mode (SCK: internal clock output (master))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY3

= 4.5 to 6.0 V

1600

3800

SCK High-, Low-Level

KL3

= 4.5 to 6.0 V

KCY3

/2-50

Widths

KH3

KCY3

/2-150

SB0, 1 Set-Up Time

SIK3

150

(vs. SCK

)

SB0, 1 Hold Time

KSI3

KCY3

(vs. SCK

)

SCK

SB0, 1 Output

KSO3

= 4.5 to 6.0 V

250

Delay Time

1000

SCK

SB0, 1

KSB

KCY3

SB0,1

SCK

SBK

KCY3

SB0, 1 Low-Level Width

SBL

KCY3

SB0, 1 High-Level Width

SBH

KCY3

(d)

SBI Mode (SCK: external clock input (slave))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY4

= 4.5 to 6.0 V

800

3200

SCK High-, Low-Level

KL4

= 4.5 to 6.0 V

400

Widths

KH4

1600

SB0, 1 Set-Up Time

SIK4

100

(vs. SCK

)

SB0, 1 Hold Time

KSI4

KCY4

(vs. SCK

)

SCK

SB0, 1 Output

KSO4

= 1 k

= 4.5 to 6.0 V

300

Delay Time

= 100 pF*

1000

SCK

SB0, 1

KSB

KCY4

SB0,1

SCK

SBK

KCY4

SB0, 1 Low-Level Width

SBL

KCY4

SB0, 1 High-Level Width

SBH

KCY4

*: R

and C

are load resistance and load capacitance of the SO output line.

PD75512(A)

(3)

A/D Converter (T

= -40 to +85

C, V

= 3.5 to 6.0 V, AV

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Absolute Accuracy*

2.5 V

REF

2.0

LSB

Conversion Time*

CONV

168/f

Sampling Time*

SAMP

44/f

Analog Input Voltage

IAN

REF

Analog Input Impedance

1000

REF

Current

REF

1.0

2.0

*1: Absolute accuracy excluding quantization error (

LSB)

2: Set ADM1 as follows, in respect to the reference voltage of the AD converter (AV

REF

ADM1 can be set to either 0 or 1 when 0.6V

REF

0.65V

3: Time since execution of conversion start instruction until EOC = 1 (40.1

s: f

= 4.19 MHz)

4: Time since execution of conversion start instruction until end of sampling (10.5

s: f

= 4.19 MHz)

2.5 V

0.6 V

0.65 V

(3.5 to 6.0 V)

ADM1=0

ADM1=1

REF

PD75512(A)

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

= 40 to +85

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data Retention Supply

DDDR

2.0

6.0

Voltage

Data Retention Supply

DDDR

= 2.0 V

0.1

Current*

Release Signal Set Time

SREL

Oscillation Stabilization

WAIT

Released by RESET

Wait Time*

Released by interrupt

*1: Does not include current flowing through internal pull-up resistor

2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent

unstable operation when oscillation is started.

3: Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3

BTM2

BTM1

BTM0

WAIT time ( ): f

= 4.19 MHz

(approx. 250 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

DATA RETENTION TIMING (releasing STOP mode by RESET)

DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)

STOP mode

Data retention mode

STOP instruction
execution

RESET

DDDR

SREL

WAIT

Operation
mode

Internal reset operation

HALT mode

STOP mode

Data retention mode

STOP instruction execution

DDDR

SREL

WAIT

Operation
mode

HALT mode

Standby release signal

(interrupt request)

PD75512(A)

11. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14

20)

detail of lead end

5°±5°

P80GF-80-3B9-2

ITEM

MILLIMETERS

INCHES

23.6±0.4

14.0±0.2

0.8

0.35±0.10

0.15

20.0±0.2

0.929±0.016

0.039

0.031

0.006

0.031 (T.P.)

0.795

NOTE

0.15

1.8±0.2

0.8 (T.P.)

0.006

+0.004

0.003

Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.

0.071

0.014

0.551

0.8±0.2

0.031

2.7

0.106

0.693±0.016

17.6±0.4

1.0

+0.009

0.008

0.1±0.1

0.004±0.004

3.0 MAX.

0.119 MAX.

+0.10

0.05

+0.009

0.008

+0.004

0.005

+0.009

0.008

+0.008

0.009

PD75512(A)

12. RECOMMENDED SOLDERING CONDITIONS

It is recommended that

PD75512(A) be soldered under the following conditions.

For details on the recommended soldering conditions, refer to Information Document "Semiconductor

Devices Mounting Manual" (IEI-616).

For other soldering methods and conditions, consult NEC.

Table 12-1 Soldering Conditions of Surface Mount Type

PD75512GF(A)-xxx-3B9: 80-pin plastic QFP (14

20 mm)

Soldering Method

Soldering Conditions

Symbol for Recommended
Condition

Infrared Reflow

Package peak temperature: 230

IR30-00-1

time: 30 seconds max. (210

C min.),

number of times: 1

VPS

Package peak temperature: 215

VP15-00-1

time: 40 seconds max. (200

C min.),

number of times: 1

Wave Soldering

Soldering bath temperature: 260

C max.,

WS60-00-1

time: 10 seconds max., number of times: 1,
pre-heating temperature: 120

C max. (package surface

temperature)

Pin Partial Heating

Pin temperature: 300

C max.,

time: 3 seconds max. (per side)

Caution: Do not use two or more soldering methods in combination (except the pin partial heating

method).

A model that can be soldered under the more stringent conditions (infrared reflow peak

temperature: 235

C, number of times: 2, and an extended number of days) is also available.

For details, consult NEC.

Notice

PD75512(A)

APPENDIX A. FUNCTIONAL DIFFERENCES AMONG

PD755XX(A) SERIES PRODUCTS

PD75512(A)

PD75516(A)

PD75P516

ROM Configuration

Mask ROM

EPROM/One-time PROM

ROM (Bit)

12160 x 8

16256 x 8

RAM (Bit)

512 x 4

Mask Option

· Ports 4, 5, 12, 14 are provided with internal pull-up

resistors.

Not provided

· Port 9 is provided with an internal pull-down resistor.

, PROM, Pins for programming

Not provided

Provided

LED Direct Drive

Not offered

Offered

Supply Voltage Range

2.7 to 6.0 V

4.75 to 5.5 V

Absolute Maximum

Differ in high-level / low-level output current

Ratings

DC Characteristics

Differ in low-level output voltage

A/D Converter

Differ in ambient temperature range and absolute accuracy

Characteristics

Quality Grade

Special

Standard

Package

80-pin plastic QFP (14 x 20 mm)

· 80-pin plastic QFP

(14 x 20 mm)

· 80-pin ceramic WQFN

Electrical

Specifi-

cations

Product

Item

PD75512(A)

APPENDIX B. DEVELOPMENT TOOLS

The following development support tools are readily available to support development of systems using

PD75512(A):

Hardware

IE-75000-R *

In-circuit emulator for 75X series

IE-75001-R

IE-75000-R-EM *

Emulation board for IE-75000-R and IE-75001-R

EP-75516GF-R

Emulation prove for

PD75512(A), provided with 80-pin conversion socket

EV-9200G-80.

PG-1500

PROM programmer

PA-75P516GF

PROM programmer adapter solely used for

PD75P516GF. It is connected

to PG-1500.

Software

IE Control Program

PG-1500 Controller

RA75X Relocatable
Assembler

* 1: Maintenance product

2: Not provided with IE-75001-R.

3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software.

Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).

EV-9200G-80

Host machine
PC-9800 series (MS-DOS

Ver.3.30 to Ver.5.00A*

)

IBM PC/AT

(PC DOS

Ver.3.1)

PD75512(A)

STATIC ELECTRICITY (ALL MOS DEVICES)

Exercise care so that MOS devices are not adversely influenced by static electricity while being

handled.

The insulation of the gates of the MOS device may be destroyed by a strong static charge.

Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,

or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use

grounding when assembling the MOS device system. Do not leave the MOS device on a plastic

plate and do not touch the pins of the device.

Handle boards on which MOS devices are mounted similarly .

PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)

Fix the input level of CMOS devices.

Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its

input pin, intermediate level input may be generated due to noise, and an inrush current may flow

through the device, causing the device to malfunction. Therefore, fix the input level of the device

by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an

output pin (whose timing is not specified), each pin should be connected to V

or GND through

a resistor.

Refer to "Processing of Unused Pins" in the documents of each devices.

STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)

The initial status of MOS devices is undefined upon power application.

Since the characteristics of an MOS device are determined by the quantity of injection at the

molecular level, the initial status of the device is not controlled during the production process. The

output status of pins, I/O setting, and register contents upon power application are not guaranteed.

However, the items defined for reset operation and mode setting are subject to guarantee after

the respective operations have been executed.

When using a device with a reset function, be sure to reset the device after power application.

GENERAL NOTES ON CMOS DEVICES

PD75512(A)

No p

art of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which

may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other

intellectual property rights of third parties b y or arising from use of a device described herein or any

other liability arising from use of such device. No license, either express, implied or otherwise, is granted

under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,

nuclear reactor control systems and life support systems. If customers intend to use NEC devices for

above applications or they intend to use "Standard" quality grade NEC devices for the applications not

intended by NEC, please contact our sales people in advance.

Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special:

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,

Anticrime system, etc.

MS-DOS is a trademark of Microsoft Corporation.

PC DOS and PC/AT are trademarks of IBM Corporation.

[MEMO]

M4 92.6

Document Outline

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Document Outline

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